Texas Instruments | LMV7219 7-ns 2.7-V to 5-V Comparator with Rail-to-Rail Output (Rev. I) | Datasheet | Texas Instruments LMV7219 7-ns 2.7-V to 5-V Comparator with Rail-to-Rail Output (Rev. I) Datasheet

Texas Instruments LMV7219 7-ns 2.7-V to 5-V Comparator with Rail-to-Rail Output (Rev. I) Datasheet
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LMV7219
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LMV7219 7-ns 2.7-V to 5-V Comparator with Rail-to-Rail Output
1 Features
3 Description
•
The LMV7219 is a low-power, high-speed comparator
with internal hysteresis. The LMV7219 operating
voltage ranges from 2.7 V to 5 V with push-pull railto-rail output. This device achieves a 7-ns
propagation delay while consuming only 1.1 mA of
supply current at 5 V.
1
•
•
•
•
•
•
•
•
(VS = 5 V, TA = 25°C, Typical Values Unless
Specified)
Propagation Delay 7 ns
Low Supply Current 1.1 mA
Input Common Mode Voltage Range Extends
200 mv Below Ground
Ideal for 2.7-V and 5-V Single Supply Applications
Internal Hysteresis Ensures Clean Switching
Fast Rise and Fall Time 1.3 ns
Available in Space-saving Packages: SC-70 and
SOT-23
Supports 105°C PCB Temperature
The LMV7219 inputs have a common mode voltage
range that extends 200 mV below ground, allowing
ground sensing. The internal hysteresis ensures
clean output transitions even with slow-moving inputs
signals.
The LMV7219 is available in the SC-70 and SOT-23
packages, which are ideal for systems where small
size and low power are critical.
Device Information(1)
2 Applications
•
•
•
•
•
•
•
Portable and Battery-powered Systems
Scanners
Set Top Boxes
High Speed Differential Line Receiver
Window Comparators
Zero-crossing Detectors
High-speed Sampling Circuits
PART NUMBER
LMV7219
PACKAGE
BODY SIZE (NOM)
SC-70 (5)
2.00 mm × 1.25 mm
SOT-23 (5)
2.88 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV7219
SNOS458I – APRIL 2000 – REVISED JUNE 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics 2.7 V ................................
Electrical Characteristics 5 V ...................................
Typical Performance Characteristics ........................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2016) to Revision I
Page
•
Added Supports 105°C PCB Temperature to Features List................................................................................................... 1
•
Changed Operating Temperature to Ambient Temperature .................................................................................................. 4
•
Added Junction Temperature of 125 °C ................................................................................................................................. 4
•
Added PCB Temperature of 105 °C ...................................................................................................................................... 4
•
Added TPCB ≤ 105°C throughout Electrical Tables ................................................................................................................ 5
Changes from Revision G (January 2015) to Revision H
Page
•
Changed "Infrared or Convection (20 sec)" from 235 °C ....................................................................................................... 4
•
Added thermal data for SOT23 and SC70 packages ............................................................................................................ 4
Changes from Revision F (April 2013) to Revision G
Page
•
Added, updated, or renamed the following sections: Device Information Table, Pin Configurations and Functions;
Specifications; Application and Implementation; Power Supply Recommendations; Layout; Device and
Documentation Support; Mechanical, Packaging, and Ordering Information ........................................................................ 1
•
Changed from "transient response" to "eliminate possible output chatter" in Circuit Layout and Bypassing ..................... 16
Changes from Revision E (March 2013) to Revision F
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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5 Pin Configuration and Functions
5-Pin SC-70 and SOT-23
Packages DCK and DBV
(Top View)
Pin Functions
PIN
I/O
DESCRIPTION
NUMBER
NAME
1
OUT
O
Output
2
V-
I
Negative Supply
3
+IN
I
Non-inverting input
4
-IN
I
Inverting input
5
V+
I
Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
Differential input voltage
See (3)
Output short circuit duration
−
+
UNIT
± Supply Voltage
Supply voltage (V - V )
5.5
V
260
°C
260 (lead temp)
°C
(V+) + 0.4
(V−) − 0.4
V
Current at input pin (4)
±10
mA
Maximum junction temperature
150
°C
150
°C
Infrared or Convection (20 sec)
Soldering information
Wave Soldering (10 sec)
Voltage at input/output pins
−65
Storage temperature
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely
affect reliability.
Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
6.2 ESD Ratings
VALUE
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic
discharge
V(ESD)
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±150
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±150 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
−
Supply voltages (V - V )
2.7
5
V
Ambient Temperature (1)
−40
+85
°C
Junction Temperature
125
°C
PCB Temperature
105
°C
+
(1)
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PC board.
6.4 Thermal Information
THERMAL METRIC (1)
LMV7219
LMV7219
DBV (SOT23)
DCK (SC70)
UNIT
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
209
296
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
170
132
°C/W
RθJB
Junction-to-board thermal resistance
68
76
°C/W
ψJT
Junction-to-top characterization parameter
52
8.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Thermal Information (continued)
THERMAL METRIC (1)
LMV7219
LMV7219
DBV (SOT23)
DCK (SC70)
5 PINS
5 PINS
UNIT
ψJB
Junction-to-board characterization parameter
68
75
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
6.5 Electrical Characteristics 2.7 V
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = V+/2, V+ = 2.7 V, V− = 0 V, CL = 10 pF and RL > 1MΩ to V−.
PARAMETER
TEST CONDITIONS
VOS
Input offset voltage
IB
Input bias current
IOS
Input offset current
CMRR
Common mode rejection ratio
0 V < VCM < 1.50 V
PSRR
Power supply rejection ratio
V+ = 2.7 V to 5 V
MIN
1
6
8
450
−40°C ≤ TJ ≤ +85°C and TPCB ≤ 105°C
50
−40°C ≤ TJ ≤ +85°C and TPCB ≤ 105°C
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
VO
dB
VCC −1
VCC −0.4
VCC −0.15
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
Sourcing, VO = 0 V (3)
20
(3)
20
IS
Supply current
No Load
VHYST
Input hysteresis voltage
See (4)
7
VTRIP
Input referred positive trip point
(see Figure 19)
3
0.9
(1)
(2)
(3)
(4)
50
mV
150
Output short circuit current
+
200
300
ISC
Sinking, VO = 2.7 V
V
VCC −0.02
15
IL = −0.4 mA,
VID = −500 mV
V
VCC −0.22
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
Output swing low
−0.1
0
130
IL = −4 mA,
VID = −500 mV
nA
VCC −1.3
VCC −0.05
IL = 0.4 mA,
VID = 500 mV
nA
85
55
VCC −0.3
Output swing high
mV
dB
55
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
UNIT
85
−0.2
IL = 4 mA,
VID = 500 mV
200
400
VCC −1.2
CMRR > 50 dB
950
2000
65
Input common-voltage range
MAX (2)
−40°C ≤ TJ ≤ +85°C and TPCB ≤ 105°C
62
VCM
TYP (1)
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
mA
1.6
2.2
mA
mV
8
mV
Typical Values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely
affect reliability.
The LMV7219 comparator has internal hysteresis. The trip points are the input voltage needed to change the output state in each
direction. The offset voltage is defined as the average of Vtrip+ and Vtrip−, while the hysteresis voltage is the difference of these two.
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Electrical Characteristics 2.7 V (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = V+/2, V+ = 2.7 V, V− = 0 V, CL = 10 pF and RL > 1MΩ to V−.
PARAMETER
VTRIP
−
tPD
TEST CONDITIONS
Input referred negative trip point (see Figure 19)
Propagation delay
TYP (1)
−8
−4
Overdrive = 5 mV, VCM = 0V (5)
12
Overdrive = 15 mV, VCM = 0 V (5)
11
(5)
10
Overdrive = 50 mV, VCM = 0 V
tSKEW
Propagation delay skew
See (6)
tr
Output rise time
tf
Output fall time
(5)
(6)
MIN
MAX (2)
UNIT
mV
ns
20
1
ns
10% to 90%
2.5
ns
90% to 10%
2
ns
Propagation delay measurements made with 100 mV steps. Overdrive is measured relative to VTrip.
Propagation Delay Skew is defined as absolute value of the difference between tPDLH and tPDHL.
6.6 Electrical Characteristics 5 V
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = V+/2, V+ = 5 V, V− = 0 V, CL = 10 pF and RL > 1 MΩ to V−.
PARAMETER
TEST CONDITIONS
VOS
Input offset voltage
IB
Input bias current
IOS
Input offset current
CMRR
Common mode rejection ratio
0 V < VCM < 3.8 V
PSRR
Power supply rejection ratio
V+ = 2.7 V to 5 V
MIN
1
6
8
500
−40°C ≤ TJ ≤ +85°C and TPCB ≤ 105°C
50
−40°C ≤ TJ ≤ +85°C and TPCB ≤ 105°C
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
CMRR > 50 dB
Output swing high
IL = 0.4 mA,
VID = 500 mV
VO
IL = −4 mA,
VID = −500 mV
Output swing low
IL = −0.4 mA,
VID = −500 mV
VCC −1
V
(1)
(2)
6
−0.1
0
V
VCC −0.13
VCC −0.3
V
VCC −0.02
VCC −0.15
80
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
180
280
10
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
nA
dB
VCC −1.3
VCC −0.05
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
nA
85
55
VCC −0.2
mV
dB
55
−0.2
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
UNIT
85
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
IL = 4 mA,
VID = 500 mV
200
400
VCC −1.2
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
950
2000
65
VCM
MAX (2)
−40°C ≤ TJ ≤ +85°C and TPCB ≤ 105°C
65
Input common-mode voltage
range
TYP (1)
50
mV
150
Typical Values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis.
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Electrical Characteristics 5 V (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = V+/2, V+ = 5 V, V− = 0 V, CL = 10 pF and RL > 1 MΩ to V−.
PARAMETER
TEST CONDITIONS
Sourcing, VO = 0 V (3)
ISC
Output short circuit current
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
MIN
TYP (1)
30
68
Sinking, VO = 5 V
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
20
1.1
Supply current
No Load
VHYST
Input hysteresis voltage
See (4)
7.5
VTrip+
Input referred positive trip point
(See Figure 19)
3.5
VTrip−
Input referred negative trip
point
(See Figure 19)
tPD
Propagation delay
−40°C ≤ TJ ≤ +85°C
and TPCB ≤ 105°C
−8
−4
9
20
19
Output rise time
tf
Output fall time
mV
mV
7
tr
mA
mV
8
8
See (6)
(5)
(6)
2.4
Overdrive = 50 mV, VCM = 0 V (5)
Overdrive = 15 mV, VCM = 0 V
Propagation delay skew
(4)
1.8
(5)
tSKEW
(3)
mA
65
IS
Overdrive = 5 mV, VCM = 0 V (5)
UNIT
20
30
(3)
MAX (2)
ns
0.4
ns
10% to 90%
1.3
ns
90% to 10%
1.25
ns
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely
affect reliability.
The LMV7219 comparator has internal hysteresis. The trip points are the input voltage needed to change the output state in each
direction. The offset voltage is defined as the average of Vtrip+ and Vtrip−, while the hysteresis voltage is the difference of these two.
Propagation delay measurements made with 100 mV steps. Overdrive is measured relative to VTrip.
Propagation Delay Skew is defined as absolute value of the difference between tPDLH and tPDHL.
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6.7 Typical Performance Characteristics
Unless otherwise specified, VS = 5 V, CL = 10 pF, TA = 25°C
Figure 1. Supply Current vs. Supply Voltage
Figure 2. VOS vs. Supply Voltage
VS = 2.7 V
Figure 3. Input Offset and Trip Voltage vs. Supply Voltage
VS = 5 V
VS = 2.7 V
Figure 5. Sourcing Current vs. Output Voltage
8
Figure 4. Sourcing Current vs. Output Voltage
Figure 6. Sinking Current vs. Output Voltage
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Typical Performance Characteristics (continued)
Unless otherwise specified, VS = 5 V, CL = 10 pF, TA = 25°C
VS = 2.7 V
VOD = 15 mV
VS = 5 V
Figure 7. Sinking Current vs. Output Voltage
VS = 5V
VOD = 15 mV
Figure 8. Propagation Delay vs. Temperature
VS = 5 V
VOD = 15 mV
Figure 9. Propagation Delay vs. Temperature
Figure 10. Propagation Delay vs. Capacitive Load
VS = 2.7 V
CL = 10 pF
VOD = 15 mV
Figure 11. Propagation Delay vs. Input Overdrive
Figure 12. Propagation Delay (tPD−)
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Typical Performance Characteristics (continued)
Unless otherwise specified, VS = 5 V, CL = 10 pF, TA = 25°C
VS = 2.7 V
CL = 10 pF
VOD = 15 mV
Figure 13. Propagation Delay (tPD+)
10
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7 Detailed Description
7.1 Overview
LMV7219 is a single supply comparator with internal hysteresis, 7 ns of propagation delay and only 1.1 mA of
supply current.
The LMV7219 has a typical input common mode voltage range of −0.2 V below the ground to 1 V below Vcc. The
differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. If
either of the input signals falls below the negative common mode limit, the parasitic PN junction formed by the
substrate and the base of the PNP will turn on, resulting in an increase of input bias current.
7.2 Functional Block Diagram
7.3 Feature Description
If one of the inputs goes above the positive common mode limit, the output will still maintain the correct logic
level as long as the other input stays within the common mode range. However, the propagation delay will
increase. When both inputs are outside the common mode voltage range, current saturation occurs in the input
stage, and the output becomes unpredictable.
7.4 Device Functional Modes
The propagation delay does not increase significantly with large differential input voltages. However, large
differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage.
The LMV7219 has a push-pull output. When the output switches, there is a direct path between VCC and ground,
causing high output sinking or sourcing current during the transition. After the transition, the output current
decreases and the supply current settles back to about 1.1 mA at 5 V, thus conserving power consumption.
Most high-speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage
on the other input due to noise or undesirable feedback. The LMV7219 has 7 mV of internal hysteresis to counter
parasitic effects and noise. The hysteresis does not change significantly with the supply voltages and the
common mode input voltages as reflected in the specification table.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following section explains in detail how to manipulate the hysteresis voltage of the LMV7219. Detailed
expressions are provided along with practical considerations for designing hysteresis.
8.2 Typical Application
Figure 14 shows the typical method of adding external hysteresis to a comparator. The positive feedback is
responsible for shifting the comparator trip point depending on the state of the output.
Figure 14. Additional Hysteresis
8.2.1 Design Requirements
The internal hysteresis creates two trip points, one for the rising input voltage and one for the falling input
voltage, as shown in Figure 19. The difference between the trip points is the hysteresis. With internal hysteresis,
when the comparator's input voltages are equal, the hysteresis effectively causes one comparator-input voltage
to move quickly past the other, thus taking the input out of the region where oscillation occurs. Standard
comparators require hysteresis to be added with external resistors. The fixed internal hysteresis eliminates these
resistors.
8.2.2 Detailed Design Procedure
8.2.2.1 Additional Hysteresis
If additional hysteresis is desired, this can be done with the addition of three resistors using positive feedback, as
shown in Figure 14. The positive feedback method slows the comparator response time. Calculate the resistor
values as follows:
1. Select R3. The current through R3 should be greater than the input bias current to minimize errors. The
current through R3 (IF) at the trip point is (VREF - VOUT) /R3. Consider the two possible output states when solving
for R3, and use the smaller of the two resulting resistor values. The two formulas are:
R3 = VREF/IF
(1)
When VOUT = 0:
12
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Typical Application (continued)
R3 = VCC - VREF /IF
(2)
When VOUT = VCC:
2. Choose a hysteresis band required (VHB).
3. Calculate R1, where R1 = R3 X(VHB/VCC)
4. Choose the trip point for VIN rising. This is the threshold voltage (VTHR) at which the comparator switches from
low to high as VIN rises about the trip point.
5. Calculate R2 as follows:
(3)
6. Verify the trip voltage and hysteresis as follows:
(4)
This method is recommended for additional hysteresis of up to a few hundred millivolts. Beyond that, the
impedance of R3 is low enough to affect the bias string and adjustment of R1 may be also required.
8.2.2.2 Zero-Crossing Detector
The inverting input is connected to ground and the non-inverting input is connected to 100mVp-p signal. As the
signal at the non-inverting input crosses 0 V, the comparator's output Changes State.
Figure 15. Zero-Crossing Detector
8.2.2.3 Threshold Detector
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. The non-inverting
input is connected to the input. As the input passes the VREF threshold, the comparator's output changes state.
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Typical Application (continued)
Figure 16. Threshold Detector
8.2.2.4 Crystal Oscillator
A simple crystal oscillator using the LMV7219 is shown in Figure 17. Resistors R1 and R2 set the bias point at
the comparator's non-inverting input. Resistors R3, R4 and C1 sets the inverting input node at an appropriate DC
average level based on the output. The crystal's path provides resonant positive feedback and stable oscillation
occurs. The output duty cycle for this circuit is roughly 50%, but it is affected by resistor tolerances and to a
lesser extent by the comparator offset.
Figure 17. Crystal Oscillator
8.2.2.5 IR Receiver
The LMV7219 is an ideal candidate to be used as an infrared receiver. The infrared photo diode creates a
current relative to the amount of infrared light present. The current creates a voltage across RD. When this
voltage level cross the voltage applied by the voltage divider to the inverting input, the output transitions.
14
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LMV7219
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SNOS458I – APRIL 2000 – REVISED JUNE 2016
Typical Application (continued)
Figure 18. IR Receiver
8.2.3 Application Curve
Figure 19. Input and Output Waveforms, Non-Inverting Input Varied
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Product Folder Links: LMV7219
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LMV7219
SNOS458I – APRIL 2000 – REVISED JUNE 2016
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9 Power Supply Recommendations
The LMV7219 can operate off a single supply or with dual supplies as long as the input CM voltage range (VCM)
has the required headroom to the positive rail V+. The input range extends to slightly below V- voltage. Supplies
should be decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the
device pins. The use of ground plane is recommended, and as in most high speed devices, it is advisable to
remove ground plane close to device sensitive pins such as the inputs.
10 Layout
10.1 Layout Guidelines
10.1.1 Circuit Layout and Bypassing
The LMV7219 requires high-speed layout. Follow these layout guidelines:
1. Power supply bypassing is critical, and will improve stability and eliminate possible output chatter. A
decoupling capacitor such as 0.1-µF ceramic should be placed as close as possible to V+ pin (and to V- pin if
used with dual supplies) as shown in Figure 20. An additional 2.2-µF tantalum capacitor may be required for
extra noise reduction.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize unwanted parasitic
feedback around the comparator.
3. The device should be soldered directly to the PC board instead of using a socket.
4. Use a PC board with a good, unbroken low inductance ground plane as shown in Figure 20. Make sure
ground paths are low-impedance, especially were heavier currents are flowing.
5. Input traces should be kept away from output traces. This can be achieved by running a topside ground
plane between the output and inputs.
6. Run the ground trace under the device up to the bypass capacitor to shield the inputs from the outputs.
7. To prevent parasitic feedback when input signals are slow-moving, a small capacitor of 1000 pF or less can
be placed between the inputs. It can also help eliminate oscillations in the transition region. However, this
capacitor can cause some degradation to tpd when the source impedance is low.
16
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LMV7219
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SNOS458I – APRIL 2000 – REVISED JUNE 2016
10.2 Layout Example
Figure 20. SOT-23 Board Layout Example
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Product Folder Links: LMV7219
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LMV7219
SNOS458I – APRIL 2000 – REVISED JUNE 2016
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Absolute Maximum Ratings for Soldering (SNOA549)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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Product Folder Links: LMV7219
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV7219M5
ACTIVE
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
C14A
LMV7219M5/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C14A
LMV7219M5X
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 85
C14A
LMV7219M5X/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C14A
LMV7219M7
ACTIVE
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 85
C15
LMV7219M7/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C15
LMV7219M7X/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C15
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LMV7219M5
SOT-23
DBV
5
1000
178.0
8.4
LMV7219M5/NOPB
SOT-23
DBV
5
1000
178.0
LMV7219M5X
SOT-23
DBV
5
3000
178.0
LMV7219M5X/NOPB
SOT-23
DBV
5
3000
LMV7219M7
SC70
DCK
5
LMV7219M7/NOPB
SC70
DCK
LMV7219M7X/NOPB
SC70
DCK
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV7219M5
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7219M5/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7219M5X
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV7219M5X/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV7219M7
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7219M7/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7219M7X/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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