Texas Instruments | INA3221 Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor with I2C- and SMBUS-Compatible Interface (Rev. B) | Datasheet | Texas Instruments INA3221 Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor with I2C- and SMBUS-Compatible Interface (Rev. B) Datasheet

Texas Instruments INA3221 Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor with I2C- and SMBUS-Compatible Interface (Rev. B) Datasheet
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INA3221
SBOS576B – MAY 2012 – REVISED MARCH 2016
INA3221 Triple-Channel, High-Side Measurement,
Shunt and Bus Voltage Monitor with I2C- and SMBUS-Compatible Interface
1 Features
3 Description
•
•
•
The INA3221 is a three-channel, high-side current
and bus voltage monitor with an I2C- and SMBUScompatible interface. The INA3221 monitors both
shunt voltage drops and bus supply voltages, in
addition to having programmable conversion times
and averaging modes for these signals. The INA3221
offers both critical and warning alerts to detect
multiple programmable out-of-range conditions for
each channel.
1
•
•
•
•
Senses Bus Voltages From 0 V to 26 V
Reports Shunt and Bus Voltage
High Accuracy:
– Offset Voltage: ±80 µV (max)
– Gain Error: 0.25% (max)
Configurable Averaging Options
Four Programmable Addresses
Programmable Alert and Warning Outputs
Power-Supply Operation: 2.7 V to 5.5 V
The INA3221 senses current on buses that can vary
from 0 V to 26 V. The device is powered from a
single 2.7-V to 5.5-V supply, and draws 350 μA (typ)
of supply current. The INA3221 is specified over the
operating temperature range of –40°C to +125°C.
The I2C- and SMBUS-compatible interface features
four programmable addresses.
2 Applications
•
•
•
•
•
•
Computers
Power Management
Telecom Equipment
Battery Chargers
Power Supplies
Test Equipment
Device Information(1)
PART NUMBER
INA3221
PACKAGE
VQFN (16)
BODY SIZE (NOM)
4.00 mm x 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Typical Application
Power Supply
(0 V to 26 V)
CBYPASS
0.1 µF
Load 1
VIN+1
VS (Supply
Voltage)
VIN±1
Power Supply
(0 V to 26 V)
10 k
SDA
CH 1
VIN+2
Bus
Voltages 1-3
CH 2
Shunt
Voltages 1-3
ADC
VIN±2
Critical Limit
Alerts 1-3
CH 3
Load 2
Shunt Voltage
Sum Alerts
I2Cand
SMBusCompatible
Interface
SCL
A0
VPU
VS
10 k
VPU
Power Valid (PV)
Critical
Warning
Timing Control (TC)
GND
VIN+3
Power Supply
(0 V to 26 V)
VIN±3
Load 3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA3221
SBOS576B – MAY 2012 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
16
8.5 Programming .......................................................... 20
8.6 Register Maps ......................................................... 24
9
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Application ................................................. 36
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
11.2 Layout Example .................................................... 38
12 Device and Documentation Support ................. 39
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
39
39
13 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2013) to Revision B
Page
•
Added Device Informationand ESD Ratings tables, and Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections ................................................................................................ 1
•
Deleted trace from SDA to SCL, and added missing connector dot to VS in front-page diagram ........................................ 1
•
Added (VIN+) + (VIN–) / 2 to common-mode analog inputs in the Absolute Maximum Ratings table ..................................... 5
•
Deleted VBUS from analog inputs in Absolute Maximum Ratings table ............................................................................... 5
•
Added operating temperature to Absolute Maximum Ratings table ....................................................................................... 5
•
Changed all VSENSE to VSHUNT throughout data sheet for consistency.................................................................................... 6
•
Changed "Status register" to "Mask/Enable register" to clarify register name in Basic ADC Functions section ................. 11
•
Changed Critical Alert section text for clarity. ...................................................................................................................... 12
•
Added Summation Control Function section ........................................................................................................................ 12
•
Changed external "RPU" to "RPU_ext" in Figure 20 ................................................................................................................. 14
•
Changed Multiple Channel Monitoring section text for clarity. ............................................................................................ 17
•
Added X and Y axis labels to Figure 25 ............................................................................................................................... 18
•
Changed "bidirectional" to "I/O" in second paragraph of Bus Overview section .................................................................. 20
•
Changed VS+ to VS in Table 1.............................................................................................................................................. 20
•
Changed references in Figure 30 to point to correct notes .................................................................................................. 22
•
Changed Figure 31 ............................................................................................................................................................... 23
•
Changed values in Table 2, Bus Timing Definitions............................................................................................................. 23
•
Added data valid time to Table 2, Bus Timing Definitions.................................................................................................... 23
•
Changed fall time to split data and clock times in Table 2, Bus Timing Definitions ............................................................. 23
•
Deleted rise time for data in Table 2, Bus Timing Definitions .............................................................................................. 23
•
Deleted trace from SDA to SCL, and added missing connector dot to VS in Figure 52 ...................................................... 36
2
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Changes from Original (May 2012) to Revision A
Page
•
Changed Shunt voltage input range parameter values in Electrical Characteristics table..................................................... 6
•
Updated Figure 19 ................................................................................................................................................................ 13
•
Changed second paragraph of Serial Bus Address section................................................................................................. 20
•
Updated Figure 27 and note (1) ........................................................................................................................................... 21
•
Updated Figure 28 and note (1) ........................................................................................................................................... 21
•
Updated Figure 29 and note (1) ........................................................................................................................................... 22
•
Updated Figure 30 and note (1) ........................................................................................................................................... 22
•
Changed bit D15 in Power Valid Upper Limit Register ........................................................................................................ 34
•
Changed bit D15 in Power Valid Lower Limit Register ........................................................................................................ 34
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SBOS576B – MAY 2012 – REVISED MARCH 2016
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5 Device Comparison Table
DEVICE
DESCRIPTION
INA226
36-V, Bidirectional, Ultrahigh Accuracy, Low- or High-Side, I2C Out, Current and Power Monitor With Alert
INA219
26-V, Bidirectional, Zero-Drift, High-Side, I2C Out, Current and Power Monitor
INA209
26-V, Bidirectional, Low- or High-Side, I2C Out, Current and Power Monitor and High-Speed Comparator
INA210, INA211, INA212,
INA213, INA214
26-V, Bidirectional, Zero-Drift, High-Accuracy, Low- or High-Side, Voltage Out, Current Shunt Monitor
6 Pin Configuration and Functions
VPU
IN+2
IN 2
TC
16
15
14
13
RGV Package
16-Pin VQFN
Top View
GND
3
10
PV
VS
4
9
Critical
8
IN 1
Warning
11
7
2
SDA
IN+3
6
IN+1
SCL
12
5
1
A0
IN 3
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Address pin. Connect to GND, SCL, SDA, or VS. Table 1 shows pin settings and
corresponding addresses.
A0
5
Digital input
Critical
9
Digital output
GND
3
Analog
IN–1
11
Analog input
Connect to load side of the channel 1 shunt resistor. Bus voltage is the measurement
from this pin to ground.
IN+1
12
Analog input
Connect to supply side of the channel 1 shunt resistor.
IN–2
14
Analog input
Connect to load side of the channel 2 shunt resistor. Bus voltage is the measurement
from this pin to ground.
IN+2
15
Analog input
Connect to supply side of the channel 2 shunt resistor.
IN–3
1
Analog input
Connect to load side of the channel 3 shunt resistor. Bus voltage is the measurement
from this pin to ground.
Conversion-triggered critical alert; open-drain output.
Ground
IN+3
2
Analog input
Connect to supply side of the channel 3 shunt resistor.
PV
10
Digital output
Power valid alert; open-drain output.
SCL
6
Digital input
SDA
7
Digital I/O
TC
13
Digital output
Timing control alert; open-drain output.
VPU
16
Analog input
Pull-up supply voltage used to bias power valid output circuitry.
VS
4
Analog
Warning
8
Digital output
4
Serial bus clock line; open-drain input.
Serial bus data line; open-drain input/output.
Power supply, 2.7 V to 5.5 V.
Averaged measurement warning alert; open-drain output.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage
MAX
UNIT
6
V
Supply, VS
Differential (VIN+) – (VIN–)
IN+, IN–
Analog inputs
(2)
Common-mode (VIN+) + (VIN–) / 2
–26
26
–0.3
26
VPU
Digital outputs
Serial bus
Current
Critical, warning, power valid
6
Timing control
26
(GND – 0.3)
6
Clock line, SCL
(GND – 0.3)
(VS + 0.3)
Input, into any pin
5
Open-drain, digital output
10
–40
(2)
V
mA
125
Junction, TJ
150
Storage, Tstg
(1)
V
Data line, SDA
Operating, TA
Temperature
V
26
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VIN+ and VIN– can have a differential voltage of –26 V to +26 V; however, the voltage at these pins must not exceed the range of
–0.3 V to +26 V.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Operating supply voltage
2.7
5.5
V
Operating temperature, TA
–40
125
°C
7.4 Thermal Information
INA3221
THERMAL METRIC (1)
RGV (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
36.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.7
°C/W
RθJB
Junction-to-board thermal resistance
14.7
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
14.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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7.5 Electrical Characteristics
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+) – (VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–163.84
163.8
mV
0
26
INPUT
VSHUNT
Shunt voltage input
VBUS
Bus voltage input
CMR
Common-mode rejection
VIN+ = 0 V to +26 V
±40
±80
μV
Shunt offset voltage, RTI (1)
TA = –40°C to +125°C
0.1
0.5
μV/°C
vs power supply, VS = 2.7 V to 5.5 V
15
VOS
PSRR
110
120
±8
VOS
Bus offset voltage, RTI (1)
PSRR
TA = –40°C to +125°C
vs power supply
Input bias current at IN+
10
IIN–
Input bias current at IN–
10 || 670
Input leakage (2)
μV/V
±16
mV
80
μV/°C
0.5
IIN+
(IN+ pin) + (IN– pin), power-down mode
0.1
V
dB
mV/V
μA
μA || kΩ
0.5
μA
DC ACCURACY
ADC native resolution
13
Shunt voltage
1-LSB step size
Bus voltage
Shunt voltage gain error
Bus voltage gain error
DNL
TA = –40°C to +125°C
Differential nonlinearity
tCONVERT
ADC conversion time
μV
8
mV
0.1%
TA = –40°C to +125°C
Bits
40
0.25%
10
50
0.1%
0.25%
10
50
±0.1
ppm/°C
ppm/°C
LSB
CT bit = 000
140
154
CT bit = 001
204
224
CT bit = 010
332
365
CT bit = 011
588
646
CT bit = 100
1.1
1.21
CT bit = 101
2.116
2.328
CT bit = 110
4.156
4.572
CT bit = 111
8.244
9.068
28
35
ms
1
μA
µs
ms
SMBus
SMBus timeout (3)
DIGITAL INPUT/OUTPUT
CI
Input capacitance
3
0 V ≤ VIN ≤ VS
Leakage input current
0.1
pF
VIH
High-level input voltage
0.7 (VS)
6
V
VIL
Low-level input voltage
–0.5
0.3 (VS)
V
VOL
Low-level output
voltage
Vhys
Hysteresis voltage
SDA, critical, warning, PV
VS > +2.7 V, IOL = 3 mA
0
0.4
TC
VS > +2.7 V, IOL = 1.2 mA
0
0.4
500
V
mV
POWER SUPPLY
Quiescent current
Power-down mode
Power-on reset threshold
(1)
(2)
(3)
6
350
450
0.5
2
2
μA
V
RTI = Referred-to-input.
Input leakage is positive (current flows into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur
under different input conditions.
SMBus timeouts in the INA3221 reset the interface whenever SCL is low for more than 28 ms.
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7.6 Typical Characteristics
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+) – (VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
0
−10
Population
Gain (dB)
−20
−30
−40
200
160
120
G001
80
100k
40
10k
0
100
1k
Frequency (Hz)
−40
10
−120
1
−160
−60
−80
−50
Input Offset Voltage (µV)
G003
Figure 2. Shunt Input Offset Voltage Production Distribution
Figure 1. Frequency Response
130
Common−Mode Rejection (dB)
Input Offset Voltage (µV)
50
45
40
35
30
−50
−25
0
25
50
75
Temperature (°C)
100
125
125
120
115
−50
150
−25
0
G004
Figure 3. Shunt Input Offset Voltage vs Temperature
25
50
75
Temperature (°C)
100
125
150
G005
Figure 4. Shunt Input Common-Mode Rejection Ratio vs
Temperature
400
Population
Input Gain Error (m%)
350
300
250
200
150
100
Input Gain Error (%)
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
50
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
150
G007
G006
Figure 5. Shunt Input Gain Error Production Distribution
Figure 6. Shunt Input Gain Error vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+) – (VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
150
Population
Input Offset Voltage (mV)
34
32
24
16
6 8 10 12 14 16 18 20 22 24 26
Common−Mode Input Voltage (V)
G008
8
4
0
2
−8
0
−24
50
−16
100
−32
Input Gain Error (m%)
200
G009
Figure 8. Bus Input Offset Voltage Production Distribution
Figure 7. Shunt Input Gain Error vs Common-Mode Voltage
4
0
Population
−4
−8
150
G010
0.4
125
0.3
100
0.2
25
50
75
Temperature (°C)
0.1
0
0
−25
−0.2
−16
−50
−0.1
−12
−0.3
Input Offset Voltage (mV)
8
Input Gain Error (%)
Figure 10. Bus Input Gain Error Production Distribution
400
50
350
45
Input Bias Current (µA)
Input Gain Error (m%)
Figure 9. Bus Input Offset Voltage vs Temperature
300
250
200
150
100
50
40
35
30
IB−
25
20
15
IB+
10
5
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
150
0
0
G012
Figure 11. Bus Input Gain Error vs Temperature
8
G011
4
8
12
16
20
Common−Mode Input Voltage (V)
24
28
G013
Figure 12. Input Bias Current vs Common-Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+) – (VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
30
450
400
IB−
Input Bias Current (nA)
Input Bias Current (µA)
25
20
15
IB+
10
350
300
250
200
150
100
5
IB+, IB−
50
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
0
−50
150
0
25
50
75
Temperature (°C)
100
125
150
G015
Figure 14. Input Bias Current vs Temperature (Shutdown)
500
3.5
450
3
Quiescent Current (µA)
Quiescent Current (µA)
Figure 13. Input Bias Current vs Temperature
400
350
300
250
2.5
2
1.5
1
0.5
200
−50
−25
0
25
50
75
Temperature (°C)
100
125
0
−50
150
G016
Figure 15. Active IQ vs Temperature
−25
0
25
50
75
Temperature (°C)
100
125
150
G017
Figure 16. Shutdown IQ vs Temperature
700
350
650
300
Quiescent Current (µA)
Quiescent Current (µA)
−25
G014
600
550
500
450
400
250
200
150
100
50
350
300
0.01
0.1
Frequency (MHz)
1
4
0
0.01
G018
Figure 17. Active IQ vs I2C Clock Frequency
0.1
Frequency (MHz)
1
4
G019
Figure 18. Shutdown IQ vs I2C Clock Frequency
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8 Detailed Description
8.1 Overview
The INA3221 is a current-shunt and bus voltage monitor that communicates over an I2C- and SMBus-compatible
interface. The INA3221 provides digital shunt and bus voltage readings necessary for accurate decision making
in precisely-controlled systems, and also monitors multiple rails to maintain compliance voltages. Programmable
registers offer flexible configuration for measurement precision, and continuous versus single-shot operation. The
Register Maps section provides details of the INA3221 registers, beginning with Table 3.
8.2 Functional Block Diagram
Bus Voltage(1)
Shunt Voltage
Channel
Channel 2
X
Power Valid
Upper Limit (2)
Channel 3
ADC
Bus Voltage
Channel
Power Valid
Lower Limit(2)
Shunt Voltage(1)
X
Critical Limit(2)
Warning Limit(2)
Channel 2
Summation(1)
Channel 3
Summation Limit(2)
10
(1)
Read-only.
(2)
Read/write.
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8.3 Feature Description
8.3.1 Basic ADC Functions
The INA3221 performs two measurements on up to three power supplies of interest. The voltage developed from
the load current passing through a shunt resistor creates a shunt voltage that is measured between the IN+ and
IN– pins. The device also internally measures the power-supply bus voltage at the IN– pin for each channel. The
differential shunt voltage is measured with respect to the IN– pin, and the bus voltage is measured with respect
to ground.
The INA3221 is typically powered by a separate power supply that ranges from 2.7 V to 5.5 V. The monitored
supply buses range from 0 V to 26 V.
CAUTION
Based on the fixed 8-mV bus-voltage register LSB (for any channel), a full-scale
register value results in 32.76 V. However, the actual voltage applied to the INA3221
input pins must not exceed 26 V.
There are no special power-supply sequencing considerations between the common-mode input ranges and the
device power-supply voltage because they are independent of each other; therefore, the bus voltages can be
present with the supply voltage off and vice versa.
The INA3221 takes two measurements for each channel: one for shunt voltage and one for bus voltage. Each
measurement can be independently or sequentially measured, based on the mode setting (bits 2-0 in the
Configuration register). When the INA3221 is in normal operating mode (that is, the MODE bits of the
Configuration register are set to 111), the device continuously converts a shunt-voltage reading followed by a
bus-voltage reading. This procedure converts one channel, and then continues to the shunt voltage reading of
the next enabled channel, followed by the bus-voltage reading for that channel, and so on, until all enabled
channels have been measured. The programmed Configuration register mode setting applies to all channels.
Any channels that are not enabled are bypassed in the measurement sequence, regardless of mode setting.
The INA3221 has two operating modes, continuous and single-shot, that determine the internal ADC operation
after these conversions complete. When the INA3221 is set to continuous mode (using the MODE bit settings),
the device continues to cycle through all enabled channels until a new configuration setting is programmed.
The Configuration register MODE control bits also enable modes to be selected that convert only the shunt or
bus voltage. This feature further allows the device to fit specific application requirements.
In single-shot (triggered) mode, setting any single-shot convert mode to the Configuration register (that is, the
Configuration register MODE bits set to 001, 010, or 011) triggers a single-shot conversion. This action produces
a single set of measurements for all enabled channels. To trigger another single-shot conversion, write to the
Configuration register a second time, even if the mode does not change. When a single-shot conversion is
initiated, all enabled channels are measured one time and then the device enters a power-down state. The
INA3221 registers can be read at any time, even while in power-down. The data present in these registers are
from the last completed conversion results for the corresponding register. The conversion ready flag bit
(Mask/Enable register, CVRF bit) helps coordinate single-shot conversions, and is especially helpful during
longer conversion time settings. The CVRF bit is set after all conversions are complete. The CVRF bit clears
under the following conditions:
1. Writing to the Configuration register, except when configuring the MODE bits for power-down mode; or
2. Reading the Mask/Enable register.
In addition to the two operating modes (continuous and single-shot), the INA3221 also has a separate selectable
power-down mode that reduces the quiescent current and turns off current into the INA3221 inputs. Power-down
mode reduces the impact of supply drain when the device is not used. Full recovery from power-down mode
requires 40 µs. The INA3221 registers can be written to and read from while the device is in power-down mode.
The device remains in power-down mode until one of the active MODE settings are written to the Configuration
register.
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Feature Description (continued)
8.3.2 Alert Monitoring
The INA3221 allows programmable thresholds that make sure the intended application operates within the
desired operating conditions. Multiple monitoring functions are available using four alert pins: Critical, Warning,
PV (power valid), and TC (timing control). These alert pins are open-drain connections.
8.3.2.1 Critical Alert
The critical-alert feature monitors functions based on individual conversions of each shunt-voltage channel. The
critical-alert limit feature compares the shunt-voltage conversion for each shunt-voltage channel to the value
programmed into the corresponding limit register, in order to determine if the measured value exceeds the
intended limit. Exceeding the programmed limit indicates that the current through the shunt resistor is too high.
At power-up, the default critical-alert limit value for each channel is set to the positive full-scale value, effectively
disabling the alert. Program the corresponding limit registers at any time to begin monitoring for out-of-range
conditions. The Critical alert pin pulls low if any channel measurement exceeds the limit present in the
corresponding-channel critical-alert limit register. When the Critical alert pulls low, read the Mask/Enable register
to determine which channel caused the critical alert flag indicator bit (CF1-3) to assert (= 1).
8.3.2.1.1 Summation Control Function
The INA3221 also allows the Critical alert pin to be controlled by the summation control function. This function
adds the single shunt-voltage conversions for the desired channels (set by SCC1-3 in the Mask/Enable register)
in order to compare the combined sum to the programmed limit.
The SCC bits either disable the summation control function or allow the summation control function to switch
between including two or three channels in the Shunt-Voltage Sum register. The Shunt-Voltage Sum Limit
register contains the programmed value that is compared to the value in the Shunt-Voltage Sum register in order
to determine if the total summed limit is exceeded. If the shunt-voltage sum limit value is exceeded, the Critical
alert pin pulls low. Either the summation alert flag indicator bit (SF) or the individual critical alert limit bits (CF1-3)
in the Mask/Enable register determine the source of the alert when the Critical alert pin pulls low.
For the summation limit to have a meaningful value, use the same shunt-resistor value on all included channels.
Unless equal shunt-resistor values are used for each channel, do not use this function to add the individual
conversion values directly together in the Shunt-Voltage Sum register to report the total current.
8.3.2.2 Warning Alert
The warning alert monitors the averaged value of each shunt-voltage channel. The averaged value of each
shunt-voltage channel is based on the number of averages set with the averaging mode bits (AVG1-3) in the
Configuration register. The average value updates in the shunt-voltage output register each time there is a
conversion on the corresponding channel. The device compares the averaged value to the value programmed in
the corresponding-channel Warning Alert Limit register to determine if the averaged value has been exceeded,
indicating whether the average current is too high. At power-up, the default warning-alert limit value for each
channel is set to the positive full-scale value, effectively disabling the alert. The corresponding limit registers can
be programmed at any time to begin monitoring for out-of-range conditions. The Warning alert pin pulls low if any
channel measurements exceed the limit present in the corresponding-channel Warning Alert Limit register. When
the Warning alert pin pulls low, read the Mask/Enable register in order to determine which channel warning alert
flag indicator bit (WF1-3) is asserted (= 1).
12
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Feature Description (continued)
8.3.2.3 Power-Valid Alert
The power-valid alert verifies if all power rails are above the required levels. This feature manages power
sequencing, and validates the reported measurements based on system configuration. Power-valid mode starts
at power-up, and detects when each channel exceeds a 10-V threshold. This 10-V level is the default value
programmed into the Power-Valid Upper-Limit register. This value can be reprogrammed when the INA3221 is
powered up to a valid supply-voltage level of at least 2.7 V. When all three bus-voltage measurements reach the
programmed value loaded to the Power-Valid Upper-Limit register, the power-valid (PV) alert pin pulls high. PV
powers up in a low state, and does not pull high until the power-valid conditions are met, indicating all busvoltage rails are above the power-valid upper-limit value. This sequence is shown in Figure 19.
All enabled channel bus voltages are
above the power-valid upper limit.
Power
Valid
Output
All enabled channel bus voltages are
above the power-valid upper limit.
High
Low
All enabled channel bus voltages are
not above the power-valid upper limit.
At least one bus voltage channel has
dropped below the power-valid lower limit.
Figure 19. Power-Valid State Diagram
When the power-valid conditions are met, and the PV pin pulls high, the INA3221 monitors if any bus-voltage
measurements drop below 9 V. This 9-V level is the default value programmed into the Power-Valid Lower-Limit
register. This value can also be reprogrammed when the INA3221 powers up to a supply voltage of at least 2.7
V. If any bus-voltage measurement on the three channels drops below the Power-Valid Lower-Limit register
value, the PV pin goes low, indicating that the power-valid condition is no longer met. At this point, the INA3221
resumes monitoring the power rails for a power-valid condition set in the Power-Valid Upper-Limit register.
The power-valid alert function is based on the power-valid conditions requirement that all three channels reach
the intended Power-Valid Upper-Limit register value. If all three channels are not used, connect the unusedchannel IN– pin externally to one of the used channels in order to use the power-valid alert function. If the
unused channel is not connected to a valid rail, the power-valid alert function cannot detect if all three channels
reach the power-valid level. Float the unused channel IN+ pin.
The power-valid function also requires that bus-voltage measurements are monitored. To detect changes in the
power-valid state, enable bus-voltage measurements through one of the corresponding MODE-bit settings in the
Configuration register. The single-shot bus-voltage mode periodically cycles between the bus-voltage
measurements to make sure that the power-valid conditions are met.
When all three bus-voltage measurements are completed, the device compares the results to the power-valid
threshold values to determine the power-valid state. The bus-voltage measurement values remain in the
corresponding channel output registers until the bus-voltage measurements are taken again, thus updating the
output registers. When the output registers are updated, the values are again compared to the power-valid
thresholds. Without taking periodic bus-voltage measurements, the INA3221 is unable to determine if the powervalid conditions are maintained.
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Feature Description (continued)
The PV pin allows for a 0-V output that indicates a power-invalid condition. An output equal to the pull-up supply
voltage connected to the VPU pin indicates a power-valid condition, as shown in Figure 20. It is also possible to
divide down the high power-valid pull-up voltage by adding a resistor to ground at the PV output, thus allowing
this function to interface with lower-voltage circuitry, if needed.
VS
INA3321
VPU
RPU_ext
PV
RPU
RDIV(1)
Power-Valid
Detection
(1)
RDIV can be used to level-shift the PV output high.
Figure 20. Power-Valid Output Structure
8.3.2.4 Timing-Control Alert
The INA3221 timing-control alert function helps verify proper power-supply sequencing. At power-up, the default
INA3221 setting is continuous shunt- and bus-voltage conversion mode, and the INA3221 internally begins
comparing the channel-1 bus voltage to determine when a 1.2-V level is reached. This comparison is made each
time the sequence returns to the channel-1 bus-voltage measurement. When a 1.2-V level is detected on the
channel-1 bus-voltage measurement, the INA3221 begins checking for a 1.2-V level present on the channel-2
bus-voltage measurement. After a 1.2-V level is detected on channel 1, if the INA3221 does not detect a 1.2-V
value or greater on the bus voltage measurement following four complete cycles of all three channels, the timing
control (TC) alert pin pulls low to indicate that the INA3221 has not detected a valid power rail on channel 2. As
shown in Figure 21, this sequence allows for approximately 28.6 ms from the time 1.2 V is detected on channel 1
for a valid voltage to be detected on channel 2. Figure 22 illustrates the state diagram for the TC alert pin.
Measure For 1.2 V on
Channel-2 Bus Voltage
1.2 V Detected on Channel-1
Bus-Voltage Measurement
Signal
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB SB
SB
SB
Channel
Ch
1
Ch
2
Ch
3
Ch
1
Ch
2
Ch
3
Ch
1
Ch
2
Ch
3
Ch
1
Ch
2
Ch
3
Ch
2
Ch
3
Ch
1
2.2 ms
28.6 ms
NOTE: The signal refers to the corresponding shunt (S) and bus (B) voltage measurement for each channel.
Figure 21. Timing Control Timing Diagram
1.2 V Detected on Channel-1
Bus-Voltage Measurement
Measure for 1.2 V
on Channel-2 Bus Voltage
1.2 V on Channel 2 Detected
High
Timing
Control
Output
28.6 ms
1.2 V on Channel 2 Not Detected
Low
Figure 22. Timing Control State Diagram
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Feature Description (continued)
The timing control alert function is only monitored at power-up or when a software reset is issued by setting the
reset bit (RST, bit 15) in the Configuration register. The timing control alert function timing is based on the default
device settings at power-up. Writing to the Configuration register before the timing control alert function
completes the full sequence results in disabling the timing control alert until power is cycled or a software reset is
issued.
8.3.2.5 Default Settings
The default register power-up states are listed in the Register Maps section. These registers are volatile; if
programmed to a value other than the default values shown in Table 3, the registers must be reprogrammed
every time the device powers up.
8.3.3 Software Reset
The INA3321 features a software reset that reinitializes the device and register settings to default power-up
values without having to cycle power to the device. Use bit 15 (RST) of the Configuration register to perform a
software reset. Setting RST reinitializes all registers and settings to the default power state with the exception of
the power-valid output state.
If a software reset is issued, the INA3221 holds the output of the PV pin until the power-valid detection sequence
completes. The Power-Valid Upper Limit and Power-Valid Lower limit registers return to the default state when
the software reset has been issued. Therefore, any reprogrammed limit registers are reset, resulting in the
original power-valid thresholds validating the power-valid conditions. This architecture prevents interruption to
circuitry connected to the power valid output during a software reset event.
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8.4 Device Functional Modes
8.4.1 Averaging Function
The INA3221 includes three channels to monitor up to three independent supply buses; however, multichannel
monitoring sometimes results in poor shunt-resistor placement. Ideally, shunt resistors are placed as close as
possible to the corresponding channel input pins. However, because of system layout and multiple power-supply
rails, one or more shunt resistors may have to be located further away, thus presenting potentially larger
measurement errors. These errors result from additional trace inductance and other parasitic impedances
between the shunt resistor and input pins. Longer traces also create an additional potential for coupling noise
into the signal if they are routed near noise-generating sections of the board.
The INA3221 averaging function mitigates this potential problem by limiting the impact that any single
measurement has on the averaged value of each measured signal. This limitation reduces the influence that
noise has on the averaged value, thereby effectively creating an input-signal filter.
The averaging function is illustrated in Figure 23. Operation begins by first measuring the shunt input signal on
channel 1. This value is then subtracted from the previous value that was present in the corresponding data
output register. This difference is then divided by the value programmed by the averaging mode setting (AVG2-0,
Configuration register bits 11-9) and stored in an internal accumulation register. The computed result is then
added to the previously-loaded data output register value, and the resulting value is loaded to the corresponding
data output register. After the update, the next signal to be measured follows the same process. The larger the
value selected for the averaging mode setting, the less impact or influence any new conversion has on the
average value, as shown in Figure 24. This averaging feature functions as a filter to reduce input noise from the
averaged measurement value.
New
Sample
+
÷
+
Output
Register
AVG #
±
+
Figure 23. Averaging Function Block Diagram
26
1 Average
16 Averages
1024 Averages
Amplitude (mV)
25
24
23
22
21
20
1000
2000
3000
4000
Samples
5000
6000
7000
G020
Figure 24. Average Setting Example
16
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Device Functional Modes (continued)
8.4.2 Multiple Channel Monitoring
The INA3221 monitors shunt and voltage measurements for up to three unique power-supply rails, and
measures up to six different signals. Adjust the number of channels and signals being measured by setting the
channel enable (CH1en to CH3en) and mode (MODE3-1) bits in the Configuration register. This adjustment allows
the device to be optimized based on application requirements for the system in use.
8.4.2.1 Channel Configuration
If all three channels must be monitored at power-up, but only one channel must be monitored after the system
has stabilized, disable the other two channels after power-up. This configuration allows the INA3221 to only
monitor the power-supply rail of interest. Disable unused channels to help improve system response time by
more quickly returning to sampling the channel of interest. The INA3221 linearly monitors the enabled channels.
That is, if all three channels are enabled for both shunt- and bus-voltage measurements, an additional five
conversions complete after a signal is measured before the device returns to that particular signal to begin
another conversion. To reduce this requirement down to two conversions before the device begins a new
conversion on a particular channel again, change the operating mode to monitor only the shunt voltage.
A timing aspect is also involved in reducing the measured signals. The amount of time to complete an allchannel, shunt- and bus-voltage sequence is equal to the sum of the shunt-voltage conversion time and the busvoltage conversion time (programmed by the CT bits in the Configuration register) multiplied by the three
channels. The conversion times for the shunt- and bus-voltage measurements are programmed independently;
however, the selected shunt- and bus-voltage conversion times apply to all channels.
Enable a single channel with only one signal measured to allow for that particular signal to be monitored solely.
This setting enables the fastest response over time to changes in that specific input signal because there is no
delay from the end of one conversion before the next conversion begins on that channel. Conversion time is not
affected by enabling or disabling other channels. Selecting both the shunt- and bus-voltage settings, as well as
enabling additional channels, extends the time from the end of one conversion on a signal before the beginning
of the next conversion of that signal.
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Device Functional Modes (continued)
8.4.2.2 Averaging and Conversion-Time Considerations
The INA3221 has programmable conversion times for both the shunt- and bus-voltage measurements. The
selectable conversion times for these measurements range from 140 μs to 8.244 ms. The conversion-time
settings, along with the programmable-averaging mode, enable the INA3221 to optimize available timing
requirements in a given application. For example, if a system requires data to be read every 2 ms with all three
channels monitored, configure the INA3221 with the conversion times for the shunt- and bus-voltage
measurements set to 332 μs.
The INA3221 can also be configured with a different conversion-time setting for the shunt- and bus-voltage
measurements. This approach is common in applications where the bus voltage tends to be relatively stable, and
allows for the time focused on the bus voltage measurement to be reduced relative to the shunt-voltage
measurement. For example, the shunt-voltage conversion time can be set to 4.156 ms with the bus-voltage
conversion time set to 588 μs for a 5-ms update time.
There are trade-offs associated with the conversion-time and averaging-mode settings. The averaging feature
significantly improves the measurement accuracy by effectively filtering the signal. This approach allows the
INA3221 to reduce the amount of noise in the measurement caused by noise coupling into the signal. A greater
number of averages allows the INA3221 to be more effective in reducing the measurement noise component.
The trade-off to this noise reduction is that the averaged value has a longer response time to input-signal
changes. This aspect of the averaging feature is mitigated to some extent with the critical-alert feature that
compares each single conversion to determine if a measured signal (with noise component) has exceeded the
maximum acceptable level.
The selected conversion times also have an impact on measurement accuracy. This effect can seen in
Figure 25. The multiple conversion times shown in Figure 25 illustrate the impact of noise on measurement.
These curves shown do not use averaging. In order to achieve the highest-accuracy measurement possible, use
a combination of the longest allowable conversion times and highest number of averages, based on system
timing requirements.
120
Conversion Time: 140 µs
Voltage (µV)
80
40
Conversion Time: 332 µs
0
í40
Conversion Time: 1.1 ms
í80
í120
0
200
400
600
Number of Conversions
800
1000
Figure 25. Noise Versus Conversion Time
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Device Functional Modes (continued)
8.4.3 Filtering and Input Considerations
Measuring current is often noisy, and such noise can be difficult to define. The INA3221 offers several filtering
options by allowing conversion times and the number of averages to be selected independently in the
Configuration register. The conversion times can be set independently for the shunt- and bus-voltage
measurements as well, for added flexibility in configuring power-supply bus monitoring.
The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. This
architecture has good inherent noise rejection; however, transients that occur at or very close to the samplingrate harmonics can cause problems. These transient signals are at 1 MHz and higher; therefore, the signals are
managed by incorporating filtering at the INA3221 input. High-frequency signals allow for the use of low-value
series resistors on the filter, with negligible effects on measurement accuracy. In general, filtering the INA3221
input is only necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate that are
greater than 1 MHz. Filter using the lowest-possible series resistance (typically 10 Ω or less) and a ceramic
capacitor. Recommended capacitor values are 0.1 μF to 1.0 μF. Figure 26 shows the INA3221 with an additional
filter added at the input.
Power Supply
(0 V to 26 V)
Ch 1
RFILTER
” 10
VIN+2
CFILTER
RFILTER
” 10
VIN
Ch 2
ADC
2
Ch 3
Load 2
CFILTER: 0.1- F to 1- F
Ceramic Capacitor
Figure 26. INA3221 With Input Filtering
The INA3221 inputs are specified to tolerate 26 V across the inputs. However, overload conditions are another
consideration for the INA3221 inputs. For example, a large differential-input scenario might be a short to ground
on the load side of the shunt. This type of event results in the full power-supply voltage applied across the shunt,
if supported by the power supply or energy-storage capacitors. Keep in mind that removing a short to ground
may result in inductive kickbacks that can exceed the 26-V differential and common-mode rating of the INA3221.
Inductive kickback voltages are best controlled by zener-type transient-absorbing devices (commonly called
transzorbs) combined with sufficient energy-storage capacitance.
In applications that do not have large energy-storage electrolytic capacitors on one or both sides of the shunt, an
input overstress condition can result from an excessive dV/dt of the voltage applied to the input. A hard physical
short is the most likely cause of this event, particularly in applications without large electrolytic capacitors
present. This problem occurs because an excessive dV/dt can activate the INA3221 ESD protection in systems
where large currents are available. Testing has demonstrated that the addition of 10-Ω resistors in series with
each INA3221 input sufficiently protects the inputs against this dV/dt failure up to the 26-V device rating.
Selecting these resistors in the range noted has minimal effect on accuracy.
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8.5 Programming
8.5.1 Bus Overview
The INA3221 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are
essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with the SMBus protocol specified
only when a difference between the two systems is discussed. Two I/O lines, the serial clock (SCL) and data
signal line (SDA), connect the INA3221 to the bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.
The bus must be controlled by the master device that generates the SCL, controls the bus access, and
generates start and stop conditions.
To address a specific device, the master initiates a start condition by pulling SDA from a high to a low logic level
while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition.
After all data are transferred, the master generates a stop condition by pulling SDA from low to high while SCL is
high. The INA3221 includes a 28-ms timeout on the interface to prevent locking up the bus.
8.5.1.1 Serial Bus Address
To communicate with the INA3221, the master must first address slave devices with a slave address byte. This
byte consists of seven address bits and a direction bit to indicate whether the intended action is a read or write
operation.
The INA3221 has one address pin, A0. Table 1 describes the pin logic levels for each of the four possible
addresses. The state of the A0 pin is sampled on every bus communication and must be set before any activity
on the interface occurs.
Table 1. Address Pins and Slave Addresses
A0
SLAVE ADDRESS
GND
1000000
VS
1000001
SDA
1000010
SCL
1000011
8.5.1.2 Serial Interface
The INA3221 only operates as a slave device on the I2C bus and SMBus. Bus connections are made using the
open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and
Schmitt triggers to minimize the effects of input spikes and bus noise. While there is spike suppression integrated
into the digital I/O lines, use proper layout to minimize the amount of coupling into the communication lines.
Noise introduction occurs from capacitively coupling signal edges between the two communication lines
themselves, or from other switching noise sources present in the system. Routing traces in parallel with ground
between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the
communication lines. Shield communication lines to reduce the possibility of unintended noise coupling into the
digital I/O lines that could be incorrectly interpreted as start or stop commands.
The INA3221 supports a transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 2.44 MHz)
modes. All data bytes are transmitted MSB first.
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8.5.2 Writing To and Reading From the INA3221
To access a specific INA3221 register, write the appropriate value to the register pointer. See Table 3 for a
complete list of registers and corresponding addresses. The value for the register pointer, as shown in Figure 27,
is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the
INA3221 requires a register pointer value.
1
9
1
9
SCL
SDA
1
0
0
0
0
0
Start By
Master
A0
R/W
D7
D6
D4
D3
D2
D1
D0
ACK By
Device
ACK By
Device
Frame 1: Two-Wire Slave Address Byte(1)
(1)
D5
Stop By
Master
Frame 2: Register Pointer Byte
The value of the Slave Address Byte is determined by the A0 pin setting; see Table 1.
Figure 27. Typical Register Pointer Set
Register writes begin with the first byte transmitted by the master. This byte is the slave address, with the R/W
bit low. The INA3221 then acknowledges receipt of a valid address. The next byte transmitted by the master is
the register address that data are written to. This register address value updates the register pointer to the
desired register. The next two bytes are written to the register addressed by the register pointer. The INA3221
acknowledges receipt of each data byte. The master terminates data transfer by generating a start or stop
condition.
When reading from the INA3221, the last value stored in the register pointer by a write operation determines
which register is read during a read operation. To change the register pointer for a read operation, write a new
value to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit low,
followed by the register pointer byte. No additional data are required. The master then generates a start condition
and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is
transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte
is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master
acknowledges receipt of the data byte. The master terminates data transfer by generating a not-acknowledge
after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are
desired, it is not necessary to continually send the register pointer bytes; the INA3221 retains the register pointer
value until it is changed by the next write operation.
Figure 28 and Figure 29 show the write and read operation timing diagrams, respectively. Note that register
bytes are sent most-significant byte first, followed by the least significant byte.
1
9
1
9
1
9
SCL
SDA
1
Start By
Master
0
0
0
0
0
A0
R/W
D9
ACK By
Device
Frame 1: Two-Wire Slave Address Byte (1)
(1)
D15 D14 D13 D12 D11 D10
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
Device
ACK By
Device
Frame 2: Data MSByte
Stop By
Master
Frame 3: Data LSByte
The value of the slave address byte is determined by the A0 pin setting; see Table 1.
Figure 28. Timing Diagram for Write Word Format
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1
9
1
9
1
9
SCL
SDA
1
0
0
0
0
0
A0 R/W
Start By
Master
D15 D14 D13 D12 D11 D10
ACK By
Device
D9
D8
From
Device
Frame 1: Two-Wire Slave Address Byte(1)
D7
D6
D5
D4
ACK By
Master
D3
D2
D1
From
Device
D0
No ACK By
Master(3)
Stop By
Master
Frame 3: Data LSByte(2)
Frame 2: Data MSByte(2)
(1)
The value of the slave address byte is determined by the A0 pin setting; see Table 1.
(2)
Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated.
See Figure 27.
(3)
The master can also send an ACK.
Figure 29. Timing Diagram for Read Word Format
Figure 30 shows the timing diagram for the SMBus Alert response operation.
1
9
1
9
SCL
SDA
0
0
0
1
Start By
Master
1
0
0
1
R/W
0
0
0
ACK By
Device
Frame 1: SMBus ALERT Response Address Byte
(1)
0
0
A0
0
From
Device
No ACK By
Master
Stop By
Master
Frame 2: Slave Address Byte(1)
The value of the Slave Address Byte is determined by the A0 pin setting; see Table 1.
Figure 30. Timing Diagram for SMBus Alert
8.5.2.1 High-Speed I2C Mode
When the bus is idle, the SDA and SCL lines are pulled high by the pull-up resistors. The master generates a
start condition followed by a valid serial byte with the high-speed (Hs) master code 00001XXX. This transmission
is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA3221 does not
acknowledge the Hs master code, but does recognize it and switches its internal filters to support 2.44-MHz
operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 2.44 MHz are allowed. Instead of using a stop condition, the master uses a repeated start
conditions to secure the bus in Hs mode. A stop condition ends the Hs mode, and switches all internal INA3221
filters to support F/S mode.
Figure 31 shows the bus timing, and Table 2 lists the bus timing definitions.
22
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t(LOW)
tfCL
tr
SCL
t(HDSTA)
t(HDDAT)
t(VDDAT)
t(HIGH)
t(SUSTA)
t(SUSTO)
t(HDSTA)
t(SUDAT)
tfDA
SDA
t(BUF)
P
S
S
P
Figure 31. Bus Timing
Table 2. Bus Timing Definitions (1)
FAST MODE
PARAMETER
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
UNIT
0.4
0.001
2.44
MHz
f(SCL)
SCL operating frequency
0.001
t(BUF)
Bus free time between stop and start conditions
1300
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
600
160
ns
t(SUSTA)
Repeated start condition setup time
600
160
ns
t(SUSTO)
STOP condition setup time
600
160
ns
t(HDDAT)
Data hold time
0
0
t(VDDAT)
Data valid time
t(SUDAT)
Data setup time
100
10
ns
t(LOW)
SCL clock low period
1300
270
ns
t(HIGH)
SCL clock high period
600
60
ns
tfDA
Data fall time
500
150
ns
tfCL
Clock fall time
300
40
ns
Clock rise time
300
40
ns
tr
(1)
1200
Clock rise time for SCLK ≤ 100 kHz
ns
260
1000
ns
ns
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not production tested.
A0 = A1 = 0.
8.5.3 SMBus Alert Response
The INA3221 responds to the SMBus alert response address. The SMBus alert response provides a quick fault
identification for simple slave devices. When an alert occurs, the master broadcasts the alert response slave
address (0001 100) with the R/W bit set high. Following this alert response, any slave devices that generated an
alert identify themselves by acknowledging the alert response, and sending their respective address on the bus.
The alert response can activate several different slave devices simultaneously, similar to the I2C general call. If
more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an
acknowledge, and continues to hold the alert line low until the interrupt is cleared.
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8.6 Register Maps
The INA3221 uses a bank of registers for holding configuration settings, measurement results, minimum and
maximum limits, and status information. Table 3 summarizes the INA3221 registers; see the Functional Block
Diagram section for an illustration of the registers.
8.6.1 Summary of Register Set
Table 3. Summary of Register Set
POINTER
ADDRESS
(Hex)
(1)
24
POWER-ON RESET
REGISTER NAME
DESCRIPTION
BINARY
HEX
TYPE (1)
0
Configuration
All-register reset, shunt and bus voltage ADC conversion times and
averaging, operating mode.
01110001 00100111
7127
R/W
1
Channel-1 Shunt Voltage
Averaged shunt voltage value.
00000000 00000000
0000
R
2
Channel-1 Bus Voltage
Averaged bus voltage value.
00000000 00000000
0000
R
3
Channel-2 Shunt Voltage
Averaged shunt voltage value.
00000000 00000000
0000
R
4
Channel-2 Bus Voltage
Averaged bus voltage value.
00000000 00000000
0000
R
5
Channel-3 Shunt Voltage
Averaged shunt voltage value.
00000000 00000000
0000
R
6
Channel-3 Bus Voltage
Averaged bus voltage value.
00000000 00000000
0000
R
7
Channel-1 Critical Alert
Limit
Contains limit value to compare each conversion value to
determine if the corresponding limit has been exceeded.
01111111 11111000
7FF8
R/W
8
Channel-1 Warning Alert
Limit
Contains limit value to compare to averaged measurement to
determine if the corresponding limit has been exceeded.
01111111 11111000
7FF8
R/W
9
Channel-2 Critical Alert
Limit
Contains limit value to compare each conversion value to
determine if the corresponding limit has been exceeded.
01111111 11111000
7FF8
R/W
A
Channel-2 Warning Alert
Limit
Contains limit value to compare to averaged measurement to
determine if the corresponding limit has been exceeded.
01111111 11111000
7FF8
R/W
B
Channel-3 Critical Alert
Limit
Contains limit value to compare each conversion value to
determine if the corresponding limit has been exceeded.
01111111 11111000
7FF8
R/W
C
Channel-3 Warning Alert
Limit
Contains limit value to compare to averaged measurement to
determine if the corresponding limit has been exceeded.
01111111 11111000
7FF8
R/W
D
Shunt-Voltage Sum
Contains the summed value of the each of the selected shunt
voltage conversions.
00000000 00000000
0000
R
E
Shunt-Voltage Sum Limit
Contains limit value to compare to the Shunt Voltage Sum register
to determine if the corresponding limit has been exceeded.
01111111 11111110
7FFE
R/W
F
Mask/Enable
Alert configuration, alert status indication, summation control and
status.
00000000 00000010
0002
R/W
10
Power-Valid Upper Limit
Contains limit value to compare all bus voltage conversions to
determine if the Power Valid level has been reached.
00100111 00010000
2710
R/W
11
Power-Valid Lower Limit
Contains limit value to compare all bus voltage conversions to
determine if the any voltage rail has dropped below the Power
Valid range.
00100011 00101000
2328
R/W
FE
Manufacturer ID
Contains unique manufacturer identification number.
01010100 01001001
5449
R
FF
Die ID
Contains unique die identification number.
00110010 00100000
3220
R
Type: R = read-only, R/W = read/write.
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8.6.2 Register Descriptions
All 16-bit INA3221 registers are two 8-bit bytes via the I2C interface. Table 4 shows a register map for the INA3221.
Table 4. Register Map
ADDRESS
(Hex)
D15
D14
D13
D12
D11
D10
D9
Configuration
00
RST
CH1en
CH2en
CH3en
AVG2
AVG1
AVG0
Channel-1 Shunt Voltage
01
SIGN
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
Channel-1 Bus Voltage
02
SIGN
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
Channel-2 Shunt Voltage
03
SIGN
SD11
SD10
SD9
SD8
SD7
SD6
SD5
Channel-2 Bus Voltage
04
SIGN
BD11
BD10
BD9
BD8
BD7
BD6
Channel-3 Shunt Voltage
05
SIGN
SD11
SD10
SD9
SD8
SD7
Channel-3 Bus Voltage
06
SIGN
BD11
BD10
BD9
BD8
Channel-1 Critical-Alert
Limit
07
C1L12
C1L11
C1L10
C1L9
Channel-1 Warning-Alert
Limit
08
W1L12
W1L11
W1L10
Channel-2 Critical-Alert
Limit
09
C2L12
C2L11
Channel-2 Warning-Alert
Limit
0A
W2L12
Channel-3 Critical-Alert
Limit
0B
Channel-3 Warning-Alert
Limit
REGISTER
D8
D7
D6
D5
D4
D3
D2
D1
D0
VSHCT2
VSHCT1
VSHCT0
MODE3
MODE2
MODE1
SD3
SD2
SD1
SD0
—
—
—
BD3
BD2
BD1
BD0
—
—
—
SD4
SD3
SD2
SD1
SD0
—
—
—
BD5
BD4
BD3
BD2
BD1
BD0
—
—
—
SD6
SD5
SD4
SD3
SD2
SD1
SD0
—
—
—
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
—
—
—
C1L8
C1L7
C1L6
C1L5
C1L4
C1L3
C1L2
C1L1
C1L0
—
—
—
W1L9
W1L8
W1L7
W1L6
W1L5
W1L4
W1L3
W1L2
W1L1
W1L0
—
—
—
C2L10
C2L9
C2L8
C2L7
C2L6
C2L5
C2L4
C2L3
C2L2
C2L1
C2L0
—
—
—
W2L11
W2L10
W2L9
W2L8
W2L7
W2L6
W2L5
W2L4
W2L3
W2L2
W2L1
W2L0
—
—
—
C3L12
C3L11
C3L10
C3L9
C3L8
C3L7
C3L6
C3L5
C3L4
C3L3
C3L2
C3L1
C3L0
—
—
—
0C
W3L12
W3L11
W3L10
W3L9
W3L8
W3L7
W3L6
W3L5
W3L4
W3L3
W3L2
W3L1
W3L0
—
—
—
Shunt-Voltage Sum
0D
SIGN
SV13
SV12
SV11
SV10
SV9
SV8
SV7
SV6
SV5
SV4
SV3
SV2
SV1
SV0
—
Shunt-Voltage Sum Limit
0E
SIGN
SVL13
SVL12
SVL11
SVL10
SVL9
SVL8
SVL7
SVL6
SVL5
SVL4
SVL3
SVL2
SVL1
SVL0
—
Mask/Enable
0F
—
SCC1
SCC2
SCC3
WEN
CEN
CF1
CF2
CF3
SF
WF1
WF2
WF3
PVF
TCF
CVRF
Power-Valid Upper Limit
10
PVU12
PVU11
PVU10
PVU9
PVU8
PVU7
PVU6
PVU5
PVU4
PVU3
PVU2
PVU1
PVU0
—
—
—
Power-Valid Lower Limit
11
PVL12
PVL11
PVL10
PVL9
PVL8
PVL7
PVL6
PVL5
PVL4
PVL3
PVL2
PVL1
PVL0
—
—
—
Manufacturer ID
FE
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
Die ID
FF
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
VBUSCT2 VBUSCT1 VBUSCT0
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8.6.2.1 Configuration Register (address = 00h) [reset = 7127h]
The Configuration register settings control the operating modes for the shunt- and bus-voltage measurements for
the three input channels. This register controls the conversion time settings for both the shunt- and bus-voltage
measurements and the averaging mode used. The Configuration register is used to independently enable or
disable each channel, as well as select the operating mode that controls which signals are selected to be
measured.
This register can be read from at any time without impacting or affecting either device settings or conversions in
progress. Writing to this register halts any conversion in progress until the write sequence is completed, resulting
in a new conversion starting, based on the new Configuration register contents. This architecture prevents any
uncertainty in the conditions used for the next completed conversion.
Figure 32. Configuration Register
15
14
13
12
11
10
9
RST
CH1en CH2en CH3en
AVG2
AVG1
AVG0
RW-0
RW-1
RW-0
RW-0
RW-0
RW-1
RW-1
8
VBUS
CT2
RW-1
7
VBUS
CT1
RW-0
6
VBUS
CT0
RW-0
5
VSH
CT2
RW-1
4
VSH
CT1
RW-0
3
VSH
CT0
RW-0
2
MODE
3
RW-1
1
MODE
2
RW-1
0
MODE
1
RW-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Configuration Register Field Descriptions
26
Bit
Field
Type
Reset
Description
15
RST
R/W
0h
Reset bit. Set this bit = 1 to generate a system reset that is the
same as a power-on reset (POR). This bit resets all registers to
default values and self-clears.
14
CH1en
R/W
7h
13
CH2en
12
CH3en
Channel enable mode. These bits allow each channel to be
independently enabled or disabled.
0 = Channel disable
1 = Channel enable (default)
11-9
AVG2-0
R/W
0h
Averaging mode. These bits set the number of samples that are
collected and averaged together.
000 = 1 (default)
001 = 4
010 = 16
011 = 64
100 = 128
101 = 256
110 = 512
111 = 1024
8-6
VBUSCT2-0
R/W
4h
Bus-voltage conversion time. These bits set the conversion time
for the bus-voltage measurement.
000 = 140 μs
001 = 204 μs
010 = 332 μs
011 = 588 μs
100 = 1.1 ms (default)
101 = 2.116 ms
110 = 4.156 ms
111 = 8.244 ms
5-3
VSHCT2-0
R/W
4h
Shunt-voltage conversion time. These bits set the conversion
time for the shunt-voltage measurement.
The conversion-time bit settings for VSHCT2-0 are the same as
VBUSCT2-0 (bits 8-6) listed in the previous row.
2-0
MODE3-1
R/W
7h
Operating mode. These bits select continuous, single-shot
(triggered), or power-down mode of operation. These bits default
to continuous shunt and bus mode.
000 = Power-down
001 = Shunt voltage, single-shot (triggered)
010 = Bus voltage, single-shot (triggered)
011 = Shunt and bus, single-shot (triggered)
100 = Power-down
101 = Shunt voltage, continuous
110 = Bus voltage, continuous
111 = Shunt and bus, continuous (default)
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8.6.2.2 Channel-1 Shunt-Voltage Register (address = 01h), [reset = 00h]
This register contains the averaged shunt-voltage measurement for channel 1. This register stores the current
shunt-voltage reading, VSHUNT, for channel 1. Negative numbers are represented in twos complement format.
Generate the twos complement of a negative number by complementing the absolute value binary number and
adding 1. Extend the sign, denoting a negative number by setting MSB = 1.
Full-scale range = 163.8 mV (decimal = 7FF8); LSB (SD0): 40 μV.
Example: For a value of VSHUNT = –80 mV:
1. Take the absolute value: 80 mV
2. Translate this number to a whole decimal number (80 mV / 40 µV) = 2000
3. Convert this number to binary = 011 1110 1000 0_ _ _ (last three bits are set to 0)
4. Complement the binary result = 100 0001 0111 1111
5. Add 1 to the complement to create the twos complement result = 100 0001 1000 0000
6. Extend the sign and create the 16-bit word: 1100 0001 1000 0000 = C180h
Figure 33. Channel-1 Shunt-Voltage Register
15
SIGN
R-0
14
SD11
R-0
13
SD10
R-0
12
SD9
R-0
11
SD8
R-0
10
SD7
R-0
9
SD6
R-0
8
SD5
R-0
7
SD4
R-0
6
SD3
R-0
5
SD2
R-0
4
SD1
R-0
3
SD0
R-0
2
—
R-0
1
—
R-0
0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Channel-1 Shunt-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
SD11-0
R
0h
Channel-1 shunt-voltage data bits
2-0
Reserved
R
0h
Reserved
8.6.2.3 Channel-1 Bus-Voltage Register (address = 02h) [reset = 00h]
This register stores the bus voltage reading, VBUS, for channel 1. Full-scale range = 32.76 V (decimal = 7FF8);
LSB (BD0) = 8 mV. Although the input range is 26 V, the full-scale range of the ADC scaling is 32.76 V. Do not
apply more than 26 V.
Figure 34. Channel-1 Bus-Voltage Register
15
SIGN
R-0
14
BD11
R-0
13
BD10
R-0
12
BD9
R-0
11
BD8
R-0
10
BD7
R-0
9
BD6
R-0
8
BD5
R-0
7
BD4
R-0
6
BD3
R-0
5
BD2
R-0
4
BD1
R-0
3
BD0
R-0
2
—
R-0
1
—
R-0
0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Channel-1 Bus-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format.
14-3
BD11-0
R
0h
Channel-1 bus-voltage data bits
2-0
Reserved
R
0h
Reserved
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8.6.2.4 Channel-2 Shunt-Voltage Register (address = 03h) [reset = 00h]
This register contains the averaged shunt voltage measurement for channel 2. Full-scale range = 163.8 mV
(decimal = 7FF8); LSB (SD0): 40 μV. Although the input range is 26 V, the full-scale range of the ADC scaling is
32.76 V. Do not apply more than 26 V.
Figure 35. Channel-2 Shunt-Voltage Register
15
SIGN
R-0
14
SD11
R-0
13
SD10
R-0
12
SD9
R-0
11
SD8
R-0
10
SD7
R-0
9
SD6
R-0
8
SD5
R-0
7
SD4
R-0
6
SD3
R-0
5
SD2
R-0
4
SD1
R-0
3
SD0
R-0
2
—
R-0
1
—
R-0
0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Channel-2 Shunt-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
SD11-0
R
0h
Channel-2 shunt-voltage data bits
2-0
Reserved
R
0h
Reserved
8.6.2.5 Channel-2 Bus-Voltage Register (address = 04h) [reset = 00h]
This register stores the bus voltage reading, VBUS, for channel 2. Full-scale range = 32.76 V (decimal = 7FF8);
LSB (BD0) = 8 mV. Although the input range is 26 V, the full-scale range of the ADC scaling is 32.76 V. Do not
apply more than 26 V.
Figure 36. Channel-2 Bus-Voltage Register
15
SIGN
R-0
14
BD11
R-0
13
BD10
R-0
12
BD9
R-0
11
BD8
R-0
10
BD7
R-0
9
BD6
R-0
8
BD5
R-0
7
BD4
R-0
6
BD3
R-0
5
BD2
R-0
4
BD1
R-0
3
BD0
R-0
2
—
R-0
1
—
R-0
0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Channel-2 Bus-Voltage Register Field Descriptions
28
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
BD11-0
R
0h
Channel-2 bus-voltage data bits
2-0
Reserved
R
0h
Reserved
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8.6.2.6 Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
This register contains the averaged shunt voltage measurement for channel 3. Full-scale range = 163.8 mV
(decimal = 7FF8); LSB (SD0): 40 μV.
Figure 37. Channel-3 Shunt-Voltage Register
15
SIGN
R-0
14
SD11
R-0
13
SD10
R-0
12
SD9
R-0
11
SD8
R-0
10
SD7
R-0
9
SD6
R-0
8
SD5
R-0
7
SD4
R-0
6
SD3
R-0
5
SD2
R-0
4
SD1
R-0
3
SD0
R-0
2
—
R-0
1
—
R-0
0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. Channel-3 Shunt-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
SD11-0
R
0h
Channel-3 shunt-voltage data bits
2-0
Reserved
R
0h
Reserved
8.6.2.7 Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
This register stores the bus voltage reading, VBUS, for channel 3. Full-scale range = 32.76 V (decimal = 7FF8);
LSB (BD0) = 8 mV. Although the input range is 26 V, the full-scale range of the ADC scaling is 32.76 V. Do not
apply more than 26 V.
Figure 38. Channel-3 Bus-Voltage Register
15
SIGN
R-0
14
BD11
R-0
13
BD10
R-0
12
BD9
R-0
11
BD8
R-0
10
BD7
R-0
9
BD6
R-0
8
BD5
R-0
7
BD4
R-0
6
BD3
R-0
5
BD2
R-0
4
BD1
R-0
3
BD0
R-0
2
—
R-0
1
—
R-0
0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. Channel-3 Bus-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
BD11-0
R
0h
Channel-3 bus-voltage data bits
2-0
Reserved
R
0h
Reserved
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8.6.2.8 Channel-1 Critical-Alert Limit Register (address = 07h) [reset = 7FF8h]
This register contains the value used to compare to each shunt voltage conversion on channel 1 to detect fast
overcurrent events.
Figure 39. Channel-1 Critical-Alert Limit Register
15
14
13
C1L12 C1L11 C1L10
RW-0 RW-1 RW-1
12
C1L9
RW-1
11
C1L8
RW-1
10
C1L7
RW-1
9
C1L6
RW-1
8
C1L5
RW-1
7
C1L4
RW-1
6
C1L3
RW-1
5
C1L2
RW-1
4
C1L1
RW-1
3
C1L0
RW-1
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. Channel-1 Critical-Alert Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15-3
C1L12-0
R/W
FFFh
Channel-1 critical-alert-limit data bits
2-0
Reserved
R/W
0h
Reserved
8.6.2.9 Warning-Alert Channel-1 Limit Register (address = 08h) [reset = 7FF8h]
This register contains the value used to compare to the averaged shunt voltage value of channel 1 to detect a
longer duration overcurrent event.
Figure 40. Channel-1 Warning-Alert Limit Register
15
14
13
W1L12 W1L11 W1L10
RW-0 RW-1 RW-1
12
W1L9
RW-1
11
W1L8
RW-1
10
W1L7
RW-1
9
W1L6
RW-1
8
W1L5
RW-1
7
W1L4
RW-1
6
W1L3
RW-1
5
W1L2
RW-1
4
W1L1
RW-1
3
W1L0
RW-1
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Channel-1 Warning-Alert Limit Register Field Descriptions
Field
Type
Reset
Description
15-3
Bit
W1L12-0
R/W
FFFh
Channel-1 warning-alert-limit data bits
2-0
Reserved
R/W
0h
Reserved
8.6.2.10 Channel-2 Critical-Alert Limit Register (address = 09h) [reset = 7FF8h]
This register contains the value used to compare to each shunt voltage conversion on channel 2 to detect fast
overcurrent events.
Figure 41. Channel-2 Critical-Alert Limit Register
15
14
13
C2L12 C2L11 C2L10
RW-0 RW-1 RW-1
12
C2L9
RW-1
11
C2L8
RW-1
10
C2L7
RW-1
9
C2L6
RW-1
8
C2L5
RW-1
7
C2L4
RW-1
6
C2L3
RW-1
5
C2L2
RW-1
4
C2L1
RW-1
3
C2L0
RW-1
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Channel-2 Critical-Alert Limit Register Field Descriptions
Bit
30
Field
Type
Reset
Description
15-3
C2L12-0
R/W
FFFh
Channel-2 critical-alert-limit data bits
2-0
Reserved
R/W
0h
Reserved
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8.6.2.11 Channel-2 Warning-Alert Limit Register (address = 0Ah) [reset = 7FF8h]
This register contains the value used to compare to the averaged shunt voltage value of channel 2 to detect a
longer duration overcurrent event.
Figure 42. Channel-2 Warning-Alert Limit Register
15
14
13
W2L12 W2L11 W2L10
RW-0 RW-1 RW-1
12
W2L9
RW-1
11
W2L8
RW-1
10
W2L7
RW-1
9
W2L6
RW-1
8
W2L5
RW-1
7
W2L4
RW-1
6
W2L3
RW-1
5
W2L2
RW-1
4
W2L1
RW-1
3
W2L0
RW-1
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Channel-2 Warning-Alert Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15-3
W2L12-0
R/W
FFFh
Channel-2 warning-alert-limit data bits
2-0
Reserved
R/W
0h
Reserved
8.6.2.12 Channel-3 Critical-Alert Limit Register (address = 0Bh) [reset = 7FF8h]
This register contains the value used to compare to each shunt voltage conversion on channel 3 to detect fast
overcurrent events.
Figure 43. Channel-3 Critical-Alert Limit Register
15
14
13
C3L12 C3L11 C3L10
RW-0 RW-1 RW-1
12
C3L9
RW-1
11
C3L8
RW-1
10
C3L7
RW-1
9
C3L6
RW-1
8
C3L5
RW-1
7
C3L4
RW-1
6
C3L3
RW-1
5
C3L2
RW-1
4
C3L1
RW-1
3
C3L0
RW-1
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Channel-3 Critical-Alert Limit Register Field Descriptions
Field
Type
Reset
Description
15-3
Bit
C3L12-0
R/W
FFFh
Channel-3 critical-alert-limit data bits
2-0
Reserved
R/W
0h
Reserved
8.6.2.13 Channel-3 Warning-Alert Limit Register (address = 0Ch) [reset = 7FF8h]
This register contains the value used to compare to the averaged shunt voltage value of channel 3 to detect a
longer duration overcurrent event.
Figure 44. Channel-3 Warning-Alert Limit Register
15
14
13
W3L12 W3L11 W3L10
RW-0 RW-1 RW-1
12
W3L9
RW-1
11
W3L8
RW-1
10
W3L7
RW-1
9
W3L6
RW-1
8
W3L5
RW-1
7
W3L4
RW-1
6
W3L3
RW-1
5
W3L2
RW-1
4
W3L1
RW-1
3
W3L0
RW-1
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Channel-3 Warning-Alert Limit Register Field Descriptions
Field
Type
Reset
Description
15-3
Bit
W3L12-0
R/W
FFFh
Channel-3 warning-alert limit data bits
2-0
Reserved
R/W
0h
Reserved
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8.6.2.14 Shunt-Voltage Sum Register (address = 0Dh) [reset = 00h]
This register contains the sum of the single conversion shunt voltages of the selected channels based on the
summation control bits 12, 13, and 14 in the Mask/Enable register.
This register is updated with the most recent sum following each complete cycle of all selected channels. The
Shunt-Voltage Sum register LSB value is 40 µV.
Figure 45. Shunt-Voltage Sum Register
15
SIGN
R-0
14
SV13
R-0
13
SV12
R-0
12
SV11
R-0
11
SV10
R-0
10
SV9
R-0
9
SV8
R-0
8
SV7
R-0
7
SV6
R-0
6
SV5
R-0
5
SV4
R-0
4
SV3
R-0
3
SV2
R-0
2
SV1
R-0
1
SV0
R-0
0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Shunt-Voltage Sum Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
SV13-0
R
0h
Shunt-voltage sum data bits
Reserved
R
0h
Reserved
14-1
0
8.6.2.15 Shunt-Voltage Sum-Limit Register (address = 0Eh) [reset = 7FFEh]
This register contains the value that is compared to the Shunt-Voltage Sum register value following each
completed cycle of all selected channels to detect for system overcurrent events. The Shunt-Voltage Sum-Limit
register LSB value is 40 µV.
Figure 46. Shunt-Voltage Sum-Limit Register
15
SIGN
RW-0
14
13
12
11
SVL13 SVL12 SVL11 SVL10
RW-1 RW-1 RW-1 RW-1
10
SVL9
RW-1
9
SVL8
RW-1
8
SVL7
RW-1
7
SVL6
RW-1
6
SVL5
RW-1
5
SVL4
RW-1
4
SVL3
RW-1
3
SVL2
RW-1
2
SVL1
RW-1
1
SVL0
RW-1
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Shunt-Voltage Sum-Limit Register Field Descriptions
32
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-1
SVL13-0
R
0h
Shunt-voltage sum-limit data bits
0
Reserved
R
0h
Reserved
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8.6.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h]
This register selects which function is enabled to control the Critical alert and Warning alert pins, and how each
warning alert responds to the corresponding channel. Read the Mask/Enable register to clear any flag results
present. Writing to this register does not clear the flag bit status. To make sure that there is no uncertainty in the
warning function setting that resulted in a flag bit being set, the Mask/Enable register should be read from to
clear the flag bit status before changing the warning function setting.
Figure 47. Mask/Enable Register
15
—
RW-0
14
SCC1
RW-0
13
SCC2
RW-0
12
SCC3
RW-0
11
WEN
RW-0
10
CEN
RW-0
9
CF1
RW-0
8
CF2
RW-0
7
CF3
RW-0
6
SF
RW-0
5
WF1
RW-0
4
WF2
RW-0
3
WF3
RW-0
2
PVF
RW-0
1
TCF
RW-1
0
CVRF
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Mask/Enable Register Field Descriptions
Bit
Field
Type
Reset
Description
15
Reserved
R/W
0h
Reserved
SCC1-3
R/W
0h
Summation channel control. These bits determine which shunt voltage measurement
channels are enabled to fill the Shunt-Voltage Sum register. The selection of these bits
does not impact the individual channel enable or disable status, or the corresponding
channel measurements. The corresponding bit is used to select if the channel is used
to fill the Shunt-Voltage Sum register.
0 = Disabled (default)
1 = Enabled
11
WEN
R/W
0h
Warning alert latch enable. These bits configure the latching feature of the Warning
alert pin.
0 = Transparent (default)
1 = Latch enabled
10
CEN
R/W
0h
Critical alert latch enable. These bits configure the latching feature of the Critical alert
pin.
0 = Transparent (default)
1 = Latch enabled
9-7
CF1-3
R/W
0h
Critical-alert flag indicator. These bits are asserted if the corresponding channel
measurement has exceeded the critical alert limit resulting in the Critical alert pin being
asserted. Read these bits to determine which channel caused the critical alert. The
critical alert flag bits are cleared when the Mask/Enable register is read back.
SF
R/W
0h
Summation-alert flag indicator. This bit is asserted if the Shunt Voltage Sum register
exceeds the Shunt Voltage Sum Limit register. If the summation alert flag is asserted,
the Critical alert pin is also asserted. The Summation Alert Flag bit is cleared when the
Mask/Enable register is read back.
WF1-3
R/W
0h
Warning-alert flag indicator. These bits are asserted if the corresponding channel
averaged measurement has exceeded the warning alert limit, resulting in the Warning
alert pin being asserted. Read these bits to determine which channel caused the
warning alert. The Warning Alert Flag bits clear when the Mask/Enable register is read
back.
2
PVF
R/W
0h
Power-valid-alert flag indicator. This bit can be used to be able to determine if the
power valid (PV) alert pin has been asserted through software rather than hardware.
The bit setting corresponds to the status of the PV pin. This bit does not clear until the
condition that caused the alert is removed, and the PV pin has cleared.
1
TCF
R/W
11h
Timing-control-alert flag indicator. Use this bit to determine if the timing control (TC)
alert pin has been asserted through software rather than hardware. The bit setting
corresponds to the status of the TC pin. This bit does not clear after it has been
asserted unless the power is recycled or a software reset is issued. The default state
for the timing control alert flag is high.
0
CVRF
R/W
0h
Conversion-ready flag. Although the INA3221 can be read at any time, and the data
from the last conversion are available, the conversion ready bit is provided to help
coordinate single-shot conversions. The conversion bit is set after all conversions are
complete. Conversion ready clears under the following conditions:
1. Writing the Configuration register (except for power-down or disable-mode
selections).
2. Reading the Mask/Enable register.
14-12
6
5-3
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8.6.2.17 Power-Valid Upper-Limit Register (address = 10h) [reset = 2710h]
This register contains the value used to determine if the power-valid conditions are met. The power-valid
condition is reached when all bus-voltage channels exceed the value set in this limit register. When the powervalid condition is met, the PV alert pin asserts high to indicate that the INA3221 has confirmed all bus voltage
channels are above the power-valid upper-limit value. In order for the power-valid conditions to be monitored, the
bus measurements must be enabled through one of the corresponding MODE bits set in the Configuration
register. The power-valid upper-limit LSB value is 8 mV. Power-on reset value is 2710h = 10.000 V.
Figure 48. Power-Valid Upper-Limit Register
15
SIGN
RW-0
14
13
PVU11 PVU10
RW-0 RW-1
12
PVU9
RW-0
11
PVU8
RW-0
10
PVU7
RW-1
9
PVU6
RW-1
8
PVU5
RW-1
7
PVU4
RW-0
6
PVU3
RW-0
5
PVU2
RW-0
4
PVU1
RW-1
3
PVU0
RW-0
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. Power-Valid Upper-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R/W
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
PVU11-0
R/W
4E2h
Power-valid upper-limit data bits
2-0
Reserved
R/W
0h
Reserved
8.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
This register contains the value used to determine if any of the bus-voltage channels drops below the power-valid
lower-limit when the power-valid conditions are met. This limit contains the value used to compare all buschannel readings to make sure that all channels remain above the power-valid lower-limit, thus maintaining the
power-valid condition. If any bus-voltage channel drops below the power-valid lower-limit, the PV alert pin pulls
low to indicate that the INA3221 detects a bus voltage reading below the power-valid lower-limit. In order for the
power-valid condition to be monitored, the bus measurements must be enabled through the mode (MODE3-1)
bits set in the Configuration register. The power-valid lower-limit LSB value is 8 mV. Power-on reset value is
2328h = 9.000 V.
Figure 49. Power-Valid Lower-Limit Register
15
SIGN
RW-0
14
13
PVL11 PVL10
RW-0 RW-1
12
PVL9
RW-0
11
PVL8
RW-0
10
PVL7
RW-0
9
PVL6
RW-1
8
PVL5
RW-1
7
PVL4
RW-0
6
PVL3
RW-0
5
PVL2
RW-1
4
PVL1
RW-0
3
PVL0
RW-1
2
—
RW-0
1
—
RW-0
0
—
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Power-Valid Lower-Limit Register Field Descriptions
34
Bit
Field
Type
Reset
Description
15
SIGN
R/W
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
PVL11-0
R/W
465h
Power-valid lower-limit data bits
2-0
Reserved
R/W
0h
Reserved
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8.6.2.19 Manufacturer ID Register (address = FEh) [reset = 5449h]
This register contains a factory-programmable identification value that identifies this device as being
manufactured by Texas Instruments. This register distinguishes this device from other devices that are on the
same I2C bus. The contents of this register are 5449h, or TI in ASCII.
Figure 50. Manufacturer ID Register
15
D15
R-0
14
D14
R-1
13
D13
R-0
12
D12
R-1
11
D11
R-0
10
D10
R-1
9
D9
R-0
8
D8
R-0
7
D7
R-0
6
D6
R-1
5
D5
R-0
4
D4
R-0
3
D3
R-1
2
D2
R-0
1
D1
R-0
0
D0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Manufacturer ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
D15-0
R
5449h
Manufacturer ID bits
8.6.2.20 Die ID Register (address = FFh) [reset = 3220]
This register contains a factory-programmable identification value that identifies this device as an INA3221. This
register distinguishes this device from other devices that are on the same I2C bus. The Die ID for the INA3221 is
3220h.
Figure 51. Die ID Register
15
D15
R-0
14
D14
R-0
13
D13
R-1
12
D12
R-1
11
D11
R-0
10
D10
R-0
9
D9
R-1
8
D8
R-0
7
D7
R-0
6
D6
R-0
5
D5
R-1
4
D4
R-0
3
D3
R-0
2
D2
R-0
1
D1
R-0
0
D0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Die ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
D15-0
R
3220h
Die ID bits
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
INA3221 is a three-channel current and bus voltage monitor with I2C/SMBUS-compatible interface. It features
programmable conversion times and averaging modes and offers both critical and warning alerts to detect
multiple programmable out-of-range conditions for each channel.
9.2
Typical Application
The INA3221 measures the voltage developed across a current-sensing resistor when current passes through it.
The device also measures the bus supply voltage at the IN- pin. Multiple monitoring functions are supported
using four alert pins: Critical, Warning, PV, and TC. Programmable thresholds make sure operation is within
desired operating conditions. This design illustrates the ability of the Critical alert pin to respond to a set
threshold.
Figure 52 illustrates a typical INA3221 application circuit using all three channels. For best performance, use a
0.1-μF ceramic capacitor for power-supply bypassing, placed as close as possible to the supply and ground pins.
The digital pins (SCL, SDA, Critical, Warning, TC) are connected to supply through pull-up resistors. The power
valid (PV) alert pin is connected to the VPU pin through a pull-up resistor to enable power-valid monitoring.
Power Supply
(0 V to 26 V)
CBYPASS
0.1 µF
Load 1
VIN+1
VS (Supply
Voltage)
VIN±1
Power Supply
(0 V to 26 V)
10 k
SDA
CH 1
VIN+2
Bus
Voltages 1-3
CH 2
Shunt
Voltages 1-3
ADC
VIN±2
Critical Limit
Alerts 1-3
CH 3
Load 2
Shunt Voltage
Sum Alerts
I2Cand
SMBusCompatible
Interface
SCL
A0
VPU
VS
10 k
VPU
Power Valid (PV)
Critical
Warning
Timing Control (TC)
GND
VIN+3
Power Supply
(0 V to 26 V)
VIN±3
Load 3
Figure 52. INA3221 as an Overcurrent Sensor
36
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the input parameters shown in Table 25. All other register settings are default.
Table 25. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Supply voltage, VS
5V
Pull-up resistors
10 kΩ
Input range
–163.84 to +163.8
Enabled channel
CH1
Operating mode
Shunt voltage, continuous
Average setting
1
Critical alert limit
80 mV
Critical Alert Limit register setting
7D0h
9.2.2 Detailed Design Procedure
This design shows two shunt voltage conversion times in order to demonstrate the difference in the alert
response times. This design generates a critical-alert response when the input voltage exceeds 80 mV on
channel 1. See Table 25 for all design parameters.
For the first example the shunt voltage conversion time is set to 1.1 ms. When the input signal exceeds 80 mV,
the Critical alert pin pulls low after the conversion cycle completes, indicating an overcurrent condition, as shown
in Figure 53.
For the second example, the conversion time is set to 588 µs, and the response is shown in Figure 54.
9.2.3 Application Curves
Critical Alert
(2 V/div)
CRITICAL ALERT
INPUT
LIMIT
Input/Limit
(50 mV/div)
CRITICAL ALERT
INPUT
LIMIT
Input/Limit
(50 mV/div)
Critical Alert
(2 V/div)
Figure 53 shows the Critical alert pin response to a shunt voltage overlimit of 80 mV for a conversion time of 1.1
ms. Figure 54 shows the response for the same limit, but with the conversion time reduced to 588 µs.
Time (200 Ps/div)
Time (100 Ps/div)
Configuration register = 4125h,
conversion time = 588 µs
Configuration register = 40DDh,
conversion time = 588 µs
Figure 53. Critical Alert Response for 1.1-ms Conversion
Time
Figure 54. Critical Alert Response for 588-µs Conversion
Time
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Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: INA3221
37
INA3221
SBOS576B – MAY 2012 – REVISED MARCH 2016
www.ti.com
10 Power Supply Recommendations
The input circuitry of the device can accurately measure signals on common-mode voltages beyond its power
supply voltage, VS. For example, the voltage applied to the VS power supply terminal can be 5 V, whereas the
load power-supply voltage being monitored (the common-mode voltage) on any one of the three channels can be
as high as 26 V. Note also that the device can withstand the full 0-V to 26-V range at the input terminals,
regardless of whether the device has power applied or not. Place the required power-supply bypass capacitors
as close as possible to the supply and ground terminals of the device to ensure stability. A typical value for this
supply bypass capacitor is 0.1 μF. Applications with noisy or high-impedance power supplies may require
additional decoupling capacitors to reject power-supply noise.
11 Layout
11.1 Layout Guidelines
Connect the input pins (IN+ and IN–) of all the used channels to the sensing resistor using a Kelvin connection or
a 4-wire connection. These connection techniques ensure that only the current-sensing resistor impedance is
detected between the input pins. Poor routing of the current-sensing resistor commonly results in additional
resistance present between the input pins. Given the very low ohmic value of the current-sensing resistor, any
additional high-current carrying impedance causes significant measurement errors. Place the power-supply
bypass capacitor as close as possible to the supply and ground pins.
To Load
To Bus Power Supply
11.2 Layout Example
Timing Control Output
IN 1
GND
PV
VS
Critical
Warning
IN+3
SDA
IN+1
SCL
To Bus Power Supply
TC
IN 2
VPU
To Bus Power
Supply
IN 3
A0
Supply
Bypass
Capacitor
IN+2
Connect to
bus powersupply rail
To Load
Connect
to VPU
Critical
Output
To Load
Via to Ground Plane
I2C- and SMBUSCompatible Interface
Via to Power Plane
Warning Output
Figure 55. Layout Example
38
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Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: INA3221
INA3221
www.ti.com
SBOS576B – MAY 2012 – REVISED MARCH 2016
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
•
For INA3221 evaluation module (EVM), go to www.ti.com/tool/INA3221EVM
12.2 Documentation Support
12.2.1 Related Documentation
•
INA3221EVM User Guide, SBOU126
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: INA3221
39
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA3221AIRGVR
ACTIVE
VQFN
RGV
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
3221
INA3221AIRGVT
ACTIVE
VQFN
RGV
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA
3221
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2017
OTHER QUALIFIED VERSIONS OF INA3221 :
• Automotive: INA3221-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
INA3221AIRGVR
VQFN
RGV
16
2500
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
INA3221AIRGVT
VQFN
RGV
16
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA3221AIRGVR
VQFN
RGV
16
2500
367.0
367.0
35.0
INA3221AIRGVT
VQFN
RGV
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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