Texas Instruments | OPA55x High-Voltage, High-Current Operational Amplifiers (Rev. B) | Datasheet | Texas Instruments OPA55x High-Voltage, High-Current Operational Amplifiers (Rev. B) Datasheet

Texas Instruments OPA55x High-Voltage, High-Current Operational Amplifiers (Rev. B) Datasheet
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OPA551, OPA552
SBOS100B – JULY 1999 – REVISED JANUARY 2016
OPA55x High-Voltage, High-Current Operational Amplifiers
1 Features
3 Description
•
•
•
•
The OPA551x devices are low-cost operational
amplifiers with high-voltage (60-V) and high-current
(200-mA) capability.
1
•
•
•
•
•
Wide Supply Range: ±4 V to ±30 V
High Output Current: 200 mA Continuous
Low Noise: 14 nV/√Hz
Fully Protected:
– Thermal Shutdown
– Output Current-Limited
Thermal Shutdown Indicator
Wide Output Swing: 2 V from Rail
Fast Slew Rate:
– OPA551: 15 V/µs
– OPA552: 24 V/µs
Wide Bandwidth:
– OPA551: 3 MHz
– OPA552: 12 MHz
Packages: PDIP-8, SOIC-8, or DDPAK/TO-263-7
The OPA551 is unity-gain stable and features high
slew rate (15 V/µs) and wide bandwidth (3 MHz). The
OPA552 is optimized for gains of 5 or greater, and
offers higher speed with a slew rate of 24 V/µs and a
bandwidth of 12 MHz. Both devices are suitable for
telephony, audio, servo, and test applications.
These laser-trimmed, monolithic integrated circuits
provide excellent low-level accuracy along with high
output swing. High performance is maintained as the
amplifier swings to its specified limits.
The OPA55x devices are internally protected against
overtemperature conditions and current overloads.
The thermal shutdown indicator flag provides a
current output to alert the user when thermal
shutdown has occurred.
The OPA55x devices are available in PDIP-8 and
SOIC-8 packages, as well as a DDPAK-7/TO-263
surface-mount plastic power package. They are
specified for operation over the extended industrial
temperature range, –40°C to +125°C.
2 Applications
•
•
•
•
•
Telephony
Test Equipment
Audio Amplifiers
Transducer Excitation
Servo Drivers
Device Information(1)
PART NUMBER
OPA55x
PACKAGE
BODY SIZE (NOM)
PDIP (8)
9.81 mm × 6.35 mm
SOIC (8)
4.9 mm × 3.91 mm
DDPAK/TO-263 (7)
10.1 mm × 8.99 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Functional Diagram
V+
V±IN
±
OPA551
V+IN
VO
+
Flag
V±
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA551, OPA552
SBOS100B – JULY 1999 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = ±30 V.......................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9
Power Supply Recommendations...................... 17
9.1 Power Supplies ....................................................... 17
10 Layout................................................................... 18
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
Safe Operating Area .............................................
Heat Sinking .........................................................
18
18
18
19
20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2003) to Revision B
Page
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Changed package references throughout document: SO-8 to SOIC-8 and DDPAK-7 to DDPAK-7/TO-263 ....................... 1
•
Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................. 4
•
Deleted charged-device model (CDM) specification from ESD Ratings table ...................................................................... 4
2
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SBOS100B – JULY 1999 – REVISED JANUARY 2016
5 Pin Configuration and Functions
OPA551, OPA552 P Package
8-Pin PDIP
Top View
NC
1
8
Flag
–In
2
7
V+
+In
3
6
Out
V–
4
5
NC
OPA551, OPA552 D Package
8-Pin SOIC
Top View
V–
1
8
Flag
–In
2
7
V+
+In
3
6
Out
V–
4
5
V–
OPA551, OPA552 KTW Package
7-Pin DDPAK/TO-263 Surface-Mount
Top View
1 2 3 4 5 6 7
+In NC V+ Flag
–In V– Out
NOTE: Tab is connected to V– supply.
Pin Functions
PIN
SOIC
PDIP
DDPAK/
TO-263
I/O
Flag
8
8
7
O
Thermal shutdown indicator
+IN
3
3
1
I
Noninverting input
Inverting input
NAME
DESCRIPTION
–IN
2
2
2
I
NC
—
1, 5
3
—
No internal connection (can be left floating)
Out
6
6
6
O
Output
Tab
—
—
Tab
—
Connect to V– supply
V+
7
7
5
—
Positive (highest) power supply
V–
1, 4, 5
4
4
—
Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply, VS = (V+) to (V–)
Input voltage range, VIN
(V–) – 0.5
Output
UNIT
60
V
(V+) + 0.5
V
See SOA Curve (Safe Operating Area)
Operating temperature, TA
–55
Junction temperature, TJ
Storage temperature, Tstg
(1)
MAX
–65
125
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±3000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS
Supply voltage
Specified temperature
MIN
MAX
8 (±4)
60 (±30)
UNIT
V
–40
125
°C
6.4 Thermal Information
OPA551, OPA552
D
(SOIC)
P
(PDIP)
KTW
(DDPAK/TO-263)
8 PINS
8 PINS
7 PINS
96.7
44.1
22.7
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
38.7
31.8
34.7
°C/W
RθJB
Junction-to-board thermal resistance
38.2
21.4
7.7
°C/W
ψJT
Junction-to-top characterization parameter
3.7
9.1
3.3
°C/W
ψJB
Junction-to-board characterization parameter
37.5
21.2
7.7
°C/W
—
—
0.6
°C/W
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1)
4
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: VS = ±30 V
At TJ = 25°C (1), RL = 3 kΩ connected to ground, and VOUT = 0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1
±3
UNIT
OFFSET VOLTAGE
VCM = 0 V, IO = 0 mA
VOS
Input offset voltage
dVOS /dT
Input offset voltage vs temperature
TJ = –40°C to 125°C
±7
PSRR
Input offset voltage vs power supply
VS = ±4 V to ±30 V, VCM = 0 V
10
30
±20
±100
pA
±3
±100
pA
TJ = –40°C to 125°C
mV
±5
µV/°C
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
NOISE
en
Input voltage noise density
f = 1 kHz
14
nV/√Hz
in
Current noise density
f = 1 kHz
3.5
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) + 2.5
–27.5 V < VCM < +27.5 V
92
(V+) – 2.5
V
102
dB
INPUT IMPEDANCE
Differential
1013 || 2
Ω || pF
Common-mode
1013 || 6
Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
RL = 3 kΩ, –28 V < VO < +28 V
110
RL = 3 kΩ, –28 V < VO < +28 V,
TJ = –40°C to 125°C
100
126
dB
RL = 300 Ω, –27 V < VO < +27 V
120
3
MHz
G=1
±15
V/µs
0.1%
G = 1, CL = 100 pF, 10-V Step
1.3
0.01%
G = 1, CL = 100 pF, 10-V Step
2
OPA551 FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
Settling time
THD+N
Total harmonic distortion + noise
Overload recovery time
f = 1 kHz, VO = 15 VRMS, RL = 3 kΩ,
G=3
0.0005%
f = 1 kHz, VO = 15 VRMS, RL = 300 kΩ,
G=3
0.0005%
VIN × Gain = VS
µs
1
µs
OPA552 FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
Settling time
THD+N
12
MHz
G=5
±24
V/µs
0.1%
G = 5, CL = 100 pF, 10-V Step
2.2
0.01%
G = 5, CL = 100 pF, 10-V Step
3
Total harmonic distortion + noise
Overload recovery time
(1)
f = 1 kHz, VO = 15 VRMS, RL = 3 kΩ,
G=5
0.0005%
f = 1 kHz, VO = 15 VRMS, RL = 300 kΩ,
G=5
0.0005%
VIN × Gain = VS
1
µs
µs
All tests are high-speed tested at 25°C ambient temperature. Effective junction temperature is 25°C unless otherwise noted.
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Electrical Characteristics: VS = ±30 V (continued)
At TJ = 25°C(1), RL = 3 kΩ connected to ground, and VOUT = 0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IO = 200 mA
VOUT
Voltage output
IO = 200 mA
TJ = –40°C to 125°C
IO = 10 mA
IO = 10 mA
TJ = –40°C to 125°C
IO
Maximum continuous current output: DC
ISC
Short-circuit current
CLOAD
Capacitive load drive
Package dependent — see Power
Dissipation section
(V–) + 3
(V+) – 3
(V–) + 3.5
(V+) – 3.5
(V–) + 2
(V+) – 2
(V–) + 2.5
(V+) – 2.7
±200
mA
±380
Stable operation
V
mA
See Figure 19
SHUTDOWN FLAG
Normal operation, sourcing
Thermal shutdown status output
Junction temperature
Thermal shutdown, sourcing
80
Voltage compliance range
V–
0.05
1
120
160
(V+) –1.5
Shutdown
160
Reset from shutdown
140
µA
V
°C
POWER SUPPLY
VS
Specified voltage
±30
Operating voltage range
IQ
Quiescent current
±4
IO = 0 mA
±7
TJ = –40°C to 125°C
V
±30
±8.5
±10
V
mA
TEMPERATURE RANGE
TJ
6
Specified range
–40
125
Operating range
–55
125
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°C
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6.6 Typical Characteristics
At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.
140
0
140
0
OPA552
OPA551
100
–40
80
–60
80
–60
Phase
60
–80
40
–100
20
0
–20
Gain
60
Phase
–80
40
–100
–120
20
–120
–140
0
–140
–20
–160
–20
–160
–40
–180
10M
–40
1
10
100
1k
10k
100k
1M
1
10
100
Frequency (Hz)
1k
10k
100k
Phase (°)
120
–40
Gain
Gain (dB)
–20
100
Phase (°)
Gain (dB)
120
–180
10M
1M
Frequency (Hz)
Figure 1. Open-Loop Gain and Phase vs Frequency
(OPA551)
Figure 2. Open-Loop Gain and Phase vs Frequency
(OPA552)
120
120
100
100
80
80
PSRR (dB)
CMRR (dB)
–PSRR
60
+PSRR
40
40
20
20
0
0
1
10
100
1k
10k
100k
1M
1
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 3. Common-Mode Rejection Ratio vs Frequency
Figure 4. Power-Supply Rejection Ratio vs Frequency
0.1
10k
VO = 15Vrms
RL = 3kΩ, 300Ω
G = 3 (OPA551)
G = 5 (OPA552)
1k
THD+N (%)
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)
60
in
100
10
0.01
0.001
en
0.0001
1
10
100
1k
10k
100k
1M
1
Frequency (Hz)
100
1k
10k
100k
Frequency (Hz)
Figure 5. Input Voltage and Current Noise Spectral Density
vs Frequency
Figure 6. Total Harmonic Distortion + Noise vs Frequency
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Typical Characteristics (continued)
±30
(V+)
±25
(V+)–1
Output Voltage Swing (V)
Maximum Output Voltage (V)
At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.
±20
OPA552
±15
OPA551
±10
±5
+85°C
+25°C
(V+)–2
–55°C
(V+)–3
(V–)+3
+25°C
–55°C
(V–)+2
Without Slew-Induced
Distortion
(V–)+1
0
+85°C
(V–)
1
10
100
1k
10k
100k
1M
10M
0
50
100
Frequency (Hz)
150
200
250
300
350
400
Output Current (mA)
Figure 7. Maximum Output Voltage Swing vs Frequency
Figure 8. Output Voltage Swing vs Output Current
100k
130
125
AOL
10k
120
110
Current (pA)
Gain (dB)
115
PSRR
105
100
CMRR
1k
+IB
100
95
90
–IB
10
85
–IOS
80
–75
–25
25
75
1
–75
125
–50
Figure 9. Open-Loop Gain, Power-Supply Rejection Ratio,
and Common-Mode Rejection Ratio vs Temperature
450
8
390
370
+ISC
4
350
3
330
2
310
1
290
0
–75
ISC (mA)
IQ (mA)
410
–ISC
5
270
–50
–25
0
25
50
75
100
50
75
100
125
125
150
OPA552
10
OPA551
1
–80 –60 –40 –20
Temperature (° C)
0
20
40
60
80
100 120 140
Temperature ( °C)
Figure 11. Quiescent Current and Short-Circuit Current
vs Temperature
8
25
100
430
IQ
6
0
Figure 10. Input Bias Current and Input Offset Current
vs Temperature
Gain Bandwidth Product (MHz)
9
7
–25
Ambient Temperature ( °C)
Ambient Temperature (°C)
Figure 12. Gain Bandwidth Product vs Temperature
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Typical Characteristics (continued)
35
30
30
25
25
Current (pA)
20
OPA551
15
10
5
5
0
0
20
40
60
80
100
120
–IB
15
10
0
–60 –40 –20
IOS
–5
–30
140
–20
–10
0
10
20
30
Junction Temperature (° C)
Common-Mode Voltage (V)
Figure 13. Slew Rate vs Temperature
Figure 14. Input Bias Current and Input Offset Current
vs Common-Mode Voltage
405
–ISC
7.2
395
IQ
6.8
385
+ISC
6.4
375
Typical production
distribution of
packaged units.
15
12
9
6
3
365
< 3.0
< –3.0
Supply Voltage (V)
< 2.4
0
35
< 1.8
30
< 1.2
25
< 0.6
20
< 0.0
15
< –0.6
10
< –1.2
5
< –1.8
0
< –2.4
6.0
18
Percent of Amplifiers (%)
7.6
Quiescent Current (mA)
+IB
20
OPA552
Short-Circuit Current (mA)
Slew Rate (V/µs)
At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.
Offset Voltage (mV)
Figure 15. Quiescent Current and Short-Circuit Current
vs Supply Voltage
Figure 16. Offset Voltage Production Distribution
18
14
OPA551
0.01%
Settling Time (µs)
Percent of Amplifiers (%)
100
Typical production
distribution of
packaged units.
16
12
10
8
6
4
OPA551
0.1%
10
OPA552
0.01%
OPA552
0.1%
2
0
< 15.0
< 13.5
< 12.0
< 10.5
< 9.0
< 7.5
< 6.0
< 4.50
< 3.0
< 1.5
< 0.0
1
1
10
100
Gain (V/V)
Offset Drift µV/°C
Figure 17. Offset Voltage Drift Production Distribution
Figure 18. Settling Time vs Closed-Loop Gain
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.
60
OPA551
G = –1
40
30
OPA551
OPA552
G = –6
5V/div
Overshoot (%)
50
OPA551, G = 1
OPA552
G = –4
20
OPA551
G = –2
10
OPA552, G = –8
0
0.01
0.1
1
10
Time (1µs/div)
G = 1, CL = 100 pF
Load Capacitance (nF)
Figure 19. Small-Signal Overshoot
vs Load Capacitance
Figure 20. Large-Signal Step Response
OPA551
OPA551
5V/div
25mV/div
OPA552
Time (1µs/div)
Time (1µs/div)
G = 1, CL = 100 pF
G = 1, CL = 100 pF
Figure 22. Small-Signal Step Response
OPA551
OPA552
OPA551
5V/div
100mV/div
Figure 21. Large-Signal Step Response
OPA552
Time (1µs/div)
Time (1µs/div)
G = 1, CL = 100 pF
G = 1, CL = 1000 pF
Figure 23. Small-Signal Step Response
OPA552
10
Figure 24. Small-Signal Step Response
OPA551
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7 Detailed Description
7.1 Overview
The OPA55x devices are low-cost, laser-trimmed, operational amplifiers that feature outstanding low-level
accuracy coupled with high output swing. High device performance is maintained as these amplifiers swing to the
specified device limits in a wide range of applications. The OPA551 is unity-gain stable while the OPA552 is
optimized for gains of 5 or greater.
7.2 Functional Block Diagram
V+
V-IN
Differential
Amplifier
V+IN
Voltage
Amplifier
High Current
Output Stage
VO
Thermal
Shutdown and
Flag Output
V-
Flag
7.3 Feature Description
7.3.1 Thermal Shutdown
Internal thermal shutdown circuitry shuts down the output when the die temperature reaches approximately
160°C and resets when the die has cooled to 140°C. The flag pin can be monitored to determine if shutdown has
occurred. During normal operation, the current source from the flag pin is less than 50 nA. During shutdown, the
flag pin sources 120 µA (typical).
7.3.2 Current Limit
The OPA55x devices are designed with internal current-limiting circuitry that limits the output current to
approximately 380 mA. The current limit varies with increasing junction temperature as shown in (Figure 11).
This feature, in combination with the thermal protection circuitry, provides protection from many types of overload
conditions, including short-circuit to ground.
7.3.3 Input Protection
The OPA55x features internal clamp diodes to protect the inputs when voltages beyond the supply rails are
encountered. However, input current must be limited to 5 mA. In some cases, an external series resistor may be
required. Many input signals are inherently current-limited; therefore, a limiting resistor may not be required.
Consider that a large series resistor, in conjunction with the input capacitance, can affect stability.
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Feature Description (continued)
7.3.4 Thermal Protection
The OPA55x has thermal shutdown circuitry that protects the amplifier from damage caused by overload
conditions. The thermal protection circuitry disables the output when the junction temperature reaches
approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C,
the output circuitry is automatically re-enabled.
The thermal shutdown function is not intended to replace proper heat sinking. Activation of the thermal shutdown
circuitry is an indication of excessive power dissipation or an inadequate heat sink. Continuously running the
amplifier into thermal shutdown can degrade reliability.
The thermal shutdown indicator (flag) pin can be monitored to determine if shutdown is occurring. During normal
operation, the current output from the flag pin is typically 50 nA. During shutdown, the current output from the
flag pin increases to 120 μA (typical). This current output allows for easy interfacing to external logic. Refer to
Figure 25 and Figure 26 for two examples that implement this function.
VOUT
OPA551
Flag
80 µA to
160 µA
+5V
HCT
27kΩ
Logic
Ground
HCT logic has relatively well-controlled logic level. A properly chosen resistor value can ensure proper logic high level
throughout the full range of flag output current.
Figure 25. Interfacing With HCT Logic
VOUT
OPA551
VLOGIC
HP5082-2835
CMOS
47kΩ
Logic
Ground
Interface to virtually any CMOS logic gate by choosing resistor value that provides a guaranteed logic high voltage
with the minimum (80 µA) flag current. A diode clamp to the logic supply voltage assures that the CMOS is not
damaged by overdrive.
Figure 26. Interfacing With CMOS Logic
7.4 Device Functional Modes
The OPA551 and OPA552 have a single functional mode. The device is operational when the power supply is
above 8 V and the junction temperature is below 160°C.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Figure 27 shows the OPA551 connected as a basic noninverting amplifier. The OPA551 can be used in virtually
any operational amplifier configuration. The OPA552 is designed for use in configurations with gains of 5 or
greater. Power-supply terminals must be bypassed with 0.1-µF capacitors, or greater, near the power-supply
pins. Be sure that the capacitors are appropriately rated for the power-supply voltage used. The OPA55x can
supply output currents up to 200 mA with excellent performance.
8.2 Typical Application
V+
10µF
G = 1+
+
R2
R1
0.1µF
R2
R1
VO
OPA551
VIN
Flag
ZL
(optional)
0.1µF
10µF
+
V–
Figure 27. Basic Circuit Connections
8.2.1 Design Requirements
•
•
•
•
Operate from power supplies between ±15 V to ±30 V
Drive passive and reactive loads up to 1 A
Drive large capacitive loads
Operate up to 125°C
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Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Capacitive Loads
The dynamic characteristics of the OPA55x have been optimized for commonly-encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and capacitive load decreases the phase margin
and may lead to gain peaking or oscillations. Figure 28 shows a circuit that preserves phase margin with a 10-nF
capacitive load. Figure 33 shows the small-signal step response for the circuit in Figure 28. Consult SBOA015 for
more information.
+30V
OPA551
RG
4kΩ
10nF
RF
4kΩ
VI
CS
1.8nF
CF
220pF
–30V
Figure 28. Driving Large Capacitive Loads
8.2.2.2 Increasing Output Current
In those applications where the 200 mA of output current is not sufficient to drive the desired load, output current
can increase by connecting two or more OPA551s or OPA552s in parallel, as shown in Figure 29. Amplifier A1 is
the master amplifier and may be configured in virtually an operational amplifier circuit. Amplifier A2, the slave, is
configured as a unity-gain buffer. Alternatively, external output transistors can be used to boost output current.
The circuit in Figure 30 is capable of supplying output currents up to 1 A. Alternatively, consider the OPA547,
OPA548, and OPA549 series power operational amplifiers for high output current drive, along with programmable
current limit and output disable capability.
R1
R2
“MASTER”
RS(1)
10Ω
OPA551
VIN
RS(1)
10Ω
OPA551
“SLAVE”
RL
NOTE: (1) RS resistors minimize the circulating
current that can flow between the two devices
due to VOS errors.
Figure 29. Parallel Amplifiers Increase Output Current Capability
14
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Typical Application (continued)
R1
R2
+30V
TIP29C
CF
R3(1)
100Ω
R4
0.2Ω
VO
OPA551
VIN
R4
0.2Ω
LOAD
TIP30C
–30V
NOTE: (1) R3 provides current limit and allows the amplifier to
drive the load when the output is between 0.7V and –0.7V.
Figure 30. External Output Transistors Boost Output Current Up to 1 A
8.2.2.3 Using the OPA552 in Low Gains
The OPA552 family is intended for applications with signal gains of 5 or greater, but it is possible to take
advantage of the high slew rate in lower gains using an external compensation technique in an inverting
configuration. This technique maintains low-noise characteristics of the OPA552 architecture at low frequencies.
Depending on the application, a small increase in high-frequency noise may result. This technique shapes the
loop gain for good stability while giving an easily-controlled, second-order, lowpass frequency response.
Considering only the noise gain (noninverting signal gain) for the circuit of Figure 31, the low-frequency noise
gain (NG1) is set by the resistor ratios, while the high-frequency noise gain (NG2) is set by the capacitor ratios.
The capacitor values set both the transition frequencies and the high-frequency noise gain. If this noise gain,
determined by NG2 = 1 + CS / CF, is set to a value greater than the recommended minimum stable gain for the
operational amplifier and the noise gain pole, set by 1 / RFCF, is placed correctly, a very well-controlled, secondorder, lowpass frequency response is the result.
To choose the values for both CS and CF, two parameters and only three equations must be solved. First, the
target for the high-frequency noise gain (NG2) must be greater than the minimum stable gain for the OPA552. In
the circuit shown in Figure 31, a target NG2 of 10 is used. Second, the signal gain of –1 shown in Figure 31 sets
the low frequency noise gain to NG1 = 1 + RF / RG (= 2 in this example). Using these two gains, knowing the gain
bandwidth product (GBP) for the OPA552 (12 MHz), and targeting a maximally flat, second-order, lowpass
Butterworth frequency response (Q = 0.707), the key frequency in the compensation can be found.
For the values shown in Figure 31, the f–3dB is approximately 956 kHz. This frequency is less than that predicted
by simply dividing the GBP by NG1. The compensation network controls the bandwidth to a lower value while
providing the full slew rate at the output and an exceptional distortion performance as a result of increased loop
gain at frequencies below NG1 × Z0. The capacitor values shown in Figure 31 are calculated for NG1 = 2 and
NG2 = 10 with no adjustment for parasitics.
Optimize the actual circuit values by checking the small-signal step response with actual load conditions.
Figure 32 shows the small-signal step response of this OPA552, G = –1 circuit with a 500-pF load. It is wellbehaved with no tendency to oscillate. If CS and CF are removed, the circuit becomes unstable.
SPACER
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Typical Application (continued)
+30V
OPA552
RG
1kΩ
VOUT
RF
1kΩ
20mV/div
OPA552
VIN
CS
1.88nF
CF
208pF
–30V
Time (1µs/div)
NG1 = 1 + RF/RG = 2
NG2 = 1 + CS/CF = 10
Figure 31. Compensation of the OPA552 for G = 1
Figure 32. Small-Signal Step Response for
Figure 31
8.2.2.4 Offset Voltage Error Calculation
The offset voltage (VOS) of the OPA51 and OPA552 is specified with a ±30-V power supply and the commonmode voltage centered between the supplies (VS / 2 = 0 V). Additional specifications for power-supply rejection
and common-mode rejection are provided to allow the user to easily calculate worst-case excepted offset under
the conditions of a given application.
Power-supply rejection ratio (PSRR) is specified in µV/V. For the OPA55x, worst-case PSRR is 30 µV/V, which
means for each volt of change in total power-supply voltage, the offset may shift by up to 30 µV/V. Commonmode rejection ratio (CMRR) is specified in dB, which can be converted to µV/V using Equation 1:
CMRR in (V/V) = 10[(CMRR in dB)/–20]
(1)
For the OPA55x, the worst-case CMRR at ±30-mV supply over the full common-mode range is 96 dB, or
approximately 15.8 µV/V. This result means that for every volt of change in common-mode, the offset may shift
up to 15.8 µV. These numbers can be used to calculate excursions from the specified offset voltage under
different applications conditions. For example, a common application might configure the amplifier with a –48-V
single supply with –6-V common-mode. This configuration represents a 12-V variation in power supply: ±30 V or
60 V in the offset specification versus 48 V in the application. In addition, this configuration has an 18-V variation
in common-mode voltage: VS / 2 = –24 V is the specification for these power supplies, but the common-mode
voltage is –6 V in the application.
Calculation of the worst-case expected offset for this example is calculated by Equation 2 and Equation 3.
Worst-case VOS = maximum specified VOS + (power-supply variation × PSRR) + (common-mode variation × CMRR) (2)
VOSwc = 5 mV + (12 V × 30 µV/V) + (18 V × 15.8 µV/V) = ±5.64 mV
(3)
16
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Typical Application (continued)
8.2.3 Application Curve
Figure 33 shows the small-signal step response for the circuit in Figure 28. Consult AB-028 for more information.
20mV/div
OPA551
Time (2.5µs/div)
Figure 33. Small-Signal Step Response for Driving Large Capacitive Loads
9 Power Supply Recommendations
9.1 Power Supplies
The OPA55x may be operated from power supplies of ±4 V to ±30 V, or a total of 60 V with excellent
performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that
vary significantly with operating voltage are shown in the Typical Characteristics.
For applications that do not require symmetrical output voltage swing, power-supply voltages do not need to be
equal. The OPA55x can operate with as little as 8 V between the supplies or with up to 60 V between the
supplies. For example, the positive supply could be set to 50 V with the negative supply at –10 V, or vice-versa.
The SOIC-8 package outline shows three negative supply (V–) pins. These pins are internally connected for
improved thermal performance.
NOTE
Pin 4 must be used as the primary current carrier for the negative supply. It is
recommended that pins 1 and 5 are not directly connected to V–. Instead, connect pins 1
and 5 to a thermal mass. DO NOT lay out the printed-circuit-board (PCB) to use pins 1
and 5 as feedthroughs to the negative supply. Such a configuration results in a
performance reduction.
The tab of the DDPAK/TO-263 package is electrically connected to the negative supply (V–). However, this
connection must not be used to carry current. For best thermal performance, solder the tab directly to the PCB
copper area (see the Heat Sinking section).
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10 Layout
10.1 Layout Guidelines
The circuit board must have as much ground plane area as possible. Power supply and output traces must be
sized to handle the required current. Keep input and output terminals separated as much as possible.
10.2 Layout Example
PDIP-8 and
SOIC-8
DDPAK-7
Flag
Gain Resistor
V-
Gain Resistor
GND
VIN
VIN
V+
0.01 µF
bypass
Grey area is
ground layer
-
0.1 µF
bypasses
V+
VOUT
+
R1
Bypass
Capacitor
Output
Flag
R2
VIN
V-
Figure 34. Layout Example (OPA551)
10.3 Power Dissipation
Internal power dissipation of these operational amplifiers can be quite large. Many of the specifications for the
OPA55x are for a specified junction temperature. If the device is not subjected to internal self-heating, the
junction temperature is the same as the ambient. However, in practical applications, the device self-heats and
the junction temperature becomes significantly higher than ambient. After junction temperature has been
established, performance parameters that vary with junction temperature can be determined from the
performance curves. The following calculation can be performed to establish junction temperature as a function
of ambient temperature and the conditions of the application.
Consider the OPA551 in a circuit configuration where the load is 600 Ω and the output voltage is 15 V. The
supplies are at ±30 V and the ambient temperature (TA) is 40°C. The θJA for the 8-pin PDIP package is 100°C/W.
First, the internal heating of the operational amplifier is in Equation 4:
PD(internal) = IQ × VS = 7.2 mA × 60 V = 432 mW
(4)
The output current (IO) can be calculated in Equation 5:
IO = VOUT/RL = 15 V/600 Ω = 25 mA
(5)
The power being dissipated (PD) in the output transistor of the amplifier can be calculated in Equation 6 and
Equation 7:
PD(output stage) = IO× (VS –– VO) = 25 mA × (30 – 15) = 375 mW
PD(total) = PD(internal) + PD(output stage) = 432 mW + 375 mW = 807 mW
(6)
(7)
The resulting junction temperature can be calculated in Equation 8 and Equation 9:
TJ = TA + PD θJA
TJ = 40°C + 807 mW × 100°C/W = 120.7°C
(8)
where
•
•
•
TJ = junction temperature (°C)
TA = ambient temperature (°C)
θJA = junction-to-air thermal resistance (°C/W)
(9)
For the DDPAK/TO-263 package, the θJA is 65°C/W with no heat sinking, resulting in a junction temperature of
92.5°C.
18
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Power Dissipation (continued)
To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature
until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the
thermal protection must trigger more than 35°C above the maximum expected ambient condition of a given
application. This limit ensures a maximum junction temperature of 125°C at the maximum expected ambient
condition.
If the OPA551 or OPA552 is to be used in an application requiring more than 0.5-W continuous power
dissipation, TI recommends that the DDPAK/TO-263 package option be used. The DDPAK/TO-263 has superior
thermal dissipation characteristics and is more easily adapted to a heatsink.
Operation from a single power supply (or unbalanced power supplies) can produce even larger power dissipation
because a larger voltage can be impressed across the conducting output transistor. Consult SBOA022 for further
information on how to calculate or measure power dissipation.
Power dissipation can be minimized by using the lowest possible supply voltage. For example, with a 200-mA
load, the output swings to within 3.5 V of the power-supply rails. Set the power supplies to no more than 3.5 V
above the maximum output voltage swing required by the application to minimize the power dissipation.
10.4 Safe Operating Area
The Safe Operating Area (SOA) curves Figure 35, Figure 36, and Figure 37 show the permissible range of
voltage and current. These curves shown represent devices soldered to a circuit board with no heatsink. The
safe output current decreases as the voltage across the output transistor (VS – VO) increases. For further insight
on SOA, consult AB-039.
Output short circuits are a very demanding case for SOA. A short-circuit to ground forces the full power-supply
voltage (V+ or V–) across the conducting transistor and produces a typical output current of 380 mA. With ±30-V
power supplies, this configuration creates an internal dissipation of 11.4 W. This dissipation far exceeds the
maximum rating and is not recommended. If operation in this region is unavoidable, use the DDPAK/TO-263
package with a heatsink.
1000
1000
25°C
25°C
100
125°C
125°C
IO (mA)
IO (mA)
100
10
85°C
10
85°C
1
1
0.1
0.1
1
10
1
100
10
100
| VS | – | VO | (V)
| VS | – | VO | (V)
Figure 35. PDIP-8 Safe Operating Area
Figure 36. SOIC-8 Safe Operating Area
1000
25°C
25°C
1" Copper
IO (mA)
100
125°C
10
125°C
1" Copper
85°C
1
0.1
1
10
100
| VS | – | VO | (V)
Figure 37. DDPAK-7/TO-263 Safe Operating Area
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10.5 Heat Sinking
Power dissipated in the OPA551 or OPA552 causes the junction temperature to rise. For reliable operation, limit
the junction temperature to 125°C. Many applications require a heatsink to assure that the maximum operating
junction temperature is not exceeded. The heatsink required depends on the power dissipated and on ambient
conditions.
For heatsinking purposes, the tab of the DDPAK/TO-263 is typically soldered directly to the PCB copper area.
Increasing the copper area improves heat dissipation. Figure 38 shows typical thermal resistance from junctionto-ambient as a function of copper area.
Depending on conditions, additional heatsinking may be required. Aavid Thermal Products Inc. manufactures
surface-mountable heatsinks designed specifically for use with DDPAK/TO-263 packages. Further information is
available on the Aavid web site, www.aavid.com.
To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature
until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the
thermal protection must trigger more than 25°C above the maximum expected ambient condition of your
application. This level produces a junction temperature of 125°C at the maximum expected ambient condition.
Thermal Resistance, θJA (°C/W)
50
OPA551, OPA552
Surface-Mount Package
1oz. copper
40
30
20
10
0
0
1
2
3
4
5
Copper Area (inches 2)
Figure 38. Thermal Resistance vs Circuit Board Copper Area
Circuit Board Copper Area
Figure 39. OPA551, OPA552 Surface-Mount Package Circuit Board Copper Area
20
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA551
Click here
Click here
Click here
Click here
Click here
OPA552
Click here
Click here
Click here
Click here
Click here
11.2.2 Related Documentation
For related documentation, please see the following:
•
•
•
Heat Sinking — TO-3 Thermal Mode (SBOA021)
Application bulletin AB-028: Feedback Plots Define Op Amp AC Performance (SBOA015)
Application bulletin AB-039: Power Amplifier Stress and Power Handling Limitations (SBOA022)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
(1)
For improved thermal performance, increase footprint area.
(2)
Mean dimensions in inches. Refer to the mechanical drawings or www.ti.com for tolerances and detailed package
drawings.
Figure 40. TO-220 and DDPAK Solder Footprints
22
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PACKAGE OPTION ADDENDUM
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6-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA551FA/500
ACTIVE
DDPAK/
TO-263
KTW
7
500
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-2-260C-1 YEAR
-40 to 125
OPA551FA
OPA551FA/500G3
ACTIVE
DDPAK/
TO-263
KTW
7
500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
OPA551FA
OPA551FAKTWT
ACTIVE
DDPAK/
TO-263
KTW
7
250
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-2-260C-1 YEAR
-40 to 125
OPA551FA
OPA551FAKTWTG3
ACTIVE
DDPAK/
TO-263
KTW
7
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
OPA551FA
OPA551PA
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
OPA551PA
OPA551PAG4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
OPA551PA
OPA551UA
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA
551UA
OPA551UA/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA
551UA
OPA551UAE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA
551UA
OPA552FA/500
ACTIVE
DDPAK/
TO-263
KTW
7
500
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-2-260C-1 YEAR
-40 to 125
OPA552FA
OPA552FAKTWT
ACTIVE
DDPAK/
TO-263
KTW
7
250
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-2-260C-1 YEAR
OPA552FA
OPA552FAKTWTG3
ACTIVE
DDPAK/
TO-263
KTW
7
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
OPA552FA
OPA552PA
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA552PA
OPA552UA
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA
552UA
OPA552UA/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA
552UA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Nov-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA551FA/500
DDPAK/
TO-263
KTW
7
500
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
OPA551FAKTWT
DDPAK/
TO-263
KTW
7
250
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
OPA551UA/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA552FA/500
DDPAK/
TO-263
KTW
7
500
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
OPA552FAKTWT
DDPAK/
TO-263
KTW
7
250
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
OPA552UA/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Nov-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA551FA/500
DDPAK/TO-263
KTW
7
500
367.0
367.0
45.0
OPA551FAKTWT
DDPAK/TO-263
KTW
7
250
367.0
367.0
45.0
OPA551UA/2K5
SOIC
D
8
2500
367.0
367.0
35.0
OPA552FA/500
DDPAK/TO-263
KTW
7
500
367.0
367.0
45.0
OPA552FAKTWT
DDPAK/TO-263
KTW
7
250
367.0
367.0
45.0
OPA552UA/2K5
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPSF015 – AUGUST 2001
KTW (R-PSFM-G7)
PLASTIC FLANGE-MOUNT
0.410 (10,41)
0.385 (9,78)
0.304 (7,72)
–A–
0.006
–B–
0.303 (7,70)
0.297 (7,54)
0.0625 (1,587) H
0.055 (1,40)
0.0585 (1,485)
0.300 (7,62)
0.064 (1,63)
0.045 (1,14)
0.252 (6,40)
0.056 (1,42)
0.187 (4,75)
0.370 (9,40)
0.179 (4,55)
0.330 (8,38)
H
0.296 (7,52)
A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C
0.000 (0,00)
0.019 (0,48)
0.104 (2,64)
0.096 (2,44)
H
0.017 (0,43)
0.050 (1,27)
C
C
F
0.034 (0,86)
0.022 (0,57)
0.010 (0,25) M
B
0.026 (0,66)
0.014 (0,36)
0°~3°
AM C M
0.183 (4,65)
0.170 (4,32)
4201284/A 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
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