Texas Instruments | LM7332 Dual Rail-to-Rail Input and Output 30-V, Wide Voltage Range, High Output, Operational Amplifier (Rev. B) | Datasheet | Texas Instruments LM7332 Dual Rail-to-Rail Input and Output 30-V, Wide Voltage Range, High Output, Operational Amplifier (Rev. B) Datasheet

Texas Instruments LM7332 Dual Rail-to-Rail Input and Output 30-V, Wide Voltage Range, High Output, Operational Amplifier (Rev. B) Datasheet
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LM7332
SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
LM7332 Dual Rail-to-Rail Input and Output 30-V, Wide Voltage Range, High Output,
Operational Amplifier
1 Features
3 Description
•
The LM7332 device is a dual rail-to-rail input and
output amplifier with a wide operating temperature
range (−40°C to +125°C) that meets the needs of
automotive, industrial, and power supply applications.
The LM7332 has an output current of 100 mA, which
is higher than that of most monolithic operational
amplifiers. Circuit designs with high output current
requirements often require discrete transistors
because many operational amplifiers have low
current output. The LM7332 has enough current
output to drive many loads directly, saving the cost
and space of the discrete transistors.
1
•
•
•
•
•
•
•
•
•
•
VS = ±15 V, TA = 25°C, Typical Values Unless
Specified
Wide Supply Voltage Range 2.5 V to 32 V
Wide Input Common Mode Voltage 0.3 V Beyond
Rails
Output Short Circuit Current > 100 mA
High Output Current (1 V from Rails) ±70 mA
GBWP 21 MHz
Slew Rate 15.2 V/µs
Capacitive Load Tolerance Unlimited
Total Supply Current 2 mA
Temperature Range −40°C to +125°C
Tested at −40°C, +125°C,
and +25°C at 5 V, ±5 V, ±15 V
2 Applications
•
•
•
•
•
•
•
•
MOSFET and Power Transistor Driver
Replaces Discrete Transistors in High Current
Output Circuits
Instrumentation 4–20 mA Current Loops
Analog Data Transmission
Multiple Voltage Power Supplies and Battery
Chargers
High-Side and Low-Side Current Sensing
Bridge and Sensor Driving
Digital-to-Analog Converter Output
The exceptionally wide operating supply voltage
range of 2.5 V to 32 V alleviates any concerns over
functionality under extreme conditions and offers
flexibility of use in a multitude of applications. Most
parameters of this device are insensitive to power
supply variations; this design enhancement is another
step in simplifying usage. Greater than rail-to-rail
input common mode voltage range allows operation
in many applications, including high-side and low-side
sensing, without exceeding the input range.
The LM7332 can drive unlimited capacitive loads
without oscillations.
The LM7332 is offered in the 8-pin VSSOP and SOIC
packages.
Device Information(1)
PART NUMBER
LM7332
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output Swing vs Sourcing Current
100
Large Signal Step Response for Various
Capacitive Loads
10
10 pF
VS = 10V, AV = +1, RL = 1 M:
125°C
1
2000 pF
85°C
5V/DIV
VOUT FROM RAIL (V)
VS = 30V
-40°C
0.1
10,000 pF
25°C
0.01
0.1
1
10
100
1000
20,000 pF
ISOURCE (mA)
2 Ps/DIV
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM7332
SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
5-V Electrical Characteristics ...................................
±5-V Electrical Characteristics ................................
±15-V Electrical Characteristics ..............................
Typical Characteristics ..............................................
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
10.3 Output Short Circuit Current and Dissipation
Issues....................................................................... 23
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
•
Added Device Information, ESD Ratings and Thermal Information table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
Changes from Original (March 2013) to Revision A
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 20
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SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
IN+ A
V
-
8
A
-
7
+
2
3
B
+
IN- A
1
6
-
OUT A
4
5
+
V
OUT B
IN- B
IN+ B
D Package
8-Pin SOIC
Top View
IN+ A
V
-
8
A
-
7
+
2
3
B
+
IN- A
1
6
-
OUT A
4
5
+
V
OUT B
IN- B
IN+ B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
IN+ A
3
I
Noninverting Input for Amplifier A
IN– A
2
I
Inverting Input for Amplifier A
IN+ B
5
I
Noninverting Input for Amplifier B
IN– B
6
I
Inverting Input for Amplifier AB
OUT A
1
O
Output for Amplifier A
OUT B
7
O
Output for Amplifier B
+
V
8
P
Positive Supply
V–
4
P
Negative Supply
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SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See
MIN
VIN differential
Output short-circuit duration
See
Junction temperature
V+ + 0.3
(5)
Soldering information
(2)
(3)
(4)
(5)
V
35
V
V− − 0.3
V
150
°C
Infrared or convection (20 sec.)
235
°C
Wave soldering (10 sec.)
260
°C
150
°C
−65
Storage temperature, Tstg
(1)
UNIT
±10
(3) (4)
Supply voltage (VS = V+ – V−)
Voltage at input/output pins
MAX
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Short-circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ 6 V at room temperature and below. For VS > 6 V,
allowable short circuit duration is 1.5 ms.
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
MIN
+
−
Supply voltage (VS = V – V )
Temperature range (1)
(1)
MAX
UNIT
2.5
32
V
−40
125
°C
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
LM7332
THERMAL METRIC
(1)
(2)
DGK (VSSOP)
D (SOIC)
8 PINS
8 PINS
UNIT
161.1
109.1
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
55
55.8
°C/W
RθJB
Junction-to-board thermal resistance
80.5
49.2
°C/W
ψJT
Junction-to-top characterization parameter
5.5
10.7
°C/W
ψJB
Junction-to-board characterization parameter
79.2
48.7
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
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6.5
SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
5-V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = 0.5 V, VO = 2.5 V, and RL > 1 MΩ
to 2.5 V. (1)
PARAMETER
VOS
Input offset voltage
TC VOS
Input offset voltage temperature
drift
IB
Input bias current
IOS
Input offset current
CMRR
Common-mode Rejection Ratio
PSRR
Power supply Rejection Ratio
CMVR
Input common-mode Voltage
Range
AVOL
Large signal Voltage Gain
TEST CONDITIONS
MIN
(2)
VCM = 0.5 V and VCM = 4.5 V
−4
At the temperature extremes
–5
VCM = 0.5 V and VCM = 4.5 V
See
(4)
(5)
±1.6
±1
20
At the temperature extremes
Output short circuit current
IOUT
Output current
2
µA
250
67
At the temperature extremes
65
nA
0 V ≤ VCM ≤ 5 V
62
At the temperature extremes
60
5 V ≤ V+ ≤ 30 V
78
At the temperature extremes
74
CMRR > 50 dB
5.1
−0.3
−0.1
5
5.3
0
0.5 V ≤ VO ≤ 4.5 V
RL = 10 kΩ to 2.5 V
70
77
At the temperature extremes
65
80
dB
70
100
60
At the temperature extremes
dB
V
dB
150
200
RL = 2 kΩ to 2.5 V
VID = 100 mV
100
300
350
5
At the temperature extremes
150
mV from
either rail
200
RL = 2 kΩ to 2.5 V
VID = −100 mV
20
At the temperature extremes
ISC
mV
µV/°C
0 V ≤ VCM ≤ 3 V
At the temperature extremes
UNIT
4
300
RL = 10 kΩ to 2.5 V
VID = −100 mV
Output swing
low
(2)
2.5
At the temperature extremes
VO
MAX
5
−2.5
RL = 10 kΩ to 2.5 V
VID = 100 mV
Output swing
high
(3)
±2
−2
At the temperature extremes
TYP
300
350
Sourcing from V+, VID = 200 mV (6)
60
90
Sinking to V−, VID = –200 mV (6)
60
90
VID = ±200 mV, VO = 1 V from rails
±55
No Load, VCM = 0.5 V
1.5
mA
mA
2.3
IS
Total supply current
SR
Slew rate (7)
AV = +1, VI = 5-V Step, RL = 1 MΩ,
CL = 10 pF
12
V/µs
fu
Unity-gain frequency
RL = 10 MΩ, CL = 20 pF
7.5
MHz
(1)
(2)
(3)
(4)
(5)
(6)
(7)
At the temperature extremes
mA
2.6
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing in the device.
Short-circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ 6 V at room temperature and below. For VS > 6 V,
allowable short circuit duration is 1.5 ms.
Slew rate is the slower of the rising and falling slew rates. Connected as a voltage follower.
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SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
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5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = 0.5 V, VO = 2.5 V, and RL > 1 MΩ
to 2.5 V.(1)
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
MAX
(2)
UNIT
GBWP
Gain bandwidth product
f = 50 kHz
19.3
MHz
en
Input-referred voltage noise
f = 2 kHz
14.8
nV/√HZ
in
Input-referred current noise
f = 2 kHz
1.35
pA/√HZ
THD+N
Total harmonic distortion + noise
AV = +2, RL = 100 kΩ, f = 1 kHz,
VO = 4 VPP
−84
dB
CT Rej.
Crosstalk rejection
f = 3 MHz, Driver RL = 10 kΩ
68
dB
6.6
±5-V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = +5 V, V− = −5 V, VCM = 0 V, VO = 0 V, and RL > 1 MΩ to
0 V. (1)
PARAMETER
VOS
Input offset voltage
TC VOS
Input offset voltage temperature
drift
IB
Input bias current
IOS
Input offset current
CMRR
Common-mode rejection ratio
PSRR
Power supply rejection ration
CMVR
Input common-mode voltage
range
AVOL
Large signal voltage gain
(1)
(2)
(3)
(4)
(5)
6
TEST CONDITIONS
MIN
(2)
VCM = −4.5 V and VCM = 4.5 V
−4
At the temperature extremes
−5
VCM = −4.5 V and VCM = 4.5 V
See
(4)
(5)
(3)
±1.6
MAX
(2)
4
5
±2
−2
At the temperature extremes
TYP
±1
−2.5
20
2
250
300
−5 V ≤ VCM ≤ 3 V
74
At the temperature extremes
75
−5 V ≤ VCM ≤ 5 V
70
At the temperature extremes
65
5 V ≤ V+ ≤ 30 V, VCM = −4.5 V
78
At the temperature extremes
74
CMRR > 50 dB
5.1
–5.3
–5.1
5
5.3
–5.1
−4 V ≤ VO ≤ 4 V
RL = 10 kΩ to 0 V
72
80
At the temperature extremes
70
At the temperature extremes
mV
µV/°C
2.5
At the temperature extremes
UNIT
µA
nA
88
dB
74
100
dB
V
dB
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing in the device.
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SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
±5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = +5 V, V− = −5 V, VCM = 0 V, VO = 0 V, and RL > 1 MΩ to
0 V.(1)
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
RL = 10 kΩ to 0 V
VID = 100 mV
Output swing
high
(3)
75
At the temperature extremes
125
10
At the temperature extremes
350
250
mV from
either rail
300
RL = 2 kΩ to 0V
VID = −100 mV
30
At the temperature extremes
350
400
+
Sourcing from V , VID = 200 mV
(6)
ISC
Output short circuit current
IOUT
Output current
IS
Total supply current
SR
Slew rate (7)
AV = +1, VI = 8-V step, RL = 1 MΩ,
CL = 10 pF
ROUT
Close-loop output resistance
AV = +1, f = 100 kHz
fu
Unity-gain frequency
RL = 10 MΩ, CL = 20 pF
GBWP
Gain bandwidth product
en
in
Sinking to V−, VID = −200 mV
UNIT
250
400
RL = 10 kΩ to 0 V
VID = −100 mV
Output swing
low
(2)
300
RL = 2 kΩ to 0 V
VID = 100 mV
At the temperature extremes
VO
MAX
(6)
90
120
90
100
VID = ±200 mV, VO = 1 V from rails
±65
No Load, VCM = −4.5 V
1.5
At the temperature extremes
mA
mA
2.4
mA
2.6
13.2
V/µs
Ω
3
7.9
MHz
f = 50 kHz
19.9
MHz
Input-referred voltage noise
f = 2 kHz
14.7
nV/√HZ
Input-referred current noise
f = 2 kHz
1.3
pA/√HZ
THD+N
Total harmonic distortion + noise
AV = +2, RL = 100 kΩ, f = 1 kHz
VO = 8 VPP
−87
dB
CT Rej.
Crosstalk rejection
f = 3 MHz, driver RL = 10 kΩ
68
dB
(6)
(7)
6.7
Short-circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ 6 V at room temperature and below. For VS > 6 V,
allowable short circuit duration is 1.5 ms.
Slew rate is the slower of the rising and falling slew rates. Connected as a voltage follower.
±15-V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = +15 V, V− = −15 V, VCM = 0 V, VO = 0 V, and RL > 1 MΩ
to 0 V. (1)
PARAMETER
VOS
Input offset voltage
TC VOS
Input offset voltage temperature
drift
IB
Input bias current
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
MIN
(2)
VCM = −14.5 V and VCM = 14.5 V
−5
At the temperature extremes
−6
VCM = −14.5 V and VCM = 14.5 V
(5)
−2
At the temperature extremes
(3)
±2
MAX
(2)
−2.5
UNIT
5
mV
6
±2
(4)
See
TYP
±1
µV/°C
2
2.5
µA
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing in the device.
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±15-V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = +15 V, V− = −15 V, VCM = 0 V, VO = 0 V, and RL > 1 MΩ
to 0 V.(1)
PARAMETER
IOS
Input offset current
CMRR
Common-mode rejection ratio
PSRR
Power supply rejection ratio
CMVR
Input common-mode voltage
range
AVOL
Large signal voltage gain
TEST CONDITIONS
MIN
TYP
(3)
20
At the temperature extremes
−15 V ≤ VCM ≤ 12 V
74
At the temperature extremes
74
−15 V ≤ VCM ≤ 15 V
72
At the temperature extremes
72
−10 V ≤ V+ ≤ 15 V, VCM = −14.5 V
78
At the temperature extremes
74
250
UNIT
nA
dB
80
100
dB
15.1
−15.3
−15.1
At the temperature extremes
15
15.3
−15
−14 V ≤ VO ≤ 14 V
RL = 10 kΩ to 0 V
72
80
At the temperature extremes
70
CMRR > 50 dB
100
At the temperature extremes
V
dB
350
400
RL = 2 kΩ to 0 V
VID = 100 mV
200
550
600
RL = 10 kΩ to 0 V
VID = −100 mV
Output swing
low
(2)
88
At the temperature extremes
VO
MAX
300
RL = 10 kΩ to 0 V
VID = 100 mV
Output swing
high
(2)
20
At the temperature extremes
450
mV from
either rail
500
RL = 2 kΩ to 0 V
VID = −100 mV
25
At the temperature extremes
550
600
+
Sourcing from V , VID = 200 mV
(6)
140
ISC
Output short circuit current
IOUT
Output current
IS
Total supply current
SR
Slew rate (7)
AV = +1, VI = 20-V Step, RL = 1 MΩ,
CL = 10 pF
fu
Unity-gain frequency
RL = 10 MΩ, CL = 20 pF
GBWP
Gain bandwidth product
f = 50 kHz
en
Input-referred voltage noise
f = 2 kHz
15.5
nV/√HZ
in
Input-referred current noise
f = 2 kHz
1
pA/√HZ
THD+N
Total harmonic distortion plus
noise
AV = +2, RL = 100 kΩ, f = 1 kHz
VO = 25 VPP
CT Rej.
Crosstalk rejection
f = 3 MHz, Driver RL = 10 kΩ
(6)
(7)
8
Sinking to V−, VID = −200 mV
(6)
VID = ±200 mV, VO = 1 V from rails
No Load, VCM = −14.5 V
mA
140
±70
2
At the temperature extremes
mA
2.5
3
mA
15.2
V/µs
9
MHz
21
MHz
−93
dB
68
dB
Short-circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ 6 V at room temperature and below. For VS > 6V,
allowable short circuit duration is 1.5 ms.
Slew rate is the slower of the rising and falling slew rates. Connected as a voltage follower.
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SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
6.8 Typical Characteristics
Unless otherwise specified, TA = 25°C.
12
0.2
VS = 10V
10
0.1
25°C
0.05
8
VOS (mV)
PERCENTAGE (%)
85°C
0.15
6
4
0
125°C
-0.05
-0.1
-40°C
-0.15
-0.2
2
-0.25
0
-2
-3
-1
0
1
2
VS = 5V
-0.3
-1
3
0
1
2
VOS (mV)
Figure 1. VOS Distribution
4
5
6
Figure 2. VOS vs VCM (Unit 1)
2.5
-1
125°C
125°C
-1.5
85°C
2
25°C
-2.5
VOS (mV)
-2
VOS (mV)
3
VCM (V)
-40°C
-3
1.5
1
25°C
-40°C
85°C
0.5
-3.5
125°C
VS = 5V
-4
-1
0
1
2
3
4
VS = 5V
0
-1
6
5
0
1
2
3
4
5
6
VCM (V)
VCM (V)
Figure 3. VOS vs VCM (Unit 2)
Figure 4. VOS vs VCM (Unit 3)
0
0
85°C
-0.5
-0.1
125°C
125°C
-40°C
-1.5
-40°C
VOS (mV)
VOS (mV)
-1
25°C
-0.2
-0.3
-0.4
-2
-2.5
85°C
-3
-0.5
25°C
-3.5
-0.6
-4
VS = 30V
-0.7
-5
0
5
10
15
20
25
30
35
-4.5
-5
VS = 30V
0
5
10
15
20
25
30
35
VCM (V)
VCM (V)
Figure 5. VOS vs VCM (Unit 1)
Figure 6. VOS vs VCM (Unit 2)
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C.
2
-0.6
125°C
85°C
-0.7
1.5
-0.8
1
VOS (mV)
VOS (mV)
-0.9
25°C
-40°C
0.5
-40°C
-1
-1.1
25°C
-1.1
85°C
-1.2
0
-1.3
-0.5
-5
0
125°C
-1.4
VS = 30V
5
10
15
20
25
30
-1.5
35
0
10
20
VCM (V)
Figure 8. VOS vs VS (Unit 1)
1
125°C
0.9
0.9
0.8
85°C
0.7
0.6
VOS (mV)
VOS (mV)
25°C
0.8
85°C
0.7
25°C
0.5
0.4
-40°C
0.6
-40°C
0.5
125°C
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
0
10
20
30
40
0
10
20
VS (V)
1400
40
Figure 10. VOS vs VS (Unit 3)
1300
-40°C
25°C
-
VCM = V + 0.5V
1200
1200
1000
-40°C
85°C
125°C
800
30
VS (V)
Figure 9. VOS vs VS (Unit 2)
600
IBIAS (nA)
IBIAS (nA)
40
VS (V)
Figure 7. VOS vs VCM (Unit 3)
1
30
400
200
25°C
1100
1000
125°C
0
85°C
900
-200
-400
VS = 5V
-600
0
1
800
2
3
4
5
5
10
15
20
25
30
35
40
VS (V)
VCM (V)
Figure 12. IBIAS vs Supply Voltage
Figure 11. IBIAS vs VCM
10
0
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C.
3.5
3.5
VS = 5V
VS = 12V
3
3
125°C
2.5
2.5
2
IS (mA)
IS (mA)
125°C
85°C
1.5
2
85°C
1.5
25°C
1
25°C
1
-40°C
0.5
0.5
-40°C
0
0
-1
0
1
2
3
4
5
6
-1
3
1
7
9
11
13
VCM (V)
VCM (V)
Figure 13. IS vs VCM
Figure 14. IS vs VCM
3.6
4
VS = 30V
3.4
3.5
3.2
3
125°C
3
125°C
85°C
2.8
IS (mA)
2.5
IS (mA)
5
2
85°C
1.5
2.6
25°C
2.4
2.2
25°C
-40°C
2
1
-40°C
1.8
0.5
1.6
0
-5
1.4
0
5
10
15
20
25
30
35
-
VCM = V + 0.5V
10
0
20
30
10
VS (V)
VCM (V)
Figure 15. IS vs VCM
Figure 16. IS vs Supply Voltage
2.4
10
VS = 5V
2.2
125°C
85°C
1.8
25°C
1.6
1.4
-40°C
1.2
1
VOUT FROM RAIL (V)
IS (mA)
2
125°C
85°C
0.1
25°C
0.01
-40°C
-
VCM = V + 0.5V
1
0
10
20
30
40
0.001
0.1
VS (V)
Figure 17. IS vs Supply Voltage
1
10
100
1000
ISINK (mA)
Figure 18. Output Swing vs Sinking Current
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C.
100
10
VS = 5V
VS = 30V
VOUT FROM RAIL (V)
VOUT FROM RAIL (V)
10
1
125°C
85°C
0.1
25°C
1
125°C
25°C
85°C
-40°C
0.1
0.01
-40°C
0.001
0.1
1
10
100
0.01
0.01
1000
10
1
0.1
ISINK (mA)
Figure 19. Output Swing vs Sinking Current
Figure 20. Output Swing vs Sourcing Current
300
VS = 30V
RL = 2 k:
10
VOUT from RAIL (mV)
VOUT FROM RAIL (V)
250
125°C
1
85°C
-40°C
0.1
0.01
0.1
1
10
125°C
85°C
200
25°C
150
-40°C
100
50
25°C
100
0
1000
0
5
10
Figure 21. Output Swing vs Sourcing Current
100
125°C
25
30
35
RL = 2 k:
90
85°C
125°C
80
120
VOUT from RAIL (mV)
VOUT from RAIL (mV)
20
Figure 22. Positive Output Swing vs Supply Voltage
160
RL = 10 k:
15
VS (V)
ISOURCE (mA)
25°C
100
80
-40°C
60
40
85°C
70
25°C
60
50
-40°C
40
30
20
20
10
0
0
0
5
10
15
20
25
30
35
0
VS (V)
5
10
15
20
25
30
35
VS (V)
Figure 23. Positive Output Swing vs Supply Voltage
12
1000
ISOURCE (mA)
100
140
100
Figure 24. Negative Output Swing vs Supply Voltage
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C.
25
140
RL = 10 k:
120
85°C
20
125°C
VOUT from RAIL (mV)
158
VS = 5V
RL = 10 M: 135
100
113
GAIN (dB)
15
25°C
10
80
20 pF
90
GAIN
60
50 pF
68
40
45
PHASE (q)
PHASE
-40°C
20
5
23
200 pF
0
0
100 pF
-20
0
15
20
25
30
1k
35
10k
100k
VS (V)
VS = 10V
RL = 10 M:
120
100
158
140
135
120
113
100
90
80
40
68
45
20
GAIN (dB)
50 pF
GAIN
PHASE (q)
GAIN (dB)
20 pF
60
158
VS = 30V
RL = 10 M: 135
113
PHASE
20 pF
60
50 pF
GAIN
40
23
200 pF
0
0
0
100 pF
-20
10k
100k
1M
10M
-20
-23
100M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
-23
100M
FREQUENCY (Hz)
Figure 27. Open-Loop Frequency Response With
Various Capacitive Loads
Figure 28. Open-Loop Frequency Response With
Various Capacitive Loads
140
140
158
VS = 30V
CL = 20 pF 135
PHASE
120
100 k:
120
60
68
10 k:
1 M:
GAIN
45
10 M:
20
GAIN (dB)
90
PHASE (q)
80
VS = 30V
80
0
0
-20
1k
10k
100k
1M
10M
-23
100M
90
VS = 10V
60
68
GAIN
40
45
20
23
23
100 k: 1 M: 10 M:
135
113
PHASE
113
10 k:
GAIN (dB)
158
RL = 1 M:
CL = 20 pF
100
100
40
68
45
100 pF
1k
90
20
23
200 pF
0
-23
100M
Figure 26. Open-Loop Frequency Response With
Various Capacitive Loads
PHASE
80
10M
FREQUENCY (Hz)
Figure 25. Negative Output Swing vs Supply Voltage
140
1M
PHASE (q)
10
0
PHASE (q)
3
0
0
VS = 5V
-20
1k
10k
100k
1M
10M
-23
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29. Open-Loop Frequency Response vs
With Various Resistive Loads
Figure 30. Open-Loop Frequency Response vs
With Various Supply Voltages
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C.
140
GAIN (dB)
80
90
-40qC
60
125qC 68
GAIN
40
45
125qC
20
RL = 2 k:
23
-40qC
125qC
60
0
PHASE MARGIN (°)
PHASE
RL = 600:
PHASE (q)
120
100
70
158
VS = 30V
RL = 1 M: 135
CL = 20 pF
113
0
-20
1k
10k
100k
1M
10M
50
RL = 10 k:
40
30 RL = 100 k: 10 M:
20
10
VS = 5V
0
20
-23
100M
100
1000
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
Figure 32. Phase Margin vs Capacitive Load
Figure 31. Open-Loop Frequency Response at Various
Temperatures
70
90
RL = 600:
70
RL = 2 k:
50
60
RL = 10 k:
CMRR (dB)
PHASE MARGIN (°)
VS = 10V
80
60
40
30 RL = 100 k: 10 M:
50
40
30
20
20
10
10
VS = 30V
0
20
100
0
10
1000
10k
100k
CAPACITIVE LOAD (pF)
Figure 33. Phase Margin vs Capacitive Load
Figure 34. CMRR vs Frequency
70
-PSRR (dB)
80
70
60
50
40
60
50
40
30
30
20
20
10
10
10
100
1k
10k
100k
VS = 10V
90
80
0
1M
100
VS = 10V
90
+PSRR (dB)
1k
FREQUENCY (Hz)
100
1M
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 36. −PSRR vs Frequency
Figure 35. +PSRR vs Frequency
14
100
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C.
100 mVPP
100 mVPP
VS = 10V, AV = +1, CL = 10 pF, RL = 1 M:
VS = 10V, AV = +1, CL = 500 pF, RL = 1 M:
1 VPP
1 VPP
2 VPP
2 VPP
5 VPP
5 VPP
500 ns/DIV
200 ns/DIV
Figure 37. Step Response for Various Amplitudes
Figure 38. Step Response for Various Amplitudes
100
1000
VS = 5V
VS = 10V, AV = +1, RL = 1 M:
10,000 pF
100
10
CURRENT
VOLTAGE
1
10
1
20,000 pF
1
100
1k
100
100
1000
VOLTAGE
1
1
1
10
100
1k
10k
0.1
100k
VOLTAGE NOISE (nV/ Hz)
10
CURRENT NOISE (pA/ Hz)
VOLTAGE NOISE (nV/ Hz)
VS = 30V
CURRENT
10
0.1
100k
Figure 40. Input-Referred Noise Density vs Frequency
VS = 10V
100
10k
FREQUENCY (Hz)
2 Ps/DIV
Figure 39. Large Signal Step Response for Various
Capacitive Loads
1000
10
10
100
CURRENT
VOLTAGE
1
10
1
1
FREQUENCY (Hz)
10
100
1k
10k
CURRENT NOISE (pA/ Hz)
5V/DIV
2000 pF
CURRENT NOISE (pA/ Hz)
VOLTAGE NOISE (nV/ Hz)
10 pF
0.1
100k
FREQUENCY (Hz)
Figure 41. Input-Referred Noise Density vs Frequency
Figure 42. Input-Referred Noise Density vs Frequency
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C.
0
0
VS = 5V
-10 f = 1 kHz
VS = 10V
-10 f = 1 kHz
THD+N (dB)
THD+N (dB)
-20 AV = +2
R = 100 k:
-30 L
-40
-50
-60
-20
AV = +2
-30
RL = 100 k:
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
0.02
0.1
1
-100
0.02
6
OUTPUT AMPLITUDE (VPP)
Figure 43. THD+N vs Output Amplitude (VPP)
130
VS = 30V
-10 f = 1 kHz
CROSSTALK REJECTION (dB)
THD+N (dB)
10 20
VS = 5V
120
-20 AV = +2
RL = 100 k:
-30
-40
-50
-60
-70
-80
-90
RL = 10 k:
110
100
90
80
70
60
50
40
30
0.1
1
10
40
20
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
OUTPUT AMPLITUDE (VPP)
Figure 45. THD+N vs Output Amplitude (VPP)
16
1
Figure 44. THD+N vs Output Amplitude (VPP)
0
-100
0.02
0.1
OUTPUT AMPLITUDE (VPP)
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Figure 46. Crosstalk vs Frequency
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7 Detailed Description
7.1 Overview
The LM7332 device is a rail-to-rail input and output amplifier with wide operating voltages and high-output
currents. The LM7322 is efficient, achieving 15.2-V/µs slew rate and 21-MHz unity gain bandwidth while requiring
only 2 mA of total supply current. The LM7332 device performance is fully specified for operation at 5 V, ±5 V
and ±15 V.
The LM7332 device is designed to drive unlimited capacitive loads without oscillations. The LM7332 is fully
tested at −40°C, 125°C, and 25°C, with modern automatic test equipment. High performance from −40°C to
+125°C, detailed specifications, and extensive testing makes them suitable for industrial, automotive, and
communications applications.
Most device parameters are insensitive to power supply voltage, and this makes the parts easier to use where
supply voltage may vary, such as automotive electrical systems and battery-powered equipment. The LM7332
has a true rail-to-rail output and can supply a respectable amount of current (±70 mA) with minimal head room
from either rail (1 V).
7.2 Functional Block Diagram
V
-
A
2
3
7
B
+
IN+ A
8
+
IN- A
1
6
-
OUT A
4
5
+
V
OUT B
IN- B
IN+ B
7.3 Feature Description
7.3.1 Estimating the Output Voltage Swing
It is important to keep in mind that the steady-state output current will be less than the current available when
there is an input overdrive present. For steady-state conditions, Figure 47 and Figure 48 plots can be used to
predict the output swing. These plots also show several load lines corresponding to loads tied between the
output and ground. In each case, the intersection of the device plot at the appropriate temperature with the load
line would be the typical output swing possible for that load. For example, a 600-Ω load can accommodate an
output swing to within 100 mV of V− and to 250 mV of V+ (VS = ±5 V) corresponding to a typical 9.65-VPP
unclipped swing.
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Feature Description (continued)
10
10
20:
50:
2 k:
1
VOUT FROM V (V)
1 k:
1
1 k:
600:
-
+
VOUT FROM V (V)
2 k:
600:
200:
100m
100:
100m
10m
200:
VS = 10V
VS = 10V
VID = 20 mV
10m
10µ
100µ
100: 50:
VID = -20 mV
20:
1m
10m
1m
10µ
100m
100µ
1m
10m
100m
IOUT (A)
IOUT (A)
Figure 48. Steady-State Output Sinking Characteristics
With Load Lines
Figure 47. Steady-State Output Sourcing Characteristics
With Load Lines
7.4 Device Functional Modes
7.4.1 Driving Capacitive Loads
The LM7332 is specifically designed to drive unlimited capacitive loads without oscillations as shown in
Figure 49.
100
100µ
VS = 10V
AV = +1
10µ
10
1µ
1
SLEW RATE (V/µS)
±1% SETTLING TIME (S)
SETTLING TIME
100 mVPP STEP
SLEW RATE
100n
10p
100p
1n
10n
100n
1µ
0.1
10µ
CL (pF)
Figure 49. Settling Time and Slew Rate vs Capacitive Load
In addition, the output current handling capability of the device allows for good slewing characteristics even with
large capacitive loads as shown in Figure 49. The combination of these features is ideal for applications such as
TFT flat panel buffers, A/D converter input amplifiers and power transistor driver.
However, as in most operational amplifiers, addition of a series isolation resistor between the operational
amplifier and the capacitive load improves the settling and overshoot performance.
Output current drive is an important parameter when driving capacitive loads. This parameter will determine how
fast the output voltage can change. Referring to Figure 49, two distinct regions can be identified. Below about
10,000 pF, the output slew rate is solely determined by the compensation capacitor value of the operational
amplifier and available current into that capacitor. Beyond 10 nF, the slew rate is determined by the available
output current of the operational amplifier. An estimate of positive and negative slew rates for loads larger than
100 nF can be made by dividing the short circuit current value by the capacitor.
18
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Device Functional Modes (continued)
7.4.2 Output Voltage Swing Close to V−
The output stage design of the LM7332 allows voltage swings to within millivolts of either supply rail for
maximum flexibility and improved useful range. Because of this design architecture, with output approaching
either supply rail, the output transistor collector-base junction reverse bias decreases. With output less than a Vbe
from either rail, the corresponding output transistor operates near saturation. In this mode of operation, the
transistor exhibits higher junction capacitance and lower ft which reduces phase margin. With the Noise Gain
(NG = 1 + RF/RG, RF and RG are external gain setting resistors) of 2 or higher, there is sufficient phase margin
that this reduction in phase margin is of no consequence. However, with lower Noise Gain (<2) and with less
than 150 mV to the supply rail, if the output loading is light, the phase margin reduction could result in unwanted
oscillations.
In the case of the LM7332, due to inherent architectural specifics, the oscillation occurs only with respect to the
output transistor at V− when output swings to within 150 mV of V−. However, if this output transistor's collector
current is larger than its idle value of a few microamps, the phase margin loss becomes insignificant. In this case,
300 μA is the required collector current of the output transistor to remedy this situation. Therefore, when all the
aforementioned critical conditions are present at the same time (NG < 2, VOUT < 150 mV from supply rails and
output load is light) it is possible to ensure stability by adding a load resistor to the output to provide the output
transistor the necessary minimum collector current (300 μA).
For 12-V (or ±6-V) operation, for example, add a 39-kΩ resistor from the output to V+ to cause 300-µA output
sinking current and ensure stability. This is equivalent to about 15% increase in total quiescent power dissipation.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM7332 is a rail-to-rail input and output part with a slightly higher GBW of 20 MHz. It has current capability
of 40-mA sourcing and 65-mA sinking, and can drive unlimited capacitive loads. The LM7332 is available in both
VSSOP and SOIC packages.
8.1.1 Similar High Current Output Devices
The LM6172 has a higher GBW of 100 MHz and over 80 mA of current output. There is also a single version, the
LM6171. The LM7372 has 120 MHz of GBW and 150 mA of current output. The LM7372 is available in an 8-pin
SO PowerPAD™, and 16-pin SOIC packages with higher power dissipation.
The LME49600 buffer has 250 mA of current out and a 110-MHz bandwidth. The LME49600 is available in a
DDPAK/TO-263 package for higher power dissipation.
Detailed information on these parts can be found at www.ti.com.
8.2 Typical Application
-
Input Signal
Ro
Rflt
RON
+
SAR ADC
CSH
Cflt
Figure 50. Drive Amplifier for SAR ADC Schematic
8.2.1 Design Requirements
Assume a portable application requires the use of a 12-bit SAR ADC with acquisition time (tAQ) of 1 µs and
sample and hold capacitance (CSH) of 80 pF.
The ADC runs on a single supply voltage of 5 V and has a full scale input of 2.5 VPP. A total harmonic distortion
plus noise (THD+N) of less than –80 dB is required to maintain signal fidelity. Determine if the LM7332 is a
suitable drive amplifier and find the values of Rflt and Cflt.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
The LM7332 can be used as a drive amplifier for SAR ADCs as shown in Figure 50.
The values of Rflt and Cflt depend on the ADC specifications as well as amplifier gain bandwidth product (GBWP)
and output resistance (RO). It is also common to have a single ground-referenced supply voltage and sample
signals up to half of the supply voltage with low distortion.
To determine whether or not the LM7332 is a suitable driver for this application, one must compare the settling
time of the amplifier to the acquisition time of the ADC with Equation 1:
GBWPmin ≥ 4 × (N+1) × ln(2) / (2π × tAQ)
where
•
•
•
GBWPmin: The minimum required gain bandwidth product of the drive amplifier
N: Number of bits in ADC
tAQ: The acquisition time of the ADC
(1)
Using a value of 12 bits for N and 1µs for tAQ, the GBWPmin must be greater than 5.7 MHz. The LM7332 has a
GBWP of 21 MHz so it is indeed a suitable driver for this application.
Next, determine the value of Cflt with Equation 2:
20 × CSH ≤ Cflt ≤ 60 × CSH
where
•
•
CSH: The ADC sample and hold capacitance
Cflt: The external filter capacitance
(2)
Using a value of 80 pF for CSH, the value of Cflt must be between 1600 pF and 4800 pF. According to Figure 39,
the LM7332 can drive a capacitive load of 2000 pF with 5 VPP and settle within 1 µs, therefore select 1800 pF as
the nearest common capacitor value within the range.
Next determine the value of Rflt with Equation 3:
Rflt = 40 / (2π × Cflt ×GBWPmin) – RO
where
•
•
•
•
Rflt: The external filter resistance
Cflt: The external filter capacitance determined above
GBWPmin: The minimum required gain bandwidth product of the drive amplifier determined above
RO: The closed loop output impedance of the drive amplifier typically specified in the electrical characteristics
table
(3)
Using a value of 1800 pF for Cflt, 5.7 MHz for GBWPmin, and a value of 3 Ω for RO the value of Rflt is determined
to be 617.5 Ω. Use closest value of 620 Ω for a filter frequency (fflt) of 142 kHz given Equation 4:
fflt=1 / (2π × (RO + Rflt) × Cflt)
(4)
The last requirement is to drive input signals of 2.5 VPP on a single 5-V supply with THD+N less than –80 dB.
Figure 51 shows the THD+N response of the LM7332 with a single supply voltage of 5 V. The LM7332 can
maintain THD+N levels as low as –83 dB for output levels up to 4 VPP. Therefore the final requirement has been
met, and the LM7332 is a suitable drive amplifier for the 12-bit SAR ADC in this design example.
Driving two independent channels of the SAR ADC within minimal crosstalk between the channels may also be
required. Figure 52 shows the crosstalk rejection over frequency. The LM7332 achieves 105 dB of crosstalk
rejection up to 20 kHz and greater than 75 dB up to 1MHz which demonstrates the suitability of measuring very
large input signals without interfering with adjacent channels.
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Typical Application (continued)
8.2.3 Application Curves
0
VS = 5V
-10 f = 1 kHz
130
CROSSTALK REJECTION (dB)
THD+N (dB)
-20 AV = +2
R = 100 k:
-30 L
-40
-50
-60
-70
-80
-90
-100
0.02
VS = 5V
120
RL = 10 k:
110
100
90
80
70
60
50
40
30
0.1
1
6
20
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
OUTPUT AMPLITUDE (VPP)
Figure 51. THD+N vs Output Amplitude
Figure 52. Crosstalk Rejection vs. Frequency
9 Power Supply Recommendations
The use of supply decoupling is mandatory in most applications. As with most relatively high-speed or high
output current operational amplifiers, best results are achieved when each supply line is decoupled with two
capacitors: a small value ceramic capacitor (approximately 0.01 µF) placed very close to the supply lead in
addition to a large value tantalum or aluminum capacitor (> 4.7 µF). The large capacitor can be shared by more
than one device if necessary. The small ceramic capacitor maintains low supply impedance at high frequencies
while the large capacitor acts as the charge bucket for fast load current spikes at the operational amplifier output.
The combination of these capacitors provides supply decoupling and helps keep the operational amplifier
oscillation free under any load.
22
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10 Layout
10.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. A ground plane underneath the device is recommended; any bypass components to ground must have a
nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding supply
pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins lowers the power supply
inductance and provide a more stable power supply.
The feedback components must be placed as close to the device as possible to minimize stray parasitics.
10.2 Layout Example
3. IN+A
4. GND
IN+A
1
IN–A
2
OUTA
1
IN–A
2
OUTA
1. OUTA VOUT
2
IN–A
2. IN–A VA
1
GND
OUT+A
2
OUTB
1
IN–B
2
OUTB
8. +3.3V
1
IN–B
1
+3.3V
2
GND
+3.3V
2
IN–B
GND
1
GND
7. OUTB
IN+B
6. IN–B
5. IN+B
OUT+B
Figure 53. LM7332 Layout Example
10.3 Output Short Circuit Current and Dissipation Issues
The LM7332 output stage is designed for maximum output current capability. Even though momentary output
shorts to ground and either supply can be tolerated at all operating voltages, longer-lasting short conditions can
cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher
supply voltage conditions. Below a supply voltage of 6 V, the output short circuit condition can be tolerated
indefinitely.
With the operational amplifier tied to a load, the device power dissipation consists of the quiescent power due to
the supply current flow into the device, in addition to power dissipation due to the load current. The load portion
of the power itself could include an average value (due to a DC load current) and an AC component. DC load
current would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the
operational amplifier operates in a single-supply application where the output is maintained somewhere in the
range of linear operation.
Therefore,
PTOTAL = PQ + PDC + PAC
(5)
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Output Short Circuit Current and Dissipation Issues (continued)
The operational amplifier quiescent power dissipation is calculated by Equation 6:
PQ = IS × VS
where
•
•
IS: Supply Current
VS: Total Supply Voltage (V+ − V−)
(6)
The DC load power is calculated by Equation 7:
PDC = IO × (Vr – Vo)
where
•
•
VO: Average Output Voltage
Vr: V+ for sourcing and V− for sinking current
(7)
The AC load power is calculated as PAC = the value shown in Table 1.
Table 1 shows the maximum AC component of the load power dissipated by the operational amplifier for
standard sinusoidal, triangular, and square waveforms:
Table 1. Normalized AC Power Dissipated in the Output Stage for Standard
Waveforms
PAC (W.Ω/V2)
SINUSOIDAL
TRIANGULAR
SQUARE
50.7 x 10−3
46.9 x 10−3
62.5 x 10−3
The table entries are normalized to VS2/RL. To figure out the AC load current component of power dissipation,
simply multiply the table entry corresponding to the output waveform by the factor VS2/RL. For example, with ±12V supplies, a 600-Ω load, and triangular waveform power dissipation in the output stage is calculated as:
PAC = (46.9 × 10−3) × [242/600] = 45.0 mW
(8)
The maximum power dissipation allowed at a certain temperature is a function of maximum die junction
temperature (TJ(MAX)) allowed, ambient temperature TA, and package thermal resistance from junction to ambient,
RθJA.
TJ(MAX) - TA
PD(MAX) =
R TJA
(9)
For the LM7332, the maximum junction temperature allowed is 150°C at which no power dissipation is allowed.
The power capability at 25°C is given by Equation 10 and Equation 11.
For VSSOP package:
PD(MAX) =
150°C ± 25°C
= 0.78W
161.1°C/W
(10)
For SOIC package:
PD(MAX) =
150°C ± 25°C
= 1.15W
109.1°C/W
(11)
Similarly, the power capability at 125°C is given by Equation 12 and Equation 13.
For VSSOP package:
150°C ± 125°C
= 0.16W
PD(MAX) =
161.1°C/W
(12)
For SOIC package:
150°C ± 125°C
= 0.23W
PD(MAX) =
109.1°C/W
24
(13)
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Figure 54 shows the power capability vs temperature for VSSOP and SOIC packages. The area under the
maximum thermal capability line is the operating area for the device. When the device works in the operating
area where PTOTAL is less than PD(MAX), the device junction temperature will remain below 150°C. If the
intersection of ambient temperature and package power is above the maximum thermal capability line, the
junction temperature will exceed 150°C, and this must be strictly prohibited.
1.4
POWER CAPABILITY (W)
1.2
M
1
ax
im
um
0.8
Ma
0.6
um
0.4
0.2
th
e
the
rm
al
ca
Operating area
0
-40 -20 0
rm
al
xim
pa
bil
ca
ity
pa
lin
bi
lity
e(
li n
e
MS
(S
O
IC
)
OP
)
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
Figure 54. Power Capability vs Temperature
When high power is required and ambient temperature cannot be reduced, providing air flow is an effective
approach to reduce thermal resistance therefore to improve power capability.
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LM7332
SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM7332MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM733
2MA
LM7332MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM733
2MA
LM7332MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AA5A
LM7332MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AA5A
LM7332MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AA5A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM7332MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM7332MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM7332MME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM7332MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM7332MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM7332MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM7332MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LM7332MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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