Texas Instruments | LM7321x Single and LM7322x Dual Rail-to-Rail Input and Output ±15-V, High-Output Current and Unlimited Capacitive Load Operational Amplifier (Rev. E) | Datasheet | Texas Instruments LM7321x Single and LM7322x Dual Rail-to-Rail Input and Output ±15-V, High-Output Current and Unlimited Capacitive Load Operational Amplifier (Rev. E) Datasheet

Texas Instruments LM7321x Single and LM7322x Dual Rail-to-Rail Input and Output ±15-V, High-Output Current and Unlimited Capacitive Load Operational Amplifier (Rev. E) Datasheet
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
LM7321x Single and LM7322x Dual Rail-to-Rail Input and Output ±15-V, High-Output
Current and Unlimited Capacitive Load Operational Amplifier
1 Features
3 Description
•
The LM732xx devices are rail-to-rail input and output
amplifiers with wide operating voltages and highoutput currents. The LM732xx family is efficient,
achieving 18-V/µs slew rate and 20-MHz unity gain
bandwidth while requiring only 1 mA of supply current
per op amp. The LM732xx device performance is fully
specified for operation at 2.7 V, ±5 V and ±15 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
(VS = ±15, TA = 25°C, Typical Values Unless
Specified.)
Wide Supply Voltage Range 2.5 V to 32 V
Output Current +65 mA/−100 mA
Gain Bandwidth Product 20 MHz
Slew Rate 18 V/µs
Capacitive Load Tolerance Unlimited
Input Common-Mode Voltage 0.3-V Beyond Rails
Input Voltage Noise 15 nV/√Hz
Input Current Noise 1.3 pA/√Hz
Supply Current/Channel 1.1 mA
Distortion THD+Noise −86 dB
Temperature Range −40°C to 125°C
Tested at −40°C, 25°C and 125°C at 2.7 V, ±5 V,
±15 V.
LM732xx are Automotive Grade Products that are
AEC-Q100 Grade 1 Qualified.
2 Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and Power Transistors
Capacitive Proximity Sensors
Driving Analog Optocouplers
High-Side Sensing
Below Ground Current Sensing
Photodiode Biasing
Driving Varactor Diodes in PLLs
Wide Voltage Range Power supplies
Automotive
International Power Supplies
The LM732xx devices are designed to drive unlimited
capacitive loads without oscillations. All LM7321x and
LM7322x parts are tested at −40°C, 125°C, and
25°C, with modern automatic test equipment. High
performance from −40°C to 125°C, detailed
specifications, and extensive testing makes them
suitable
for
industrial,
automotive,
and
communications applications.
Greater than rail-to-rail input common-mode voltage
range with 50 dB of common-mode rejection across
this wide voltage range, allows both high-side and
low-side sensing. Most device parameters are
insensitive to power supply voltage, and this makes
the parts easier to use where supply voltage may
vary, such as automotive electrical systems and
battery powered equipment. These amplifiers have
true rail-to-rail output and can supply a respectable
amount of current (15 mA) with minimal head- room
from either rail (300 mV) at low distortion (0.05%
THD+Noise).
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM7321
LM7322
SOIC (8)
4.90 mm × 3.91 mm
SOT (5)
2.90 mm × 1.60 mm
LM7322
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output Swing vs. Sourcing Current
Large Signal Step Response
10
12,200 pF
VS = ±15V
25V/DIV
+
VOUT from V (V)
8,600 pF
1
125°C
VS = ±15V, AV = +1
85°C
0.1
2,200 pF
10 pF
25°C
-40°C
INPUT
0.01
0.1
1
10
100
5 Ps/DIV
ISOURCE (mA)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description continued ...........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
2.7-V Electrical Characteristics ............................... 5
±5-V Electrical Characteristics ................................. 7
±15-V Electrical Characteristics ............................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 23
9
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application ................................................. 25
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision C (May 2008) to Revision D
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 25
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
5 Description continued
There are several package options for each part. Standard SOIC versions of both parts make upgrading existing
designs easy. LM7322x are offered in a space-saving 8-Pin VSSOP package. The LM7321x are offered in small
SOT-23 package, which makes it easy to place this part close to sensors for better circuit performance.
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
OUT
-
V
D Package
8-Pin SOIC
Top View
5
1
+
V
N/C
-IN
2
+
+IN
+IN
3
4
1
8
2
+
3
7
6
N/C
V
+
OUT
-IN
V
-
4
5
N/C
DGK Package
8-Pin VSSOP or SOIC
Top View
+IN A
V
-
8
A
3
7
+
2
B
+
-IN A
1
6
-
OUT A
4
5
+
V
OUT B
-IN B
+IN B
Pin Functions
PIN
NAME
SOT-23
NO.
SOIC NO.
VSSOP,
SOIC NO.
I/O
DESCRIPTION
OUT
1
6
—
O
Output
OUT A
—
—
1
O
Output for Amplifier A
OUT B
—
—
7
O
Output for Amplifier B
V+
5
7
7
P
Positive Supply
V–
2
4
4
P
Negative Supply
+IN
3
3
—
I
Noninverting Input
–IN
4
2
—
I
Inverting Input
+IN A
—
—
3
I
Noninverting Input for Amplifier A
–IN A
—
—
2
I
Inverting Input for Amplifier A
+IN B
—
—
5
I
Noninverting Input for Amplifier B
–IN B
—
—
6
I
Inverting Input for Amplifier B
N/C
—
1, 5, 8
—
—
No connection
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
3
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
VIN Differential
Output Short Circuit Current
See
Junction Temperature
Soldering
Information:
V+ + 0.8
(2)
(3)
(4)
V
35
V
V− − 0.8
V
(4)
150
°C
Infrared or Convection (20 sec.)
235
°C
Wave Soldering (10 sec.)
260
°C
150
°C
−65
Storage Temperature
(1)
UNIT
±10
(3)
Supply Voltage (VS = V+ - V−)
Voltage at Input/Output pins
MAX
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5 ms.
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PCB.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge (1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (3)
±1000
Machine Model
(1)
(2)
(3)
UNIT
V
200
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Supply Voltage (VS = V+ - V−)
Temperature Range
(1)
(1)
MIN
MAX
2.5
32
UNIT
V
−40
125
°C
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PCB.
7.4 Thermal Information
LM7321
THERMAL METRIC (1)
RθJA (2)
(1)
(2)
4
Junction-to-ambient thermal resistance
D (SOIC)
DBV (SOT)
DGK (VSSOP)
8 PINS
5 PINS
8 PINS
165
325
235
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PCB.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
7.5
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
2.7-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 0.5 V, VOUT = 1.35 V, and RL > 1 MΩ
to 1.35 V. (1)
PARAMETER
TEST CONDITION
VOS
Input Offset Voltage
VCM = 0.5 V and VCM = 2.2 V
TC VOS
Input Offset Voltage
Temperature Drift
VCM = 0.5 V and VCM = 2.2 V (4)
VCM = 0.5 V (5)
IB
Input Bias Current
VCM = 2.2 V
IOS
Input Offset Current
VCM = 0.5 V and VCM = 2.2 V
Common-Mode
Rejection Ratio
0 V ≤ VCM ≤ 2.7 V
PSRR
Power Supply Rejection
Ratio
2.7 V ≤ VS ≤ 30 V
Common-Mode Voltage
Range (Min)
CMRR > 50 dB
Common-Mode Voltage
Range (Max)
CMRR > 50 dB
CMVR
0.5 V ≤ VO ≤ 2.2 V
RL = 10 kΩ to 1.35 V
AVOL
Open-Loop Voltage Gain
0.5 V ≤ VO ≤ 2.2 V
RL = 2 kΩ to 1.35V
Output Voltage Swing
High
RL = 10 kΩ to 1.35 V
VID = 100 mV
(1)
(2)
(3)
(4)
(5)
(6)
Output Current
−5
±0.7
+5
−6
−2
TA = –40°C to +125°C
Sinking
VID = −200 mV, VOUT = 2.7
V (6)
104
3
V
2.7
65
72
62
59
dB
66
55
50
TA = –40°C to +125°C
150
160
100
20
250
280 mV from
120 either rail
150
40
TA = –40°C to +125°C
120
150
30
48
20
40
TA = –40°C to +125°C
−0.1
0
2.8
TA = –40°C to +125°C
dB
74
−0.3
TA = –40°C to +125°C
dB
70
TA = –40°C to +125°C
TA = –40°C to +125°C
nA
50
78
TA = –40°C to +125°C
µA
100
60
55
TA = –40°C to +125°C
200
300
70
TA = –40°C to +125°C
1
1.5
20
TA = –40°C to +125°C
mV
µV/C
−2.5
TA = –40°C to +125°C
TA = –40°C to +125°C
UNIT
−1.2
TA = –40°C to +125°C
RL = 10 kΩ to 1.35 V
VID = −100 mV
RL = 2 kΩ to 1.35 V
VID = −100 mV
+6
0.45
TA = –40°C to +125°C
Sourcing
VID = 200 mV, VOUT = 0 V (6)
IOUT
MAX (2)
±2
RL = 2 kΩ to 1.35 V
VID = 100 mV
VOUT
Output Voltage Swing
Low
TYP (3)
(5)
0 V ≤ VCM ≤ 1 V
CMRR
TA = –40°C to +125°C
MIN (2)
65
mA
30
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing into the device.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS ≤ 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
5
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
2.7-V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 0.5 V, VOUT = 1.35 V, and RL > 1 MΩ
to 1.35 V.(1)
PARAMETER
LM7321
IS
TYP (3)
MAX (2)
0.95
1.3
TA = –40°C to +125°C
Supply Current
1.9
2
LM7322
(7)
MIN (2)
TEST CONDITION
TA = –40°C to +125°C
2.5
UNIT
mA
3.8
SR
Slew Rate
AV = +1, VI = 2-V Step
8.5
V/µs
fu
Unity Gain Frequency
RL = 2 kΩ, CL = 20 pF
7.5
MHz
GBW
Gain Bandwidth
f = 50 kHz
16
MHz
en
Input Referred Voltage
Noise Density
f = 2 kHz
11.9
nV/√H
in
Input Referred Current
Noise Density
f = 2 kHz
0.5
pA/√H
THD+N
Total Harmonic
Distortion + Noise
V+ = 1.9 V, V− = −0.8 V
f = 1 kHz, RL = 100 kΩ, AV = +2
VOUT = 210 mVPP
−77
dB
CT Rej.
Crosstalk Rejection
f = 100 kHz, Driver RL = 10 kΩ
60
dB
(7)
6
Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
7.6
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
±5-V Electrical Characteristics
Unless otherwise specified, all limited ensured for TA = 25°C, V+ = 5 V, V− = −5V, VCM = 0 V, VOUT = 0 V, and RL > 1 MΩ to 0
V. (1)
PARAMETER
TEST CONDITION
VOS
Input Offset Voltage
VCM = −4.5 V and VCM =
4.5 V
TC VOS
Input Offset Voltage
Temperature Drift
VCM = −4.5 V and VCM = 4.5 V (4)
TA = –40°C to +125°C
VCM = −4.5 V (5)
IB
Input Bias Current
MIN (2)
TYP (3)
MAX (2)
−5
±0.7
+5
−6
±2
−2.0
TA = –40°C to +125°C
+6
−1.2
0.45
TA = –40°C to +125°C
IOS
Input Offset Current
VCM = −4.5 V and VCM =
4.5 V
−5 V ≤ VCM ≤ 3 V
CMRR
Common Mode
Rejection Ratio
−5 V ≤ VCM ≤ 5 V
PSRR
Power Supply Rejection
Ratio
2.7 V ≤ VS ≤ 30 V,
VCM = −4.5 V
Common-Mode Voltage
Range (Min)
CMRR > 50 dB
Common-Mode Voltage
Range (Max)
CMRR > 50 dB
CMVR
AVOL
Open-Loop Voltage
Gain
Output Voltage Swing
High
−4 V ≤ VO ≤ 4 V
RL = 10 kΩ to 0 V
−4 V ≤ VO ≤ 4 V
RL = 2 kΩ to 0 V
RL = 10 kΩ to 0 V
VID = 100 mV
IOUT
(1)
(2)
(3)
(4)
(5)
(6)
Output Current
Sourcing
VID = 200 mV, VOUT = −5
V (6)
Sinking
VID = −200 mV, VOUT = 5
V (6)
5.3
80
70
65
TA = –40°C to +125°C
250
280
160
350
450
35
200
250
80
TA = –40°C to +125°C
mV
from
either
rail
200
250
35
70
20
50
TA = –40°C to +125°C
dB
74
100
TA = –40°C to +125°C
V
5
68
TA = –40°C to +125°C
−5.1
−5
74
RL = 10 kΩ to 0 V
VID = −100 mV
dB
74
5.1
TA = –40°C to +125°C
RL = 2 kΩ to 0 V
VID = −100 mV
104
−5.3
TA = –40°C to +125°C
dB
80
TA = –40°C to +125°C
TA = –40°C to +125°C
nA
62
78
TA = –40°C to +125°C
µA
100
70
65
TA = –40°C to +125°C
200
300
80
RL = 2 kΩ to 0 V
VID = 100 mV
VOUT
Output Voltage Swing
Low
20
TA = –40°C to +125°C
1
1.5
TA = –40°C to +125°C
TA = –40°C to +125°C
mV
µV/°C
−2.5
VCM = 4.5 V (5)
UNIT
85
mA
30
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing into the device.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS ≤ 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
7
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
±5-V Electrical Characteristics (continued)
Unless otherwise specified, all limited ensured for TA = 25°C, V+ = 5 V, V− = −5V, VCM = 0 V, VOUT = 0 V, and RL > 1 MΩ to 0
V.(1)
PARAMETER
LM7321
IS
Supply Current
VCM = −4.5 V
TYP (3)
MAX (2)
1.0
1.3
TA = –40°C to
+125°C
UNIT
2
2.3
LM7322
(7)
MIN (2)
TEST CONDITION
TA = –40°C to
+125°C
2.8
mA
3.8
SR
Slew Rate
AV = +1, VI = 8-V Step
12.3
V/µs
fu
Unity Gain Frequency
RL = 2 kΩ, CL = 20 pF
9
MHz
GBW
Gain Bandwidth
f = 50 kHz
16
MHz
en
Input Referred Voltage
Noise Density
f = 2 kHz
in
Input Referred Current
Noise Density
f = 2 kHz
THD+N
Total Harmonic
Distortion + Noise
CT Rej. Crosstalk Rejection
(7)
14.3
nV/√H
1.35
pA/√H
f = 1 kHz, RL = 100 kΩ, AV = +2
VOUT = 8 VPP
−79
dB
f = 100 kHz, Driver RL = 10 kΩ
60
dB
Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
7.7
±15-V Electrical Characteristics
Unless otherwise specified, all limited ensured for TA = 25°C, V+ = 15 V, V− = −15 V, VCM = 0 V, VOUT = 0 V, and RL > 1 MΩ to
15 V. (1)
PARAMETER
TEST CONDITION
VOS
Input Offset Voltage
VCM = −14.5 V and
VCM = 14.5 V
TC VOS
Input Offset Voltage
Temperature Drift
VCM = −14.5 V and VCM = 14.5 V (4)
VCM = −14.5 V (5)
IB
Input Bias Current
VCM = 14.5 V (5)
IOS
Input Offset Current
VCM = −14.5 V and
VCM = 14.5 V
−15 V ≤ VCM ≤ 12 V
CMRR
Common-Mode Rejection
Ratio
−15 V ≤ VCM ≤ 15 V
PSRR
(1)
(2)
(3)
(4)
(5)
8
Power Supply Rejection
Ratio
–40°C to +125°C
MIN (2)
TYP (3)
MAX (2)
−6
±0.7
+6
−8
±2
−2
–40°C to +125°C
+8
mV
µV/°C
−1.1
−2.5
0.45
1
30
300
–40°C to +125°C
µA
1.5
–40°C to +125°C
500
80
–40°C to +125°C
UNIT
100
75
72
–40°C to +125°C
70
2.7 V ≤ VS ≤ 30 V, VCM
= −14.5 V
–40°C to +125°C
78
74
nA
80
100
dB
dB
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing into the device.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
±15-V Electrical Characteristics (continued)
Unless otherwise specified, all limited ensured for TA = 25°C, V+ = 15 V, V− = −15 V, VCM = 0 V, VOUT = 0 V, and RL > 1 MΩ to
15 V.(1)
PARAMETER
Common-Mode Voltage
Range (Min)
TEST CONDITION
CMRR > 50 dB
CMVR
Common-Mode Voltage
Range (Max)
CMRR > 50 dB
−13 V ≤ VO ≤ 13 V
RL = 10 kΩ to 0 V
AVOL
Open-Loop Voltage Gain
Output Voltage Swing
High
Output Voltage Swing
Low
IOUT
Output Current
Supply Current
–40°C to +125°C
RL = 10 kΩ to 0 V
VID = 100 mV
–40°C to +125°C
15.3
RL = 10 kΩ to 0 V
VID = −100 mV
–40°C to +125°C
RL = 2 kΩ to 0 V
VID = −100 mV
–40°C to +125°C
65
130
Sinking
VID = −200 mV, VOUT = 15 V (6)
60
100
Unity Gain Frequency
RL = 2 kΩ, CL = 20 pF
Gain Bandwidth
f = 50 kHz
en
Input Referred Voltage
Noise Density
f = 2 kHz
in
Input Referred Current
Noise Density
f = 2 kHz
THD+N
Total Harmonic Distortion
+Noise
f = 1 kHz, RL 100 kΩ,
AV = +2, VOUT = 23 VPP
mV
from
either
rail
300
400
65
GBW
200
250
40
fu
550
650
Sourcing
VID = 200 mV, VOUT = −15 V (6)
AV = +1, VI = 20-V Step
300
350
60
VCM = −14.5 V
V
dB
78
250
–40°C to +125°C
UNIT
85
150
RL = 2 kΩ to 0 V
VID = 100 mV
Slew Rate (7)
(7)
−15.1
70
70
–40°C to +125°C
SR
(6)
−15.3
15
75
–40°C to +125°C
LM7322
CT Rej. Crosstalk Rejection
MAX (2)
−15
15.1
LM7321
IS
TYP (3)
–40°C to +125°C
−13 V ≤ VO ≤ 13 V
RL = 2 kΩ to 0 V
VOUT
MIN (2)
mA
1.1
–40°C to +125°C
2.4
2.5
–40°C to +125°C
f = 100 kHz, Driver RL = 10 kΩ
1.7
4
mA
5.6
18
V/µs
11.3
MHz
20
MHz
15
nV/√H
1.3
pA/√H
−86
dB
60
dB
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS ≤ 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms.
Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
9
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
7.8 Typical Characteristics
Unless otherwise specified: TA = 25°C.
10
10
VOUT from V (V)
1
+
VOUT from V (V)
VS = 2.7V
125°C
85°C
0.1
VS = 2.7V
1
125°C
85°C
0.1
25°C
25°C
-40°C
0.01
0.1
1
-40°C
10
0.01
0.1
100
1
ISOURCE (mA)
Figure 1. Output Swing vs. Sourcing Current
10
VOUT from V (V)
VS = ±5V
1
+
VOUT from V (V)
100
Figure 2. Output Swing vs. Sinking Current
10
125°C
85°C
0.1
10
ISINK (mA)
VS = ±5V
1
125°C
0.1
85°C
25°C
25°C
-40°C
-40°C
0.01
0.1
1
10
0.01
0.1
100
1
ISOURCE (mA)
Figure 3. Output Swing vs. Sourcing Current
100
Figure 4. Output Swing vs. Sinking Current
10
10
VS = ±15V
VOUT from V (V)
VS = ±15V
1
+
VOUT from V (V)
10
ISINK (mA)
125°C
85°C
0.1
25°C
1
125°C
0.1
85°C
-40°C
25°C
-40°C
0.01
0.1
1
10
100
0.01
0.1
ISOURCE (mA)
10
100
ISINK (mA)
Figure 5. Output Swing vs. Sourcing Current
10
1
Figure 6. Output Swing vs. Sinking Current
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
-0.5
12
VS = ±5V
10
-0.9
-1.1
8
VOS (mV)
PERCENTAGE (%)
VS = 2.7V
-0.7
6
4
-40°C
-1.3
-1.5
25°C
-1.7
85°C
-1.9
-2.1
2
125°C
-2.3
0
-2.5
-2
-3
-1
0
1
2
3
-1
0
1
VOS (mV)
2
3
4
VCM (V)
Figure 7. VOS Distribution
Figure 8. VOS vs. VCM (Unit 1)
0
-0.5
VS = 2.7V
VS = 2.7V
-0.7
-0.1
-40°C
-0.9
-0.2
VOS (mV)
VOS (mV)
-1.1
-0.3
85°C
-0.4
-40°C
-0.5
125°C
-0.6
-0.8
-1
-1.7
85°C
-2.1
125°C
125°C
-2.3
-40°C
0
25°C
-1.5
-1.9
25°C
-0.7
-1.3
1
2
3
-2.5
4
-1
0
1
VCM (V)
2
3
4
VCM (V)
Figure 9. VOS vs. VCM (Unit 2)
Figure 10. VOS vs. VCM (Unit 3)
-1
-0.3
VS = ±5V
VS = ±5V
-1.25
-0.4
-40°C
85°C
VOS (mV)
VOS (mV)
-1.5
25°C
-1.75
85°C
-0.5
-40°C
-0.6
125°C
-2
125°C
-0.7
-2.25
-2.5
-6
-4
25°C
-2
0
2
4
6
-0.8
-6
VCM (V)
-4
-2
0
0
4
6
VCM (V)
Figure 11. VOS vs. VCM (Unit 1)
Figure 12. VOS vs. VCM (Unit 2)
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
11
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
-0.5
-1
VS = ±15V
VS = ±5V
-0.75
-40°C
-1.25
VOS (mV)
VOS (mV)
-1.25
-40°C
-1
25°C
-1.5
-1.75
85°C
-1.5
25°C
-1.75
85°C
125°C
-2
125°C
-2
-2.25
-2.5
-6
-4
-2
2
0
4
-2.25
-20 -15 -10
6
-5
0
-0.7
15
20
VS = ±15V
-0.9
-40°C
125°C
85°C
-0.3
-1.1
-0.4
VOS (mV)
VOS (mV)
10
-0.5
VS = ±15V
-0.2
25°C
-0.5
-40°C
-0.6
-1.3
25°C
-1.5
-1.7
-0.7
-1.9
-0.8
-2.1
-0.9
85°C
125°C
-2.3
-1
-20 -15
-10
-5
0
5
15
20
-10
-5
0
5
10
15
VCM (V)
Figure 15. VOS vs. VCM (Unit 2)
Figure 16. VOS vs. VCM (Unit 3)
20
0
VCM = V +0.5V
-40°C
-1.3
10
-2.5
-20 -15
VCM (V)
-1.1
VCM = V +0.5V
-0.1
-1.5
-0.2
25°C
VOS (mV)
VOS (mV)
5
Figure 14. VOS vs. VCM (Unit 1)
Figure 13. VOS vs. VCM (Unit 2)
-0.1
0
VCM (V)
VCM (V)
-1.7
-1.9
85°C
125°C
-2.1
-0.3
-0.4
85°C
25°C
-0.5
-2.3
-0.6
-2.5
-0.7
-40°C
125°C
0
10
20
30
40
0
10
15
20
25
30
35
40
VS (V)
VS (V)
Figure 17. VOS vs. VS (Unit 1)
12
5
Submit Documentation Feedback
Figure 18. VOS vs. VS (Unit 2)
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
-1
0
VCM = V +0.5V
+
VCM = V -0.5V
-1.2
-0.5
VOS (mV)
VOS (mV)
-40°C
-1
25°C
-1.5
-40°C
-1.4
-1.6
25°C
85°C
-2
85°C
-1.8
125°C
125°C
-2.5
-2
0
5
10
15
20
25
30
35
40
5
0
10
15
20
0
35
40
-1
+
VCM = V -0.5V
VCM = V+ -0.5V
-1.2
-0.2
-40°C
-0.3
-1.4
-0.4
VOS (mV)
VOS (mV)
30
Figure 20. VOS vs. VS (Unit 1)
Figure 19. VOS vs. VS (Unit 3)
-0.1
25
VS (V)
VS (V)
85°C
-0.5
125°C
-0.6
-1.6
25°C
-1.8
-0.7
25°C
-0.8
-1
0
5
10
15
20
25
30
85°C
-2
-40°C
-0.9
35
-2.2
40
125°C
5
0
10
15
20
VS (V)
25
30
35
40
VS (V)
Figure 21. VOS vs. VS (Unit 2)
Figure 22. VOS vs. VS (Unit 3)
1
1
VS = 2.7V
-40°C
VS = ±5V
25°C
0.5
0.5
IBAIS (PA)
IBIAS (PA)
85°C 125°C
0
-0.5
0
-0.5
125°C
-1
85°C
25°C
-1
-1.5
0
0.5
1
1.5
2
2.5
3
-1.5
-5
VCM (V)
-40°C
-3
-1
1
3
5
VCM (V)
Figure 23. IBIAS vs. VCM
Figure 24. IBIAS vs. VCM
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
13
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
-1
1
VCM = V +0.5V
VS = ±15V
-1.1
0.5
85°C
125°C
0
IBIAS (PA)
IBIAS (PA)
-1.2
-0.5
-40°C
-1.4
85°C
125°C
25°C
-1.3
-1
-1.5
-1.5
-15
-40°C
25°C
-10
-5
0
5
10
-1.6
15
0
5
10
15
VCM (V)
-40°C
VS = 2.7V
40
125°C
85°C
0.55
0.5
25°C
25°C
1
0.8
-40°C
85°C
0.45
0.6
125°C
0.4
0.4
0.35
0.2
0
-1
0.3
0
10
20
30
40
0
1
VS (V)
2
3
4
VCM (V)
Figure 27. IBIAS vs. VS
Figure 28. IS vs. VCM (LM7321)
3.5
2
125°C
1.8
3
VS = ±5V
1.6
85°C
2.5
1.4
25°C
2
IS (mA)
IS (mA)
35
1.2
IS (mA)
IBIAS (PA)
1.6
1.4
0.6
30
1.8
+
VCM = V -0.5V
0.65
25
Figure 26. IBIAS vs. VS
Figure 25. IBIAS vs. VCM
0.7
20
VS (V)
-40°C
1.5
1.2
125°C
85°C
1
25°C
0.8
0.6
1
-40°C
0.4
0.5
0.2
VS = 2.7V
0
-1
0
1
2
3
4
0
-6
VCM (V)
-2
0
2
4
6
VCM (V)
Figure 29. IS vs. VCM (LM7322)
14
-4
Submit Documentation Feedback
Figure 30. IS vs. VCM (LM7321)
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
4
2.5
VS = ±5V
VS = ±15V
3.5
2
3
125°C
IS (mA)
IS (mA)
2.5
85°C
2
25°C
1.5
1.5
125°C
85°C
1
25°C
-40°C
1
-40°C
0.5
0.5
0
-6
-4
-2
2
0
4
0
-20 -15 -10
6
-5
VCM (V)
Figure 31. IS vs. VCM (LM7322)
4.5
VS = ±15V
3.5
15
20
-
125°C
1.2
3
85°C
1
25°C
IS (mA)
IS (mA)
10
VCM = V +0.5V
1.4
85°C
2
5
Figure 32. IS vs. VCM (LM7321)
1.6
4
2.5
0
VCM (V)
25°C
25°C
0.8
-40°C
0.6
1.5
-40°C
0.4
1
0.2
0.5
0
-20 -15 -10
-5
0
5
10
15
0
20
0
5
10
15
VCM (V)
25
20
30
30
40
VS (V)
Figure 33. IS vs. VCM (LM7322)
Figure 34. IS vs. VS (LM7321)
2.5
4.5
+
VCM = V -0.5V
4
2
125°C
3.5
85°C
125°C
85°C
25°C
2.5
IS (mA)
IS (mA)
3
-40°C
2
1.5
25°C
1
-40°C
1.5
1
0.5
0.5
0
+
VCM = V -0.5V
0
5
10
15
20
25
30
35
40
0
0
VS (V)
5
10
15
20
25
30
35
40
VS (V)
Figure 35. IS vs. VS (LM7322)
Figure 36. IS vs. VS (LM7321)
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
15
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
3
0.3
85°C
RL = 2 k:
125°C
2.5
125°C
0.25
85°C
25°C
1.5
-40°C
1
0.2
-40°C
0.15
0.1
0.05
0.5
0
25°C
VOUT from RAIL (V)
IS (mA)
2
VCM = V +0.5V
5
0
10
15
20
25
30
35
0
40
0
10
20
30
40
VS (V)
VS (V)
Figure 37. IS vs. VS (LM7322)
Figure 38. Positive Output Swing vs. Supply Voltage
0.16
0.16
125°C
RL = 10 k:
RL = 2 k:
125°C
0.14
0.14
0.12
VOUT from RAIL (V)
85°C
0.1
25°C
0.08
-40°C
0.06
0.04
0.12
25°C
0.1
-40°C
0.08
0.06
0.04
0.02
0.02
0
0
5
10
15
20
25
30
35
0
40
0
10
20
VS (V)
30
Figure 39. Positive Output Swing vs. Supply Voltage
Figure 40. Negative Output Swing vs. Supply Voltage
0.07
140
158
VS = r15V
RL = 10 M: 135
RL = 10 k:
120
125°C
100
0.05
85°C
0.04
GAIN (dB)
VOUT from RAIL (V)
0.06
25°C
0.03
-40°C
PHASE
80
60
40
68
45
0
30
90
20 pF
50 pF
100 pF
200 pF
23
0
500 pF
1000 pF
0
20
100 pF
50 pF
40
20
-20
1k
VS (V)
113
200 pF
GAIN
0.01
10
1000 pF
500 pF
0.02
0
40
VS (V)
10k
100k
PHASE (q)
VOUT from RAIL (V)
85°C
1M
10M
-23
100M
FREQUENCY (Hz)
Figure 41. Negative Output Swing vs. Supply Voltage
16
Figure 42. Open-Loop Frequency Response with Various
Capacitive Load
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
120
PHASE
120
113
100
600:
100
140
158
VS = r15V
CL = 20 pF 135
158
RL = 2 k:
CL = 20 pF 135
PHASE
113
VS = 30V
90
10 k:
60
68
GAIN
40
100 k:
2 k:
600:
20
45
10 M:
0
-20
1k
10k
100k
1M
80
GAIN
40
20
0
0
68
VS = 30V
45
VS = 2.7V
23
0
VS = 10V
-20
1k
10k
100k
1M
10M
-23
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43. Open-Loop Frequency Response with Various
Resistive Load
Figure 44. Open-Loop Frequency Response with Various
Supply Voltage
100
70
VS = ±15V
90
60
RL = 600:
80
50
70
RL = 2 k:
CMRR (dB)
PHASE MARGIN (°)
90
VS = 10V
VS = 2.7V
60
23
-23
100M
10M
GAIN (dB)
80
PHASE (q)
GAIN (dB)
2 k:
PHASE (q)
140
40
30
RL = 10 M:, 10 k:, 100 k:
60
50
40
30
20
20
10
10
VS = ±15V
0
10
0
10
1000
100
10k
1k
100k
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
Figure 45. Phase Margin vs. Capacitive Load
Figure 46. CMRR vs. Frequency
120
100
VS = 2.7V
VCM = 2V
80
VS = 10V
VCM = 8V
-PSRR (dB)
80
1M
VS = 30V
90
VCM = 0.7V
100
+PSRR (dB)
100
VS = 30V
60 VCM = 28V
40
70 VS = 10V
VCM = 2V
60
50
VS = 2.7V
VCM = 2V
40
30
20
20
10
0
10
100
1k
10k
100k
1M
0
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 47. +PSRR vs. Frequency
Figure 48. −PSRR vs. Frequency
1M
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
17
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
12,200 pF
VS = ±5V
1000 pF
AV = +1
8,600 pF
100 mV/DIV
750 pF
25V/DIV
500 pF
330 pF
VS = ±15V, AV = +1
2,200 pF
100 pF
10 pF
10 pF
INPUT
INPUT
200 ns/DIV
5 Ps/DIV
Figure 49. Small Signal Step Response
1000
Figure 50. Large Signal Step Response
1000
100
100
VOLTAGE
1
10
CURRENT
1
1
10
100
1k
10k
VOLTAGE NOISE (nV Hz)
10
CURRENT NOISE (pA/ Hz)
VOLTAGE NOISE (nV Hz)
100
100
10
CURRENT
VOLTAGE
1
10
0.1
100k
1
1
10
FREQUENCY (Hz)
100
1k
10k
CURRENT NOISE (pA/ Hz)
VS = ±5V
VS = 2.7V
0.1
100k
FREQUENCY (Hz)
Figure 51. Input Referred Noise Density vs. Frequency
1000
Figure 52. Input Referred Noise Density vs. Frequency
100
0
AV = +2
VS = ±15V
10
CURRENT
VOLTAGE
1
10
RL = 100 k:
-20
THD+N (dB)
100
CURRENT NOISE (pA/ Hz)
VOLTAGE NOISE (nV Hz)
-10 VIN = 520 mVPP
-30
-40
-50
VS = 2.7V, VCM = 0.8V
-60
-70
1
1
10
100
1k
10k
0.1
100k
VS = ±15V
-80
10
FREQUENCY (Hz)
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 53. Input Referred Noise Density vs. Frequency
18
VS = ±5V
Submit Documentation Feedback
Figure 54. THD+N vs. Frequency
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C.
0
0
VS = 2.7V
VS = ±5V
-10 f = 1 kHz
-10 VCM = 0.8V
-20
f = 1 kHz
-20
-30 A = +2
V
-40
-30
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
0.001
0.01
RL = 100 k:
AV = +2
THD+N (dB)
THD+N (dB)
RL = 100 k:
0.1
1
-90
0.001
10
0.01
0.1
1
10
100
OUTPUT AMPLITUDE (VPP)
OUTPUT AMPLITUDE (VPP)
Figure 56. THD+N vs. Output Amplitude
Figure 55. THD+N vs. Output Amplitude
0
VS = ±15V
-10 f = 1 kHz
-20
RL = 100 k:
AV = +2
THD+N (dB)
-30
-40
-50
-60
-70
-80
-90
0.001
0.01
0.1
1
10
100
OUTPUT AMPLITUDE (VPP)
Figure 57. THD+N vs. Output Amplitude
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
19
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The LM732xx devices are rail-to-rail input and output amplifiers with wide operating voltages and high-output
currents. The LM732xx family is efficient, achieving 18-V/µs slew rate and 20-MHz unity gain bandwidth while
requiring only 1 mA of supply current per op amp. The LM732xx device performance is fully specified for
operation at 2.7 V, ±5 V and ±15 V.
The LM732xx devices are designed to drive unlimited capacitive loads without oscillations. All LM7321x and
LM7322x parts are tested at −40°C, 125°C, and 25°C, with modern automatic test equipment. High performance
from −40°C to 125°C, detailed specifications, and extensive testing makes them suitable for industrial,
automotive, and communications applications.
Greater than rail-to-rail input common-mode voltage range with 50 dB of common-mode rejection across this
wide voltage range, allows both high-side and low-side sensing. Most device parameters are insensitive to power
supply voltage, and this makes the parts easier to use where supply voltage may vary, such as automotive
electrical systems and battery-powered equipment. These amplifiers have true rail-to-rail output and can supply a
respectable amount of current (15 mA) with minimal head room from either rail (300 mV) at low distortion (0.05%
THD+Noise).
8.2 Functional Block Diagram
V+
-IN
±
OUT
+IN
+
V-
8.3 Feature Description
8.3.1 Output Short Circuit Current and Dissipation Issues
The LM732xx output stage is designed for maximum output current capability. Even though momentary output
shorts to ground and either supply can be tolerated at all operating voltages, longer lasting short conditions can
cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher
supply voltage conditions. Below supply voltage of 6 V, the output short circuit condition can be tolerated
indefinitely.
With the op amp tied to a load, the device power dissipation consists of the quiescent power due to the supply
current flow into the device, in addition to power dissipation due to the load current. The load portion of the
power itself could include an average value (due to a DC load current) and an AC component. DC load current
would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the op amp
operates in a single supply application where the output is maintained somewhere in the range of linear
operation.
Therefore,
PTOTAL = PQ + PDC + PAC
20
(1)
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
Feature Description (continued)
The Op Amp Quiescent Power Dissipation is calculated as:
PQ = IS × VS
where
•
•
IS: Supply Current
VS: Total Supply Voltage (V+ − V−)
(2)
The DC Load Power is calculated as:
PDC = IO × (Vr - Vo)
where
•
•
VO: Average Output Voltage
Vr: V+ for sourcing and V− for sinking current
(3)
The AC Load Power is calculated as PAC = See Table 1.
Table 1 shows the maximum AC component of the load power dissipated by the op amp for standard Sinusoidal,
Triangular, and Square Waveforms:
Table 1. Normalized AC Power Dissipated in the Output Stage for Standard Waveforms
PAC (W.Ω/V2)
Sinusoidal
Triangular
Square
50.7 × 10−3
46.9 × 10−3
62.5 × 10−3
The table entries are normalized to VS2/RL. To figure out the AC load current component of power dissipation,
simply multiply the table entry corresponding to the output waveform by the factor VS2/RL. For example, with ±12V supplies, a 600-Ω load, and triangular waveform power dissipation in the output stage is calculated as:
PAC = (46.9 × 10−3) × (242/600) = 45.0 mW
(4)
The maximum power dissipation allowed at a certain temperature is a function of maximum die junction
temperature (TJ(MAX)) allowed, ambient temperature TA, and package thermal resistance from junction to ambient,
θJA.
TJ(MAX) - TA
PD(MAX) =
TJA
(5)
For the LM732xx, the maximum junction temperature allowed is 150°C at which no power dissipation is allowed.
The power capability at 25°C is given by the following calculations:
For VSSOP package:
PD(MAX) =
150°C ± 25°C
= 0.53 W
235°C/W
(6)
For SOIC package:
PD(MAX) =
150°C ± 25°C
= 0.76 W
165°C/W
(7)
Similarly, the power capability at 125°C is given by:
For VSSOP package:
PD(MAX) =
150°C ± 125°C
= 0.11 W
235°C/W
(8)
For SOIC package:
PD(MAX) =
150°C ± 125°C
= 0.15 W
165°C/W
(9)
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
21
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Figure 58 shows the power capability vs. temperature for VSSOP and SOIC packages. The area under the
maximum thermal capability line is the operating area for the device. When the device works in the operating
area where PTOTAL is less than PD(MAX), the device junction temperature will remain below 150°C. If the
intersection of ambient temperature and package power is above the maximum thermal capability line, the
junction temperature will exceed 150°C and this should be strictly prohibited.
1.4
POWER CAPABILITY (W)
1.2
M
1
ax
im
um
0.8
Ma
0.6
um
0.4
0.2
th
e
the
rm
al
ca
Operating area
0
-40 -20 0
rm
al
xi m
pa
bil
ca
p
ity
ab
lin
i li t
y
e(
li n
e
(S
O
IC
)
MS
OP
)
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
Figure 58. Power Capability vs. Temperature
When high power is required and ambient temperature can't be reduced, providing air flow is an effective
approach to reduce thermal resistance therefore to improve power capability.
8.3.2 Estimating the Output Voltage Swing
It is important to keep in mind that the steady-state output current will be less than the current available when
there is an input overdrive present. For steady-state conditions, the Output Voltage vs. Output Current plot
(Typical Characteristics section) can be used to predict the output swing. Figure 59 and Figure 60 show this
performance along with several load lines corresponding to loads tied between the output and ground. In each
cases, the intersection of the device plot at the appropriate temperature with the load line would be the typical
output swing possible for that load. For example, a 1-kΩ load can accommodate an output swing to within 250
mV of V− and to 330 mV of V+ (VS = ±15 V) corresponding to a typical 29.3 VPP unclipped swing.
Figure 59. Output Sourcing Characteristics With Load
Lines
22
Figure 60. Output Sinking Characteristics With Load Lines
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
8.4 Device Functional Modes
8.4.1 Driving Capacitive Loads
The LM732xx are specifically designed to drive unlimited capacitive loads without oscillations as shown in
Figure 61.
Figure 61. ±5% Settling Time vs. Capacitive Load
In addition, the output current handling capability of the device allows for good slewing characteristics even with
large capacitive loads as shown in Figure 62 and Figure 63.
Figure 62. +SR vs. Capacitive Load
Figure 63. −SR vs. Capacitive Load
The combination of these features is ideal for applications such as TFT flat panel buffers, A/D converter input
amplifiers, and so forth.
However, as in most op amps, addition of a series isolation resistor between the op amp and the capacitive load
improves the settling and overshoot performance.
Output current drive is an important parameter when driving capacitive loads. This parameter will determine how
fast the output voltage can change. Referring to the Slew Rate vs. Capacitive Load Plots (Typical Characteristics
section), two distinct regions can be identified. Below about 10,000 pF, the output Slew Rate is solely determined
by the compensation capacitor value of the op amp and available current into that capacitor. Beyond 10 nF, the
Slew Rate is determined by the available output current of the op amp.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
23
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Device Functional Modes (continued)
NOTE
Because of the lower output sourcing current compared to the sinking one, the Slew Rate
limit under heavy capacitive loading is determined by the positive transitions.
An estimate of positive and negative slew rates for loads larger than 100 nF can be made by dividing the short
circuit current value by the capacitor.
For the LM732xx, the available output current increases with the input overdrive. Referring to Figure 64 and
Figure 65, it can be seen that both sourcing and sinking short circuit current increase as input overdrive
increases. In a closed-loop amplifier configuration, during transient conditions while the fed back output has not
quite caught up with the input, there will be an overdrive imposed on the input allowing more output current than
would normally be available under steady-state condition. Because of this feature, the output stage quiescent
current of the op amp can be kept to a minimum, thereby reducing power consumption, while enabling the device
to deliver large output current when the need arises (such as during transients).
Figure 64. Output Short Circuit Sourcing Current vs. Input
Overdrive
Figure 65. Output Short Circuit Sinking Current vs. Input
Overdrive
Figure 66 shows the output voltage, output current, and the resulting input overdrive with the device set for AV =
+1 and the input tied to a 1-VPP step function driving a 47-nF capacitor. As can be seen, during the output
transition, the input overdrive reaches 1-V peak and is more than enough to cause the output current to increase
to its maximum value (see Figure 64 and Figure 65 plots).
NOTE
Because of the larger output sinking current compared to the sourcing one, the output
negative transition is faster than the positive one.
Figure 66. Buffer Amplifier Scope Photo
24
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Similar High-Output Devices
The LM7332 is a dual rail-to-rail amplifier with a slightly lower GBW capable of sinking and sourcing 100 mA. It is
available in SOIC and VSSOP packages.
The LM4562 is dual op amp with very low noise and 0.7-mV voltage offset.
The LME49870 and LME49860 are single and dual low-noise amplifiers that can work from ±22-V supplies.
9.1.2 Other High Performance SOT-23 Ampliers
The LM7341 is a 4-MHz rail-to-rail input and output part that requires only 0.6 mA to operate, and can drive
unlimited capacitive load. It has a voltage gain of 97 dB, a CMRR of 93 dB, and a PSRR of 104 dB.
The LM6211 is a 20-MHz part with CMOS input, which runs on ±12-V or 24-V single supplies. It has rail-to-rail
output and low noise.
The LM7121 has a gain bandwidth of 235 MHz.
Detailed information on these parts can be found at www.ti.com.
9.2 Typical Application
Figure 67 shows a typical application where the LM732xx is used as a buffer amplifier for the VCOM signal
employed in a TFT LCD flat panel:
Figure 67. VCOM Driver Application Schematic
9.2.1 Design Requirements
For this example application, the supply voltage is +5 V, and noninverting gain is necessary.
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
25
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
Figure 68 shows the time domain response of the amplifier when used as a VCOM buffer/driver with VREF at
ground. In this application, the op amp loop will try and maintain its output voltage based on the voltage on its
noninverting input (VREF) despite the current injected into the TFT simulated load. As long as this load current is
within the range tolerable by the LM732xx (45-mA sourcing and 65-mA sinking for ±5-V supplies), the output will
settle to its final value within less than 2 μs.
Figure 68. VCOM Driver Performance Scope Photo
9.2.3 Application Curve
CROSSTALK REJECTION (dB)
90
80
70
VS = ±15V
60
50
VS = ±5V
40
+
V = 1.8V
30
VCM = 0.9V
20
10
0
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 69. Crosstalk Rejection vs. Frequency
26
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321, LM7322
www.ti.com
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
10 Power Supply Recommendations
The use of supply decoupling is mandatory in most applications. As with most relatively high-speed or highoutput current op amps, best results are achieved when each supply line is decoupled with two capacitors; a
small value ceramic capacitor ( about 0.01 μF) placed very close to the supply lead in addition to a large value
Tantalum or Aluminum (> 4.7 μF). The large capacitor can be shared by more than one device if necessary. The
small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor will act as
the charge bucket for fast load current spikes at the op amp output. The combination of these capacitors will
provide supply decoupling and will help keep the op amp oscillation free under any load.
11 Layout
11.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. A ground plane underneath the device is recommended; any bypass components to ground should have
a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding
supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the
power supply inductance and provide a more stable power supply.
The feedback components should be placed as close to the device as possible to minimize stray parasitics.
11.2 Layout Example
Figure 70. LM732xx Layout Example
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
27
LM7321, LM7322
SNOSAW8E – MAY 2008 – REVISED SEPTEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM7321
Click here
Click here
Click here
Click here
Click here
LM7322
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Submit Documentation Feedback
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM7321MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM732
1MA
LM7321MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM732
1MA
LM7321MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU4A
LM7321MFE/NOPB
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU4A
LM7321MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AU4A
LM7321QMF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AR8A
LM7321QMFE/NOPB
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AR8A
LM7321QMFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AR8A
LM7322MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM732
2MA
LM7322MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM732
2MA
LM7322MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AZ4A
LM7322MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AZ4A
LM7322QMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM732
2QMA
LM7322QMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM732
2QMA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM7321, LM7321-Q1, LM7322, LM7322-Q1 :
• Catalog: LM7321, LM7322
• Automotive: LM7321-Q1, LM7322-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM7321MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM7321MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LM7321MFE/NOPB
SOT-23
DBV
5
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LM7321MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LM7321QMF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LM7321QMFE/NOPB
SOT-23
DBV
5
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LM7321QMFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LM7322MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM7322MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM7322MME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM7322QMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM7321MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM7321MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LM7321MFE/NOPB
SOT-23
DBV
5
250
210.0
185.0
35.0
LM7321MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LM7321QMF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LM7321QMFE/NOPB
SOT-23
DBV
5
250
210.0
185.0
35.0
LM7321QMFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LM7322MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM7322MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM7322MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LM7322QMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising