Texas Instruments | LMV727x Single and Dual, 1.8-V Low Power Comparators With Rail-to-Rail Input (Rev. I) | Datasheet | Texas Instruments LMV727x Single and Dual, 1.8-V Low Power Comparators With Rail-to-Rail Input (Rev. I) Datasheet

Texas Instruments LMV727x Single and Dual, 1.8-V Low Power Comparators With Rail-to-Rail Input (Rev. I) Datasheet
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LMV7271, LMV7272, LMV7275
SNOSA56I – FEBRUARY 2003 – REVISED SEPTEMBER 2015
LMV727x Single and Dual, 1.8-V Low Power Comparators With Rail-to-Rail Input
1 Features
3 Description
•
The LMV727x devices are rail-to-rail input low power
comparators, characterized at supply voltages 1.8 V,
2.7 V, and 5 V. They consume as little as 9-uA supply
current per channel while achieving a 800-ns
propagation delay.
1
•
•
•
•
•
•
•
•
(VS = 1.8 V, TA = 25°C, Typical Values Unless
Specified).
Single or Dual Supplies
Ultra Low Supply Current 9 µA Per Channel
Low Input Bias Current 10 nA
Low Input Offset Current 200 pA
Low Ensured VOS 4 mV
Propagation Delay 880 ns (20-mV Overdrive)
Input Common Mode Voltage Range 0.1 V
Beyond Rails
LMV7272 is Available in DSBGA Package
The LMV7271 and LMV7275 (single) are available in
SC70 and SOT-23 packages. The LMV7272 (dual) is
available in the DSBGA package. With these tiny
packages, the PCB area can be significantly reduced.
They are ideal for low voltage, low power, and spacecritical designs.
The LMV7271 and LMV7272 both feature a push-pull
output stage which allows operation with minimum
power consumption when driving a load.
2 Applications
•
•
•
•
The LMV7275 features an open-drain output stage
that allows for wired-OR configurations. The opendrain output also offers the advantage of allowing the
output to be pulled to any voltage up to 5.5 V,
regardless of the supply voltage of the LMV7275,
which is useful for level-shifting applications.
Wearable Devices
Mobile Phones and Tablets
Battery-Powered Electronics
General Purpose Low Voltage Applications
The LMV727x devices are built with Texas
Instruments' advance submicron silicon-gate BiCMOS
process. They all have bipolar inputs for improved
noise performance, and CMOS outputs for rail-to-rail
output swing.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMV7271,
LMV7275
SC70 (5)
1.25 mm × 2.00 mm
SOT-23 (5)
1.60 mm × 2.90 mm
LMV7272
DSBGA (8)
1.50 mm x 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Circuit
VIN
VCC
R1
C1 =
0.1µF
C2 =
10µF
+
VOUT
R2
-
VREF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV7271, LMV7272, LMV7275
SNOSA56I – FEBRUARY 2003 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
4
5
5
6
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
1.8-V Electrical Characteristics .................................
1.8-V AC Electrical Characteristics ...........................
2.7-V Electrical Characteristics .................................
2.7-V AC Electrical Characteristics ...........................
5-V Electrical Characteristics ....................................
5-V AC Electrical Characteristics ............................
Typical Characteristics ............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 18
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (February 2013) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Removed Soldering Information from Absolute Maximum Ratings table .............................................................................. 4
Changes from Revision G (February 2013) to Revision H
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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Product Folder Links: LMV7271 LMV7272 LMV7275
LMV7271, LMV7272, LMV7275
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SNOSA56I – FEBRUARY 2003 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
DBV or DGK Package
5-Pin SOT-23 or SC70
Top View
1
5
+IN
+
V
2
GND
-IN
4
3
VOUT
YZR Package
8-Pin DSBGA
Top View
V
OUT A
A1
-IN A
B1
+IN A
C1
+
A2
C2
V
A3
OUT B
B3
-IN B
C3
+ IN B
-
See DSBGA Light Sensitivity and DSBGA Mounting in the Layout Guidelines section for mounting precautions.
Pin Functions
PIN
I/O
DESCRIPTION
SOT-23,
SC70
DSBGA
+IN
1
—
I
Noninverting Input
GND
2
—
P
Negative Supply Voltage
-IN
3
—
I
Invering Input
VOUT
4
—
O
Output
V+
5
A2
P
Positive Supply Voltage
OUT A
—
A1
O
Output, Channel A
-IN A
—
B1
I
Inverting Input, Channel A
+IN A
—
C1
I
Noninverting Input, Channel A
V-
—
C2
P
Negative Supply Voltage
+IN B
—
C3
I
Noninverting Input, Channel B
-IN B
—
B3
I
Inverting Input, Channel B
OUT B
—
A3
O
Output, Channel B
NAME
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
MIN
VIN Differential
MAX
UNIT
±Supply
Voltage
V
6
V
Supply Voltage (V+ - V−)
−
+
Voltage at Input/Output pins
(V ) + 0.1
(V ) − 0.1
V
150
°C
150
°C
Junction Temperature (3)
Storage Temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and
specifications.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
6.2 ESD Ratings
VALUE
UNIT
SOT-23, SC70 PACKAGE
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2000
Machine Model (MM) (3)
±200
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2000
V
DSBGA PACKAGE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Machine Model (MM)
(3)
V
±200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human body model, 1.5 kΩ in series with 100 pF.
Machine Model, 0 Ω in series with 200 pF.
6.3 Recommended Operating Conditions
MIN
MAX
Supply Voltage
1.8
5.5
V
Temperature (1)
–40
85
°C
(1)
UNIT
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
6.4 Thermal Information
LMV7271, LMV7275
THERMAL METRIC
RθJA
(1)
(2)
4
(1)
Junction-to-ambient thermal resistance (2)
LMV7272
DBV (SOT-23)
DGK (SC70)
YZR (DSBGA)
5 PINS
5 PINS
8 PINS
325
265
220
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
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SNOSA56I – FEBRUARY 2003 – REVISED SEPTEMBER 2015
6.5 1.8-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8 V, V− = 0 V.
PARAMETER
VOS
Input Offset Voltage
TC VOS Input Offset Temperature Drift
IB
Input Bias Current
IOS
Input Offset Current
MIN (1)
CONDITION
TYP (2)
MAX (1)
0.3
4
At the temperature extremes
VCM = 0.9 V
(3)
20
uV/°C
10
nA
200
LMV7271/LMV7275
At the temperature
extremes
LMV7272
At the temperature
extremes
Supply Current
ISC
Output Short Circuit Current
mV
6
9
IS
UNIT
pA
12
µA
14
18
25
µA
28
Sourcing, VO = 0.9 V
(LMV7271/LMV7272 only)
3.5
6
4
6
IO = 0.5 mA
1.7
1.74
IO = 1.5 mA
1.47
1.63
Sinking, VO = 0.9 V
mA
VOH
Output Voltage High
(LMV7271/LMV7272 only)
VOL
Output Voltage Low
VCM
Input Common-Mode Voltage
Range
CMRR > 45 dB
CMRR
Common-Mode Rejection Ratio
0 < VCM < 1.8 V
46
78
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
55
80
dB
ILEAKAG
Output Leakage Current
VO = 1.8 V (LMV7275 only)
2
pA
V
IO = −0.5 mA
52
100
IO = −1.5 mA
166
220
mV
1.9
V
−0.1
V
E
(1)
(2)
(3)
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
6.6 1.8-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V −.
PARAMETER
tPHL
tPLH
(1)
(2)
CONDITION
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
MIN (1)
TYP (2)
MAX (1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
880
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
570
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1100
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
800
ns
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
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6.7 2.7-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V.
PARAMETER
MIN (1)
CONDITIONS
TYP (2)
MAX (1)
0.3
4
UNIT
VOS
Input Offset Voltage
TC VOS
Input Offset Temperature Drift
20
µV/°C
IB
Input Bias Current
10
nA
IOS
Input offset Current
200
At the temperature extremes
VCM = 1.35 V (3)
pA
9
IS
LMV7271/LMV7275
At the temperature
extremes
LMV7272
At the temperature
extremes
Supply Current
ISC
Output Short Circuit Current
mV
6
13
µA
15
18
25
µA
28
Sourcing, VO = 1.35 V
(LMV7271/LMV7272 only)
10
15
Sinking, VO = 1.35 V
10
15
IO = 0.5 mA
2.63
2.66
IO = 2.0 mA
2.48
2.55
mA
VOH
Output Voltage High
(LMV7271/LMV7272 only)
VOL
Output Voltage Low
VCM
Input Common Voltage Range
CMRR > 45 dB
CMRR
Common-Mode Rejection Ratio
0 < VCM < 2.7 V
46
78
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
55
80
dB
ILEAKAGE
Output Leakage Current
VO = 2.7 V (LMV7275 only)
2
pA
(1)
(2)
(3)
IO = −0.5 mA
IO = −2 mA
V
50
70
155
220
mV
2.8
V
−0.1
V
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
6.8 2.7-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V −.
PARAMETER
tPHL
tPLH
(1)
(2)
6
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
CONDITION
MIN (1)
TYP (2)
MAX (1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1200
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
810
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1300
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
860
ns
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
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SNOSA56I – FEBRUARY 2003 – REVISED SEPTEMBER 2015
6.9 5-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V.
PARAMETER
VOS
Input Offset Voltage
TC VOS
Input Offset Temperature Drift
IB
Input Bias Current
IOS
Input Offset Current
MIN (1)
CONDITIONS
TYP (2)
MAX (1)
0.3
4
At the temperature extremes
VCM = 2.5 V (3)
20
µV/°C
10
nA
200
LMV7271/LMV7275
At the temperature
extremes
LMV7272
At the temperature
extremes
Supply Current
ISC
Output Short Circuit Current
pA
14
18
34
Sinking, VO = 2.5 V
18
34
IO = 0.5 mA
4.93
4.96
IO = 4.0 mA
4.675
4.77
VOL
Output Voltage Low
VCM
Input Common Voltage Range
CMRR > 45 dB
CMRR
Common-Mode Rejection Ratio
0 < VCM < 5.0 V
27
µA
30
Sourcing, VO = 2.5 V
(LMV7271/LMV7272 only)
Output Voltage High
(LMV7271/LMV7272 only)
µA
16
20
VOH
mA
V
IO = −0.5 mA
27
70
IO = −4.0 mA
225
315
mV
5.1
V
−0.1
+
PRSS
Power Supply Rejection Ratio
V = 1.8 V to 5 V
ILEAKAGE
Output Leakage Current
VO = 5 V (LMV7275 only)
(1)
(2)
(3)
mV
6
10
IS
UNIT
46
78
dB
55
80
dB
2
pA
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
6.10 5-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5.0 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V −.
PARAMETER
tPHL
tPLH
(1)
(2)
CONDITION
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
MIN (1)
TYP (2)
MAX (1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
2100
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
1380
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1800
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
1100
ns
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
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6.11 Typical Characteristics
TA = 25°C, Unless otherwise specified.
VSUPPLY = ±0.9V
800
800
VSUPPLY = ±1.35V
-40°C
-40°C
400
400
VOS (PV)
VOS (PV)
25°C
0
0
85°C
-400
-400
25°C
85°C
-800
-800
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
-1.35
-0.9
-0.45
0
VCM (V)
VSUPPLY = ±2.5V
400
VOS (PV)
-40°C
0
-400
25°C
85°C
-800
-2.5 -2
-1
0.9
1.35
Figure 2. VOS vs. VCM
SHORT CIRCUIT OUTPUT CURRENT (mA)
Figure 1. VOS vs. VCM
800
0.45
VCM (V)
0
1
2 2.5
40
SOURCE
30
20
SINK
10
0
1.8
2.44
VCM (V)
3.08
3.72
4.36
5.0
SUPPLY VOLTAGE (V)
Figure 3. VOS vs. VCM
Figure 4. Short Circuit vs. Supply Voltage
25
10
9
SUPPLY CURRENT (PA)
SUPPLY CURRENT (PA)
85°C
85°C
85°C
8
25°C
7
6
20
15
25°C
10
-40°C
5
-40°C
VOUT = HIGH
0
5
1.8
2.44
3.08
3.72
4.36
5.0
1.5
2
8
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3
3.5
4
4.5
5
VSUPPLY (V)
SUPPLY VOLTAGE (V)
Figure 5. Supply Current vs. Supply Voltage (LMV7271)
2.5
Figure 6. Supply Current vs. Supply Voltage (LMV7272)
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Typical Characteristics (continued)
TA = 25°C, Unless otherwise specified.
600
25
20
500
V - VOUT (mV)
15
10
25°C
+
SUPPLY CURRENT (PA)
ISOURCE
85°C
-40°C
400
4mA
300
2mA
200
1.5mA
5
100
0.5mA
VOUT = LOW
0
0
1.5
2
2.5
3
3.5
4
1.8
5
4.5
2.3
2.8
3.3
3.8
4.3
4.8
VSUPPLY (V)
VSUPPLY (V)
Figure 8. Output Positive Swing vs. VSUPPLY
Figure 7. Supply Current vs. Supply Voltage (LMV7272)
600
0.8
VSUPPLY = 1.8V
ISINK
0.7
500
85°C
V - VOUT (V)
400
4mA
-
VOUT - V (mV)
0.6
300
+
2mA
200
0.5
25°C
0.4
0.3
1.5mA
0.2
-40°C
100
0.1
0.5mA
0
0
1.8
2.3
2.8
3.3
3.8
4.3
4.8
0
0.5
1
1.5
2
2.5
3
3.5
4
ISOURCE (mA)
VSUPPLY (V)
Figure 9. Output Negative Swing vs. VSUPPLY
Figure 10. Output Positive Swing vs. ISOURCE
0.5
0.8
VSUPPLY = 1.8V
VSUPPLY = 2.7V
0.45
0.7
85°C
85°C
0.4
0.6
V - VOUT (V)
-
VOUT - V (V)
0.35
0.5
25°C
+
0.4
0.3
25°C
0.3
0.25
0.2
0.15
0.2
-40°
0.1
-40°C
0.1
0.05
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
ISINK (mA)
Figure 11. Output Negative Swing vs. ISINK
1
1.5
2
2.5
3
3.5
4
ISOURCE (mA)
Figure 12. Output Positive Swing vs. ISOURCE
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Typical Characteristics (continued)
TA = 25°C, Unless otherwise specified.
0.5
0.4
VSUPPLY = 2.7V
0.45
VSUPPLY = 5V
85°C
85°C
0.4
0.35
25°C
-
0.3
VOUT - V (V)
-
VOUT - V (V)
0.3
25°C
0.25
0.2
0.2
0.15
0.1
0.1
-40°C
-40°C
0.05
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0.5
0
1
1.5
Figure 13. Output Negative Swing vs. ISINK
VSUPPLY = 5V
85°C
25°C
INPUT VOLTAGE
(mV)
-40°C
0
0
4
VCC = 1.8V
TEMP = 25°C
LOAD = 5k: 50pF
4
3
50mV
20mV
2
1
|
0.5
1
1.5
2
2.5
3
3.5
|
100
0
OVERDRIVE
-100
4
0
500
1000
OUTPUT VOLTAGE
(V)
5
VCC = 1.8 V
4 TEMP = 25°C
3 LOAD = 5k: 50pF
50mV
1
2500 3000
Figure 16. Propagation Delay (tPLH)
Figure 15. Output Positive Swing vs. ISOURCE
2
1500 2000
TIME (ns)
ISOURCE (mA)
OUTPUT VOLTAGE
(V)
3.5
0
0.2
0.1
20mV
5
VCC = 2.7V
TEMP = 25°C
LOAD = 5k: 50pF
4
3
50mV
2
20mV
1
0
|
|
100
OVERDRIVE
0
-100
500
1000
1500
2000 2500 3000
INPUT VOLTAGE
(mV)
0
INPUT VOLTAGE
(mV)
3
5
+
V - VOUT (V)
0.3
10
2.5
Figure 14. Output Negative Swing vs. ISINK
OUTPUT VOLTAGE
(V)
0.4
0
2
ISINK (mA)
ISINK (mA)
|
|
100
0
OVERDRIVE
-100
0
500
1000
1500 2000 2500 3000
TIME (ns)
TIME (ns)
Figure 17. Propagation Delay (tPHL)
Figure 18. Propagation Delay (tPLH)
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Typical Characteristics (continued)
5
VCC = 2.7 V
TEMP = 25°C
LOAD = 5k: 50pF
4
3
2
50mV
1
5
OUTPUT VOLTAGE
(V)
OUTPUT VOLTAGE
(V)
TA = 25°C, Unless otherwise specified.
20mV
VCC = 5.0V
TEMP = 25°C
3 LOAD = 5k: 50pF
20mV
2
1
0
|
|
100
INPUT VOLTAGE
(mV)
INPUT VOLTAGE
(mV)
0
OVERDRIVE
0
-100
0
500
1000 1500
|
|
100
0
OVERDRIVE
-100
2000 2500 3000
0
500
1000 1500 2000
TIME (ns)
Figure 20. Propagation Delay (tPLH)
5
8
VCC = 5.0 V
4
TEMP = 25°C
3 LOAD = 5k: 50pF
7
VS = 5V
6
2
50mV
1
0
tPHL (PS)
OUTPUT VOLTAGE
(V)
2500 3000
TIME (ns)
Figure 19. Propagation Delay (tPHL)
INPUT VOLTAGE
(mV)
50mV
4
20mV
|
|
100
OVERDRIVE
5
4
VS = 2.7V
3
2
0
1
-100
VS = 1.8V
0
0
500
1000 1500
2000 2500 3000
0
10
TIME (ns)
100
1000
OVERDRIVE (mV)
Figure 21. Propagation Delay (tPHL)
Figure 22. tPHL vs. Overdrive
5
VS = 5V
4.5
4
tPLH (PS)
3.5
3
2.5
VS = 2.7V
2
1.5
1
VS = 1.8V
0.5
0
1
10
100
1000
OVERDRIVE (mV)
Figure 23. tPLH vs. Overdrive
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7 Detailed Description
7.1 Overview
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 24, the comparator
compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output (VO) is low.
However, if VIN is greater than VREF, the output voltage (VO) is high.
VOLTS
VO
VREF
TIME
VIN
Figure 24. LMV7271 Basic Comparator
7.2 Functional Block Diagram
V
VREF
+
VO
VIN
+
V
-
7.3 Feature Description
7.3.1 Rail-to-Rail Input Stage
The LMV727X has an input common mode voltage range (VCM) of −0.1V below the V− to 0.1 V above V+. This is
achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN pair is on
and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The crossover point
between the NPN and PNP input stages is around 950mV from V+. Because each input stage has its own offset
voltage (VOS), the VOS of the comparator becomes a function of the VCM. See curves for VOS vs. VCM in the
Typical Characteristics section. In application design, it is recommended to keep the VCM away from the
crossover point to avoid problems. The wide input voltage range makes LMV727X ideal in power supply
monitoring circuits, where the comparators are used to sense signals close to ground and power supplies.
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Feature Description (continued)
7.3.2 Output Stage, LMV7271 and LMV7272
Figure 25. LMV7271 and LMV7272 Push-Pull Output Stage
The LMV7271 and LMV7272 have a push-pull output stage. This output stage keeps the total system power
consumption to the absolute minimum by eliminating the need for a pullup resistor. The only current consumed is
the low supply current and the current going directly into the load.
When the output switches, both PMOS and NMOS at the output stage are on at the same time for a very short
time. This allows current to flow directly between V+ and V− through output transistors. The result is a short spike
of current (called shoot-through current) drawn from the supply and glitches in the supply voltages. The glitches
can spread to other parts of the board as noise. To prevent the glitches in supply lines, power supply bypass
capacitors must be installed. See Circuit Techniques for Avoiding Oscillations in Comparator Applications for
supply bypassing for details.
7.3.3 Output Stage, LMV7275
Figure 26. LMV7275 Open-Drain Output
The LMV7275 has an open-drain output that requires a pullup resistor to a positive supply voltage for the output
to operate properly. The internal circuitry is identical to the LMV7271 except that the upper P-channel output
device is absent. When the internal output transistor is off, the output voltage will be pulled up to the external
positive voltage by the external pullup resistor. This allows the output to be OR'ed with other open-drain outputs
on the same bus. The output pullup resistor may be connected to any voltage level between V- and V+ for level
shifting applications.
7.4 Device Functional Modes
7.4.1 Capacitive and Resistive Loads
The propagation delay is not affected by capacitive loads at the output of the LMV7271 or LMV7272. However,
resistive loads slightly effect the propagation delay on the falling edge depending on the load resistance value.
The propagation delay on the rising edge of the LMV7275 depends on the load resistance and capacitance
values.
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Device Functional Modes (continued)
7.4.2 Noise
Most comparators have rather low gain. This allows the output to alternate between high and low when the input
signal changes slowly. The result is the output may oscillate between high and low when the differential input is
near zero and triggers on noise. The high gain of this comparator eliminates this problem. Less than 1 μV of
change on the input will drive the output from one rail to the other rail. If the input signal is noisy, the output
cannot ignore the noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)
7.4.3 Hysteresis
It is a standard procedure to use hysteresis (positive feedback) around a comparator to prevent oscillation due to
the comparator triggering its own noise on slowly ramping signals. The following sections will describe various
ways to apply hysteresis.
7.4.3.1 Noninverting Comparator With Hysteresis
VCC
-
VREF
VA
VIN
VO
+
R1
RL
R2
Figure 27. Noninverting Comparator With Hysteresis
A noninverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up
to VIN1 where VIN1 is calculated by:
VREF (R1 R2 )
'VIN1
R2
(1)
As soon as VO switches to VCC, VA steps to a value greater than VREF which is given by:
(VCC VIN1 )R1
VA VIN
R1 R2
(2)
To make the comparator switch back to its low state, VIN must equal VREF before VA will again equal VREF. VIN2
can be calculated by:
VREF (R1 R2 ) VCC R1
VIN2
R2
(3)
The hysteresis of this circuit is the difference between VIN1 and VIN2.
ΔVIN = VCCR1 / R2
(4)
Figure 28. Noninverting Comparator Thresholds
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Device Functional Modes (continued)
7.4.3.2 Inverting Comparator With Hysteresis
Figure 29. Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
VCC of the comparator (Figure 29). When VIN at the inverting input is less than VA, the voltage at the noninverting
node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as high as VCC).
The three network resistors can be represented as R1||R3 in series with R2. The lower input trip voltage VA1 is
defined as
VA1 =
VCC R2
(R1||R3) + R2
(5)
When VIN is greater than VA (VIN > VA), the output voltage is low and very close to ground. In this case the three
network resistors can be presented as R2//R3 in series with R1. The upper trip voltage VA2 is defined as
VA2 =
VCC (R2||R3)
R1 + (R2||R3)
(6)
The total hysteresis provided by the network is defined as
ΔVA = VA1 - VA2
(7)
A good typical value of ΔVA would be in the range of 5 to 50 mV. This is easily obtained by choosing R3 as 1000
to 100 times (R1||R2) for 5-V operation, or as 300 to 30 times (R1||R2) for 1.8-V operation.
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Device Functional Modes (continued)
7.4.4 Zero Crossing Detector
Figure 30. Simple Zero Crossing Detector
In a zero crossing detector circuit, the inverting input is connected to ground and the noninverting input is
connected to a 100 mVPP AC signal. As the signal at the noninverting input crosses 0 V, the output of the
comparator changes state.
7.4.4.1 Zero Crossing Detector With Hysteresis
VCC
R3
R1
R4
R2
-
VIN
V2
D1
VO
V1
+
R6
R5
Figure 31. Zero Crossing Detector With Hysteresis
To improve switching times and centering the input threshold to ground a small amount of positive feedback is
added to the circuit. Voltage divider R4 and R5 establishes a reference voltage, V1, at the positive input. By
making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, will be satisfied when VIN
= 0.
The positive feedback resistor, R6, is made very large with respect to R5 || R6 = 2000 R5). The resultant
hysteresis established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output
voltage transitions.
Diode D1 is used to insure that the inverting input terminal of the comparator never goes below approximately
−100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1 and R2 to
approximately −700 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below ground.
The maximum negative input overdrive is limited by the current handling ability of D1.
7.4.5 Threshold Detector
Figure 32. Threshold Detector
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Device Functional Modes (continued)
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on
the noninverting input passes the VREF threshold, the output of the comparator changes state. It is important to
use a stable reference voltage to ensure a consistent switching point.
7.4.6 Universal Logic Level Shifter (LMV7275 only)
VB
VA
LOGIC
IN
REXT
-
1k:
LMV7275
+
LOGIC
OUT
1k:
Figure 33. Logic Level Shifter
The output of LMV7275 is an unconnected drain of an NMOS device, which can be pulled up, through a resistor,
to any desired output level within the permitted power supply range. Hence, the following simple circuit works as
a universal logic level shifter, pulling up the signal to the desired level.
For example, VA could be the 5-V analog supply voltage, where VB could be the 3.3-V supply of the processor.
The output will now be compatable with the 3.3-V logic.
7.4.7 OR'ING the Output (LMV7275 only)
Figure 34. OR’ing the Outputs
Because the LMV7275 output is an unconnected NMOS drain, many open-drain outputs can be tied together,
pulled up to V+ by a common resistor to provide an output OR'ing function. If any of the comparator outputs goes
low, the output VO goes low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV727x devices are single-supply comparators with 880 ns of propagation delay and only 12 µA of supply
current.
8.2 Typical Applications
8.2.1 Square Wave Oscillator
+
V
4.3k:
R4 = 100k:
C1 = 750pF
VC
VO
+
R1 = 100k:
VA
R3 = 100k:
+
R2 = 100k:
V
0
f | 10KHz
Figure 35. Square Wave Oscillator Application
8.2.1.1 Design Requirements
A typical application for a comparator is as a square wave oscillator. Figure 35 generates a square wave whose
period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is limited by
the large signal propagation delay of the comparator, and by the capacitive loading at the output, which limits the
output slew rate.
8.2.1.2 Detailed Design Procedure
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than
the noninverting input (VA).
Figure 36. Squarewave Oscillator Timing Thresholds
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Typical Applications (continued)
This causes the C1 to get charged through R4, and the voltage VC increases till it is equal to the noninverting
input. The value of VA at this point is
VCC.R2
VA1 =
R2 + R1||R3
(8)
If R1 = R2 = R3, then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is
VCC (R2||R3)
VA2 =
R1 + (R2||R3)
(9)
If R1 = R2 = R3, then VA2 = VCC/3
The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2)
8.2.1.3 Application Curve
Figure Figure 37 shows the simulated results of an oscillator using the following values:
1.
2.
3.
4.
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 750 pF, CL = 20 pF
V+ = 5 V, V- = GND
CSTRAY (not shown) from Va to GND = 10 pF
6
VOUT
5
Va
VOUT (V)
4
3
2
1
Vc
0
-1
0
100
200
300
400
TIME (µs)
500
C001
Figure 37. Square Wave Oscillator Output Waveforms
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Typical Applications (continued)
8.2.2 Positive Peak Detector
+VCC
VIN
R1
1k:
+
-
VOUT
C1
10PF
+
R2
1M:
Figure 38. Positive Peak Detector
The positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a
capacitor as a load to store the highest voltage. A diode is added at the output to prevent the capacitor from
discharging through the pullup resistor. When the input VIN increases, the inverting input of the comparator
follows it, thus charging the capacitor. When the input voltage decreases, the cap discharges through the 1-MΩ
resistor.
The decay time can be modified by changing R2. The output should be accessed through a high-impedance
input follower circuit to prevent loading. Upper output swing headroom is determined by the forward voltage of
the diode (VMAX = VCC – VF). A Shottky signal diode can be used to reduce the required headroom to around 300
mV.
This circuit can use any of the LMV727x devices, but R1 is not required for the LMV7271 or LMV7272.
8.2.3 Negative Peak Detector
+VCC
VIN
+
VOUT
-
R1
1M:
+
C1
10PF
-VCC
Figure 39. Negative Peak Detector (LMV7275 Only)
The Negative Peak Detector circuit will store the peak negative voltage below ground ( 0 V to –VCC). For the
negative detector, the LMV7275 must be used because the output transistor acts as a low-impedance current
sink. Because there is no pullup resistor, the only discharge path will be the 1-MΩ resistor and any load
impedance used. Decay time is changed by varying the 1-MΩ resistor.
NOTE
The negative peak detector does require a negative supply voltage! +VCC can be grounded
to save dynamic range because the output does not swing above ground
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Typical Applications (continued)
8.2.4 Window Detector
V
+
R1
+
VREF2
A
OUTPUT A
B
OUTPUT B
R2
VIN
+
-
VREF1
R3
Figure 40. Window Detector
A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are
true (high) when VREF1 < VIN < VREF2
VIN
V
OUTPUT B
+
VREF2
VREF1
OUTPUT A
BOTH OUTPUTS
ARE HIGH
Figure 41. Window Detector Output Signal
The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or within the window, where these are
defined as:
VREF1 = R3 / R1 + R2 + R3) × V+
(10)
VREF2 = R2 + R3) / R1 + R2 + R3) × V+
(11)
To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be
reversed to invert the logic.
The LMV7275 with an open-drain output should be used if the outputs are to be tied together for a common logic
output.
Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.
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9 Power Supply Recommendations
To minimize supply noise, power supplies should be decoupled by a 0.01-μF ceramic capacitor in parallel with a
10-μF capacitor.
Due to the nanosecond edges on the output transition, peak supply currents will be drawn during the time the
output is transitioning. Peak current depends on the capacitive loading on the output. The output transition can
cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power
supply to ring due to trace inductance and low self-resonance frequency of high ESR bypass capacitors.
Treat the LMV727x as a high-speed device. Keep the ground paths short and place small (low-ESR ceramic)
bypass capacitors directly between the V+ and V– pins.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
10 Layout
10.1 Layout Guidelines
10.1.1 Circuit Techniques for Avoiding Oscillations in Comparator Applications
Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow
voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid
oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended:
1. Power supply bypassing is critical, and will improve stability and transient response. Resistance and
inductance from power supply wires and board traces increase power supply line impedance. When supply
current changes, the power supply line will move due to its impedance. Large enough supply line shift will
cause the comparator to mis-operate. To avoid problems, a small bypass capacitor, such as 0.1-µF ceramic,
should be placed immediately adjacent to the supply pins. An additional 6.8 μF or greater tantalum capacitor
should be placed at the point where the power supply for the comparator is introduced onto the board. These
capacitors act as an energy reservoir and keep the supply impedance low. In a dual-supply application, a
0.1-μF capacitor is recommended to be placed across V+ and V− pins.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted
coupling from any high-level signals (such as the output). The comparators can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the inputs through stray capacitance. This shows up
only during the output voltage transition intervals as the comparator changes states. Try to avoid a long loop
which could act as an inductor (coil).
3. It is a good practice to use an unbroken ground plane on a printed-circuit-board to provide all components
with a low inductive ground connection. Make sure ground paths are low-impedance where heavier currents
are flowing to avoid ground level shift. Preferably there should be a ground plane under the component.
4. The output trace should be routed away from inputs. The ground plane should extend between the output
and inputs to act as a guard. This can be achieved by running a topside ground plane between the output
and inputs. A typical PCB layout is shown in Figure 43.
5. When the signal source is applied through a resistive network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor with the same value, for both DC and AC
consideration. Input traces should be laid out symmetrically if possible.
6. All pins of any unused comparators should be tied to the negative supply.
10.1.2 DSBGA Light Sensitivity
Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as
Halogen lamps can also affect electrical performance if brought near to the device. The wavelengths, which have
the most detrimental effect, are reds and infrareds. Be aware of internal light sources, such as keyboard or
display backlights, that may pass through a PCB. A copper plane should be placed on a lower layer under the
DSBGA to block light. Be careful using vias under the device, as they may pass light.
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Layout Guidelines (continued)
10.1.3 DSBGA Mounting
The DSBGA package requires specific mounting techniques, which are detailed in Application Note AN-1112
(SNVA009).
10.1.4 LMV7272 DSBGA to DIP Conversion Board
To facilitate characterization and testing, a DSBGA to DIP conversion board, LMV7272TLCONV, is available. It is
a 2-layer board, with the LMV7272 mounted on the bottom layer, and a capacitor (C1, between the positive and
negative supplies) added to the top layer.
LMV7272
+
OUTB
LMV7272 (DSBGA)
(Bottom Layer)
V
-INB
OUTA
+INB
-INA
-
+INA
V
C1 (Top Layer)
Figure 42. LMV7272TLCONV Diagram
10.2 Layout Example
V
+
OUT B
OUT A
-INA
-INB
+INA
+INB
V
-
Figure 43. Typical PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For developmental support, see the following:
• LMV7271 PSPICE Model (can also be used for LMV7272), SNOM052
• LMV7275 PSPICE Model, SNOM555
• TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
• DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
• TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-74 A Quad of Independently Functioning Comparators, SNOA654
• AN-1112 Micro SMD Wafer Level Chip Scale Package, SNVA009
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV7271
Click here
Click here
Click here
Click here
Click here
LMV7272
Click here
Click here
Click here
Click here
Click here
LMV7275
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
24
Submit Documentation Feedback
Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: LMV7271 LMV7272 LMV7275
LMV7271, LMV7272, LMV7275
www.ti.com
SNOSA56I – FEBRUARY 2003 – REVISED SEPTEMBER 2015
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: LMV7271 LMV7272 LMV7275
Submit Documentation Feedback
25
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV7271MF
ACTIVE
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
C25A
LMV7271MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C25A
LMV7271MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C25A
LMV7271MG
ACTIVE
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 85
C34
LMV7271MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C34
LMV7271MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C34
LMV7272TL/NOPB
ACTIVE
DSBGA
YZR
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
01
LMV7272TLX/NOPB
ACTIVE
DSBGA
YZR
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
01
LMV7275MF
ACTIVE
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
C26A
LMV7275MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C26A
LMV7275MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C26A
LMV7275MG
ACTIVE
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 85
C35
LMV7275MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C35
LMV7275MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C35
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV7275 :
• Automotive: LMV7275-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LMV7271MF
SOT-23
DBV
5
1000
178.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
LMV7271MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7271MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7271MG
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7271MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7271MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7272TL/NOPB
DSBGA
YZR
8
250
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
LMV7272TLX/NOPB
DSBGA
YZR
8
3000
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
LMV7275MF
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7275MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7275MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7275MG
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7275MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7275MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV7271MF
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7271MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7271MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV7271MG
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7271MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7271MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV7272TL/NOPB
DSBGA
YZR
8
250
210.0
185.0
35.0
LMV7272TLX/NOPB
DSBGA
YZR
8
3000
210.0
185.0
35.0
LMV7275MF
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7275MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7275MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV7275MG
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7275MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7275MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
YZR0008xxx
D
0.600±0.075
E
TLA08XXX (Rev C)
D: Max = 1.55 mm, Min = 1.489 mm
E: Max = 1.55 mm, Min = 1.489 mm
4215045/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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