Texas Instruments | LMH6657 and LMH6658 270-MHz Single Supply, Single and Dual Amplifiers (Rev. G) | Datasheet | Texas Instruments LMH6657 and LMH6658 270-MHz Single Supply, Single and Dual Amplifiers (Rev. G) Datasheet

Texas Instruments LMH6657 and LMH6658 270-MHz Single Supply, Single and Dual Amplifiers (Rev. G) Datasheet
Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
LMH6657 and LMH6658 270-MHz Single Supply, Single and Dual Amplifiers
1 Features
3 Description
VS = 5 V, TA = 25°C, RL = 100 Ω (Typical Values
Unless Specified)
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
−3dB BW (AV = +1) 270 MHz
Supply Voltage Range 3 V to 12 V
Slew Rate, (VS = ±5 V) 700 V/µs
Supply Current 6.2 mA/amp
Output Current +80/−90 mA
Input Common-Mode Volt. 0.5 V Beyond V−, 1.7 V
from V+
Output Voltage Swing (RL = 2 kΩ) 0.8 V from
Rails
Input Voltage Noise 11 nV/√Hz
Input Current Noise 2.1 pA√Hz/
DG Error 0.03%
DP Error 0.10°
THD (5MHz) −55 dBc
Settling Time (0.1%) 37ns
Fully Characterized for 5 V, and ±5 V
Output Overdrive Recovery 18 ns
Output Short Circuit Protected(1)
No Output Phase Reversal With CMVR Exceeded
2 Applications
•
•
•
•
•
CD/DVD ROM
ADC Buffer Amps
Portable Video
Current Sense Buffers
Portable Communications
(1) Short Circuit Test is a momentary test.
See Note 3 under Absolute Maximum Ratings.
The LMH6657 and LMH6658 devices are low-cost
operational amplifiers that operate from a single
supply with input voltage range extending below the
V−. Based on easy to use voltage feedback topology
and boasting fast slew rate (700 V/µs) and high
speed (140 MHz GBWP), the LMH6657 (Single) and
LMH6658 (dual) can be used in high speed large
signal applications. These applications include
instrumentation, communication devices, set-top
boxes, and so forth.
With a -3dB BW of 100 MHz (AV = +2) and DG & DP
of 0.03% & 0.10° respectively, the LMH6657 and
LMH6658 are well suited for video applications. The
output stage can typically supply 80 mA into the load
with a swing of about 1 V from either rail.
For Industrial applications, the LMH6657 and
LMH6658 are excellent cost-saving choices. Input
referred voltage noise is low and the input voltage
can extend below V− to ease amplification of low level
signals that could be at or near the system ground.
With low distortion and fast settling, LMH6657 and
LMH6658 can provide buffering for A/D and D/A
applications.
The LMH6657 and LMH6658 versatility and ease of
use is extended even further by offering these high
slew rate, high-speed operational amplifiers in
miniature packages such as SOT-23-5, SC70, SOIC8, and VSSOP-8.
Device Information(1)
PART NUMBER
PACKAGE
LMH6657
LMH6658
BODY SIZE (NOM)
SC70 (5)
2.00 mm × 1.25 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Noninverting Frequency Response, Gain
Noninverting Frequency Response, Phase
0
AV = +1
0
AV = +5
-3
AV = +2
AV = +1
-5
VS = ±2.5V
-7
AV = +10
AV = +10
PHASE
GAIN
-1
-50
AV = +5
-100
AV = +2
-150
-200
VS = ±2.5V
RL = 100:
RL = 100:
VOUT = 200mVPP
VOUT = 200mVPP
1M
10M
100M
FREQUENCY (Hz)
500M
1M
10M
100M
FREQUENCY (Hz)
500M
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics, 5 V ..................................
Electrical Characteristics, ±5 V ................................
Typical Characteristics ..............................................
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Feature Description................................................. 17
7.3 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2013) to Revision G
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision E (March 2013) to Revision F
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
5 Pin Configuration and Functions
DBV and DCK Package
5-Pin SOT-23 and SC70
Top View
D and DGK Package
8-Pin SOIC and VSSOP
Top View
5
1
OUTPUT
V
+
1
8
+
V
OUT A
A
2
V
-
+
7
OUT B
2
-
+
+IN
-
-IN A
3
6
+IN A
4
3
-IN B
B
+
-
-IN
V
-
4
5
+IN B
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
SOT-23
AND SC70
SOIC AND
VSSOP
OUTPUT
1
—
O
Output
–IN
4
—
I
Inverting input
+IN
3
—
I
Noninverting input
OUT A
—
1
O
Output A
–IN A
—
2
I
Inverting input A
+IN A
—
3
I
Noninverting input A
V
2
4
I
Negative Supply
OUT B
—
7
O
Output B
–IN B
—
6
I
Inverting input channel B
+IN B
—
5
I
Noninverting input channel B
V+
5
8
I
Positive supply
–
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
3
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VIN Differential
Output Short Circuit Duration
MAX
UNIT
±2.5
V
See
(2) (3)
Input Current
±10
mA
Supply Voltage (V+ - V−)
12.6
V
+
V
−
V − 0.8
Voltage at Input/Output pins
Soldering Information
V + 0.8
Infrared or Convection (20 sec.)
260
Wave Soldering (10 sec.)
260
Storage temperature, Tstg
–65
Junction Temperature (4)
(1)
(2)
(3)
(4)
°C
100
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Output short circuit duration is infinite for VS < 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is
1.5ms.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2000
Machine Model (3)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
Human body model, 1.5 kΩ in series with 100 pF.
Machine Model, 0 Ω in series with 200 pF.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
+
−
Supply Voltage (V – V )
Operating Temperature (1)
(1)
MIN
MAX
UNIT
3
12
V
−40
85
°C
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
LMH6657
DBV (SOT23)
THERMAL METRIC (1)
LMH6658
DCK (SC70)
D (SOIC)
5 PINS
RθJA
(1)
(2)
4
Junction-to-ambient thermal resistance (2)
265
DGK
(VSSOP)
UNIT
8 PINS
478
190
235
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
6.5 Electrical Characteristics, 5 V
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL = 100Ω (or as
specified) tied to V+/2.
PARAMETER
GB
Gain Bandwidth Product
SSBW
−3-dB BW
GFP
TEST CONDITIONS
MIN (1)
TYP (2)
VOUT < 200 mVPP
MAX (1)
UNIT
140
AV = +1, VOUT = 200 mVPP
220
MHz
270
MHz
AV = +2 or −1, VOUT = 200 mVPP
100
Frequency Response
Peaking
AV = +2, VOUT = 200 mVPP,
DC to 100 MHz
1.5
GFR
Frequency Response
Rolloff
AV = +2, VOUT = 200 mVPP,
DC to 100 MHz
0.5
LPD1°
1° Linear Phase Deviation
AV = +2, VOUT = 200 mVPP, ±1°
30
MHz
GF0.1dB
0.1-dB Gain Flatness
AV = +2, ±0.1 dB, VOUT = 200 mVPP
13
MHz
PBW
Full Power Bandwidth
−1 dB, VOUT = 3 VPP, AV = −1
55
MHz
DG
Differential Gain
NTSC, VCM = 2 V, RL = 150 Ω to V+/2, Pos. Video Only
DP
Differential Phase
NTSC, VCM = 2 V, RL=150 Ω to V+/2 Pos. Video Only
0.1
AV = +2, VOUT = 500 mVPP
3.3
AV = −1, VOUT = 500 mVPP
3.4
18%
dB
dB
0.03%
deg
TIME DOMAIN RESPONSE
tr
Rise and Fall Time
OS
Overshoot, Undershoot
AV = +2, VOUT = 500 mVPP
ts
Settling Time
VO = 2 VPP, ±0.1%, RL = 500 Ω to V+/2, AV = −1
Slew Rate (3)
SR
ns
37
AV = −1, VO = 3VPP (4)
470
AV = +2, VO = 3VPP (4)
420
ns
V/µs
DISTORTION AND NOISE RESPONSE
HD2
2nd Harmonic Distortion
f = 5MHz, VO = 2VPP, AV = -1
−70
dBc
HD3
3rd Harmonic Distortion
f = 5MHz, VO = 2VPP, AV = -1
−57
dBc
THD
Total Harmonic Distortion
f = 5MHz, VO = 2VPP, AV = -1
−55.5
dBc
Input-Referred Voltage
Noise
f = 100KHz
11
f = 1KHz
19
Input-Referred Current
Noise
f = 100KHz
2.1
f = 1KHz
7.5
Cross-Talk Rejection
(LMH6658)
f = 5MHz, RL (SND) = 100Ω
RCV: RF = RG = 1k
69
Vn
In
XTLKA
nV/√Hz
pA/√Hz
dB
STATIC, DC PERFORMANCE
AVOL
Large Signal Voltage Gain
VO = 1.25V to 3.75V,
RL = 2k to V+/2
85
95
VO = 1.5V to 3.5V,
RL = 150Ω to V+/2
75
85
VO = 2V to 3V,
RL = 50Ω to V+/2
70
80
−0.2
−0.5
CMRR ≥ 50dB
CMVR
At the temperature extremes
Input Common-Mode
Voltage Range
VOS
Input Offset Voltage
TC VOS
Input Offset Voltage
Average Drift
(1)
(2)
(3)
(4)
(5)
−0.1
3
At the temperature extremes
dB
V
3.3
2.8
±1.1
At the temperature extremes
±5
±7
See (5)
±2
mV
μV/C
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Slew rate is the "worst case" of the rising and falling slew rates.
Output Swing not limited by Slew Rate limit.
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
5
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Electrical Characteristics, 5 V (continued)
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL = 100Ω (or as
specified) tied to V+/2.
PARAMETER
MIN (1)
TEST CONDITIONS
See (6)
TYP (2)
MAX (1)
−5
−20
IB
Input Bias Current
TC IB
Input Bias Current
Average Drift
IOS
Input Offset Current
CMRR
Common-Mode Rejection
Ratio
VCM Stepped from 0V to 3.0V
72
82
+PSRR
Positive Power Supply
Rejection Ratio
V+ = 4.5V to 5.5V, VCM = 1V
72
82
IS
Supply Current (per
channel)
No load
−30
At the temperature extremes
See (5)
0.01
50
At the temperature extremes
At the temperature extremes
μA
nA/°C
300
500
6.2
UNIT
nA
dB
dB
8.5
10
mA
MISCELLANEOUS PERFORMANCE
RL = 2k to V+/2
Output Swing
High
VOH
4.1
At the temperature extremes
3.8
At the temperature extremes
3.7
RL = 150Ω to V+/2
4
RL = 75Ω to V+/2
3.85
At the temperature extremes
RL = 2k to V+/2
Output Swing
Low
VOL
At the temperature extremes
1100
At the temperature extremes
1200
At the temperature extremes
1250
970
R L = 75Ω to V+/2
IOUT
Output Current
VOUT = 1V from either
rail
990
Sourcing
Sinking
Sourcing to V+/2
Output Short
CircuitCurrent (7)
ISC
At the temperature extremes
Sinking to V+/2
800
870
40
85
105
100
155
80
220
3
CIN
Common-Mode Input
Capacitance
1.8
ROUT
Output Impedance
6
mA
mA
80
Common-Mode Input
Resistance
(6)
(7)
mV
885
RIN
f = 1MHz, AV = +1
V
4.15
–40
100
At the temperature extremes
4.19
3.5
900
RL = 150Ω to V+/2
4.25
0.06
MΩ
pF
Ω
Positive current corresponds to current flowing into the device.
Short circuit test is a momentary test. See Note 3 under Absolute Maximum Ratings.
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
6.6
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
Electrical Characteristics, ±5 V
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = −5 V, VCM = VO, and RL = 100 Ω (or as
specified) tied to 0 V.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
VOUT < 200 mVPP
MAX (1)
UNIT
GB
Gain Bandwidth Product
140
SSBW
−3-dB BW
GFP
Frequency Response
Peaking
AV = +2, VOUT = 200 mVPP,
DC to 100 MHz
1
GFR
Frequency Response
Rolloff
AV = +2, VOUT = 200 mVPP,
DC to 100 MHz
0.9
LPD1°
1° Linear Phase Deviation
AV = +2, VOUT = 200mVPP, ±1°
30
MHz
GF0.1dB
0.1-dB Gain Flatness
AV = +2, ±0.1 dB, VOUT = 200 mVPP
20
MHz
PBW
Full Power Bandwidth
−1 dB, VOUT = 8 VPP, AV = −1
30
MHz
DG
Differential Gain
NTSC, RL = 150 Ω, Pos. or Neg. Video
DP
Differential Phase
NTSC,RL = 150 Ω, Pos. or Neg. Video
0.1
AV = +2, VOUT = 500 mVPP
3.3
AV = −1, VOUT = 500 mVPP
3.3
16%
AV = +1, VOUT = 200 mVPP
220
MHz
270
AV = +2 or −1, VOUT = 200 mVPP
MHz
100
dB
dB
0.03%
deg
TIME DOMAIN RESPONSE
tr
Rise and Fall Time
OS
Overshoot, Undershoot
AV = +2, VOUT = 500 mVPP
ts
Settling Time
VO = 5 VPP, ±0.1%, RL =500 Ω,
AV = −1
SR
Slew Rate (3)
ns
35
AV = −1, VO = 8 VPP
700
AV = +2, VO = 8 VPP
500
ns
V/µs
DISTORTION AND NOISE RESPONSE
HD2
2nd Harmonic Distortion
rd
f = 5 MHz, VO = 2 VPP, AV = -1
−70
dBc
HD3
3 Harmonic Distortion
f = 5 MHz, VO = 2 VPP, AV = -1
−57
dBc
THD
Total Harmonic Distortion
f = 5 MHz, VO = 2 VPP, AV = -1
−55.5
dBc
Vn
Input-Referred Voltage
Noise
f = 100 KHz
11
f = 1 KHz
19
In
Input-Referred Current
Noise
f = 100 KHz
2.1
f = 1 KHz
7.5
XTLKA
Cross-Talk Rejection
(LMH6658)
f = 5 MHz, RL (SND) = 100 Ω
RCV: RF = RG = 1 k
69
nV/√Hz
pA/√Hz
dB
STATIC, DC PERFORMANCE
AVOL
VO = −3.75 V to 3.75 V, RL = 2 k
87
100
Large Signal Voltage Gain VO = −3.5 V to 3.5 V, RL = 150 Ω
80
90
75
85
−5.2
−5.5
VO = −3 V to 3 V, RL = 50 Ω
CMRR ≥ 50 dB
CMVR
At the temperature extremes
Input Common-Mode
Voltage Range
VOS
Input Offset Voltage
TC VOS
Input Offset Voltage
Average Drift
(1)
(2)
(3)
(4)
−5.1
3
At the temperature extremes
V
3.3
2.8
±1
Apply at the temperature extremes
See
dB
±5
±7
(4)
±2
mV
μV/C
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Slew rate is the "worst case" of the rising and falling slew rates.
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
7
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Electrical Characteristics, ±5 V (continued)
Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = −5 V, VCM = VO, and RL = 100 Ω (or as
specified) tied to 0 V.
PARAMETER
MIN (1)
TEST CONDITIONS
See
(5)
TYP (2)
MAX (1)
−5
−20
UNIT
μA
IB
Input Bias Current
TCIB
Input Bias Current
Average Drift
IOS
Input Offset Current
CMRR
Common-Mode Rejection
Ratio
VCM Stepped from −5 V to 3 V
75
84
+PSRR
Positive Power Supply
Rejection Ratio
V+ = 4.5 V to 5.5 V, VCM = −4 V
75
82
dB
−PSRR
Negative Power Supply
Rejection Ratio
V− = −4.5 V to −5.5 V
78
85
dB
IS
Supply Current (per
channel)
No load
−30
At the temperature extremes
See
(4)
0.01
50
At the temperature extremes
nA/°C
300
500
6.5
At the temperature extremes
nA
dB
9
11
mA
MISCELLANEOUS PERFORMANCE
RL = 2 k
4.1
At the temperature extremes
Output Swing
High
VOH
RL = 150 Ω
4
At the temperature extremes
3.85
At the temperature extremes
−4.05
At the temperature extremes
−3.8
At the temperature extremes
−3.65
RL = 150 Ω
−3.9
R L = 75 Ω
−3.8
Output Current
VOUT = 1 V from
either rail
Sourcing to
Ground
4.18
−4.19
−4.05
−4
Sourcing
Sinking
At the temperature extremes
45
100
–45
–110
120
180
100
ISC
Output Short Circuit
Current (6)
RIN
Common-Mode Input
Resistance
4
CIN
Common-Mode Input
Capacitance
1.8
ROUT
Output Impedance
(5)
(6)
8
Sinking to
Ground
V
−3.5
At the temperature extremes
IOUT
V
3.5
RL = 2 k
Output Swing
Low
4.2
3.7
RL = 75 Ω
VOL
4.25
3.8
120
At the temperature extremes
230
mA
mA
100
f = 1 MHz, AV = +1
0.06
MΩ
pF
Ω
Positive current corresponds to current flowing into the device.
Short circuit test is a momentary test. See Note 3 under Absolute Maximum Ratings.
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
6.7 Typical Characteristics
AV = -1
0
AV = +10
-1
-1
AV = -10
-3
GAIN
AV = +5
GAIN
AV = -2
0
AV = +2
-3
AV = -5
AV = +1
-5
-5
VS = ±2.5V
VS = ±2.5V
RL = 100:
-7
10M
100M
FREQUENCY (Hz)
1M
RL = 100:
-7
VOUT = 200mVPP
VOUT = 200mVPP
1M
500M
Figure 1. Noninverting Frequency Response, Gain
10M
100M
FREQUENCY (Hz)
Figure 2. Inverting Frequency Response, Gain
0
0
AV = -2
AV = +1
-50
AV = -1
AV = -5
AV = +5
-100
AV = -10
-50
AV = +10
-100
PHASE
PHASE
500M
AV = +2
-150
-150
AV = -1
-200
VS = ±2.5V
-200
VS = ±2.5V
AV = -2
RL = 100:
RL = 100:
VOUT = 200mVPP
VOUT = 200mVPP
1M
10M
100M
FREQUENCY (Hz)
500M
Figure 3. Noninverting Frequency Response, Phase
1M
AV = -5
10M
100M
FREQUENCY (Hz)
500M
Figure 4. Inverting Frequency Response, Phase
140
VS = ±5V
25°C
RL = 100:
80
60
40
20
GAIN
10
85°C
fu (MHz)
Im = 35.2°
PHASE (°)
GAIN (dB)
130
100
PHASE
-40°C
120
20
0
0
110
133MHz
VS = ±5V
RL = 100:
100k
1G
10M
100M
1M
FREQUENCY (Hz)
Figure 5. Open Loop Gain/Phase vs. Frequency
100
-5
-4
-3
-2
-1 0 1
VCM (V)
2
3
4
5
Figure 6. Unity Gain Frequency vs. VCM
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
9
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Typical Characteristics (continued)
45
5
VS = ±5V
VS = ±2.5V, AV = -1
4.5
RL = 100:
40
RL = 100:
4
-40°C
f = 50MHz
f = 40MHz
PM (°)
35
OUTPUT (VPP)
3.5
25°C
30
85°C
f = 30MHz
3
f = 20MHz
2.5
2
1.5
f = 60MHz
25
1
f = 70MHz
0.5
20
f = 80MHz
0
-5
-4
-3
-2
-1
0
1
2
3
4
0.5
5
1
VCM (V)
9
3.5
100
VS = ±5V
90
AV = -1
8
3
Figure 8. Output vs. Input
f = 20MHz
VS = ±5V
2.5
2
INPUT (VPP)
Figure 7. Phase Margin vs. VCM
10
1.5
f = 1MHz
RL = 100:
80
f = 40MHz
6
CMRR (dB)
f = 30MHz
f = 50MHz
5
4
3
70
60
50
40
2
f = 60MHz
f = 70MHz
1
30
f = 80MHz
0
20
1
3
2
4
5
7
6
8
9
10
1k
10k
90
100M
100
0.03
RF = RG = 750:
+PSRR
80
0.025
70
0.02
DG (%)
-PSRR
PSRR (dB)
10M
Figure 10. CMRR vs. Frequency
Figure 9. Output vs. Input
60
50
RL = 150:
VS = ±5V
NTSC
75
0.015
0.01
50
DG
0.005
40
25
0
DP
30
-0.005
20
10
100
1k
10k 100k
1M
10M 100M
-0.01
-100 -80 -60 -40 -20
FREQUENCY (Hz)
Submit Documentation Feedback
0
0
20 40 60 80 100
IRE (%)
Figure 11. PSRR vs. Frequency
10
1M
100k
FREQUENCY (Hz)
INPUT (VPP)
DP (milli_deg)
OUTPUT (VPP)
7
Figure 12. DG/DP vs. IRE
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
Typical Characteristics (continued)
120
70
140
60
100
50
80
40
VOLTAGE
30
60
20
40
CURRENT
100
90
CT (dB)
120
NOISE CURRENT (pA/ Hz)
NOISE VOLTAGE (nV/ Hz)
110
0
10
1k
100
60
40
VS = ±5V
SND: RL = 100:
30 RCV = R = R = 1k
F
G
20
100
10k 100k
1M
1k
FREQUENCY (Hz)
0
100k
10k
70
50
10
20
80
FREQUENCY (Hz)
100M
Figure 14. Crosstalk Rejection vs. Frequency
Figure 13. Noise vs. Frequency
-40
100
f = 500KHz
AV = +1
AV = -1
-50
10
VS = ±5V
THD (dBc)
1
0.1
THD
RL = 100:
-60
ROUT (:)
10M
HD3
-70
-80
HD2
0.01
-90
0.001
100
-100
1k
10k 100k
1M
0
10M 100M 1G
1
2
3
4
5
6
8
7
9
VOUT (VPP)
FREQUENCY (Hz)
Figure 15. Output Impedance vs. Frequency
Figure 16. HD vs. VOUT
-40
-20
VS = ±2.5V
THD
-45
-30
-50
AV = +2
10MHz, 150:
-40
HD3
THD (dBc)
THD (dBc)
-55
-60
HD2
-65
-70
f = 5MHz
AV = -1
-75
10MHz, 1k:
-60
-70
1MHz, 150:
-80
VS = ±5V
-80
-50
-90
RL = 100:
-85
1MHz, 1k:
-100
0
1
2
3
4
5 6
VOUT (VPP)
7
8
9
0
0.5
1
1.5
2
2.5
3
VOUT (VPP)
Figure 17. HD vs. VOUT
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Figure 18. THD vs. VOUT
Submit Documentation Feedback
11
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Typical Characteristics (continued)
-20
-20
VOUT = 2VPP
VOUT = 5VPP
AV = -1
-30
THD
VS = ±5V
-50
-60
THD
VS = ±5V
-40
RL = 100:
HD (dBc)
HD (dBc)
-40
AV = -1
-30
RL = 100:
-50
-60
HD2
HD2
-70
-70
HD3
-80
-80
HD3
-90
100
1k
10k
-90
100
100k
1k
10k
FREQUENCY (KHz)
Figure 19. HD vs. Frequency
Figure 20. HD vs. Frequency
10
10
VS = ±2.5V
VS = ±2.5V
85°C
125°C
85°C
25°C
-
VOUT FROM V (V)
125°C
-40°C
+
VOUT FROM V (V)
100k
FREQUENCY (KHz)
25°C
-40°C
1
125°C
-40°C
1
-40°C
125°C
85°C
0.1
0.1
0
50
100
150
200
50
0
100
IOUT (mA)
150
200
250
IOUT (mA)
Figure 21. VOUT vs. ISOURCE
Figure 22. VOUT vs. ISINK
10
10
VS = ±5V
VS = ±5V
125°C
125°C
25°C
-
VOUT FROM V (V)
-40°C
+
VOUT FROM V (V)
85°C
25°C
25°C
1
125°C
-40°C
1
-40°C
125°C
85°C
85°C
0.1
0
50
100
150
200
0.1
50
0
IOUT (mA)
Submit Documentation Feedback
150
200
250
IOUT (mA)
Figure 23. VOUT vs. ISOURCE
12
100
Figure 24. VOUT vs. ISINK
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
Typical Characteristics (continued)
250
200
-40°C
25°C
180
200
140
25°C
ISINK (mA)
ISOURCE (mA)
160
120
85°C, 125°C
100
80
85°C, 125°C
150
100
60
-40°C
50
40
20
0
0
2
4
6
8
10
12
14
4
2
8
6
VS (V)
Figure 25. Short Circuit Current
40
0.1%
0.1%
35
35
30
30
SETTLING TIME (ns)
SETTLING TIME (ns)
14
Figure 26. Short Circuit Current
40
1%
25
20
AV = -1
15
VS = ±2.5V
25
20
1%
AV = -1
15
VS = ±5V
RL = 500:
RL = 500:
10
10
0
0.5
1
2
1.5
1
0
2.5
2
3
4
5
6
VOUT (VPP)
VOUT (VPP)
Figure 27. Settling Time vs. Output Step Amplitude
Figure 28. Settling Time vs. Output Step Amplitude
140
+4
AV = -1
85°C
VS = 10V
120
+2
ZL = 500: || CL
100
0
RSERIES = 20:
'VOS (mV)
SETTLING TIME (ns)
12
10
VS (V)
80
POSITIVE
60
25°C
-2
-40°C
-4
-6
40
NEGATIVE
20
-8
0
-10
VS = ±2.5V
RL = 150:
10
100
10k
1k
-2
CL (pF)
Figure 29. 0.1% Settling Time vs. Cap Load
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
-1
0
VOUT (V)
1
2
Figure 30. ΔVOS vs. VOUT
Submit Documentation Feedback
13
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Typical Characteristics (continued)
8
2
85°C
85°C
25°C
1
7
25°C
0
6
-40°C
-40°C
-2
IS (mA)
'VOS (mV)
-1
-3
-4
4
3
-5
-6
5
2
VS = ±5V
1
-7 R = 150:
L
-
VCM = V +0.5V
0
-8
-5
-4
4
2
6
10
8
VS (V)
Figure 31. ΔVOS vs. VOUT
Figure 32. IS /Amp vs. VS
-2
-1
0
1
2
3
4
5
14
10
9
9
85°C
8
8
7
25°C
6
-40°C
85°C
7
IS (mA)
IS (mA)
12
VOUT (V)
-3
5
25°C
6
-40°C
5
4
4
3
3
2
VS = ±2.5V
VS = ±5V
1
2
-0.5 0
0.5
1
1.5
2
2.5
3
-6
3.5 4
-5
-4
-3
-2
-1
0
1
2
3
VCM (V)
VCM (V)
Figure 33. IS/Amp vs. VCM
Figure 34. IS/Amp vs. VCM
4
0
0
25°C
-40°C
UNIT 1
-0.5
-0.5
UNIT 1
-1
VOS (mV)
VOS (mV)
-1
-1.5
UNIT 2
-2
-1.5
UNIT 2
-2
UNIT 3
UNIT 3
-2.5
-2.5
-3
-3
2
4
6
8
10
12
14
4
2
Figure 35. VOS vs. VS (for 3 Representative Units)
Submit Documentation Feedback
8
10
12
14
VS (V)
VS (V)
14
6
Figure 36. VOS vs. VS (for 3 Representative Units)
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
Typical Characteristics (continued)
-1.1
0
85°C
UNIT 1
-1.2
-0.5
85°C
-1.3
VOS (mV)
VOS (mV)
-1
-1.5
UNIT 2
-2
-40°C
-1.4
-1.5
-1.6
25°C
-1.7
UNIT 3
-2.5
-1.8
VS = ±5V
-3
-1.9
2
4
8
6
10
12
14
-6
-5
-4
VS (V)
-3
-2 -1 0
VCM (V)
1
2
3
4
Figure 38. VOS vs. VCM (A Typical Unit)
Figure 37. VOS vs. VS (for 3 Representative Units)
0.16
6
85°C
0.14
5
25°C
0.12
25°C
IOS (PA)
IB (PA)
4
3
0.1
-40°C
0.08
-40°C
0.06
2
0.04
85°C
1
0.02
0
0
2
4
6
8
12
10
14
2
VS (V)
4
6
8
10
12
14
VS (V)
Figure 39. |IB| vs. VS
0.1 V/DIV
0.1 V/DIV
Figure 40. IOS vs. VS
VS = ±2.5V
VS = ±2.5V
AV = +1
AV = +2
RL = 100:
RL = 100:
2 ns/DIV
5 ns/DIV
Figure 41. Small Signal Step Response
Figure 42. Small Signal Step Response
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
15
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
0.1 V/DIV
0.1 V/DIV
Typical Characteristics (continued)
VS = ±5V
VS = ±5V
AV = +1
AV = +2
RL = 100:
RL = 100:
5 ns/DIV
2 ns/ DIV
Figure 44. Small Signal Step Response
1 V/DIV
0.4 V/DIV
Figure 43. Small Signal Step Response
VS = ±5V
VS = ±2.5V
AV = +1
AV = +2
RL = 100:
RL = 100:
5 ns/DIV
10 ns/DIV
Figure 46. Large Signal Step Response
1 V/DIV
Figure 45. Large Signal Step Response
VS = ±5V
AV = +2
RL = 100:
10 ns/DIV
Figure 47. Large Signal Step Response
16
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
7 Detailed Description
7.1 Overview
7.1.1 Large Signal Behavior
The LMH6657 and LMH6658 are large-bandwidth, fast slew rate, voltage feedback operational ampplifers ideal
for high-speed, large signal applications. The low input referred voltage noise in conjunction with an input voltage
range, which extends below V–, eases the adoption of this part in applications having a tiny signal at or near
system ground, as well as other high-speed, low-distortion, and low-noise systems. Also, the large Gain
Bandwidth Product allows high gain operation that does not compromise speed.
7.2 Feature Description
The LMH6657 and LMH6658 input stage is designed to provide excess overdrive when needed. This occurs
when fast input signal excursions cannot be followed by the output stage. In these situations, the device
encounters larger input signals than would be encountered under normal closed loop conditions. The LMH6657
and LMH6658 input stage is designed to take advantage of this "input overdrive" condition. The larger the
amount of this overdrive, the greater is the speed with which the output voltage can change. Here is a plot of
how the output slew rate limitation varies with respect to the amount of overdrive imposed on the input:
800
VS = ±5V
700
SLEW RATE (V/Ps)
600
500
400
300
200
100
0
0.00
1.00
2.00
3.00
INPUT OVERDRIVE (V)
Figure 48. Plot Showing the Relationship Between Slew Rate and Input Overdrive
To relate the explanation above to a practical example, consider the following application example. Consider the
case of a closed loop amplifier with a gain of −1 amplifying a sinusoidal waveform. From the plot of Output vs.
Input (Figure 8), with a 30-MHz signal and 7VPP input signal, it can be seen that the output will be limited to a
swing of 6.9 VPP. From the frequency Response plot it can be seen that the inverting gain of −1 has a −32°
output phase shift at this frequency.
It can be shown that this setup will result in about 1.9 VPP differential input voltage corresponding to 650 V/μs of
slew rate from Figure 48, above (SR = VO(pp) × π × f = 650V/μs)
Note that the amount of overdrive appearing on the input for a given sinusoidal test waveform is affected by the
following:
• Output swing
• Gain setting
• Input/output phase relationship for the given test frequency
• Amplifier configuration (inverting or noninverting)
Due to the higher frequency phase shift between input and output, there is no closed form solution to input
overdrive for a given input. Therefore, Figure 48 is not very useful by itself in determining the output swing.
The following plots aid in predicting the output transition time based on the amount of swing required for a given
gain setting.
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
17
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Feature Description (continued)
18
18
AV = +10, POS
RL = 100:
16
16
14
AV = +1, POS
AV = +6, POS
8
6 AV = +6, NEG
AV = +2, POS
AV = -10, POS
10
AV = -5, NEG
8
6
AV = -1, POS
AV = -5, POS
4
4
2
AV = +1, NEG
AV = -10, NEG
12
Tr (ns)
Tr (ns)
10
14
AV = +10, NEG
12
RL = 100:
AV = +2, NEG
0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
AV = -1, NEG
2
0
VO (VPP)
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VO (VPP)
Figure 49. Output 20%-80% Transition vs. Output Voltage
Swing (Noninverting Gain)
Figure 50. Output 20%-80% Transition vs. Output Voltage
Swing (Inverting Gain)
Beyond a gain of 5 or so, the LMH6657/6658 output transition would be limited by bandwidth. For example, with
a gain of 5, the −3dB BW would be around 30MHz corresponding to a rise time of about 12ns (10% - 90%).
Assuming a near linear transition, the 20%-80% transition time would be around 9ns which matches the
measured results as shown in Figure 49.
When the output is heavily loaded, output swing may be limited by current capability of the device. Refer to
Output Current Capability section for more details.
7.3 Device Functional Modes
7.3.1 Output Phase Reversal
This is a problem with some operational amplifiers. This effect is caused by phase reversal in the input stage due
to saturation of one or more of the transistors when the inputs exceed the normal expected range of voltages.
Some applications, such as servo control loops among others, are sensitive to this kind of behavior and would
need special safeguards to ensure proper functioning. The LMH6657 and LMH6658 is immune to output phase
reversal with input overload. With inputs exceeded, the LMH6657 and LMH6658 output will stay at the clamped
voltage from the supply rail. Exceeding the input supply voltages beyond the Absolute Maximum Ratings of the
device could however damage or otherwise adversely effect the reliability or life of the device.
18
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Output Characteristics
8.1.1.1 Output Current Capability
The LMH6657/6658 output swing for a given load can be determined by referring to the Output Voltage vs.
Output Current plots in Typical Characteristics. Characteristic Tables show the output current when the output is
1V from either rail. The plots and table values can be used to predict closed loop continuous value of current for
a given load. If left unchecked, the output current capability of the LMH6657 and LMH6658 could easily result in
junction temperature exceeding the maximum allowed value specified under Absolute Maximum Ratings. Proper
heat sinking or other precautions are required if conditions as such exist.
Under transient conditions, such as when the input voltage makes a large transition and the output has not had
time to reach its final value, the device can deliver output currents in excess of the typical plots mentioned above.
Plots shown in Figure 51 and Figure 52 depict how the output current capability improves under higher input
overdrive voltages:
10
10
VS = ±5V
25°C
VOUT FROM V (V)
-
+
VOUT FROM V (V)
VS = ±5V
25°C
1
20mV
500mV
0.1
-20mV
1
-500mV
0.1
0
50
100
IOUT (mA)
150
200
0
50
100
150
200
250
IOUT (mA)
Figure 51. VOUT vs. ISOURCE (for Various Overdrive)
Figure 52. VOUT vs. ISINK (for Various Overdrive)
The LMH6657 and LMH6658 output stage is designed to swing within approximately one diode drop of each
supply voltage by utilizing specially designed high speed output clamps. This allows adequate output voltage
swing even with 5-V supplies and yet avoids some of the issues associated with rail-to-rail output operational
amplifiers. Some of these issues are:
• Supply current increases when output reaches saturation at or near the supply rails
• Prolonged recovery when output approaches the rails
The LMH6657 and LMH6658 output is exceedingly well-behaved when it comes to recovering from an overload
condition. As can be seen from Figure 53, the LMH6657 and LMH6658 will typically recover from an output
overload condition in about 18 ns, regardless of the duration of the overload.
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
19
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Application Information (continued)
2 V/DIV
OUTPUT
INPUT
VS = ±5V, AV = +6, RF = 1k
RG = 200:RL = OPEN
20 ns/DIV
Figure 53. Output Overload Recovery
8.1.1.2 Driving Capacitive Loads
The LMH6657 and LMH6658 can drive moderate values of capacitance by utilizing a series isolation resistor
between the output and the capacitive load. Typical Characteristics shows the settling time behavior for various
capacitive loads and 20 Ω of isolation resistance. Capacitive load tolerance will improve with higher closed loop
gain values. Applications such as ADC buffers, among others, present complex and varying capacitive loads to
the operational amplifier; best value for this isolation resistance is often found by experimentation and actual trial
and error for each application.
8.1.1.3 Distortion
Applications with demanding distortion performance requirements are best served with the device operating in
the inverting mode. The reason for this is that in the inverting configuration, the input common-mode voltage
does not vary with the signal and there is no subsequent ill effects due to this shift in operating point and the
possibility of additional non-linearity. Moreover, under low closed loop gain settings (most suited to low
distortion), the noninverting configuration is at a further disadvantage of having to contend with the input common
voltage range. There is also a strong relationship between output loading and distortion performance (that is, 1
kΩ vs. 100 Ω distortion improves by about 20 dB at 100 KHz) especially at the lower frequency end where the
distortion tends to be lower. At higher frequency, this dependence diminishes greatly such that this difference is
only about 4 dB at 10 MHz. But, in general, lighter output load leads to reduced HD3 term and thus improves
THD.
9 Power Supply Recommendations
The LMH665x can operate off a single-supply or with dual supplies. The input CM capability of the parts (CMVR)
extends all the way down to the V- rail to simplify single-supply applications. Supplies should be decoupled with
low-inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. TI recommends
the use of ground plane, and as in most high-speed devices, it is advisable to remove ground plane close to
device sensitive pins such as the inputs.
10 Layout
10.1 Layout Guidelines
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations. See Application Note OA-15, Frequent Faux Pas in Applying Wideband Current
Feedback Amplifiers (SNOA367) for more information. TI suggests the following evaluation boards as a guide for
high frequency layout and as an aid in device testing and characterization:
20
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
Layout Guidelines (continued)
Table 1. Evaluation Board Guide
DEVICE
PACKAGE
EVALUATION BOARD PIN
LMH6657MF
SOT-23-5
LMH730216
LMH6657MG
SC-70
LMH730165
LMH6658MA
8-Pin SOIC
LMH730036
LMH6658MM
8-Pin VSSOP
LMH730123
Another important parameter in working with high speed/high performance amplifiers, is the component values
selection. Choosing external resistors that are large in value will effect the closed loop behavior of the stage
because of the interaction of these resistors with parasitic capacitances. These capacitors could be inherent to
the device or a by-product of the board layout and component placement. Either way, keeping the resistor values
lower, will diminish this interaction to a large extent. On the other hand, choosing very low value resistors will
load down nodes and will contribute to higher overall power dissipation.
10.2 Layout Example
SC-70 Board Layout (Actual size = 1.5 in × 1.5 in)
Figure 54. Layer 1 Silk
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
21
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Layout Example (continued)
SC-70 Board Layout (Actual size = 1.5 in × 1.5 in)
Figure 55. Layer 2 Silk
22
Submit Documentation Feedback
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
LMH6657, LMH6658
www.ti.com
SNOSA35G – AUGUST 2002 – REVISED JULY 2015
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
See Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, SNOA367
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMH6657
Click here
Click here
Click here
Click here
Click here
LMH6658
Click here
Click here
Click here
Click here
Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: LMH6657 LMH6658
Submit Documentation Feedback
23
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH6657MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A85A
LMH6657MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A85A
LMH6657MG
NRND
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 85
A76
LMH6657MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A76
LMH6658MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH66
58MA
LMH6658MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH66
58MA
LMH6658MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A88A
LMH6658MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A88A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
LMH6657MF/NOPB
SOT-23
LMH6657MFX/NOPB
LMH6657MG
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
1.4
4.0
8.0
Q3
DBV
5
1000
178.0
8.4
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMH6657MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMH6658MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMH6658MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMH6658MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
3.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6657MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMH6657MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMH6657MG
SC70
DCK
5
1000
210.0
185.0
35.0
LMH6657MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMH6658MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMH6658MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMH6658MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising