Texas Instruments | THS312x Low-Noise, High-Speed, 450-mA Current Feedback Amplifiers (Rev. E) | Datasheet | Texas Instruments THS312x Low-Noise, High-Speed, 450-mA Current Feedback Amplifiers (Rev. E) Datasheet

Texas Instruments THS312x Low-Noise, High-Speed, 450-mA Current Feedback Amplifiers (Rev. E) Datasheet
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THS3122, THS3125
SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
THS312x Low-Noise, High-Speed, 450-mA Current Feedback Amplifiers
1 Features
3 Description
•
The THS3122 and THS3125 are low-noise, highspeed current feedback amplifiers, with high output
current drive. This makes them ideal for any
application that requires low distortion over a wide
frequency with heavy loads. The THS3122 and
THS3125 can drive four serially-terminated video
lines while maintaining a differential gain error less
than 0.03%.
1
•
•
•
•
•
•
Low Noise:
– 2.9-pA/√Hz Noninverting Current Noise
– 10.8-pA/√Hz Inverting Current Noise
– 2.2-nV/√Hz Voltage Noise
– 128-MHz , –3-dB BW (RL = 50 Ω, RF = 470 Ω)
– 1550-V/µs Slew Rate (G = 2, RL= 50Ω )
High Output Current: 450 mA
High Speed:
– 128-MHz , –3-dB BW (RL = 50 Ω, RF = 470 Ω)
– 1550-V/µs Slew Rate (G = 2, RL= 50Ω )
– 26-VPP Output Voltage, RL= 50 Ω
– –80 dBc (1 MHz, 2 VPP, G = 2)
Wide Output Swing:
– 26-VPP Output Voltage, RL= 50 Ω
– –80 dBc (1 MHz, 2 VPP, G = 2)
– 370-µA Shutdown Supply Current
Low Distortion:
– –80 dBc (1 MHz, 2 VPP, G = 2)
– 370-µA Shutdown Supply Current
Low-Power Shutdown Mode (THS3125)
– 370-µA Shutdown Supply Current
Standard SOIC, HSOP PowerPAD™, and
HTSSOP PowerPAD Packages
The high output drive capability of the THS3122 and
THS3125 enables the devices to drive 50-Ω loads
with low distortion over a wide range of output
voltages:
• –80-dBc THD at 2 VPP
• –75-dBc THD at 8 VPP
The THS3122 and THS3125 operate from ±5-V to
±15-V supply voltages while drawing as little as
7.2 mA of supply current per channel. The THS3125
offers a low-power shutdown mode, reducing the
supply current to only 370 µA. The THS3122 and
THS3125 are packaged in SOIC, HSOP, and
HTSSOP packages.
Device Information(1)
PART NUMBER
THS3122
THS3125
2 Applications
•
•
•
•
•
Voltage Noise and Current Noise
vs
Frequency
100
Vn - Voltage Noise - nV/ÖHz
In - Current Noise - pA/ÖHz
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
HSOP (8)
4.89 mm × 3.90 mm
SOIC (14)
8.65 mm × 3.91 mm
HTSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Video Distribution
Instrumentation
Line Drivers
Motor Drivers
Piezo Drivers
VCC = ±5 V to ±15 V
TA = +25°C
THS3122
SOIC (D) and
HSOP (SOIC PowerPAD, DDA) Package
(Top View)
1 OUT
1 IN−
1 IN+
VCC−
In−
In+
10
PACKAGE
Vn
1
8
2
7
3
6
4
5
VCC+
2 OUT
2 IN−
2 IN+
THS3125
SOIC (D) and
HTSSOP PowerPAD (PWP) Package
(Top View)
1 OUT
1 IN−
1 IN+
VCC−
N/C
REF
N/C
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC+
2 OUT
2 IN−
2 IN+
N/C
SHUTDOWN
N/C
1
0.01
0.1
1
10
f − Frequency − kHz
100
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS3122, THS3125
SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings ..................................... 4
Dissipation Ratings Table ......................................... 4
Recommended Operating Conditions....................... 4
Electrical Characteristics: Dynamic Performance ..... 5
Electrical Characteristics: Noise and Distortion
Performance............................................................... 5
7.6 Electrical Characteristics: DC Performance.............. 6
7.7 Electrical Characteristics: Input Characteristics ....... 6
7.8 Electrical Characteristics: Output Characteristics ..... 6
7.9 Electrical Characteristics: Power Supply .................. 7
7.10 Electrical Characteristics: Shutdown Characteristics
(THS3125 Only) ......................................................... 7
7.11 Typical Characteristics: Table Of Graphs ............... 7
7.12 Typical Characteristics ............................................ 8
8
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Feature Description................................................. 14
8.3 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2011) to Revision E
Page
•
Added missing minus sign to temperature range in Available Options table ........................................................................ 3
•
Changed Input Offset parameter maximum values in Electrical Charateristics for DC Performance .................................... 6
•
Added Detailed Description section...................................................................................................................................... 14
•
Added Application and Implementation section.................................................................................................................... 18
•
Change Application Information section ............................................................................................................................... 18
Changes from Revision C (July 2010) to Revision D
•
Page
Changed output current (absolute maximum) from 275 mA to 550 mA................................................................................. 4
Changes from Revision B (October, 2009) to Revision C
Page
•
Corrected REF pin name for THS3125 shown in front-page figure ....................................................................................... 1
•
Deleted Shutdown pin input levels parameters and specifications from Recommended Operating Conditions table........... 4
•
Updated Shutdown Characteristics table test conditions; changed GND to REF, corrected VSHDN notations ....................... 7
•
Added VREF and VSHDN parameters and speciifications to Shutdown Characteristics table ................................................... 7
•
Revised second and fourth paragraphs of Saving Power with Shutdown Functionality section.......................................... 14
•
Updated equation in Power-Down Reference Pin Operation section that describes usable range at the REF pin............. 15
•
Revised paragraph in Power-Down Reference Pin Operation that discusses behavior of unterminated REF pin .............. 15
2
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Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: THS3122 THS3125
THS3122, THS3125
www.ti.com
SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
5 Device Options (1)
PACKAGED DEVICE
(1)
TA
SOIC-8
(D)
HSOP-8 PowerPAD
(DDA)
SOIC-14
(D)
HTSSOP-14
(PWP)
0°C to +70°C
THS3122CD
THS3122CDDA
THS3125CD
THS3125CPWP
–40°C to +85°C
THS3122ID
THS3122IDDA
THS3125ID
THS3125IPWP
EVALUATION
MODULES
THS3122EVM,
THS3125EVM
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
6 Pin Configuration and Functions
THS3122: D and DDA Packages
SOIC-8 and HSOP-8
Top View
1 OUT
1 INí
1 IN+
VCC í
1
2
3
4
8
7
6
5
THS3125: D and PWP Packages
SOIC-14 and HTSSOP-14
Top View
VCC +
2 OUT
2 INí
2 IN+
1 OUT
1 INí
1 IN+
VCC í
N/C
REF
N/C
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC+
2 OUT
2 INí
2 IN+
N/C
SHUTDOWN
N/C
Pin Functions
PIN
NAME
I/O
DESCRIPTION
THS3122
THS3125
1 IN+
3
3
I
Noninverting amplifier 1 input
1 IN–
2
2
I
Inverting amplifier 1 input
1 OUT
1
1
O
Amplifier 1 output
2 IN+
5
11
I
Noninverting amplifier 2 input
2 IN–
6
12
I
Inverting amplifier 2 input
2 OUT
7
13
O
Amplifier 2 output
N/C
—
5, 7, 8, 10
—
No internal connection.
SHUTDOWN
—
9
I
Shutdown control. Logic low = active; logic high = power down.
REF
—
6
I
Reference for shutdown threshold control
VCC+
8
14
P
Positive power supply
VCC–
4
4
P
Negative power supply
Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: THS3122 THS3125
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
33
V
–VCC
+VCC
V
–4
+4
V
550
mA
Supply voltage, VCC+ to VCC–
Input voltage
Differential input voltage
Output current (2)
Total power dissipation at (or below) +25°C free-air temperature
See Dissipation Ratings Table
Maximum junction temperature
Commercial
Operating free-air temperature, TA
Storage temperature, Tstg
(1)
(2)
0
150
°C
70
°C
Industrial
–40
+85
°C
Commercial
–65
+125
°C
Industrial
–65
+125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The THS3122 and THS3125 may incorporate a PowerPAD on the underside of the chip. This pad acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD thermally-enhanced package.
7.2 Dissipation Ratings Table
(1)
PACKAGE
θJA
TA = +25°C
POWER RATING
D-8
95°C/W (1)
1.32 W
DDA
67°C/W
1.87 W
D-14
66.6°C/W (1)
1.88 W
PWP
37.5°C/W
3.3 W
These data were taken using the JEDEC proposed high-K test PCB.
For the JEDEC low-K test PCB, the θJA is 168°C/W for the D-8
package and 122.3°C/W for the D-14 package.
7.3 Recommended Operating Conditions
MIN
Supply voltage, VCC+ to VCC–
Operating free-air temperature, TA
4
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NOM
MAX
UNIT
±15
V
Dual supply
±5
Single supply
10
30
V
0
+70
°C
–40
+85
°C
C-suffix
I-suffix
Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: THS3122 THS3125
THS3122, THS3125
www.ti.com
SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
7.4 Electrical Characteristics: Dynamic Performance
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
PARAMETER
TEST CONDITIONS
RL = 50 Ω
MHz
160
MHz
VCC = ±5 V
126
MHz
VCC = ±15 V
128
MHz
VCC = ±5 V
20
MHz
VCC = ±15 V
30
MHz
VO(PP) = 4 V
VCC = ±5 V
47
MHz
VO(PP) = 20 V
VCC = ±15 V
64
MHz
VO = 10 VPP
VCC = ±15 V
1550
V/µs
VCC = ±5 V
500
V/µs
VCC = ±15 V
1000
V/µs
RF = 470 Ω, G = 2
Slew rate (1), G = 8
SR
ts
(1)
Settling time to 0.1%
RF = 470 Ω, G = 2
G = –1
G = 2, RF = 680Ω
G = –1
UNIT
138
BW
Full power bandwidth
MAX
VCC = ±15 V
Small-signal bandwidth (–3 dB)
Bandwidth (0.1 dB)
TYP
VCC = ±5 V
RF = 50 Ω, G = 1
RL = 50 Ω
MIN
VO = 5 VPP
VO = 2 VPP
VCC = ±5 V
53
ns
VO= 5 VPP
VCC = ±15 V
64
ns
Slew rate is defined from the 25% to the 75% output levels.
7.5 Electrical Characteristics: Noise and Distortion Performance
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
PARAMETER
THD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G = 2, RF = 470 Ω, VCC= ±15 V,
f = 1 MHz
VO(PP) = 2 V
–80
dBc
VO(PP) = 8 V
–75
dBc
G = 2, RF = 470 Ω, VCC= ±5 V,
f = 1 MHz
VO(PP)= 2 V
–77
dBc
VO(PP)= 5 V
–76
dBc
VCC = ±5 V, ±15 V
f = 10 kHz
2.2
nV/√Hz
Noninverting Input
VCC = ±5 V, ±15 V
f = 10 kHz
2.9
pA/√Hz
Inverting Input
VCC = ±5 V, ±15 V
f = 10 kHz
10.8
pA/√Hz
VCC = ±5 V
–67
dBc
dBc
Total harmonic distortion
Vn
Input voltage noise
In
Input current
noise
Crosstalk
G = 2, f = 1 MHz, VO = 2 VPP
VCC= ±15 V
–67
VCC = ±5 V
0.01%
Differential gain error
G = 2, RL = 150 Ω
40 IRE modulation,
±100 IRE Ramp
NTSC and PAL
VCC= ±15 V
0.01%
G = 2, RL = 150 Ω
40 IRE modulation
±100 IRE Ramp
NTSC and PAL
VCC = ±5 V
0.011
degrees
Differential phase error
VCC= ±15 V
0.011
degrees
Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: THS3122 THS3125
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7.6 Electrical Characteristics: DC Performance
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
PARAMETER
VIO
TEST CONDITIONS
MIN
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
TA = +25°C
Channel offset voltage matching
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
TA = +25°C
Offset drift
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
IN- Input bias current
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
TA = +25°C
IN+ Input bias current
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
TA = +25°C
Input offset voltage
TYP MAX
6
TA = full range
1
TA = full range
TA = full range
TA = full range
IIB
0.33
TA = full range
IIO
Input offset current
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
TA = +25°C
ZOL
Open-loop transimpedance
VCC = ±5 V, VCC = ±15 V
RL = 1 kΩ
±20
mV
±25
mV
3
mV
4
mV
10
6
5.4
TA = full range
UNIT
µV/°C
23
µA
30
µA
2
µA
3
µA
22
µA
30
1
µA
MΩ
7.7 Electrical Characteristics: Input Characteristics
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
PARAMETER
VICR
TEST CONDITIONS
Input common-mode voltage range
MIN
TYP MAX
VCC = ±5 V
TA = full range
±2.5
±2.7
V
VCC= ±15 V
TA = full range
±12.5
±12.7
V
TA = +25°C
58
62
dB
TA = full range
56
TA = +25°C
63
TA = full range
60
VCC = ±5 V, VI = –2.5 V to +2.5 V
CMRR
Common-mode rejection ratio
VCC = ±15 V, VI = –12.5 V to +12.5 V
RI
Input resistance
CI
Input capacitance
UNIT
dB
67
dB
dB
IN+
1.5
IN–
15
MΩ
Ω
2
pF
7.8 Electrical Characteristics: Output Characteristics
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
PARAMETER
VO
Output voltage swing
IO
Output current drive
ro
Output resistance
6
TEST CONDITIONS
G = 4,
VI = 1.06 V, VCC = ±5 V,
RL = 1 kΩ
G = 4,
VI = 1.025 V, VCC= ±5 V,
RL = 50Ω
G = 4,
VI = 3.6 V, VCC= ±15 V,
RL = 1 kΩ
MIN
TA = +25°C
TA = +25°C
3.8
TA = full range
3.7
TA = +25°C
TA = +25°C
12
TYP MAX
UNIT
4.1
V
4
V
V
14.2
V
13.3
V
G = 4,
VI = 3.325 V, VCC= ±15 V,
RL = 50Ω
TA = full range
11.5
G = 4,
VI = 1.025 V, VCC= ±5 V,
RL = 10 Ω
TA = +25°C
200
280
mA
G = 4,
VI = 3.325 V, VCC = ±15 V,
RL = 25 Ω
TA = +25°C
360
440
mA
14
Ω
Open loop
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TA = +25°C
V
Copyright © 2001–2015, Texas Instruments Incorporated
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SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
7.9 Electrical Characteristics: Power Supply
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TA = +25°C
VCC = ±5 V
ICC
TYP
7.2
TA = full range
Quiescent current (per channel)
TA = +25°C
VCC = ±15 V
8.4
TA = full range
VCC = ±5 V ±1 V
PSRR
MIN
Power-supply rejection ratio
VCC = ±15 V ±1 V
TA = +25°C
53
TA = full range
50
TA = +25°C
60
TA = full range
55
MAX
UNIT
9
mA
10
mA
10.5
mA
11.5
mA
60
dB
dB
69
dB
dB
7.10 Electrical Characteristics: Shutdown Characteristics (THS3125 Only)
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
PARAMETER
ICC(SHDN)
Shutdown quiescent current (per channel)
tDIS
Disable time
tEN
TEST CONDITIONS
REF = 0 V, VCC= ±5 V to ±15 V
(1)
MIN
VSHDN = 3.3 V
TYP
MAX
UNIT
370
500
µA
REF = 0 V, VCC= ±5 V to ±15 V
500
Enable time (1)
REF = 0 V, VCC= ±5 V to ±15 V
200
IIL(SHDN)
Shutdown pin low level leakage current
REF = 0 V, VCC= ±5 V to ±15 V
VSHDN = 0 V
IIH(SHDN)
Shutdown pin high level leakage current
REF = 0 V, VCC= ±5 V to ±15 V
VSHDN = 3.3 V
VREF
REF pin voltage level
VSHDN
(1)
18
110
VCC–
Enable
SHUTDOWN pin voltage level
Disable
µs
µs
25
µA
130
µA
VCC+ – 4
V
REF + 0.8
V
REF + 2
V
Disable and enable times are defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current
has reached half of its final value.
7.11 Typical Characteristics: Table Of Graphs
TITLE
FIGURE
Small-signal closed-loop gain
vs Frequency
Figure 1 to Figure 10
Small- and large-signal output
vs Frequency
Figure 11, Figure 12
vs Frequency
Figure 13 to Figure 15
Harmonic distortion
vs Peak-to-peak output voltage
Figure 16, Figure 17
Vn, In
Voltage noise and current noise
vs Frequency
Figure 18
CMRR
Common-mode rejection ratio
vs Frequency
Figure 19
Crosstalk
vs Frequency
Figure 20
Zo
Output impedance
vs Frequency
Figure 21
SR
Slew rate
vs Output voltage step
Figure 22
vs Free-air temperature
Figure 24
vs Common-mode input voltage
Figure 24
VIO
Input offset voltage
IB
Input bias current
vs Free-air temperature
Figure 25
VO
Output voltage
vs Load current
Figure 26
vs Free-air temperature
Figure 27
vs Supply voltage
Figure 28
Quiescent current
ICC
Shutdown supply current
vs Free-air temperature
Differential gain and phase error
vs 75-Ω serially terminated loads
Shutdown response
Figure 29
Figure 30, Figure 31
Figure 32
Small-signal pulse response
Figure 33, Figure 34
Large-signal pulse response
Figure 35, Figure 36
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7.12 Typical Characteristics
3
RF = 330 Ω
3
Small Signal Closed Loop Gain − dB
Small Signal Closed Loop Gain − dB
6
0
−3
RF = 680 Ω
−6
RF = 500 Ω
−9
−12
−15
−18
−21
G = −1,
VCC = ±5 V,
RL = 50 Ω
−24
−27
−30
0.1
1
10
100
0
RF = 680 Ω
−3
RF = 500 Ω
−6
RF = 330 Ω
−9
−12
−15
−18
−21
G = −1,
VCC = ±15 V,
RL = 50 Ω
−24
−27
−30
0.1
1000
Figure 1. Small-Signal Closed-Loop Gain vs Frequency
Small Signal Closed Loop Gain − dB
Small Signal Closed Loop Gain − dB
0
RF = 750 Ω
RF = 560 Ω
−2
−3
−4
G = 1,
VCC = ±5 V,
RL = 50 Ω
−6
0.1
1
10
100
RF = 470 Ω
RF = 560 Ω
−3
RF = 750 Ω
−6
−9
G = 1,
VCC = ±15 V,
RL = 50 Ω
−12
0.1
1000
100
1000
9
Small Signal Closed Loop Gain − dB
Small Signal Closed Loop Gain − dB
10
Figure 4. Small-Signal Closed-Loop Gain vs Frequency
9
RF = 430 Ω
6
RF = 500 Ω
RF = 470 Ω
3
0
G = 2,
VCC = ±5 V,
RL = 50 Ω
1
10
100
1000
RF = 430 Ω
3
RF = 500 Ω
6
RF = 470 Ω
0
−3
G = 2,
VCC = ±15 V,
RL = 50 Ω
−6
0.1
Figure 5. Small-Signal Closed-Loop Gain vs Frequency
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1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
8
1
f − Frequency − MHz
Figure 3. Small-Signal Closed-Loop Gain vs Frequency
−6
0.1
1000
0
f − Frequency − MHz
−3
100
3
RF = 470 Ω
1
−5
10
Figure 2. Small-Signal Closed-Loop Gain vs Frequency
2
−1
1
f − Frequency − MHz
f − Frequency − MHz
Figure 6. Small-Signal Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
15
RF = 200 Ω
12
Small Signal Closed Loop Gain − dB
Small Signal Closed Loop Gain − dB
15
9
RF = 270 Ω
6
RF = 390 Ω
3
0
−3
−6
−9
G = 4,
VCC = ±5 V,
RL = 50 Ω
−12
−15
1
10
100
9
RF = 270 Ω
6
RF = 390 Ω
3
0
−3
−6
−9
−12
−15
G = 4,
VCC = ±15 V,
RL = 50 Ω
−18
0.1
−18
0.1
RF = 200 Ω
12
1000
1
Figure 7. Small-Signal Closed-Loop Gain vs Frequency
1000
15
Small Signal Closed Loop Gain − dB
Small Signal Closed Loop Gain − dB
100
Figure 8. Small-Signal Closed-Loop Gain vs Frequency
15
12
RF = 200 Ω
9
6
RF = 470 Ω
3
0
RF = 560 Ω
−3
−6
VCC = ±5 V,
RL = 50 Ω
−9
−12
RF = 200 Ω
12
9
RF = 470 Ω
6
3
RF = 560 Ω
0
−3
−6
VCC = ±15 V,
RL = 50 Ω
−9
−12
0.1
1
10
100
1000
0.1
1
f − Frequency − MHz
18
Small and Large Signal Output − dB
12
2 VPP
6
1 VPP
0
0.5 VPP
−6
0.25 VPP
−12
0.125 VPP
−18
−24
0.1
1
10
100
1000
100
Figure 10. Small-Signal Closed-Loop Gain vs Frequency
18
G = 2, VCC = ±5 V,
RL = 680 Ω, RL = 50 Ω
4 VPP
10
f − Frequency − MHz
Figure 9. Small-Signal Closed-Loop Gain vs Frequency
Small and Large Signal Output − dB
10
f − Frequency − MHz
f − Frequency − MHz
1000
G = 2, VCC = ±15 V,
RL = 680 Ω,RL = 50 Ω
4 VPP
12
2 VPP
6
1 VPP
0
0.5 VPP
−6
0.25 VPP
−12
0.125 VPP
−18
−24
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
Figure 11. Small- and Large-Signal Output vs Frequency
Figure 12. Small- and Large-Signal Output vs Frequency
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Typical Characteristics (continued)
0
0
G = 2,
VCC = ±5 V,
VO(PP) = 2 V,
RF = 470 Ω,
RL = 50 Ω
−20
−30
3rd Harmonic
−40
5th Harmonic
−50
−60
2nd Harmonic
−70
−80
−90
1
−20
−30
2nd Harmonic
−40
3rd Harmonic
−50
5th Harmonic
−60
−70
−80
4th Harmonic
−90
4th Harmonic
−100
0.1
G = 2,
VCC = ±15 V,
VO(PP) = 2 V,
RF = 470 Ω,
RL = 50 Ω
−10
Harmonic Distortion − dB
Harmonic Distortion − dB
−10
10
−100
0.1
100
1
10
100
f − Frequency − MHz
f − Frequency − MHz
Figure 13. Harmonic Distortion vs Frequency
Figure 14. Harmonic Distortion vs Frequency
0
0
G = 2,
VCC = ±15 V,
VO(PP) = 8 V,
RF = 470 Ω,
RL = 50 Ω
−20
−30
−40
−50
3rd Harmonic
−60
2nd Harmonic
−70
5th Harmonic
−80
−90
−20
−30
−40
−50
5th Harmonic
2nd Harmonic
−60
3rd Harmonic
−70
−80
−90
4th Harmonic
−100
0.1
4th Harmonic
1
−100
10
f − Frequency − MHz
0
0.5
1
1.5 2
Hz
V n − Voltage Noise − nV/
−30
−40
−50
5th Harmonic
−60
2nd Harmonic
−70
3rd Harmonic
−80
I n − Current Noise − pA/ Hz
100
G = 2,
VCC = ±15 V,
f = 1 MHz,
RF = 470 Ω,
RL = 50 Ω
−20
3
3.5
4
4.5
5
Figure 16. Harmonic Distortion vs Peak-to-Peak Output
Voltage
0
−10
2.5
VPP − Peak-to-Peak Output Voltage − V
Figure 15. Harmonic Distortion vs Frequency
Harmonic Distortion − dB
G = 2,
VCC = ±5 V,
f = 1 MHz,
RF = 470 Ω,
RL = 50 Ω
−10
Harmonic Distortion − dB
Harmonic Distortion − dB
−10
VCC = ±5 V to ±15 V
TA = 25°C
In−
In+
10
Vn
−90
4th Harmonic
1
−100
0
1
2
3
4
5
6
7
8
0.01
9
VPP − Peak-to-Peak Output Voltage − V
Figure 17. Harmonic Distortion vs Peak-to-Peak Output
Voltage
10
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0.1
1
10
100
f − Frequency − kHz
Figure 18. Voltage Noise and Current Noise vs Frequency
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Typical Characteristics (continued)
CMRR − Common-Mode Rejection Ratio − dB
80
0
70
−20
Crosstalk − dBc
60
50
VCC = ±5 V
40
30
20
10
0
0.1
G = 2,
VCC = ±5 V, ±15 V
RF = 470 Ω,
RL = 50 Ω,
−10
VCC = ±15 V
G = 2,
RF = 470 Ω,
RL = 50 Ω,
TA = 25°C
−30
−40
−50
−60
−70
1
10
100
−80
0.1
1000
1
100
1000
Figure 20. Crosstalk vs Frequency
Figure 19. Common-Mode Rejection Ratio vs Frequency
1800
100
VCC = ±5 V, ±15 V
RF = 1 kΩ,
G = 2,
RF = 470 Ω,
RL = 50 Ω,
TA = 25°C
1600
SR − Slew Rate − V/µ s
ZO − Output Impedance − Ω
10
f − Frequency − MHz
f − Frequency − MHz
10
1
0.1
1400
1200
VCC = ±15 V
1000
800
600
VCC = ±5 V
400
200
0
0.01
0.1
1
10
100
1000
0
1
Figure 21. Output Impedance vs Frequency
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
4
5
6
7
8
9 10
2
VCC = ±15 V,
VCM = 0 V,
RL = 100 Ω
2
3
4
5
6
7
−40
3
Figure 22. Slew Rate vs Output Voltage Step
0
1
2
VO − Output Voltage Step − V
f − Frequency − MHz
VCC = ±15 V,
RL = 100 Ω,
TA = 25°C
1.5
1
0.5
0
−0.5
−1
−1.5
−15
10
35
60
85
−2
−15
TA − Free-Air Temperature − °C
−10
−5
0
5
10
15
VCM − Common-Mode Input Voltage − V
Figure 23. Input Offset Voltage vs Free-Air Temperature
Figure 24. Input Offset Voltage vs Common-Mode Input
Voltage
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Typical Characteristics (continued)
15
12
VCC = ±15 V, IIB+
14
VO − Output Voltage − V
I IB − Input Bias Current − µ A
10
8
VCC = ±15 V, IIB−
6
4
VCC = ±5 V, IIB+
VCC = ±5 V, IIB−
2
13
12
VCC = ±15 V,
RF = 330 Ω,
TA = 25°C
11
0
−2
−40
10
−15
10
35
60
0
85
50 100 150 200 250 300 350 400 450
IL − Load Current − mA
Figure 25. Input Bias Current vs Free-Air Temperature
Figure 26. Output Voltage vs Load Current
12
12
VCC = ±15 V
8
VCC = ±5 V
6
4
2
0
−40
−15
10
85 °C
10
35
60
8
25 °C
6
−40 °C
4
2
0
85
0
2.5
TA − Free-Air Temperature − °C
Figure 27. Quiescent Current vs Free-Air Temperature
0.08
VSD = 3.3 V
RF = 750 Ω
Differenrtial Gain Error − %
Shutdown Supply Current − µ A
VCC = ±15 V
300
250
VCC = ±5 V
200
150
100
12.5
15
0.35
0.06
0.3
0.25
0.05
0.2
Gain Error
0.04
Phase Error
0.15
0.03
0.1
0.02
0.05
0.01
50
0
0
0
−40
−15
10
35
60
85
1
2
TA − Free-Air Temperature − °C
Figure 29. Shutdown Supply Current vs Free-Air
Temperature
12
10
VCC = ±5 V,
G = 2,
40 IRE Modulation
±100 IRE Ramp
NTSC
0.07
350
7.5
Figure 28. Quiescent Current vs Supply Voltage
450
400
5
VCC − Supply Voltage − ±V
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Differential Phase Error − Degree °
10
I CC − Quiescent Current − mA
I CC − Quiescent Current − mA/ Per Channel
TA − Free-Air Temperature − °C
3
4
5
6
7
8
75 Ω Serially Terminated Loads
Figure 30. Differential Phase and Gain Error vs 75-Ω
Serially-Terminated Loads
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Typical Characteristics (continued)
0.1
0
4
3
2
1
0
2
−0.1
−0.2
−0.3
1.5
VCC = ±5 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
0
100
200
300
1
0.5
0
400
500
600
0
1
2
3
t − Time − ns
0.2
0.2
VO − Output Voltage − V
VO − Output Voltage − V
0.3
0.1
0
−0.3
6
7
8
9
10
Figure 32. THS3125 Shutdown Response
0.3
VCC = ±5 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
−0.2
5
t − Time − ns
Figure 31. Differential Phase and Gain Error vs 75-Ω
Serially-Terminated Loads
−0.1
4
Shutdown Pulse − V
0.2
VO − Output Voltage − V
5
VO − Output Voltage − V
0.3
0.1
0
−0.1
VCC = ±15 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
−0.2
−0.3
0
100
200
300
400
500
600
0
100
200
300
400
500
600
t − Time − ns
Figure 33. THS3125 Shutdown Response
Figure 34. Small-Signal Pulse Response
3
3
2
2
VO − Output Voltage − V
VO − Output Voltage − V
t − Time − ns
1
0
−1
VCC = ±5 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
−2
1
0
−1
−3
−3
0
100
200
300
VCC = ±15 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
−2
400
500
600
0
100
200
300
400
500
600
t − Time − ns
t − Time − ns
Figure 35. Large-Signal Pulse Response
Figure 36. Large-Signal Pulse Response
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8 Detailed Description
8.1 Overview
The THS3122 and THS3125 family of dual-channels, bipolar-input, high-speed current feedback amplifiers offers
a low-noise of 2.2 nV/√Hz with a high output current drive of 450 mA. This performance is ideal for any
application that requires low distortion over a wide range of frequencies with heavy loads.
8.2 Feature Description
8.2.1 Maximum Slew Rate For Repetitive Signals
The THS3125 and THS3122 are recommended for high slew rate pulsed applications where the internal nodes
of the amplifier have time to stabilize between pulses. It is recommended to have at least 20-ns delay between
pulses.
The THS3125 and THS3122 are not recommended for applications with repetitive signals (sine, square,
sawtooth, or other) that exceed 900 V/µs. Using the part in these applications results in excessive current draw
from the power supply and possible device damage.
For applications with high slew rate, repetitive signals, the THS3091 and THS3095 (single versions), or THS3092
and THS3096 (dual versions) are recommended.
8.2.2 Saving Power with Shutdown Functionality and Setting Threshold Levels with the Reference Pin
The THS3125 features a shutdown pin (SHUTDOWN) that lowers the quiescent current from 8.4 mA/amp down
to 370 µA/amp, ideal for reducing system power.
The shutdown pin of the amplifier defaults to the REF pin voltage in the absence of an applied voltage, putting
the amplifier in the normal on mode of operation. To turn off the amplifier in an effort to conserve power, the
shutdown pin can be driven towards the positive rail. The threshold voltages for power-on and power-down (or
shutdown) are relative to the supply rails and are given in the Electrical Characteristics: Shutdown
Characteristics (THS3125 Only) table. Below the Enable threshold voltage, the device is on. Above the Disable
threshold voltage, the device is off. Behavior between these threshold voltages is not specified.
Note that this shutdown functionality is self-defining: the amplifier consumes less power in shutdown mode. The
shutdown mode is not intended to provide a high-impedance output. In other words, the shutdown functionality is
not intended to allow use as a 3-state bus driver. When in shutdown mode, the impedance looking back into the
output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the
device itself varies depending on the voltage applied to the outputs.
As with most current feedback amplifiers, the internal architecture places some limitations on the system when in
shutdown mode. Most notably is the fact that the amplifier actually turns on if there is a ±0.7 V or greater
difference between the two input nodes (IN+ and IN–) of the amplifier. If this difference exceeds ±0.7 V, the
output of the amplifier creates an output voltage equal to approximately [(IN+ – IN–) – 0.7V] × Gain. Also, if a
voltage is applied to the output while in shutdown mode, the IN– node voltage is equal to VO(applied) × RG/(RF +
RG) . For low gain configurations and a large applied voltage at the output, the amplifier may actually turn on
because of the behavior described here.
The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to
reach either 10% or 90% of the final output voltage. The time delays are in the order of microseconds because
the amplifier moves in and out of the linear mode of operation in these transitions.
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Feature Description (continued)
8.2.3 Power-Down Reference Pin Operation
In addition to the shutdown pin, the THS3125 features a reference pin (REF) which allows the user to control the
enable or disable power-down voltage levels applied to the SHUTDOWN pin. In most split-supply applications,
the reference pin is connected to ground. In either case, the user must be aware of voltage-level thresholds that
apply to the shutdown pin. Table 1 shows examples and illustrate the relationship between the reference voltage
and the power-down thresholds. In the table, the threshold levels are derived by the following equations:
SHUTDOWN ≤ REF + 0.8 V for enable
SHUTDOWN ≥ REF + 2V for disable
Where the usable range at the REF pin is:
VCC– ≤ VREF ≤ (VCC+ – 4V)
The recommended mode of operation is to tie the REF pin to midrail, therefore setting the enable/disable
thresholds to V(midrail) + 0.8 V and V(midrail) = 2 V, respectively.
Table 1. Shutdown Threshold Voltage Levels
SUPPLY VOLTAGE (V)
REFERENCE PIN VOLTAGE (V)
ENABLE LEVEL (V)
DISABLE LEVEL (V)
±15, ±5
0
0.8
2.0
±15
2.0
2.8
4.0
±15
–2.0
–1.2
0
±5
1.0
1.8
3.0
±5
–1.0
–0.2
1.0
+30
15.0
15.8
17
+10
5.0
5.8
7.0
Note that if the REF pin is left unterminated, it floats to the positive rail and falls outside of the recommended
operating range given above VCC– ≤ VREF ≤ (VCC+ – 4V). As a result, it no longer serves as a reliable reference
for the SHUTDOWN pin, and the enable/disable thresholds given above no longer apply. If the SHUTDOWN pin
is also left unterminated, it floats to the positive rail and the device is disabled. If balanced, split supplies are
used (±VS) and the REF and SHUTDOWN pins are grounded, the device is enabled.
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8.3 Device Functional Modes
8.3.1 Wideband, Noninverting Operation
The THS3125 and THS3122 are unity gain stable 130-MHz current-feedback operational amplifiers, designed to
operate from a ±5-V to ±15-V power supply.
Figure 37 shows the THS3125 in a noninverting gain of 2-V/V configuration used to generate the typical
characteristic curves. Most of the curves were characterized using signal sources with 50-Ω source impedance
and with measurement equipment that presents a 50-Ω load impedance.
+15 V
+VS
+
6.8 mF
0.1 mF
50-W Source
VI
49.9 W
THS3125
49.9 W
50-W Load
470 W
RF
470 W
RG
+
-15 V
-VS
0.1 mF
6.8 mF
Figure 37. Wideband, Noninverting Gain Configuration
Current-feedback amplifiers are highly dependent on the feedback resistor RF for maximum performance and
stability. Table 2 shows the optimal gain setting resistors RF and RG at different gains to give maximum
bandwidth with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense
of added peaking in the frequency response, by using even lower values for RF. Conversely, increasing RF
decreases the bandwidth, but stability is improved.
Table 2. Recommended Resistor Values For Optimum Frequency Response
THS3125 and THS3122 RF and RG VALUES FOR MINIMAL PEAKING WITH RL = 50 Ω, ±5-V to ±15-V POWER SUPPLY
GAIN (V/V)
RG (Ω)
RF (Ω)
1
—
560
2
470
470
4
66.5
200
8.3.2 Wideband, Inverting Operation
Figure 38 shows the THS3125 in a typical inverting gain configuration where the input and output impedances
from Figure 37 are retained in an inverting circuit configuration.
+15 V
+VS
+
6.8 mF
0.1 mF
49.9 W
50-W Source
RG
470 W
THS3125
50-W Load
470 W
VI
RF
56.2 W
RM
+
-15 V
-VS
6.8 mF
0.1 mF
Figure 38. Wideband, Inverting Gain Configuration
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8.3.3 Single-Supply Operation
The THS3125 and THS3122 have the capability to operate from a single supply voltage ranging from 10 V to 30
V. When operating from a single power supply, biasing the input and output at mid-supply allows for the
maximum output voltage swing. The circuits in Figure 39 show inverting and noninverting amplifiers configured
for single-supply operation.
+VS
50-W Source
VI
49.9 W
THS3125
RT
49.9 W
50-W Load
RF
470 W
+VS/2
RG
470 W
+VS/2
+VS
RG
470 W
50-W Source
RF
470 W
VI
49.9 W
THS3125
56.2 W
RT
+VS/2
50-W Load
+VS/2
Figure 39. DC-Coupled, Single-Supply Operation
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Video Distribution
The wide bandwidth, high slew rate, and high output drive current of the THS3125 and THS3122 match the
demands for video distribution to deliver video signals down multiple cables. To ensure high signal quality with
minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to
minimize group delay variations from the amplifier. A high slew rate minimizes distortion of the video signal, and
supports component video and RGB video signals that require fast transition times and fast settling times for high
signal quality. Figure 40 illustrates a typical video distribution amplifier application configuration.
470 W
470 W
+15 V
75-W Transmission Line
VO(1)
75 W
VI
75 W
-15 V
75 W
n lines
VO(n)
75 W
75 W
Figure 40. Video Distribution Amplifier Application
9.1.2 Driving Capacitive Loads
Applications such as FET drivers and line drivers can be highly capacitive and cause stability problems for highspeed amplifiers.
Figure 41 through Figure 47 show recommended methods for driving capacitive loads. The basic idea is to use a
resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier
feedback path. See Figure 41 for recommended resistor values versus capacitive load.
Recommended RISO Resistance (W)
60
50
40
30
20
10
0
10
100
CL - Capacitive Load (pF)
Figure 41. Recommended RISO vs Capacitive Load
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Application Information (continued)
Placing a small series resistor, RISO, between the amplifier output and the capacitive load, as shown in Figure 42,
is an easy way of isolating the load capacitance.
RF
+VS
RG
RISO
5.11 W
100-W Load
1 mF
-VS
+VS
49.9 W
Figure 42. Resistor To Isolate Capacitive Load
Using a ferrite chip in place of RISO, as Figure 43 shows, is another approach of isolating the output of the
amplifier. The ferrite impedance characteristic versus frequency is useful to maintain the low frequency load
independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. Use a
ferrite with similar impedance to RISO, 20 Ω to 50 Ω, at 100 MHz and low impedance at dc.
RF
+VS
RG
Ferrite
Bead
100-W Load
1 mF
-VS
+VS
49.9 W
Figure 43. Ferrite Bead To Isolate Capacitive Load
Figure 44 shows another method used to maintain the low-frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback is mainly from
the load side of RISO. At high frequency, the feedback is mainly via the 27-pF capacitor. The resistor RIN in series
with the negative input is used to stabilize the amplifier and should be equal to the recommended value of RF at
unity gain. Replacing RIN with a ferrite of similar impedance at about 100 MHz as shown in Figure 45 gives
similar results with reduced dc offset and low frequency noise.
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Application Information (continued)
RF
27 pF
+VS
RG
560 W
5.11 W
100-W Load
RIN
1 mF
-VS
+VS
49.9 W
Figure 44. Feedback Technique With Input Resistor For Capacitive Load
RF
27 pF
RG
Ferrite
Bead
+VS
5.11 W
FIN
100-W Load
1 mF
+VS
-VS
49.9 W
Figure 45. Feedback Technique With Input Ferrite Bead For Capacitive Load
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SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
Application Information (continued)
Figure 46 shows a configuration that uses two amplifiers in parallel to double the output drive current to larger
capacitive loads. This technique is used when more output current is needed to charge and discharge the load
faster as when driving large FET transistors.
RF
+VS
RG
5.11 W
24.9 W
-VS
RF
+VS
+VS
1 nF
RG
5.11 W
24.9 W
-VS
Figure 46. Parallel Amplifiers For Higher Output Drive
Figure 47 shows a push-pull FET driver circuit typical of ultrasound applications with isolation resistors to isolate
the gate capacitance from the amplifier.
+VS
+VS
5.11 W
-VS
RF
2RG
RF
+VS
5.11 W
-VS
-VS
Figure 47. Powerfet Drive Circuit
Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: THS3122 THS3125
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www.ti.com
10 Layout
10.1 Layout Guidelines
10.1.1 Printed-Circuit Board Layout Techniques For Optimal Performance
Achieving optimum performance with high-frequency amplifiers such as the THS3125 and THS3122 requires
careful attention to board layout parasitic and external component types. Recommendations that optimize
performance include:
• Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O
pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the board.
• Minimize the distance [0.25 inch, (6,4 mm)] from the power-supply pins to high-frequency 0.1-µF and 100-pF
decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity
to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and
the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling capacitors, effective at lower frequencies, should also be used
on the main supply pins. These capacitors may be placed somewhat farther from the device and may be
shared among several devices in the same area of the printed circuit board (PCB).
• Careful selection and placement of external components preserve the high-frequency performance of the
THS3125 and THS3122. Resistors should be a very low reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Again, keep the leads and PCB trace length as short as possible. Never use
wirebound type resistors in a high-frequency application. Because the output pin and inverting input pins are
the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any,
as close as possible to the inverting input pins and output pins. Other network components, such as input
termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic
capacitance that shunts the external resistors, excessively high resistor values can create significant time
constants that can degrade performance. Good axial metal-film or surface-mount resistors have
approximately 0.2 pF in shunt with the resistor. For resistor values greater than 2.0 kΩ, this parasitic
capacitance can add a pole and/or a zero that can affect circuit operation. Keep resistor values as low as
possible, consistent with load driving considerations.
• Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces [0.05 inch (1,3 mm) to 0.1 inch (2,54 mm)] should be used,
preferably with ground and power planes opened up around them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (less than 4 pF)
may not need an RS because the THS3125 and THS3122 are nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (thus
increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable, implement a matched-impedance transmission line using
microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout
techniques). A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment
improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance
based on board material and trace dimensions, a matching series resistor into the trace from the output of the
THS3125/THS3122 is used as well as a terminating shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input
impedance of the destination device: this total effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This
configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of
the destination device is low, there is some signal attenuation as a result of the voltage divider formed by the
series output into the terminating impedance.
• Socketing a high-speed device such as the THS3125 and THS3122 is not recommended. The additional lead
length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic
network which can make it almost impossible to achieve a smooth, stable frequency response. Best results
are obtained by soldering the THS3125/THS3122 amplifiers directly onto the board.
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THS3122, THS3125
www.ti.com
SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
Layout Guidelines (continued)
10.1.2 PowerPAD Design Considerations
The THS3125 and THS3122 are available in a thermally-enhanced PowerPAD family of packages. These
packages are constructed using a downset leadframe upon which the die is mounted [see Figure 48(a) and
Figure 48(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of
the package [see Figure 48(c)]. Because this thermal pad has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a good thermal path away from the thermal pad. Note that
devices such as the THS312x have no electrical connection between the PowerPAD and the die.
DIE
(a) Side View
Thermal
Pad
DIE
(b) End View
(c) Bottom View
Figure 48. Views Of Thermally-Enhanced Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: THS3122 THS3125
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THS3122, THS3125
SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
www.ti.com
Layout Guidelines (continued)
10.1.3 PowerPAD Layout Considerations
0.205
(5,21)
0.060
(1,52)
Pin 1
0.017
(0,432)
0.013
(0,33)
0.075
(1,91)
0.094
(2,39)
0.030
(0,76)
0.025
(0,64)
0.010
(0,254)
vias
0.040
(1,01)
0.035
(0,89)
Top View
Dimensions are in inches (millimeters).
Figure 49. DGN PowerPAD PCB Etch and Via Pattern
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
1. PCB with a top side etch pattern as shown in Figure 49.
2. Place five holes in the area of the thermal pad. These holes should be 0.01 inch (0,254 mm) in diameter.
Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These vias
help dissipate the heat generated by the THS3125/THS3122 IC. These additional vias may be larger than
the 0.01-inch (0,254-mm) diameter vias directly under the thermal pad. They can be larger because they are
not in the thermal pad area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane. Note that the PowerPAD is electrically isolated from the
silicon and all leads. Connecting the PowerPAD to any potential voltage, such as VS–, is acceptable as there
is no electrical connection to the silicon.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This resistance makes the soldering of vias that have plane connections
easier. In this application; however, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the holes under the THS3125/THS3122 PowerPAD package should make the connection to the
internal ground plane with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
configuration prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow
operation as any standard surface-mount component. This procedure results in a part that is properly
installed.
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THS3122, THS3125
www.ti.com
SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
Layout Guidelines (continued)
10.1.4 Power Dissipation And Thermal Considerations
The THS3125 and THS3122 incorporate automatic thermal shutoff protection. This protection circuitry shuts
down the amplifier if the junction temperature exceeds approximately +160°C. When the junction temperature
reduces to approximately +140°C, the amplifier turns on again. However, for maximum performance and
reliability, the designer must take care to ensure that the design does not exceed a junction temperature of
+125°C. Between +125°C and +150°C, damage does not occur, but the performance of the amplifier begins to
degrade and long-term reliability suffers. The thermal characteristics of the device are dictated by the package
and the PCB. Maximum power dissipation for a given package can be calculated using the following formula.
T - TA
PDMax = max
qJA
where:
θJA
• PDMax is the maximum power dissipation in the amplifier (W)
• Tmax is the absolute maximum junction temperature (°C)
• TA is the ambient temperature (°C)
= θJC + θCA
where:
•
•
θJC is the thermal coefficient from the silicon junctions to the case (°C/W)
θCA is the thermal coefficient from the case to ambient air (°C/W)
PDMax - Maximum Power Dissipation (W)
For systems where heat dissipation is more critical, the THS3125 and THS3122 are also available in an 8-pin
MSOP with PowerPAD package that offers even better thermal performance. The thermal coefficient for the
PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are
depicted in Figure 50 for the available packages. The data for the PowerPAD packages assume a board layout
that follows the PowerPAD layout guidelines discussed above and detailed in the PowerPAD application note
(literature number SLMA002). Figure 50 also illustrates the effect of not soldering the PowerPAD to a PCB. The
thermal impedance increases substantially, which may cause serious heat and performance issues. Always
solder the PowerPAD to the PCB for optimum performance.
4.0
TJ = +125°C
3.5
3.0
qJA = 58.4°C/W
2.5
2.0
qJA = 95°C/W
1.5
1.0
0.5
qJA = 158°C/W
0
-40
-20
0
20
40
60
80
100
TA - Free-Air Temperature (°C)
Results shown are with no air flow and PCB size of 3 in × 3 in (76,2 mm × 76,2 mm).
•
θJA = 58.4°C/W for 8-pin MSOP with PowerPAD (DGN package)
•
θJA = 95°C/W for 8-pin SOIC High-K test PCB (D package)
•
θJA = 158°C/W for 8-pin MSOP with PowerPAD without solder
Figure 50. Maximum Power Dissipation vs Ambient Temperature
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important
to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this type of
dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power
dissipation can provide visibility into a possible problem.
Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: THS3122 THS3125
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SLOS382E – SEPTEMBER 2001 – REVISED MAY 2015
www.ti.com
11 Device and Documentation Support
11.1 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
THS3122
Click here
Click here
Click here
Click here
Click here
THS3125
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Product Folder Links: THS3122 THS3125
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
THS3122CD
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3122C
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
3122C
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3122I
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3122I
THS3125CPWP
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
HS3125C
THS3125ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
THS3125I
THS3125IPWP
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
HS3125I
THS3125IPWPR
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
HS3125I
THS3122ID
THS3122IDDA
SOIC
Eco Plan
D
THS3122CDDA
ACTIVE
Package Type Package Pins Package
Drawing
Qty
ACTIVE SO PowerPAD
ACTIVE
SOIC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS3125IPWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
14
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS3125IPWPR
HTSSOP
PWP
14
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
A
SEATING PLANE
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
8X
B
4.0
3.8
NOTE 4
0.51
0.31
0.25
1.7 MAX
C A B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
3.4
2.8
0.25
GAGE PLANE
9
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.71
2.11
TYPICAL
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
9
SYMM
(1.3)
TYP
(3.4)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
( 0.2) TYP
VIA
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
9
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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