Texas Instruments | OPA627 and OPA637 Precision High-Speed Difet® Operational Amplifiers (Rev. A) | Datasheet | Texas Instruments OPA627 and OPA637 Precision High-Speed Difet® Operational Amplifiers (Rev. A) Datasheet

Texas Instruments OPA627 and OPA637 Precision High-Speed Difet® Operational Amplifiers (Rev. A) Datasheet
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OPA627, OPA637
SBOS165A – SEPTEMBER 2000 – REVISED OCTOBER 2015
OPA627 and OPA637 Precision High-Speed Difet® Operational Amplifiers
1 Features
•
•
1
•
•
•
•
•
The OPA6x7 is fabricated on a high-speed,
dielectrically-isolated
complementary
NPN/PNP
process. It operates over a wide range of power
supply voltage of ±4.5 V to ±18 V. Laser-trimmed
Difet input circuitry provides high accuracy and lownoise performance comparable with the best bipolarinput operational amplifiers.
Very Low Noise: 4.5 nV/√Hz at 10 kHz
Fast Settling Time:
– OPA627—550 ns to 0.01%
– OPA637—450 ns to 0.01%
Low VOS: 100-µV maximum
Low Drift: 0.8-µV/°C maximum
Low IB: 5-pA maximum
OPA627: Unity-Gain Stable
OPA637: Stable in Gain ≥ 5
High frequency complementary transistors allow
increased circuit bandwidth, attaining dynamic
performance not possible with previous precision FET
operational amplifiers. The OPA627 is unity-gain
stable. The OPA637 is stable in gains equal to or
greater than five.
2 Applications
•
•
•
•
•
•
•
•
Difet fabrication achieves extremely low input bias
currents without compromising input voltage noise
performance. Low input bias current is maintained
over a wide input common-mode voltage range with
unique cascode circuitry.
Precision Instrumentation
Fast Data Acquisition
DAC Output Amplifier
Optoelectronics
Sonar, Ultrasound
High-Impedance Sensor Amps
High-Performance Audio Circuitry
Active Filters
The OPA6x7 is available in plastic PDIP, SOIC, and
metal TO-99 packages. Industrial and military
temperature range models are available.
Device Information(1)
PART NUMBER
3 Description
OPA627
OPA637
The OPA6x7 Difet® operational amplifiers provide a
new level of performance in a precision FET
operational amplifier. When compared to the popular
OPA111 operational amplifier, the OPA6x7 has lower
noise, lower offset voltage, and higher speed. The
OPA6x7 is useful in a broad range of precision and
high speed analog circuitry.
PACKAGE
BODY SIZE (NOM)
SOIC (8)
3.91 mm × 4.9 mm
PDIP (8)
6.35 mm × 9.81 mm
TO-99 (8)
8.95 mm (metal can
diameter)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
OPA627 Simplified Schematic
Trim
1
7
+VS
Trim
5
Output
6
+In
3
–In
2
–VS
4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA627, OPA637
SBOS165A – SEPTEMBER 2000 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Settling Time ...........................................................
12
12
12
19
7.5 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2000) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Removed Lead Temperature from Absolute Maximum Ratings table. ................................................................................. 3
2
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5 Pin Configuration and Functions
P and D Packages
8-Pin PDIP and SOIC
Top View
LMC Package
8-Pin TO-99
Top View
No Internal Connection
Offset Trim
1
8
No Internal Connection
–In
2
7
+VS
8
+VS
Offset Trim
1
+In
3
6
Output
–VS
4
5
Offset Trim
–In
7
2
6
3
+In
Output
5
4
Offset Trim
–VS
Case connected to –VS.
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
Offset Trim
—
2
–In
I
Input offset voltage trim (leave floating if not used)
Inverting input
3
+In
I
Noninverting input
4
–VS
—
Negative (lowest) power supply
5
Offset Trim
—
Input offset voltage trim (leave floating if not used)
6
Output
O
Output
7
+VS
—
Positive (highest) power supply
8
NC
—
No internal connection (can be left floating)
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
±18
V
+VS + 2
–VS – 2
V
Supply Voltage
Input Voltage Range
Differential Input
Power Dissipation
Operating Temperature
Junction Temperature
Storage temperature, Tstg
(1)
Total VS + 4
V
1000
mW
LMC Package
–55
125
P, D Package
–40
125
LMC Package
175
P, D Package
150
LMC Package
–65
150
P, D Package
–40
125
°C
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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6.2 ESD Ratings
VALUE
UNIT
±2500
V
±1000
V
OPA627 and OPA637 in PDIP and SOIC Packages
Electrostatic
discharge
V(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
OPA627 and OPA637 in SOIC Packages
Electrostatic
discharge
V(ESD)
(1)
(2)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vs = (V+) - (V-)
Specified
temperature
MIN
NOM
MAX
UNIT
9 (±4.5)
30 (±15)
36 (±18)
V
P and D packages
–25
25
85
°C
LMC package
–55
25
125
°C
6.4 Thermal Information
OPA627, OPA637
THERMAL METRIC (1)
P (DIP)
D (SOIC)
LMC (TO-99)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
46.2
107.9
200
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
34.5
57.3
—
°C/W
RθJB
Junction-to-board thermal resistance
23.5
49.7
—
°C/W
ψJT
Junction-to-top characterization parameter
11.7
11.7
—
°C/W
ψJB
Junction-to-board characterization parameter
23.3
48.9
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
At TA = 25°C, and VS = ±15 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE (1)
BM, SM grades
Input offset voltage
Average drift
40
100
AM grade
130
250
BP grade
100
250
AP, AU grades
280
500
BM, SM grades
0.4
0.8
AM grade
1.2
2
BP grade
0.8
2
AP, AU grades
Power supply rejection
µV
µV/°C
2.5
VS = ±4.5 to ±18 V
BM, BP, SM grades
106
120
AM, AP, AU grades
100
116
dB
INPUT BIAS CURRENT (2)
TA = 25°C
VCM = 0 V
BM, BP, SM grades
1
5
AM, AP, AU grades
2
10
BM, BP grades
Over specified
temperature
Input bias current
1
SM grade
50
AM, AP, AU grades
VCM = ±10 V, over common-mode voltage
TA = 25°C
Input offset current
VCM = 0 V
nA
2
BM, BP, SM grades
1
AM, AP, AU grades
2
BM, BP, SM grades
0.5
5
AM, AP, AU grades
1
10
BM, BP grades
Over specified
temperature
pA
pA
pA
1
SM grade
50
AM, AP, AU grades
nA
2
NOISE
f = 10 Hz
f = 100 Hz
Input voltage noise density
f = 1 kHz
f = 10 kHz
Input voltage noise
BW = 0.1 Hz to 10 Hz
Input bias-current noise
density
f = 100 Hz
Input bias-current noise
BW = 0.1 Hz to 10 Hz
BM, BP, SM grades
15
AM, AP, AU grades
20
BM, BP, SM grades
8
AM, AP, AU grades
10
BM, BP, SM grades
5.2
AM, AP, AU grades
5.6
BM, BP, SM grades
4.5
AM, AP, AU grades
4.8
BM, BP, SM grades
0.6
AM, AP, AU grades
0.8
BM, BP, SM grades
1.6
AM, AP, AU grades
2.5
BM, BP, SM grades
30
AM, AP, AU grades
48
40
20
8
nV/√Hz
6
1.6
2.5
60
µVp-p
fA/√Hz
fAp-p
INPUT IMPEDANCE
1013 || 8
Differential
13
Common-mode
10
|| 7
Ω || pF
Ω || pF
INPUT VOLTAGE RANGE
Common-mode input range
Common-mode rejection
(1)
(2)
TA = 25°C
±11
±11.5
±10.5
±11
BM, BP, SM grades
106
116
AM, AP, AU grades
100
110
Over specified temperature
VCM = ±10.5 V
V
dB
Offset voltage measured fully warmed-up.
High-speed test at TJ = 25°C. See Typical Characteristics for warmed-up performance.
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Electrical Characteristics (continued)
At TA = 25°C, and VS = ±15 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
BM, BP, SM grades
112
120
AM, AP, AU grades
106
116
BM, BP grades
106
117
SM grade
100
114
AM, AP, AU grades
100
110
G = –1, 10-V step, OPA627
40
55
G = –4, 10-V step, OPA637
100
135
MAX
UNIT
OPEN-LOOP GAIN
TA = 25°C
Open-loop voltage gain
VO = ±10 V, RL = 1kΩ
Over specified
temperature
dB
FREQUENCY RESPONSE
Slew rate
G = –1, 10-V step,
OPA627
0.01%
550
0.1%
450
G = –4, 10-V step,
OPA637
0.01%
450
0.1%
300
Settling time
Gain-bandwidth product
Total harmonic distortion +
noise
G = 1, OPA627
16
G = 10, OPA637
80
G = 1, f = 1 kHz
0.00003%
V/µs
ns
MHz
POWER SUPPLY
Specified operating voltage
±15
Operating voltage range
±4.5
Current
±7
V
±18
V
±7.5
mA
OUTPUT
Voltage output
Current output
RL = 1 kΩ
Over specified temperature
±12.3
±11
±11.5
±35
±70/–55
VO = ±10 V
V
±45
Short-circuit current
Output impedance, open-loop
±11.5
1 MHz
mA
±100
mA
Ω
55
TEMPERATURE RANGE
Temperature range
specification
6
AP, BP, AM, BM, AU grades
–25
85
SM grade
–55
125
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6.6 Typical Characteristics
At TA = 25°C, and VS = ±15 V, unless otherwise noted.
100
Input Voltage Noise (µV)
Voltage Noise (nV/ √ Hz)
1k
100
10
1
10
1
0.1
RMS
0.01
1
10
100
1k
10k
100k
1M
10M
1
10
100
Frequency (Hz)
10k
100k
1M
10M
Figure 2. Total Input Voltage Noise vs Bandwidth
1k
140
–
120
Voltage Gain (dB)
+
Voltage Noise (nV/ √ Hz)
1k
Bandwidth (Hz)
Figure 1. Input Voltage Noise Spectral Density vs Frequency
RS
100
Comparison with
OPA27 Bipolar Op
Amp + Resistor
OPA627 + Resistor
10
OPA637
100
80
60
40
OPA627
20
Spot Noise
at 10kHz
Resistor Noise Only
0
–20
1
1k
10k
100k
1M
10M
100M
1
10
Source Resistance ( Ω)
Figure 3. Voltage Noise vs Source Resistance
–120
20
Phase
–150
–10
1
10
Gain (dB)
30
Gain
0
10k
100k
1M
10M
100M
Figure 4. Open-Loop Gain vs Frequency
–90
Phase (Degrees)
20
75° Phase
Margin
1k
Frequency (Hz)
30
10
100
–90
–120
Phase
Gain
10
–180
0
–210
100
–10
–150
Phase (Degrees)
100
Gain (dB)
p-p
Noise Bandwidth:
0.1Hz to indicated
frequency.
–180
–210
1
10
100
Frequency (MHz)
Frequency (MHz)
Figure 5. OPA627 Gain/Phase vs Frequency
Figure 6. OPA637 Gain/Phase vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, and VS = ±15 V, unless otherwise noted.
100
Output Resistance (Ω)
125
Voltage Gain (dB)
120
115
110
80
60
40
20
105
–75
0
–50
–25
0
25
50
75
100
2
125
20
200
2k
120
Common-Mode Rejection (dB)
Common-Mode Rejection Ratio (dB)
2M
20M
130
OPA637
100
80
OPA627
60
40
20
1
10
100
1k
10k
100k
1M
120
110
100
90
80
–15
0
10M
–10
–5
0
5
10
15
Frequency (Hz)
Common-Mode Voltage (V)
Figure 9. Common-Mode Rejection vs Frequency
Figure 10. Common-Mode Rejection vs Input Common-Mode
Voltage
125
140
120
PSR
100
–VS PSRR 627
and 637
80
60
+VS PSRR 627
637
40
CMR and PSR (dB)
Power-Supply Rejection (dB)
200k
Figure 8. Open-Loop Output Impedance vs Frequency
Figure 7. Open-Loop Gain vs Temperature
140
120
CMR
115
110
20
105
0
1
8
20k
Frequency (Hz)
Temperature (°C)
10
100
1k
10k
100k
1M
10M
–75
–50
–25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
Figure 11. Power-Supply Rejection vs Frequency
Figure 12. Power-Supply Rejection and Common-Mode
Rejection vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, and VS = ±15 V, unless otherwise noted.
8
100
Output Current (mA)
Supply Current (mA)
+IL at VO = 0V
80
7.5
7
6.5
+IL at VO = +10V
60
40
–IL at VO = 0V
20
–IL at VO = –10V
0
6
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 13. Supply Current vs Temperature
Figure 14. Output Current Limit vs Temperature
60
24
160
120
16
55
GBW
12
8
–75
100
140
80
120
GBW
–25
0
25
50
75
100
100
60
80
40
50
–50
125
–50
–75
–25
0
Temperature (°C)
G = +1
VI
–
600 Ω
1
+
VO = ±10V
–
600Ω
5kΩ
100pF
G = +10
VI
0.1
549 Ω
VO = ±10V
5k Ω
600Ω
VI
100
Measurement BW: 80kHz
G = +10
0.0001
+
125
VO = ±10V
–
5k Ω
100pF
549Ω
0.001
75
G = +50
+
–
100pF
THD+N (%)
THD+N (%)
0.01
VI
50
Figure 16. OPA637 Gain-Bandwidth and Slew Rate vs
Temperature
G = +10
VO = ±10V
+
25
Temperature (°C)
Figure 15. OPA627 Gain-Bandwidth and Slew Rate vs
Temperature
0.1
Slew Rate (V/µs)
Slew Rate
Gain-Bandwidth (MHz)
20
Slew Rate (V/µs)
Gain-Bandwidth (MHz)
Slew Rate
600Ω
100pF
102 Ω
0.01
G = +50
Measurement BW: 80kHz
0.001
G = +1
0.00001
G = +10
0.0001
20
100
1k
10k
20k
20
100
1k
10k
20k
Frequency (Hz)
Frequency (Hz)
Figure 17. OPA627 Total Harmonic Distortion + Noise vs
Frequency
Figure 18. OPA637 Total Harmonic Distortion + Noise vs
Frequency
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Typical Characteristics (continued)
At TA = 25°C, and VS = ±15 V, unless otherwise noted.
20
10k
100
Input Bias Current (pA)
Input Current (pA)
1k
IB
10
IOS
1
NOTE: Measured fully
warmed-up.
15
TO-99
10
Plastic
DIP, SOIC
5
TO-99 with 0807HS Heat Sink
0
0.1
–50
–25
0
25
50
75
100
125
150
±8
±10
±12
±14
±16
±18
Supply Voltage (±V S)
Figure 19. Input Bias and Offset Current vs Junction
Temperature
Figure 20. Input Bias Current vs Power Supply Voltage
50
Beyond Linear
Common-Mode Range
1.1
Offset Voltage Change (µV)
Input Bias Current Multiplier
±6
Junction Temperature (°C)
1.2
1
0.9
Beyond Linear
Common-Mode Range
0.8
25
0
–25
–50
–15
–10
–5
0
5
Common-Mode Voltage (V)
10
15
0
1
2
3
4
5
6
Time From Power Turn-On (Min)
Figure 21. Input Bias Current vs Common-Mode Voltage
Figure 22. Input Offset Voltage Warm-up vs Time
100
30
Error Band: ±0.01%
Settling Time (µs)
Output Voltage (Vp-p)
±4
20
OPA637
10
10
OPA627
1
OPA637
OPA627
0.1
0
100k
10
1M
10M
100M
–1
–10
–100
–1000
Frequency (Hz)
Closed-Loop Gain (V/V)
Figure 23. Maximum Output Voltage vs Frequency
Figure 24. Settling Time vs Closed-Loop Gain
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Typical Characteristics (continued)
At TA = 25°C, and VS = ±15 V, unless otherwise noted.
1500
–
1000
+
RF
–5V
2kΩ
OPA627
RI 2kΩ
RF 2kΩ
CF 6pF
OPA637
500Ω
2kΩ
4pF
OPA627
G = –1
500
Settling Time (µs)
+5V
RI
Settling Time (ns)
3
CF
OPA637
G = –4
Error Band:
±0.01%
2
OPA627
G = –1
1
OPA637
G = –4
0
0.001
0
0.01
0.1
1
10
0
150
200
300
400
500
Load Capacitance (pF)
Error Band (%)
Figure 25. Settling Time vs Error Band
Figure 26. Settling Time vs Load Capacitance
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7 Detailed Description
7.1 Overview
The OPA6x7 Difet operational amplifiers provide a new level of performance in a precision FET operational
amplifier. When compared to the popular OPA111 operational amplifier, the OPA6x7 has lower noise, lower
offset voltage, and higher speed. The OPA6x7 is useful in a broad range of precision and high speed analog
circuitry.
The OPA6x7 is fabricated on a high-speed, dielectrically-isolated complementary NPN/PNP process. It operates
over a wide range of power supply voltage of ±4.5 V to ±18 V. Laser-trimmed Difet input circuitry provides high
accuracy and low-noise performance comparable with the best bipolar-input operational amplifiers.
High frequency complementary transistors allow increased circuit bandwidth, attaining dynamic performance not
possible with previous precision FET operational amplifiers. The OPA627 is unity-gain stable. The OPA637 is
stable in gains equal to or greater than five.
Difet fabrication achieves extremely low input bias currents without compromising input voltage noise
performance. Low input bias current is maintained over a wide input common-mode voltage range with unique
cascode circuitry.
The OPA6x7 is available in plastic PDIP, SOIC, and metal TO-99 packages. Industrial and military temperature
range models are available.
7.2 Functional Block Diagram
Trim
1
7
+VS
Trim
5
Output
6
+In
3
–In
2
–VS
4
7.3 Feature Description
The OPA627 is unity-gain stable. The OPA637 may achieve higher speed and bandwidth in circuits with noise
gain greater than five. Noise gain refers to the closed-loop gain of a circuit, as if the noninverting operational
amplifier input were being driven. For example, the OPA637 may be used in a noninverting amplifier with gain
greater than five, or an inverting amplifier of gain greater than four.
When choosing between the OPA627 or OPA637, consider the high frequency noise gain of your circuit
configuration. Circuits with a feedback capacitor (see Figure 27) place the operational amplifier in unity noisegain at high frequency. These applications must use the OPA627 for proper stability. An exception is the circuit in
Figure 28, where a small feedback capacitance is used to compensate for the input capacitance at the inverting
input of the operational amplifier. In this case, the closed-loop noise gain remains constant with frequency, so if
the closed-loop gain is equal to five or greater, the OPA637 may be used.
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Feature Description (continued)
RF < 4RI
–
+
OPA627
OPA627
–
+
Buffer
Non-Inverting Amp
G<5
RI
RF < 4R
RI
OPA627
–
+
OPA627
–
+
Bandwidth
Limiting
Inverting Amp
G < |–4|
OPA627
OPA627
–
–
+
+
Integrator
Filter
Figure 27. Circuits With Noise Gain Less Than Five Require the OPA627 for Proper Stability
C2
R2
C1
–
+
R1
OPA637
C1 = CIN + CSTRAY
C2 =
R1 C1
R2
Figure 28. Circuits With Noise Gain Equal to or Greater Than Five May Use the OPA637
7.3.1 Offset Voltage Adjustment
The OPA6x7 is laser-trimmed for low offset voltage and drift, so many circuits will not require external
adjustment. Figure 29 shows the optional connection of an external potentiometer to adjust offset voltage. This
adjustment should not be used to compensate for offsets created elsewhere in a system (such as in later
amplification stages or in an A/D converter), because this could introduce excessive temperature drift. Generally,
the offset drift will change by approximately 4 µV/°C for 1 mV of change in the offset voltage due to an offset
adjustment (as shown in Figure 29).
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Feature Description (continued)
+VS
100kΩ
7
10kΩ to 1MΩ
Potentiometer
(100kΩ preferred)
1
2
3
–
+
5
6
OPA627/637
4
–VS
±10mV Typical
Trim Range
Figure 29. Optional Offset Voltage Trim Circuit
7.3.2 Noise Performance
Some bipolar operational amplifiers may provide lower voltage noise performance, but both voltage noise and
bias current noise contribute to the total noise of a system. The OPA6x7 provides both low voltage noise and low
current noise. This provides optimum noise performance over a wide range of sources, including reactive-source
impedances. This can be seen in the performance curve showing the noise of a source resistor combined with
the noise of an OPA627. Above a 2-kΩ source resistance, the operational amplifier contributes little additional
noise. Below 1 kΩ, operational amplifier noise dominates over the resistor noise, but compares favorably with
precision bipolar operational amplifiers.
7.3.3 Input Bias Current
Difet fabrication of the OPA6x7 provides low input bias current. Because the gate current of a FET doubles
approximately every 10°C, to achieve lowest input bias current, keep the die temperature as low as possible. The
high speed, and therefore higher quiescent current, of the OPA6x7 can lead to higher chip temperature. A simple
press-on heat sink such as the Burr-Brown model 807HS (TO-99 metal package) can reduce chip temperature
by approximately 15°C, lowering the IB to one-third its warmed-up value. The 807HS heat sink can also reduce
low-frequency voltage noise caused by air currents and thermoelectric effects. See the data sheet on the 807HS
for details.
Temperature rise in the plastic PDIP and SOIC packages can be minimized by soldering the device to the circuit
board. Wide copper traces also help dissipate heat.
The OPA6x7 may also be operated at reduced power supply voltage, to minimize power dissipation and
temperature rise. Using ±5-V power supplies reduces power dissipation to one-third of that at ±15 V. This
reduces the IB of TO- 99 metal package devices to approximately one-fourth the value at ±15 V.
Leakage currents between printed-circuit-board traces can easily exceed the input bias current of the OPA6x7. A
circuit board guard pattern (see Figure 30) reduces leakage effects. By surrounding critical high impedance input
circuitry with a low impedance circuit connection at the same potential, leakage current will flow harmlessly to the
low-impedance node. The case (TO-99 metal package only) is internally connected to –VS.
Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts
and circuit boards may be removed with cleaning solvents and deionized water. Each rinsing operation should be
followed by a 30-minute bake at 85°C.
Many FET-input operational amplifiers exhibit large changes in input bias current with changes in input voltage.
Input stage cascode circuitry makes the input bias current of the OPA6x7 virtually constant with wide commonmode voltage changes. This is ideal for accurate, high input-impedance buffer applications.
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Feature Description (continued)
Non-inverting
2
Buffer
2
–
6
3
In
+
Out
3
In
OPA627
–
6
Out
+
OPA627
TO-99 Bottom View
Inverting
In
OPA627
2
3
–
4
3
5
6
Out
+
2
Board Layout for Input Guarding:
Guard top and bottom of board.
Alternate—use Teflon ® standoff for sensitive input pins.
6
7
1
Teflon ® E.I. du Pont de Nemours & Co.
8 No Internal Connection
To Guard Drive
B.
Figure 30. Connection of Input Guard for Lowest IB
7.3.4 Phase-Reversal Protection
The OPA6x7 has internal phase-reversal protection. Many FET-input operational amplifiers exhibit a phase
reversal when the input is driven beyond its linear common-mode range. This is most often encountered in
noninverting circuits when the input is driven below –12 V, causing the output to reverse into the positive rail. The
input circuitry of the OPA6x7 does not induce phase reversal with excessive common-mode voltage, so the
output limits into the appropriate rail.
7.3.5 Output Overload
When the inputs to the OPA6x7 are overdriven, the output voltage of the OPA6x7 smoothly limits at
approximately 2.5 V from the positive and negative power supplies. If driven to the negative swing limit, recovery
takes approximately 500 ns. When the output is driven into the positive limit, recovery takes approximately 6 µs.
Output recovery of the OPA627 can be improved using the output clamp circuit shown in Figure 31. Placing
diodes at the inverting input prevent degradation of input bias current.
+VS
5kΩ
(2)
HP 5082-2811
ZD1
Diode Bridge
BB: PWS740-3
5kΩ
ZD1 : 10V IN961
1kΩ
RF
VI
–
RI
+
–VS
VO
OPA627
Clamps output
at VO = ±11.5V
Figure 31. Clamp Circuit for Improved Overload Recovery
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Feature Description (continued)
7.3.6 Capacitive Loads
As with any high-speed operational amplifier, best dynamic performance can be achieved by minimizing the
capacitive load. Because a load capacitance presents a decreasing impedance at higher frequency, a load
capacitance which is easily driven by a slow operational amplifier can cause a high-speed operational amplifier to
perform poorly. See the typical curves showing settling times as a function of capacitive load. The lower
bandwidth of the OPA627 makes it the better choice for driving large capacitive loads. Figure 32 shows a circuit
for driving very large load capacitance. The two-pole response of this circuit can also be used to sharply limit
system bandwidth, often useful in reducing the noise of systems which do not require the full bandwidth of the
OPA627.
RF
1kΩ
200pF
CF
–
G = +1
BW ≥ 1MHz
RO
20Ω
+
G = 1+
RF
R1
Optional Gain
Gain > 1
CL
5nF
OPA627
R1
For Approximate Butterworth Response:
2 RO CL
RF >> RO
CF =
RF
f–3dB =
1
2p √ RF RO CF CL
Figure 32. Driving Large Capacitive Loads
7.3.7 Input Protection
The inputs of the OPA6x7 are protected for voltages from +VS + 2 V to –VS – 2 V. If the input voltage can exceed
these limits, the amplifier should be protected. The diode clamps shown in (a) in Figure 33 prevent the input
voltage from exceeding one forward diode voltage drop beyond the power supplies, which is well within the safe
limits. If the input source can deliver current in excess of the maximum forward current of the protection diodes,
use a series resistor, RS, to limit the current. Be aware that adding resistance to the input increases noise. The 4nV/√Hz theoretical thermal noise of a 1-kΩ resistor will add to the 4.5-nV/√Hz noise of the OPA6x7 (by the
square-root of the sum of the squares), producing a total noise of 6 nV/√Hz. Resistors less than 100 Ω add
negligible noise.
Leakage current in the protection diodes can increase the total input bias current of the circuit. The specified
maximum leakage current for commonly used diodes such as the 1N4148 is approximately 25 nA, more than a
thousand times larger than the input bias current of the OPA6x7. Leakage current of these diodes is typically
much lower and may be adequate in many applications. Light falling on the junction of the protection diodes can
dramatically increase leakage current, so common glass-packaged diodes should be shielded from ambient light.
Very low leakage can be achieved by using a diode-connected FET as shown. The 2N4117A is specified at 1 pA
and its metal case shields the junction from light.
Sometimes input protection is required on I/V converters of inverting amplifiers; see (b) in Figure 33. Although in
normal operation, the voltage at the summing junction will be near zero (equal to the offset voltage of the
amplifier), and large input transients may cause this node to exceed 2 V beyond the power supplies. In this case,
the summing junction should be protected with diode clamps connected to ground. Even with the low voltage
present at the summing junction, common signal diodes may have excessive leakage current. Because the
reverse voltage on these diodes is clamped, a diode-connected signal transistor can act as an inexpensive low
leakage diode; see (b) in Figure 33.
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Feature Description (continued)
+VS
–
VO
D
+
D
OPA627
D: IN4148 — 25nA Leakage
2N4117A — 1pA Leakage
Siliconix
Optional RS
–VS
=
(a)
IIN
–
D
D
VO
+
OPA627
D: 2N3904
=
(b)
NC
Figure 33. Input Protection Circuits
7.3.8 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this report provides the EMIRR IN+, which specifically describes the EMIRR performance when
the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the noninverting
input is tested for EMIRR for the following three reasons:
• Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
• The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to
the noninverting input terminal with no complex interactions from other components or connecting PCB
traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in application report EMI
Rejection Ratio of Operational Amplifiers (SBOA128), available for download at www.ti.com.
The EMIRR IN+ of the OPA627 is plotted versus frequency as shown in Figure 34. If available, any dual and
quad operational amplifier device versions have nearly similar EMIRR IN+ performance. The OPA627 unity-gain
bandwidth is 16 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
operational amplifier bandwidth.
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Feature Description (continued)
140
PRF = -10 dbm
120 VS = r15 V
VCM = 0 V
EMIRR IN+ (db)
100
80
60
40
20
0
10M
100M
1G
Frequency (MHz)
10G
Figure 34. OPA627 EMIRR IN+ vs Frequency
Table 1 shows the EMIRR IN+ values for the OPA627 at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 1. OPA627 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION / ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite/space operation, weather, radar, UHF
46.2 dB
900 MHz
GSM, radio com/nav./GPS (to 1.6 GHz), ISM, aeronautical mobile,
UHF
60.3 dB
1.8 GHz
GSM, mobile personal comm. broadband, satellite, L-band
81 dB
2.4 GHz
802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur
radio/satellite, S-band
96.9 dB
3.6 GHz
Radiolocation, aero comm./nav., satellite, mobile, S-band
108.9 dB
5 Ghz
802.11a/n, aero comm./nav., mobile comm., space/satellite
operation, C-band
116.8 dB
7.3.8.1 EMIRR IN+ Test Configuration
Figure 35 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input terminal using a transmission line. The operational amplifier is configured
in a unity gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter
(DMM). A large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this
effect is characterized and accounted for when determining the EMIRR IN+. The resulting DC offset voltage is
sampled and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that may
interfere with multimeter accuracy. Refer to SBOA128 for more details.
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Ambient temperature: 25Û&
+VS
±
50
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
-VS
Sample /
Averaging
Not shown: 0.1 µF and 10 µF
supply decoupling
Digital Multimeter
Figure 35. EMIRR IN+ Test Configuration Schematic
7.4 Settling Time
The OPA627 and OPA637 have fast settling times, as low as 300 ns. Figure 36 illustrates the circuit used to
measure settling time for the OPA627 and OPA637.
Error Out
/
RI
2kWΩ
CF
HP50822835
RI , R 1
CF
Error Band
(0.01%)
2kΩ
OPA627
OPA637
2kΩ
6pF
±0.5mV
500Ω
4pF
±0.2mV
+15V
High Quality
Pulse Generator
RI
–
51Ω
±5V
Out
+
NOTE: CF is selected for best settling time performance
depending on test fixture layout. Once optimum value is
determined, a fixed capacitor may be used.
–15V
Figure 36. Settling Time and Slew Rate Test Circuit
7.5 Device Functional Modes
The OPA627 and OPA6377 have a single functional mode and are operational when the power-supply voltage is
greater than 9V (±4.5 V). The maximum power supply voltage for the OPA627 and OPA637 are 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA627 and OPA637 are ideally suited to use as input amplifiers in instrumentation amplifier configurations
requiring high speed, fast settling and high input impedance.
–In
+
OPA637
–
RF
5kWΩ
Gain = 100
CMRR » 116dB
Bandwidth » 1MHz
2
Input Common-Mode
Range = ±5V
RG
101Ω
25kΩ
25kΩ
INA105
Differential
Amplifier
3pF
–
3
+In
–
RF
5kΩ
+
OPA637
5
Output
6
+
25kΩ
25kΩ
1
Differential Voltage Gain = 1 + 2R F /RG
Figure 37. High Speed Instrumentation Amplifier, Gain = 100
–In
+
–
Gain = 1000
CMRR » 116dB
Bandwidth » 400kHz
OPA637
RF
5kΩ
2
Input Common-Mode
Range = ±10V
RG
101Ω
10kΩ
INA106
Differential
Amplifier
3pF
3
–
+In
+
RF
5kΩ
100kΩ
5
–
6
Output
+
10kΩ
100kΩ
1
OPA637
Differential Voltage Gain = (1 + 2R F /RG) • 10
Figure 38. High Speed Instrumentation Amplifier, Gain = 1000
This composite amplifier uses the OPA603 current-feedback op amp to
provide extended bandwidth and slew rate at high closed-loop gain. The
feedback loop is closed around the composite amp, preserving the
precision input characteristics of the OPA627/637. Use separate power
supply bypass capacitors for each op amp.
R2
–
A1
VI
+
∗Minimize capacitance at this node.
VO
+
–
OPA603
R1
R3
*
R4
RL ‡ 150Ω
for ±10V Out
GAIN
(V/V)
A1
OP AMP
W
100
1000
OPA627
OPA637
R1
(Ω )
R2
(kΩ)
R3
(Ω )
R4
(kΩ)
–3dB
(MHz)
SLEW RATE
(V/µs)
50.5 (1) 4.99
49.9 4.99
20
12
1
1
15
11
700
500
NOTE: (1) Closest 1/2% value.
Figure 39. Composite Amplifier for Wide Bandwidth
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Application Information (continued)
SMALL SIGNAL RESPONSE
LARGE SIGNAL RESPONSE
(A)
(B)
FPO
When used as a unity-gain buffer, large common-mode input voltage steps
produce transient variations in input-stage currents. This causes the rising
edge to be slower and falling edges to be faster than nominal slew rates
observed in higher-gain circuits.
G=1
–
+
OPA627
Figure 40. OPA627 Dynamic Performance, G = 1
LARGE SIGNAL RESPONSE
+10
0
(C)
–10
VOUT (V)
VOUT (V)
+10
0
(D)
–10
6pF(1)
When driven with a very fast input step (left), common-mode
transients cause a slight variation in input stage currents which
will reduce output slew rate. If the input step slew rate is reduced
(right), output slew rate will increase slightly.
NOTE: (1) Optimum value will
depend on circuit board layout and stray capacitance at
the inverting input.
2kΩ
G = –1
–
2kΩ
+
VOUT
OPA627
Figure 41. OPA627 Dynamic Performance, G = –1
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Application Information (continued)
OPA637
LARGE SIGNAL RESPONSE
OPA637
SMALL SIGNAL RESPONSE
+100
0
VOUT (mV)
VOUT (V)
+10
(E)
0
(F)
FPO
–100
–10
4pF(1)
2kΩ
G=5
–
+
OPA637
VOUT
500Ω
NOTE: (1) Optimum value will depend on circuit
board layout and capacitance at inverting input.
Figure 42. OPA637 Dynamic Response, G = 5
8.2 Typical Application
Low pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA627 and OPA637 are ideally suited to construct high speed, high precision active filters. Figure 43
illustrates a second order low pass filter commonly encountered in signal processing applications.
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
C2
39 nF
±
Output
+
OPA627
Figure 43. Second Order Low Pass Filter
8.2.1 Design Requirements
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low pass cutoff frequency = 25 kHz
• Second order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 43. Use Equation 1
to calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(1)
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Typical Application (continued)
This circuit produces a signal inversion. For this circuit the gain at DC and the low pass cutoff frequency can be
calculated using Equation 2.
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multi-stage active filter solutions within minutes.
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 44. OPA627 2nd Order 25 kHz, Chebyshev, Low Pass Filter
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9 Power Supply Recommendations
The OPA627 and OPA637 are specified for operation from 9 V to 36 V (±4.5 V to ±18 V); many specifications
apply from –25°C to 85°C (P and D packages) and –55°C to 125°C (LMC package). Parameters that can exhibit
significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
– The OPA6x7 is capable of high-output current (in excess of 45 mA). Applications with low impedance
loads or capacitive loads with fast transient signals demand large currents from the power supplies.
Larger bypass capacitors such as 1-µF solid tantalum capacitors may improve dynamic performance
in these applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information refer to Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 45, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• The case (TO-99 metal package only) is internally connected to the negative power supply, as with most
common operational amplifiers.
• Pin 8 of the plastic PDIP, SOIC, and TO-99 packages has no internal connection.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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Product Folder Links: OPA627 OPA637
OPA627, OPA637
www.ti.com
SBOS165A – SEPTEMBER 2000 – REVISED OCTOBER 2015
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
Offset trim
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
Offset trim
RG
Use low-ESR,
ceramic bypass
capacitor
GND
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
VS±
Ground (GND) plane on another layer
Figure 45. OPA627 Layout Example for the Noninverting Configuration
Non-inverting
2
Buffer
2
–
6
In
3
+
Out
In
OPA627
3
–
6
Out
+
OPA627
TO-99 Bottom View
Inverting
In
OPA627
2
3
–
6
4
3
5
Out
+
2
Board Layout for Input Guarding:
Guard top and bottom of board.
Alternate—use Teflon ® standoff for sensitive input pins.
6
7
1
Teflon ® E.I. du Pont de Nemours & Co.
8 No Internal Connection
To Guard Drive
B.
Figure 46. Board Layout for Input Guarding (LMC Package)
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Product Folder Links: OPA627 OPA637
25
OPA627, OPA637
SBOS165A – SEPTEMBER 2000 – REVISED OCTOBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners. Available as a web based tool from the WEBENCH® Design Center,
WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multi-stage active filter
solutions within minutes.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
The OPA627 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Circuit Board Layout Techniques, SLOA089.
• Op Amps for Everyone, SLOD006.
• Compensate Transimpedance Amplifiers Intuitively, SBOS055.
• Noise Analysis for High Speed op Amps, SBOA066.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA627
Click here
Click here
Click here
Click here
Click here
OPA637
Click here
Click here
Click here
Click here
Click here
11.4 Trademarks
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Difet is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
26
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Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: OPA627 OPA637
OPA627, OPA637
www.ti.com
SBOS165A – SEPTEMBER 2000 – REVISED OCTOBER 2015
11.4 Trademarks (continued)
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: OPA627 OPA637
27
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA627AM
NRND
TO-99
LMC
8
20
Green (RoHS
& no Sb/Br)
AU
N / A for Pkg Type
OPA627AM
OPA627AP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA627AP
OPA627APG4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA627AP
OPA627AU
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
627AU
OPA627AU/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
627AU
OPA627AU/2K5E4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
627AU
OPA627AUE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
627AU
OPA627AUG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
627AU
OPA627BM
NRND
TO-99
LMC
8
1
Green (RoHS
& no Sb/Br)
AU
N / A for Pkg Type
OPA627BM
OPA627BP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA627BP
OPA627SM
NRND
TO-99
LMC
8
20
Green (RoHS
& no Sb/Br)
AU
N / A for Pkg Type
OPA627SM
OPA637AM
NRND
TO-99
LMC
8
20
Green (RoHS
& no Sb/Br)
AU
N / A for Pkg Type
OPA637AM
OPA637AP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA637AP
OPA637AU
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
637AU
OPA637AU/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
637AU
OPA637AUG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
OPA
637AU
OPA637BM
NRND
TO-99
LMC
8
20
Green (RoHS
& no Sb/Br)
AU
N / A for Pkg Type
Addendum-Page 1
OPA637BM
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA637BP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA637BP
OPA637BPG4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA637BP
OPA637SM
NRND
TO-99
LMC
8
20
Green (RoHS
& no Sb/Br)
AU
N / A for Pkg Type
OPA637SM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA627AU/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA637AU/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA627AU/2K5
SOIC
D
8
2500
367.0
367.0
35.0
OPA637AU/2K5
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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