Texas Instruments | INA217 Low-Noise, Low-Distortion Instrumentation Amplifier Replacement for SSM2017 (Rev. C) | Datasheet | Texas Instruments INA217 Low-Noise, Low-Distortion Instrumentation Amplifier Replacement for SSM2017 (Rev. C) Datasheet

Texas Instruments INA217 Low-Noise, Low-Distortion Instrumentation Amplifier Replacement for SSM2017 (Rev. C) Datasheet
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INA217
SBOS247C – JUNE 2002 – REVISED NOVEMBER 2015
INA217 Low-Noise, Low-Distortion Instrumentation Amplifier Replacement for SSM2017
1 Features
•
•
•
•
•
•
•
1
Low Noise: 1.3 nV/M √Hz at 1 kHz
Low THD+N: 0.004% at 1 kHz, G = 100
Wide Bandwidth: 800 kHz at G = 100
Wide Supply Range: ±4.5 V to ±18 V
High CMR: > 100 dB
Gain Set With External Resistor
DIP-8 and SOL-16 Widebody Packages
2 Applications
•
•
•
•
Professional Microphone Preamps
Moving-coil Transducer Amplifiers
Differential Receivers
Bridge Transducer Amplifiers
3 Description
The INA217 device is a low-noise, low-distortion,
monolithic
instrumentation
amplifier.
Currentfeedback circuitry allows the INA217 device to
achieve wide bandwidth and excellent dynamic
response over a wide range of gain. The INA217
device is ideal for low-level audio signals such as
balanced
low-impedance
microphones.
Many
industrial, instrumentation, and medical applications
also benefit from its low noise and wide bandwidth.
Unique distortion cancellation circuitry reduces
distortion to extremely low levels, even in high gain.
The INA217 device provides near-theoretical noise
performance for 200-Ω source impedance. The
INA217 device features differential input, low noise,
and low distortion that provides superior performance
in professional microphone amplifier applications.
The INA217device features wide supply voltage,
excellent output voltage swing, and high output
current drive, making it an optimal candidate for use
in high-level audio stages.
The INA217 device is available in the same DIP-8
and SOL-16 wide body packages and pinouts as the
SSM2017. For a smaller package, see the INA163
device in SO-14 narrow. The INA217 device is
specified over the temperature range of –40°C to
85°C.
Device Information(1)
PART NUMBER
INA217
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA217
SBOS247C – JUNE 2002 – REVISED NOVEMBER 2015
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Simplified Schematic
V+
7
INA217
VIN–
2
6kΩ
6kΩ
A1
1
RG1
5kΩ
6
A3
5kΩ
VOUT
G=1+
8
6kΩ
RG2
10kΩ
RG
6kΩ
A2
VIN+
3
4
V–
2
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5
REF
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SBOS247C – JUNE 2002 – REVISED NOVEMBER 2015
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
3
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = ±15 V.......................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2005) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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INA217
SBOS247C – JUNE 2002 – REVISED NOVEMBER 2015
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5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
P Package
8-Pin PDIP
Top View
NC
1
16 NC
RG1
2
15 RG2
NC
3
14 NC
VIN–
4
13 V+
VIN+
5
12 NC
NC
6
11 VOUT
V–
7
10 REF
NC
8
9
RG1
1
8
RG2
VIN–
2
7
V+
VIN+
3
6
VOUT
V–
4
5
REF
DIP-8
NC
SOL-16
NC = No Internal Connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
PDIP
NC
1
—
No internal connection
RG1
2
I
NC
3
—
VIN–
4
I
Inverting input
VIN+
5
I
Non-inverting input
NC
6
—
No internal connection
V–
7
I
negative power supply
NC
8
—
No internal connection
NC
9
—
No internal connection
REF
10
I
Reference input
VOUT
11
O
Output
NC
12
—
No internal connection
V+
13
I
Positive power supply
NC
14
—
No internal connection
RG2
15
I
NC
16
—
RG1
1
I
Gain setting pin, for gains greater than one, connect an external resistor between pins 1 and 8
VIN–
2
I
Inverting input
VIN+
3
I
Non-inverting input
V–
4
I
negative power supply
REF
5
I
Reference input
VOUT
6
O
Output
V+
7
I
Positive power supply
RG2
8
I
Gain setting pin, for gains greater than one, connect an external resistor between pins 2 and 15
Gain setting pin, for gains greater than one, connect an external resistor between pins 2 and 15
No internal connection
Gain setting pin, for gains greater than one, connect an external resistor between pins 2 and 15
No internal connection
SOIC
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
V+ to V–
MAX
UNIT
±18
V
Supply voltage
Voltage
Signal input terminals
(2)
(V–) – 0.5
(V+) + 0.5
V
10
mA
Current (2)
Output short circuit (3)
Continuous
Operating temperature
–55
Junction temperature
Tstg
(1)
(2)
(3)
Storage temperature
–55
125
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V+ to V–
Supply voltage
TA
Ambient Temperature
MIN
NOM
MAX
±4.5
±15
±18
UNIT
V
-40
25
85
°C
6.4 Thermal Information
INA217
THERMAL METRIC (1)
DW (SOIC)
P (PDIP)
UNIT
16 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
64.3
46.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.9
34.5
°C/W
RθJB
Junction-to-board thermal resistance
29.4
23.5
°C/W
ψJT
Junction-to-top characterization parameter
3.3
11.7
°C/W
ψJB
Junction-to-board characterization parameter
28.8
23.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: VS = ±15 V
TA = 25°C, RL = 2 kΩ, VS = ±15 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
GAIN EQUATION (1)
TYP
MAX
G = 1 + 10k/RG
Range
1 to 10000
Gain Error
UNIT
V/V
G=1
±0.1%
±0.25%
G = 10
±0.2%
±0.7%
G = 100
±0.2%
G = 1000
±0.5%
GAIN TEMPERATURE DRIFT COEFFICIENT
Nonlinearity
G=1
TA = –40°C to 85°C
±3
±10
ppm/°C
G > 10
TA = –40°C to 85°C
±40
±100
ppm/°C
G=1
±0.0003
% of FS
G = 100
±0.0006
% of FS
1.3
nV/√Hz
fO = 100 Hz
1.5
nV/√Hz
fO = 10 Hz
3.5
nV/√Hz
fO = 1 kHz
0.8
pA/√Hz
90
nV/√Hz
INPUT STAGE NOISE
fO = 1 kHz
Voltage Noise
Current Noise,
RSOURCE = 0 Ω
OUTPUT STAGE NOISE
Voltage Noise,
fO = 1 kHz
INPUT OFFSET VOLTAGE
Input Offset Voltage
VCM = VOUT = 0 V
50 + 2000/G
vs Temperature
TA = –40°C to 85°C
1 + 20/G
vs Power Supply
VS = ±4.5 V to ±18 V
1 + 50/G
250 + 5000/G
µV
µV/°C
3 + 200/G
µV/V
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
CommonMode
Rejection
G=1
VIN+ – VIN– = 0V
(V+) – 4
(V+) – 3
VIN+ – VIN– = 0V
(V–) + 4
(V–) + 3
V
70
80
dB
100
116
dB
VCM = ±11 V, RSRC = 0 Ω
G = 100
V
INPUT BIAS CURRENT
Initial Bias Current
vs Temperature
2
TA = –40°C to 85°C
Initial Offset Current
vs Temperature
10
0.1
TA = –40°C to 85°C
12
0.5
µA
nA/°C
1
µA
nA/°C
INPUT IMPEDANCE
Differential
60 || 2
MΩ || pF
Common-Mode
60 || 2
MΩ || pF
DYNAMIC RESPONSE
Bandwidth, Small Signal, –3d B
G=1
3.4
MHz
G = 100
800
kHz
15
V/µs
Slew Rate
THD+Noise, f = 1 kHz
Settling Time
6
0.004%
0.1%
G = 100, 10V Step
2
µs
0.01%
G = 100, 10V Step
3.5
µs
1
µs
Overload Recovery
(1)
G = 100
50% Overdrive
Gain accuracy is a function of external RG.
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Electrical Characteristics: VS = ±15 V (continued)
TA = 25°C, RL = 2 kΩ, VS = ±15 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP
(V+) – 2
(V–) + 2
(V+) – 1.8
(V–) + 1.8
MAX
UNIT
OUTPUT
Voltage
RL to GND
Load Capacitance Stability
Short Circuit Current
Continuous-to-Common
V
V
1000
pF
±60
mA
POWER SUPPLY
Rated Voltage
±15
Voltage Range
Current, Quiescent
±4.5
IO = 0 mA
±10
V
±18
V
±12
mA
TEMPERATURE RANGE
Specification
–40
85
°C
Operating
–40
125
°C
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6.6 Typical Characteristics
At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.
0.1
70
G = 1000
60
G = 1000
50
G = 100
30
20
0.01
THD+N (%)
Gain (dB)
40
G = 10
G = 100
0.001
10
0
G = 10
G=1
0.0001
–20
10k
100k
1M
20
10M
100
1k
Figure 2. THD+N vs Frequency
Figure 1. Gain vs Frequency
10.0
Current Noise Density (pA/ Hz)
Noise (RTI) (nV/√Hz)
1k
G=1
100
G = 10
10
G = 1000
G = 500
G = 100
1
0.1
1
10
100
1k
10k
1
10
Frequency (Hz)
100
1k
10k
Frequency (Hz)
Figure 3. Noise Voltage (RTI) vs Frequency
Figure 4. Current Noise Spectral Density
140
140
G = 1000
100
G = 100
80
G = 10
60
G=1
Power-Supply Rejection (dB)
120
Input Referred CMR (dB)
10k 20k
Frequency (Hz)
Frequency (Hz)
40
20
120
G = 100, 1000
G = 10
100
G=1
80
60
40
20
0
0
10
100
1k
10k
100k
1M
1
Figure 5. CMR vs Frequency
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
8
VO = 7Vrms
RL = 10kΩ
G=1
–10
Figure 6. Power-Supply Rejection vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.
V+
10
20V Step
8
(V+) – 4
Settling Time (µs)
Output Voltage to Rail (V)
(V+) – 2
(V+) – 6
(V–) + 6
(V–) + 4
0.01%
6
4
2
(V–) + 2
0.1%
0
V–
0
10
20
30
40
50
1
60
10
100
1000
Gain
Output Current (mA)
Figure 8. Settling Time vs Gain
20mV/div
20mV/div
Figure 7. Output Voltage Swing vs Output Current
10µs/div
2.5µs/div
G=1
G = 100
Figure 10. Small-Signal Transient Response
5V/div
5V/div
Figure 9. Small-Signal Transient Response
2.5µs/div
2.5µs/div
G=1
G = 100
Figure 11. Large-Signal Transient Response
Figure 12. Large-Signal Transient Response
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7 Detailed Description
7.1 Overview
The INA217 is a classical three-amp instrumentation amplifier designed for audio applications. Featuring low
noise and low distortion the INA217 is ideally suited for amplifying low level audio signals. With a wide supply
voltage, wide output voltage swing, and high output current drive the INA217 is also ideally suited for processing
high level audio signals. Specified from –40°C to 85°C the INA217 is well suited for industrial applications.
7.2 Functional Block Diagram
V+
7
INA217
VIN–
2
6kΩ
6kΩ
A1
1
RG1
5kΩ
6
A3
5kΩ
VOUT
G=1+
8
6kΩ
RG2
10kΩ
RG
6kΩ
A2
VIN+
3
4
V–
5
REF
7.3 Feature Description
7.3.1 Basic Connections
Figure 13 shows the basic connections required for operation. Power supplies should be bypassed with 0.1-μF
tantalum capacitors near the device pins. The output Reference (pin 5) should be a low-impedance connection.
Resistance of a few Ωs in series with this connection will degrade the common-mode rejection of the INA217.
10
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Feature Description (continued)
V+
0.1µF
7
INA217
2
VIN–
1
6kΩ
6kΩ
A1
5kΩ
RG
A3
5kΩ
VOUT
6
G=1+
8
VIN+
6kΩ
6kΩ
A2
10000
RG
REF
5
3
4 0.1µF
V+
Sometimes Shown in
Simplified Form:
VIN–
RG
INA217
V–
GAIN
(V/V)
(dB)
1
0
2
6
5
14
10
20
20
26
50
34
100
40
200
46
500
54
1000
60
2000
66
RG
(Ω)
NC(1)
10000
2500
1111
526
204
101
50
20
10
5
NOTE: (1) NC = No Connection.
VO
VIN+
V–
Figure 13. Basic Circuit Connections
7.3.2 Gain-Set Resistor
Gain is set with an external resistor, RG, as shown in Figure 13. The two internal 5-kΩ feedback resistors are
laser-trimmed to 5-kΩ within approximately ±0.2%. Equation 1 shows the gain equation for the INA217.
10 000
G = 1+
RG
(1)
The temperature coefficient of the internal 5-kΩ resistors is approximately ±25 ppm/°C. Accuracy and TCR of the
external RG will also contribute to gain error and temperature drift. These effects can be inferred from the gain
equation. Make a short, direct connection to the gain set resistor, RG. Avoid running output signals near these
sensitive input nodes.
7.3.3 Noise Performance
The INA217 provides very low noise with low-source impedance. Its 1.3-nV/M √Hz voltage noise delivers neartheoretical noise performance with a source impedance of 200 Ω. The input stage design used to achieve this
low noise results in relatively high input bias current and input bias current noise. As a result, the INA217 may
not provide the best noise performance with a source impedance greater than 10 kΩ. For source impedance
greater than 10 kΩ, other instrumentation amplifiers may provide improved noise performance.
7.3.4 Input Considerations
Very low source impedance (less than 10 Ω) can cause the INA217 to oscillate. This depends on circuit layout,
signal source, and input cable characteristics. An input network consisting of a small inductor and resistor, as
shown in Figure 14, can greatly reduce any tendency to oscillate. This is especially useful if a variety of input
sources are to be connected to the INA217. Although not shown in other figures, this network can be used as
needed with all applications shown.
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Feature Description (continued)
V+
47Ω
2
VIN–
1.2µH
1
1.2µH
8
7
6
INA217
VIN+
VO
5
4
3
47Ω
V–
Figure 14. Input Stabilization Network
7.3.5 Offset Voltage Trim
A variable voltage applied to pin 5, as shown in Figure 15, can be used to adjust the output offset voltage. A
voltage applied to pin 5 is summed with the output signal. An operational amplifier connected as a buffer is used
to provide a low impedance at pin 5 to assure good common-mode rejection.
V+
2
7
1
6
INA217
RG
8
3
VO
V+
5
4
100µA
V–
150Ω
OPA237
10kΩ
150Ω
100µA
V–
Figure 15. Offset Voltage Adjustment Circuit
7.4 Device Functional Modes
The INA217 has a single functional mode of operation. The mode is operational when the power supply voltage
exceeds ±4.5 V. The maximum power supply voltage is ±18 V. The INA217 is specified over the temperature
range from –40°C to 85°C and is operational to 125°C.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA217 is used in professional audio equipment such as professional microphone preamps, moving-coil
transducer amplifiers, differential receivers, and bridge transducer amplifiers.
8.2 Typical Application
Figure 16 shows a typical circuit for a professional microphone input amplifier.
Phantom Power
+48V
R3
47kΩ
R1
6.8kΩ
47µF
R2
6.8kΩ
+15V
+15V
C1(1)
47µF
+
1
Female XLR
Connector
+
3
IN4148(4)
7
+15V
60V
2
0.1µF
R6(2)
8Ω
A1
INA217
C2(1)
47µF
+
IN4148(4)
4
R7(3)
1.6kΩ
60V
–15V
VO
5
–15V
R4
2.2kΩ
6
R5
2.2kΩ
1MΩ
0.1µF
0.1µF
Optional DC
output control loop.
A2
OPA137
–15V
NOTES: (1) Use non-polar capacitors if phantom power is to be
turned off. (2) R6 sets maximum gain. (3) R7 sets minimum gain.
(4) Optional IN4148 prevents damage due to ESD and hot-plugging.
Figure 16. Phantom-Powered Microphone Preamplifier
8.2.1 Design Requirements
•
•
•
•
48-V, Phantom powered, remotely located microphone
Circuitry operates from ±15-V power supplies
Low distortion and noise over the audio frequency band
Gain range from to 20 db to 60 db
8.2.2 Detailed Design Procedure
R1 and R2 provide a current path for conventional 48-V phantom power source for a remotely located
microphone. An optional switch allows phantom power to be disabled. C1 and C2 block the phantom power
voltage from the INA217 input circuitry. Non-polarized capacitors should be used for C1 and C2 if phantom power
is to be disabled. For additional input protection against ESD and hot-plugging, four IN4148 diodes may be
connected from the input to supply lines.
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Typical Application (continued)
R4 and R5 provide a path for input bias current of the INA217. Input offset current (typically 100 nA) creates a DC
differential input voltage that will produce an output offset voltage. This is generally the dominant source of output
offset voltage in this application. With a maximum gain of 1000 (60 dB), the output offset voltage can be several
volts. This may be entirely acceptable if the output is AC-coupled into the subsequent stage. An alternate
technique is shown in Figure 16. An inexpensive FET-input operational amplifier in a feedback loop drives the
DC output voltage to 0 V. A2 is not in the audio signal path and does not affect signal quality.
Gain is set with a variable resistor, R7, in series with R6. R6 determines the maximum gain. The total resistance,
R6 + R7, determines the lowest gain. A special reverse-log taper potentiometer for R7 can be used to create a
linear change (in dB) with rotation.
8.2.3 Application Curve
0.05
0.03
0.02
Gain = 20 dB
Gain = 40 dB
Gain = 60 dB
THD + N (%)
0.01
0.007
0.005
0.003
0.002
0.001
0.0007
0.0005
0
5000
10000
15000
Frequency (Hz)
20000
D001
Figure 17. THD + Noise for the Phantom Powered Microphone Circuit
9 Power Supply Recommendations
The INA217 is specified for operation from ±4.5 V to ±18 V; many specifications apply from –40°C to 85°C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
the Typical Characteristics.
14
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: INA217
INA217
www.ti.com
SBOS247C – JUNE 2002 – REVISED NOVEMBER 2015
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information, see Circuit Board Layout Techniques, SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• TI recommends cleaning the PCB following board assembly for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
RG
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible
Place component close
to device to reduce
parasitic errors
RG1
RG2
INVERTING
INPUT
VIN-
V+
NON-INVERTING
INPUT
VIN+
VOUT
VS±
V±
REF
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible
V+
OUT
Ground
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible
Figure 18. INA217 Layout Example
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: INA217
15
INA217
SBOS247C – JUNE 2002 – REVISED NOVEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Circuit Board Layout Techniques, SLOA089.
• Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
16
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: INA217
INA217
www.ti.com
SBOS247C – JUNE 2002 – REVISED NOVEMBER 2015
11.4 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: INA217
17
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA217AIDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
INA217
INA217AIDWT
ACTIVE
SOIC
DW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
INA217
INA217AIP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
INA217
INA217AIPG4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
INA217
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
INA217AIDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
INA217AIDWT
SOIC
DW
16
250
180.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA217AIDWR
SOIC
DW
16
2000
367.0
367.0
38.0
INA217AIDWT
SOIC
DW
16
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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