Texas Instruments | LM7121 235-MHz Tiny Low Power Voltage Feedback Amplifier (Rev. A) | Datasheet | Texas Instruments LM7121 235-MHz Tiny Low Power Voltage Feedback Amplifier (Rev. A) Datasheet

Texas Instruments LM7121 235-MHz Tiny Low Power Voltage Feedback Amplifier (Rev. A) Datasheet
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LM7121
SNOS750A – AUGUST 1999 – REVISED OCTOBER 2014
LM7121 235-MHz Tiny Low Power Voltage Feedback Amplifier
1 Features
3 Description
•
•
•
•
The LM7121 is a high performance operational
amplifier which addresses the increasing AC
performance needs of video and imaging
applications, and the size and power constraints of
portable applications.
1
•
•
•
•
•
•
(Typical Unless Otherwise Noted). VS = ±15 V
Easy to use Voltage Feedback Topology
Stable with Unlimited Capacitive Loads
Tiny SOT23-5 Package — Typical Circuit Layout
Takes Half the Space Of SO-8 Designs
Unity Gain Frequency: 175 MHz
Bandwidth (−3 dB, AV = +1, RL = 100Ω): 235 MHz
Slew Rate: 1300V/μs
Supply Voltages:
– SO-8: 5 V to ±15 V
– SOT23-5: 5 V to ±5 V
Characterized for: +5 V, ±5 V, ±15 V
Low Supply Current: 5.3 mA
2 Applications
•
•
•
•
•
•
Scanners, Color Fax, Digital Copiers
PC Video Cards
Cable Drivers
Digital Cameras
ADC/DAC Buffers
Set-top Boxes
The LM7121 can operate over a wide dynamic range
of supply voltages, from 5 V (single supply) up to
±15V (see Application and Implementation for more
details). It offers an excellent speed-power product
delivering 1300 V/μs and 235 MHz Bandwidth (−3 dB,
AV = +1). Another key feature of this operational
amplifier is stability while driving unlimited capacitive
loads.
Due to its tiny SOT23-5 package, the LM7121 is ideal
for designs where space and weight are the critical
parameters. The benefits of the tiny package are
evident in small portable electronic devices, such as
cameras, and PC video cards. Tiny amplifiers are so
small that they can be placed anywhere on a board
close to the signal source or near the input to an A/D
converter.
Device Information(1)
PART NUMBER
LM7121
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.921 mm × 1.651 mm
SOIC (8)
4.902 mm × 3.912 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Circuit for AV = +1 Operation
(VS= 6 V)
Unity Gain Frequency vs. Supply Voltage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM7121
SNOS750A – AUGUST 1999 – REVISED OCTOBER 2014
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
±15V DC Electrical Characteristics ...........................
±15V AC Electrical Characteristics ...........................
±5V DC Electrical Characteristics .............................
6.8
6.9
6.10
6.11
7
±5V AC Electrical Characteristics .............................
+5V DC Electrical Characteristics .............................
+5V AC Electrical Characteristics ...........................
Typical Characteristics ............................................
7
8
8
9
Application and Implementation ........................ 21
7.1 Application Information............................................ 21
7.2 Typical Applications ................................................ 22
8
Device and Documentation Support.................. 26
8.1 Trademarks ............................................................. 26
8.2 Electrostatic Discharge Caution .............................. 26
8.3 Glossary .................................................................. 26
9
Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 1999) to Revision A
Page
•
Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions,
Application and Implementation; Power Supply Recommendations ; Layout; Device and Documentation Support;
Mechanical, Packaging, and Ordering Information................................................................................................................. 1
•
Deleted TJ = 25°C from Electrical Characteristics tables ....................................................................................................... 5
2
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5 Pin Configuration and Functions
Package DBV
5-Pin
Top View
Package D0008A
8-Pin
Top View
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
DBV
D0008A
-IN
4
2
I
Inverting input
+IN
3
3
I
Non-inverting input
N/C
––
5, 8
––
No connection
OUTPUT
1
6
O
Output
V-
2
4
I
Negative supply
V+
5
7
I
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Differential Input Voltage
MAX
UNIT
±2
V
(V+)−1.4,
(V−)+1.4
V
36
V
(2)
Voltage at Input/Output Pins
Supply Voltage (V+–V−)
Output Short Circuit to Ground
(3)
Continuous
Lead Temperature (soldering, 10 sec)
260
°C
Junction Temperature (4)
150
˚C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max)–TA)/RθJA. All numbers apply for packages soldered directly into a PC board.
Typical Values represent the most likely parametric norm.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
MIN
MAX
UNIT
−65
+150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
2000
V
JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Human body
model, 1.5 k in series with 100 pF.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Operating Temperature Range
NOM
MAX
-40
85
UNIT
°C
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
D0008A (8)
DBV (5)
UNIT
165
325
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 ±15V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = +15V, V− = −15V, VCM = VO = 0 V and RL > 1 MΩ. Boldface limits apply
at the temperature extremes.
PARAMETER
TEST CONDITIONS
TYP (1)
LM7121I
LIMIT (2)
UNIT
VOS
Input Offset Voltage
0.9
8
15
mV
max
IB
Input Bias Current
5.2
9.5
12
µA
max
IOS
Input Offset Current
0.04
4.3
7
µA
max
RIN
Input Resistance
CIN
Input Capacitance
Common Mode
10
MΩ
Differential Mode
3.4
MΩ
Common Mode
2.3
pF
CMRR
Common Mode Rejection Ratio
−10V ≤ VCM ≤ 10V
93
73
70
+PSRR
Positive Power Supply Rejection Ratio
10V ≤ V+ ≤ 15 V
86
70
68
dB
min
−PSRR
Negative Power Supply Rejection Ratio
−15V ≤ V− ≤ −10V
81
68
65
dB
min
VCM
Input Common-Mode Voltage Range
CMRR ≥ 70 dB
AV
Large Signal Voltage Gain
RL = 2 kΩ , VO = 20 VPP
13
11
V min
−13
−11
V max
72
65
57
dB
min
13.4
11.1
10.8
V
min
−13.4
−11.2
−11.0
V
max
10.2
7.75
7.0
V
min
−7.0
−5.0
−4.8
V
max
Sourcing
71
54
44
mA
min
Sinking
52
39
34
mA
min
5.3
6.6
7.5
mA
max
RL = 2 kΩ
VO
Output Swing
RL = 150 Ω
ISC
IS
(1)
(2)
dB
min
Output Short Circuit Current
Supply Current
Typical Values represent the most likely parametric norm.
All limits are ensured by testing or statistical analysis.
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6.6 ±15V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 15V, V− = −15V, VCM = VO = 0 V and RL > 1 MΩ. Boldface limits apply
at the temperature extremes.
PARAMETER
TEST CONDITIONS
TYP (1)
LM7121I
LIMIT (2)
UNIT
SR
Slew Rate (3)
AV = +2, RL = 1 kΩ, VO = 20 VPP
1300
V/µs
GBW
Unity Gain-Bandwidth
RL = 1 kΩ
175
MHz
Øm
Phase Margin
63
Deg
RL = 100 Ω, AV = +1
235
RL = 100 Ω, AV = +2
50
f (−3 dB)
Bandwidth (4) (5)
ts
Settling Time
10 VPP Step, to 0.1%, RL = 500 Ω
74
ns
tr, tf
Rise and Fall Time (5)
AV = +2, RL = 100 Ω, VO = 0.4 VPP
5.3
ns
AD
Differential Gain
AV = +2, RL = 150 Ω
0.3%
ØD
Differential Phase
AV = +2, RL = 150 Ω
0.65
en
Input-Referred Voltage Noise
f = 10 kHz
in
Input-Referred Current Noise
f = 10 kHz
T.H.D.
(1)
(2)
(3)
(4)
(5)
Total Harmonic Distortion
MHz
Deg
17
nV / √HZ
1.9
pA / √HZ
2 VPP Output, RL = 150 Ω,
AV = +2, f = 1 MHz
0.065%
2 VPP Output, RL = 150 Ω,
AV = +2, f = 5 MHz
0.52%
Typical Values represent the most likely parametric norm.
All limits are ensured by testing or statistical analysis.
Slew rate is the average of the rising and falling slew rates.
Unity gain operation for ±5 V and ±15 V supplies is with a feedback network of 510 Ω and 3 pF in parallel (see Application and
Implementation). For +5V single supply operation, feedback is a direct short from the output to the inverting input.
AV = +2 operation with 2 kΩ resistors and 2 pF capacitor from summing node to ground.
6.7 ±5V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 5V, V− = −5V, VCM = VO = 0 V and RL > 1 MΩ. Boldface limits apply at
the temperature extremes.
PARAMETER
TEST CONDITIONS
TYP (1)
LM7121I
LIMIT (2)
UNIT
VOS
Input Offset Voltage
1.6
8
15
mV
max
IB
Input Bias Current
5.5
9.5
12
µA
max
IOS
Input Offset Current
0.07
4.3
7.0
µA
max
RIN
Input Resistance
CIN
Common Mode
6.8
MΩ
Differential Mode
3.4
MΩ
Input Capacitance
Common Mode
2.3
pF
CMRR
Common Mode Rejection Ratio
−2V ≤ VCM ≤ 2V
75
65
60
dB
min
+PSRR
Positive Power Supply Rejection Ratio
3V ≤ V+ ≤ 5V
89
65
60
dB
min
−PSRR
Negative Power Supply Rejection Ratio
−5V ≤ V− ≤ −3V
78
65
60
dB
min
(1)
(2)
6
Typical Values represent the most likely parametric norm.
All limits are ensured by testing or statistical analysis.
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±5V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = 5V, V− = −5V, VCM = VO = 0 V and RL > 1 MΩ. Boldface limits apply at
the temperature extremes.
TYP (1)
LM7121I
LIMIT (2)
3
2.5
V
min
−3
−2.5
V
max
66
60
58
dB
min
3.62
3.0
2.75
V
min
−3.62
−3.0
−2.70
V
max
3.1
2.5
2.3
V
min
−2.8
−2.15
−2.00
V
max
Sourcing
53
38
33
mA
min
Sinking
29
21
19
mA
min
5.1
6.4
7.2
mA
max
PARAMETER
VCM
TEST CONDITIONS
CMRR ≥ 60 dB
Input Common Mode Voltage Range
AV
Large Signal Voltage Gain
RL = 2 kΩ, VO = 3 VPP
RL = 2 kΩ
VO
Output Swing
RL = 150 Ω
ISC
Output Short Circuit Current
IS
UNIT
Supply Current
6.8 ±5V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 5V, V− = −5V, VCM = VO = 0 V and RL > 1 MΩ. Boldface limits apply at
the temperature extremes.
PARAMETER
TEST CONDITIONS
TYP (1)
LM7121I
LIMIT (2)
UNIT
SR
Slew Rate (3)
AV = +2, RL = 1 kΩ, VO = 6 VPP
520
V/µs
GBW
Unity Gain-Bandwidth
RL = 1 kΩ
105
MHz
Øm
Phase Margin
RL = 1 kΩ
74
Deg
f (−3 dB)
Bandwidth (4) (5)
RL = 100 Ω, AV = +1
160
MHz
RL = 100 Ω, AV = +2
50
MHz
ts
Settling Time
5 VPP Step, to 0.1%, RL = 500 Ω
65
ns
tr, tf
Rise and Fall Time (5)
AV = +2, RL = 100 Ω, VO = 0.4 VPP
5.8
ns
AD
Differential Gain
AV = +2, RL = 150 Ω
0.3%
ØD
Differential Phase
AV = +2, RL = 150 Ω
0.65
en
Input-Referred Voltage Noise
f = 10 kHz
17
nV / √Hz
in
Input-Referred Current Noise
f = 10 kHz
2
pA / √Hz
T.H.D.
(1)
(2)
(3)
(4)
(5)
Total Harmonic Distortion
2 VPP Output, RL = 150 Ω,
AV = +2, f = 1 MHz
0.1%
2 VPP Output, RL = 150 Ω,
AV = +2, f = 5 MHz
0.6
Deg
Typical Values represent the most likely parametric norm.
All limits are ensured by testing or statistical analysis.
Slew rate is the average of the rising and falling slew rates.
Unity gain operation for ±5 V and ±15 V supplies is with a feedback network of 510 Ω and 3 pF in parallel (see Application and
Implementation). For +5V single supply operation, feedback is a direct short from the output to the inverting input.
AV = +2 operation with 2 kΩ resistors and 2 pF capacitor from summing node to ground.
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6.9 +5V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = +5V, V− = 0 V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply
at the temperature extremes.
PARAMETER
VOS
Input Offset Voltage
IB
Input Bias Current
IOS
Input Offset Current
RIN
Input Resistance
TYP (1)
TEST CONDITIONS
LM7121I
LIMIT (2)
UNIT
2.4
mV
4
µA
0.04
µA
Common Mode
2.6
M
Differential Mode
3.4
M
CIN
Input Capacitance
Common Mode
2.3
pF
CMRR
Common Mode Rejection Ratio
2V ≤ VCM ≤ 3V
65
dB
dB
+
+PSRR
Positive Power Supply Rejection Ratio
4.6V ≤ V ≤ 5V
85
−PSRR
Negative Power Supply Rejection Ratio
0V ≤ V− ≤ 0.4V
61
dB
3.5
V min
VCM
Input Common-Mode Voltage Range
CMRR 45 dB
1.5
V max
AV
Large Signal Voltage Gain
RL = 2 kΩ to V+/2
64
dB
RL = 2 kΩ to V+/2, High
3.7
RL = 2 kΩ to V+/2, Low
1.3
VO
Output Swing
ISC
Output Short Circuit Current
IS
Supply Current
+
RL = 150 Ω to V /2, High
3.48
RL = 150 Ω to V+/2, Low
1.59
Sourcing
Sinking
(1)
(2)
V
33
mA
20
mA
4.8
mA
Typical Values represent the most likely parametric norm.
All limits are ensured by testing or statistical analysis.
6.10 +5V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = +5V, V− = 0 V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply
at the temperature extremes.
PARAMETER
Slew Rate (3)
AV = +2, RL = 1 kΩ to V /2,
VO = 1.8 VPP
GBW
Unity Gain-Bandwidth
Øm
Phase Margin
Bandwidth (4) (5)
tr, tf
Rise and Fall Time (5)
T.H.D.
(1)
(2)
(3)
(4)
(5)
8
Total Harmonic Distortion
LM7121I
LIMIT (2)
UNIT
+
SR
f (−3 dB)
TYP (1)
TEST CONDITIONS
145
V/µs
RL = 1k to V+/2
80
MHz
RL = 1k to V+/2
70
Deg
RL = 100 Ω to V+/2, AV = +1
200
RL = 100 Ω to V+/2, AV = +2
45
AV = +2, RL = 100 Ω , VO = 0.2 VPP
8
0.6 VPP Output, RL = 150 Ω,
AV = +2, f = 1 MHz
0.067%
0.6 VPP Output, RL = 150 Ω,
AV = +2, f = 5 MHz
0.33%
MHz
ns
Typical Values represent the most likely parametric norm.
All limits are ensured by testing or statistical analysis.
Slew rate is the average of the rising and falling slew rates.
Unity gain operation for ±5 V and ±15 V supplies is with a feedback network of 510 Ω and 3 pF in parallel (see Application and
Implementation). For +5V single supply operation, feedback is a direct short from the output to the inverting input.
AV = +2 operation with 2 kΩ resistors and 2 pF capacitor from summing node to ground.
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6.11 Typical Characteristics
Figure 1. Supply Current vs. Supply Voltage
Figure 2. Supply Current vs. Temperature
Figure 3. Input Offset Voltage vs. Temperature
Figure 4. Input Bias Current vs Temperature
Figure 5. Input Offset Voltage vs. Common Mode Voltage
at VS = ±15 V
Figure 6. Input Offset Voltage vs. Common Mode Voltage
at VS = ±5 V
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Typical Characteristics (continued)
10
Figure 7. Short Circuit Current vs. Temperature (Sourcing)
Figure 8. Short Circuit Current vs Temperature (Sinking)
Figure 9. Output Voltage vs Output Current
(ISINK, VS = ±15 V)
Figure 10. Output Voltage vs Output Current
(ISOURCE, VS = ±15 V)
Figure 11. Output Voltage vs Output Current
(ISOURCE, VS = ±5 V)
Figure 12. Output Voltage vs Output Current
(ISINK, VS = ±5 V)
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Typical Characteristics (continued)
Figure 13. Output Voltage vs. Output Current
(ISOURCE, VS = +5 V)
Figure 14. Output Voltage vs Output Current
(ISINK, VS = +5 V)
Figure 15. CMRR vs. Frequency
Figure 16. PSRR vs. Frequency
Figure 17. PSRR vs. Frequency
Figure 18. Open Loop Frequency Response
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Typical Characteristics (continued)
12
Figure 19. Open Loop Frequency Response
Figure 20. Open Loop Frequency Response
Figure 21. Unity Gain Frequency vs. Supply Voltage
Figure 22. GBWP at 10 MHz vs. Supply Voltage
Figure 23. Large Signal Voltage Gain vs. Load, VS = ±15 V
Figure 24. Large Signal Voltage Gain vs. Load, VS = ±5 V
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Typical Characteristics (continued)
Figure 25. Input Voltage Noise vs. Frequency
Figure 26. Input Current Noise vs. Frequency
Figure 27. Input Voltage Noise vs. Frequency
Figure 28. Input Current Noise vs. Frequency
Figure 29. Slew Rate vs. Supply Voltage
Figure 30. Slew Rate vs. Input Voltage
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Typical Characteristics (continued)
14
Figure 31. Slew Rate vs. Input Voltage
Figure 32. Slew Rate vs. Load Capacitance
Figure 33. Large Signal Pulse Response,
AV = -1 VS = ±15 V
Figure 34. Large Signal Pulse Response,
AV = -1, VS = ±5V
Figure 35. Large Signal Pulse Response,
AV = -1, VS = +5 V
Figure 36. Large Signal Pulse Response,
AV = +1, VS = ±15 V
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Typical Characteristics (continued)
Figure 37. Large Signal Pulse Response,
AV = +1, VS = ±5 V
Figure 39. Large Signal Pulse Response,
AV = +2, VS = ±15 V
Figure 41. Large Signal Pulse Response,
AV = +2, VS = +5 V
Figure 38. Large Signal Pulse Response,
AV = +1, VS = +5 V
Figure 40. Large Signal Pulse Response,
AV= +2, VS = ±5 V
Figure 42. Small Signal Pulse Response,
AV = -1, VS = ±15 V, RL = 100 Ω
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Typical Characteristics (continued)
16
Figure 43. Small Signal Pulse Response,
AV = - 1, VS = ±5 V, RL= 100 Ω
Figure 44. Small Signal Pulse Response,
AV = -1, VS = +5 V, RL = 100 Ω
Figure 45. Small Signal Pulse Response,
A V = +1, VS = ±15 V, RL = 100 Ω
Figure 46. Small Signal Pulse Response,
A V = +1, V S = ±5 V, RL = 100 Ω
Figure 47. Small Signal Pulse Response,
AV = +1, VS = +5 V, RL = 100 Ω
Figure 48. Small Signal Pulse Response,
AV = +2, VS = ±15 V, RL = 100 Ω
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Typical Characteristics (continued)
Figure 49. Small Signal Pulse Response,
AV = +2, VS = ±5 V, RL = 100 Ω
Figure 50. Small Signal Pulse Response,
AV = +2, VS = +5 V, RL = 100 Ω
Figure 51. Closed Loop Frequency Response vs.
Temperature,
VS = ±15 V, AV = +1, RL = 100 Ω
Figure 52. Closed Loop Frequency Response
vs. Temperature
VS = ±5 V, AV = +1, RL = 100 Ω
Figure 53. Closed Loop Frequency Response
vs. Temperature,
VS = +5 V, AV = +1, RL= 100 Ω
Figure 54. Closed Loop Frequency Response
vs. Temperature,
VS = ±15 V, AV = +2, RL= 100 Ω
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Typical Characteristics (continued)
18
Figure 55. Closed Loop Frequncy Response
vs. Temperature,
VS = ±5 V, AV = +2 , RL = 100 Ω
Figure 56. Closed Loop Frequency Response
vs. Temperature,
VS = +5 V, AV = +2, RL = 100 Ω
Figure 57. Closed Loop Frequency Response
vs. Capacitance Load
(AV = +1, VS = ±15 V)
Figure 58. Closed Loop Frequency Response
vs. Capacitive Load
(AV = +1, VS = ±5 V)
Figure 59. Closed Loop Frequency Response
vs. Capacitive Load
(AV = +2, VS = ±15 V)
Figure 60. Closed Loop Frequency Response
vs. Capacitive Load
(AV = +2, VS = ±5 V)
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Typical Characteristics (continued)
Figure 61. Total Harmonic Distortion vs. Frequency
Figure 62. Total Harmonic Distortion vs. Frequency
Figure 63. Total Harmonic Distortion vs. Frequency
Figure 64. Total Harmonic Distortion vs. Frequency
Figure 65. Undistorted Output Swing vs. Frequency
Figure 66. Undistorted Output Swing vs. Frequency
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Typical Characteristics (continued)
Figure 67. Undistorted Output Swing vs. Frequency
20
Figure 68. Total Power Dissipation vs. Ambient Temperature
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7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
Table 1 depicts the maximum operating supply voltage for each package type
Table 1. Maximum Supply Voltage Values
SOT-23
SO-8
Single Supply
10 V
30 V
Dual Supplies
±5 V
±15 V
Stable unity gain operation is possible with supply voltage of 5 V for all capacitive loads. This allows the
possibility of using the device in portable applications with low supply voltages with minimum components around
it.
Above a supply voltage of 6 V (±3 V Dual supplies), an additional resistor and capacitor (shown in Figure 69)
should be placed in the feedback path to achieve stability at unity gain over the full temperature range.
The package power dissipation should be taken into account when operating at high ambient temperatures
and/or high power dissipative conditions. Refer to the power derating curves in the data sheet for each type of
package.
In determining maximum operable temperature of the device, make sure the total power dissipation of the device
is considered; this includes the power dissipated in the device with a load connected to the output as well as the
nominal dissipation of the op amp.
The device is capable of tolerating momentary short circuits from its output to ground but prolonged operation in
this mode will damage the device, if the maximum allowed junction temperation is exceeded.
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7.2 Typical Applications
Figure 69. Typical Circuit for AV = +1 Operation (VS = 6 V)
Figure 70. Simple Circuit to Improve Linearity and Output Drive Current
Figure 71. AV = -1
CC = 2 pF for RL = 100 Ω
CC = Open for RL = Open
Figure 72. AV = +2
22
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Typical Applications (continued)
Figure 73. AV = +2, Capacitive Load
RF = 0 Ω, CC = Open for VS < 6 V
RF = 510 Ω, CC = 3 pF for VS ≥ 6 V
Figure 74. AV = +1
RF = 0 Ω, CC = Open for VS < 6 V
RF = 510 Ω, CC = 3 pF for VS ≥ 6 V
Figure 75. AV = +1. VS = +5 V, Single Supply Operation
7.2.1 Design Requirements
7.2.1.1 Current Boost Circuit
The circuit in Figure 70 can be used to achieve good linearity along with high output current capability.
By proper choice of R3, the LM7121 output can be set to supply a minimal amount of current, thereby improving
its output linearity.
R3 can be adjusted to allow for different loads:
R3 = 0.1 RL
(1)
Figure 70 has been set for a load of 100 Ω. Reasonable speeds (< 30 ns rise and fall times) can be expected up
to 120 mApp of load current (see Figure 77 for step response across the load).
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Typical Applications (continued)
7.2.2 Detailed Design Procedure
It is very important to keep the lead lengths to a minimum and to provide a low impedance current path by using
a ground-plane on the board.
CAUTION
If RL is removed, the current balance at the output of LM7121 would be disturbed and
it would have to supply the full amount of load current. This might damage the part if
power dissipation limit is exceeded.
7.2.2.1 Color Video on Twisted Pairs Using Single Supply
The circuit shown in Figure 76 can be used to drive in excess of 25 meters length of twisted pair cable with no
loss of resolution or picture definition when driving a NTSC monitor at the load end.
Pin numbers shown are for SO-8 package.
* Input termination of NTSC monitor.
Figure 76. Single Supply Differential Twister Pair Cable Transmitter/Receiver,
8.5 V ≤ VCC ≤ 30 V
24
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Typical Applications (continued)
Differential Gain and Differential Phase errors measured at the load are less than 1% and 1˚ respectively
RG and CC can be adjusted for various cable lengths to compensate for the line losses and for proper response
at the output. Values shown correspond to a twisted pair cable length of 25 meters with about 3 turns/inch (see
Figure 78 for step response).
The supply voltage can vary from 8.5 V up to 30 V with the output rise and fall times under 12 ns. With the
component values shown, the overall gain from the input to the output is about 1.
Even though the transmission line is not terminated in its nominal characteristic impedance of about 600 Ω, the
resulting reflection at the load is only about 5% of the total signal and in most cases can be neglected. Using 75
termination instead, has the advantage of operating at a low impedance and results in a higher realizable
bandwidth and signal fidelity.
7.2.3 Application Performance Plots
Figure 77. Waveform across a 100-Ω Load
Figure 78. Step Response to a 1 VPP Input Signal
Measured across the 75-Ω Load
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8 Device and Documentation Support
8.1 Trademarks
All trademarks are the property of their respective owners.
8.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
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1-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM7121IM
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 85
LM71
21IM
LM7121IM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM71
21IM
LM7121IM5
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
A03A
LM7121IM5/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A03A
LM7121IM5X/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
A03A
LM7121IMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM71
21IM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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