Texas Instruments | Wideband, Low-Distortion, Fully Differential Amplifier, THS4500-EP | Datasheet | Texas Instruments Wideband, Low-Distortion, Fully Differential Amplifier, THS4500-EP Datasheet

Texas Instruments Wideband, Low-Distortion, Fully Differential Amplifier, THS4500-EP Datasheet
THS4500-EP
www.ti.com
SLOS832 – JUNE 2013
WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIER
Check for Samples: THS4500-EP
FEATURES
1
•
•
•
•
•
•
•
23
•
•
•
Fully Differential Architecture
Bandwidth: 370 MHz
Slew Rate: 2800 V/μs
IMD3: –90 dBc at 30 MHz
OIP3: 49 dBm at 30 MHz
Output Common-Mode Control
Wide Power-Supply Voltage Range: 5 V, ±5 V,
12 V, 15 V
Input Common-Mode Range Shifted to Include
Negative Power-Supply Rail
Power-Down Capability (THS4500)
Evaluation Module Available
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
•
•
High Linearity Analog-to-Digital Converter
Preamplifier
Wireless Communication Receiver Chains
Single-Ended to Differential Conversion
Differential Line Driver
Active Filtering of Differential Signals
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Military (–55°C to 125°C)
Temperature Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
VIN−
1
8
VIN+
VOCM
2
7
PD
VS+
3
6
VS−
VOUT+
4
5
VOUT−
RELATED DEVICES
DEVICE (1)
(1)
DESCRIPTION
THS4500/1
370 MHz, 2800 V/μs, VICR Includes VS–
THS4502/3
370 MHz, 2800 V/μs, Centered VICR
THS4120/1
3.3 V, 100 MHz, 43 V/μs, 3.7 nV/√Hz
THS4130/1
±15 V, 150 MHz, 51 V/μs, 1.3 nV/√Hz
THS4140/1
±15 V, 160 MHz, 450 V/μs, 6.5 nV/√Hz
THS4150/1
±15 V, 150 MHz, 650 V/μs, 7.6 nV/√Hz
Even-numbered devices feature power-down capability.
DESCRIPTION
The THS4500 is a high-performance, fully differential amplifier from Texas Instruments. The THS4500, featuring
power-down capability, sets new performance standards for fully differential amplifiers with unsurpassed linearity,
supporting 14-bit operation through 40 MHz. Available in an MSOP-8 with PowerPAD™ package for a smaller
footprint, enhanced ac performance, and improved thermal dissipation capability.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
SLOS832 – JUNE 2013
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50 Ω
VS
0.1 µF
374 Ω
24.9 Ω
+
56.2 Ω
−
−
ADC
12 Bit/80 MSps
IN
VOCM
1 µF
IN
+
24.9 Ω
402 Ω
392 Ω
10 pF
2
5V
10 µF
Vref
THIRD-ORDER INTERMODULATION
DISTORTION
10
−62
VS = 5 V
−68
VS = ±5 V
−74
12
Bits
392 Ω
5V
IMD 3 − Third-Order Intermodulation Distortion − dBc
10 pF
APPLICATION CIRCUIT DIAGRAM
−80
392 Ω
50 Ω
−86
374 Ω
2.5 V
56.2 Ω
VS
−92
402 Ω
VS+
VOUT
+−
−+
VS−
392 Ω
−98
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10
20
30
40
50
60
14
800 Ω
VOCM
70
80
90
16
100
f − Frequency − MHz
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SLOS832 – JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TJ
-55°C to 125°C
(1)
PACKAGE
MSOP PowerPAD™
(DGN)
ORDERABLE PART NUMBER
Reel of 3000
THS4500MDGNREP
Tube of 80
THS4500MDGNEP
TOP-SIDE
MARKING
SJE
VID NUMBER
V62/13610-01XE
V62/13610-01XE-T
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
PIN ASSIGNMENTS
DGN
(TOP VIEW)
VIN– 1
8 VIN+
VOCM 2
7 PD
VS+ 3
6 VS-
VOUT+ 4
5 VOUT-
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ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage, VS
16.5 V
Input voltage, VI
±VS
Output current, IO
(2)
150 mA
Differential input voltage, VID
Maximum junction temperature, TJ
4V
(3)
+150°C
Storage temperature range, Tstg
–65°C to +150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD rating:
(1)
(2)
(3)
+300°C
HBM
4000 V
CDM
1000 V
MM
100 V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The THS4500/1 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally-enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
THERMAL INFORMATION
THS4500
THERMAL METRIC (1)
DGN
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance (2)
63.1
θJCtop
Junction-to-case (top) thermal resistance (3)
46.2
θJB
Junction-to-board thermal resistance (4)
33.9
ψJT
Junction-to-top characterization parameter (5)
1.9
ψJB
Junction-to-board characterization parameter (6)
33.6
θJCbot
Junction-to-case (bottom) thermal resistance (7)
11.9
(1)
(2)
(3)
(4)
(5)
(6)
(7)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
Dual supply
Single supply
Operating junction temperature, TJ
4
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NOM
MAX
±5
±7.5
5
15
-55
125
UNIT
V
°C
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ELECTRICAL CHARACTERISTICS: VS = ±5 V
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC PERFORMANCE
Small-signal bandwidth
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
G = +1, PIN = –20 dBm, RF = 392 Ω
370
MHz
G = +2, PIN = –30 dBm, RF = 1 kΩ
175
MHz
G = +5, PIN = –30 dBm, RF = 2.4 kΩ
70
MHz
G = +10, PIN = –30 dBm, RF = 5.1 kΩ
30
MHz
G > +10
300
MHz
PIN = –20 dBm
150
MHz
VP = 2 V
220
MHz
Slew rate
4 VPP Step
2800
V/μs
Rise time
2 VPP Step
0.4
ns
Fall time
2 VPP Step
0.5
ns
Settling time to 0.01%
VO = 4 VPP
8.3
ns
VO = 4 VPP
6.3
ns
0.1%
Harmonic distortion
2nd harmonic
3rd harmonic
Third-order intermodulation distortion
Third-order output intercept point
G = +1, VO = 2 VPP
f = 8 MHz
–82
dBc
f = 30 MHz
–71
dBc
f = 8 MHz
–97
dBc
f = 30 MHz
–74
dBc
VO= 2 VPP, fC= 30 MHz, RF = 392 Ω,
200 kHz tone spacing
–90
dBc
fC = 30 MHz, RF = 392 Ω,
Referenced to 50 Ω
49
dBm
Input voltage noise
f > 1 MHz
7
nV/√Hz
Input current noise
f > 100 kHz
1.7
pA/√Hz
Overdrive = 5.5 V
60
ns
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
49
Input offset voltage
-11
Average offset voltage drift
dB
6
Input bias current
mV
μV/°C
±10
μA
6.6
Average bias current drift
±10
Input offset current
nA/°C
μA
2
Average offset current drift
±40
nA/°C
INPUT
Common-mode input range
-5.1
Common-mode rejection ratio
2
V
70
dB
107 || 1
Input impedance
Ω || pF
OUTPUT
Differential output voltage swing
RL = 1 kΩ
±7.25
V
Differential output current drive
RL = 20 Ω
90
mA
Output balance error
Closed-loop output impedance (singleended)
PIN = –20 dBm, f = 100 kHz
-58
dB
f = 1 MHz
0.1
Ω
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ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
RL = 400 Ω
180
MHz
Slew rate
2 VPP Step
92
V/μs
Minimum gain
0.98
V/V
Maximum gain
Common-mode offset voltage
Input bias current
-7.6
VOCM = 2.5 V
Input voltage range
1.08
V/V
15
mV
170
μA
±3.4
Input impedance
V
25 || 1
Maximum default voltage
VOCM left floating
Minimum default voltage
VOCM left floating
kΩ || pF
0.10
-0.10
V
V
POWER SUPPLY
Specified operating voltage
7.5
V
Maximum quiescent current
40
mA
Minimum quiescent current
11
mA
Power-supply rejection (±PSRR)
70
dB
POWER-DOWN
Enable voltage threshold
Device enabled ON above –2.9 V
Disable voltage threshold
Device disabled OFF below –4.3 V
-2.9
V
Power-down quiescent current
Input bias current
-4.3
V
1400
μA
260
μA
Input impedance
50 || 1
kΩ || pF
Turn-on time delay
1000
ns
Turn-off time delay
800
ns
6
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ELECTRICAL CHARACTERISTICS: VS = 5 V
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC PERFORMANCE
Small-signal bandwidth
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
G = +1, PIN = –20 dBm, RF = 392 Ω
320
MHz
G = +2, PIN = –30 dBm, RF = 1 kΩ
160
MHz
G = +5, PIN = –30 dBm, RF = 2.4 kΩ
60
MHz
G = +10, PIN = –30 dBm, RF = 5.1 kΩ
30
MHz
G > +10
300
MHz
PIN = –20 dBm
180
MHz
VP = 1 V
200
MHz
Slew rate
2 VPP Step
1300
V/μs
Rise time
2 VPP Step
0.5
ns
Fall time
Settling time to 0.01%
0.1%
Harmonic distortion
2nd harmonic
3rd harmonic
2 VPP Step
0.6
ns
VO = 2 V Step
13.1
ns
VO = 2 V Step
8.3
ns
G = +1, VO = 2 VPP
f = 8 MHz,
-80
dBc
f = 30 MHz
-55
dBc
f = 8 MHz
-76
dBc
f = 30 MHz
-60
dBc
Input voltage noise
f > 1 MHz
7
nV/√Hz
Input current noise
f > 100 kHz
1.7
pA/√Hz
Overdrive = 5.5 V
60
ns
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
48
Input offset voltage
-11
Average offset voltage drift
dB
6
μV/°C
±10
Input bias current
8
Average bias current drift
±10
Input offset current
μA
nA/°C
2
Average offset current drift
mV
±20
μA
nA/°C
INPUT
Common-mode input range
-0.1
Common-mode rejection ratio
65
2
107 || 1
Input Impedance
V
dB
Ω || pF
OUTPUT
Differential output voltage swing
RL = 1 kΩ, Referenced to 2.5 V
±2.7
V
Output current drive
RL = 20 Ω
80
mA
Output balance error
PIN = –20 dBm, f = 100 kHz
-58
dB
f = 1 MHz
0.1
Ω
Closed-loop output impedance (singleended)
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ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
RL = 400 Ω
180
MHz
Slew rate
2 VPP Step
80
V/μs
Minimum gain
0.92
V/V
Maximum gain
Common-mode offset voltage
-5.6
Input bias current
VOCM = 2.5 V
Input voltage range
1.3
1.17
V/V
35
mV
3
μA
3.7
Input impedance
25 || 1
Maximum default voltage
VOCM left floating
Minimum default voltage
VOCM left floating
V
kΩ || pF
2.75
2.25
V
V
POWER SUPPLY
Specified operating voltage
15
V
Maximum quiescent current
38
mA
Minimum quiescent current
10
mA
Power-supply rejection (+PSRR)
66
dB
POWER -DOWN
Enable voltage threshold
Device enabled ON above 2.1 V
2.1
Disable voltage threshold
Device disabled OFF below 0.7 V
0.7
V
V
Power-down quiescent current
1400
Input bias current
140
μA
μA
Input impedance
50 || 1
kΩ || pF
Turn-on time delay
1000
ns
Turn-off time delay
800
ns
100,000,000
Estimated Life (Hours)
10,000,000
Wirebond Voiding Fail Mode
1,000,000
100,000
Electromigration Failure Mode
10,000
1,000
80
90
100
110
120
130
140
150
Continuous TJ (°C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
Enhanced plastic product disclaimer applies.
(4)
Electromigration calculation is based on output switching 50% duty cycle at max load of 120 mA.
Figure 1. THS4500-EP Derating Chart
8
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TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL FREQUENCY
RESPONSE
1
22
0.5
20
0.3
−1
−1.5
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = ±5 V
−2.5
−3
0.2
1
14
Gain = 5, Rf = 2.4 kΩ
12
10
8
4
RL = 800 Ω
PIN = −30 dBm
0
VS = ±5 V
−2
0.1
1
10
100
1000
−0.3
10
100
LARGE-SIGNAL FREQUENCY
RESPONSE
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
1
−30
−40
−50
−60
−70
HD2
−80
10
100
−100
0.1
1000
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = ±5 V
−10
−90
−4
1
10
−20
−30
−40
−50
−60
−70
HD2
−80
−90
HD3
HD3
−100
0.1
100
1
f − Frequency − MHz
f − Frequency − MHz
10
100
f − Frequency − MHz
Figure 5.
Figure 6.
Figure 7.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
0
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
Harmonic Distortion − dBc
−10
−60
−70
HD2
HD3
−90
1
10
f − Frequency − MHz
−20
−30
−40
−50
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
−60
−70
−80
HD2
−90
100
Figure 8.
−100
0.1
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = ±5 V
−10
Harmonic Distortion − dBc
0.1
−20
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = ±5 V
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−3
−100
0.1
1000
Figure 4.
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = 10 dBm
VS = ±5 V
−80
100
Figure 3.
−2
−50
10
1
1000
Figure 2.
−1
−40
Rf = 392 Ω
−0.1
f − Frequency − MHz
0
−30
0
−0.2
0
−20
Rf = 499 Ω
f − Frequency − MHz
−10
−10
0.1
f − Frequency − MHz
1
Large Signal Gain − dB
Gain = 2, Rf = 1 kΩ
6
2
−4
0.1
16
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = ±5 V
Gain = 10, Rf = 5.1 kΩ
0.1 dB Gain Flatness − dB
−0.5
−3.5
Harmonic Distortion − dBc
0.1-dB GAIN FLATNESS FREQUENCY
RESPONSE
18
0
Small Signal Gain − dB
Small Signal Unity Gain − dB
SMALL-SIGNAL UNITY-GAIN
FREQUENCY RESPONSE
−20
−30
−40
−50
−60
−70
HD2
−80
−90
HD3
HD3
−100
1
10
f − Frequency − MHz
Figure 9.
100
0
0.5
1
1.5 2
2.5
3
3.5 4
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Figure 10.
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4.5
VO − Output Voltage Swing − V
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TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
−20
−30
−40
−50
−60
−70
HD2
−80
−90
HD3
0.5
1
1.5 2
2.5
3
3.5 4
4.5
−40
−50
−60
HD2
−70
−80
5
HD3
1
1.5 2
2.5
3
3.5 4
4.5
0
1.5 2
2.5
3
3.5 4
4.5
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
1
10
f − Frequency − MHz
−20
−30
−40
−50
−60
HD2
−70
HD3
−80
−20
−30
−40
−50
−60
HD2
−70
−80
HD3
−90
−100
−100
0.1
100
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = ±5 V
−10
−90
−100
1
10
f − Frequency − MHz
0.1
100
1
10
f − Frequency − MHz
100
Figure 14.
Figure 15.
Figure 16.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
0
Harmonic Distortion − dBc
−50
HD2
−60
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
−10
−70
−80
HD3
−20
−30
−40
−50
−60
−70
HD2
−80
−90
−90
Figure 17.
100
−20
−30
−40
−50
−60
−70
−80
HD2
−90
HD3
−100
1
10
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
−10
Harmonic Distortion − dBc
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = ±5 V
5
0
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = ±5 V
−10
HD3
−100
0.1
1
HARMONIC DISTORTION
vs
FREQUENCY
−90
−40
0.5
Figure 13.
HD2
−30
HD3
Figure 12.
−80
−20
−80
Figure 11.
−70
−10
HD2
−70
VO − Output Voltage Swing − V
−60
0.1
−60
5
Harmonic Distortion − dBc
−50
−50
VO − Output Voltage Swing − V
Harmonic Distortion − dBc
−40
−40
−100
0.5
0
−30
−30
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = ±5 V
−20
−20
−90
0
0
−10
Harmonic Distortion − dBc
−30
−100
0
Harmonic Distortion − dBc
−20
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
−10
−90
−100
10
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
−10
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−10
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HD3
−100
0
0.5
1
1.5 2
2.5
3
3.5 4
4.5
5
0
0.5
1
1.5 2
2.5
3
3.5 4
VO − Output Voltage Swing − V
VO − Output Voltage Swing − V
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 30 MHz
VS = ±5 V
−20
−30
−40
−50
HD2
−60
−70
−80
−20
HD3
−30
−40
−50
−60
HD2
−80
HD3
−30
−40
−50
−60
0.5
1
1.5 2
2.5
3
3.5 4
4.5
5
−80
0
0.5
1
1.5 2
2.5
3
3.5 4
4.5
5
−100
0
400
800
1200
1600
RL − Load Resistance − Ω
Figure 20.
Figure 21.
Figure 22.
HARMONIC DISTORTION
vs
LOAD RESISTANCE
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
−10
−20
−30
−40
−50
−60
HD2
−70
−80
HD3
−90
−100
400
800
1200
1600
−50
Third-Order Output Intercept Point - dBm
Third-Order Intermodulation Distortion − dBc
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
−60
−70
−80
−90
−100
10
RL − Load Resistance − Ω
100
55
Gain = 1
RF = 392 W
VO = 2 VPP
VS = ± 5 V
50
45
40
35
30
0
20
f − Frequency − MHz
Figure 23.
40
Rising Edge
1000
1.0
0.4
VO - Output Voltage - V
VO − Output Voltage − V
0.6
1500
120
SETTLING TIME
Rising Edge
2000
100
1.5
0.8
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VS = ±5 V
80
Figure 25.
SETTLING TIME
3000
60
f - Frequency - MHz
Figure 24.
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP
2500
HD3
VO − Output Voltage Swing − V
0
0
HD2
−70
−90
−100
0
SR − Slew Rate − V/ µ s
−20
−90
−100
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
−10
−70
−90
Harmonic Distortion − dBc
0
Differentia Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
−10
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−10
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
LOAD RESISTANCE
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
0.2
0
−0.2
−0.4
Falling Edge
Gain = 1
RL = 800 W
RF = 499 W
f = 1 MHz
VS = ±5 V
0.5
0
-0.5
Falling Edge
-1.0
500
−0.6
0
−0.8
0
0.5 1
1.5 2
2.5
3 3.5
4
4.5
5
VO − Differential Output Voltage Step − V
Figure 26.
0
5
10
15
20
-1.5
0
2
4
6
8
t − Time − ns
t - Time - ns
Figure 27.
Figure 28.
10
12
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TYPICAL CHARACTERISTICS: ±5 V (continued)
SMALL-SIGNAL TRANSIENT
RESPONSE
1
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0.5
0
−0.5
−1
0
100
200
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0.1
0
−0.1
−0.2
300
400
−0.4
−100
500
2
2
1.5
1
1
0.5
0
0
−1
−0.5
−2
−1
−3
−1.5
−4
−2
−2.5
−5
0
100
200
300
400
0
500
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − µs
t − Time − ns
Figure 30.
Figure 31.
OVERDRIVE RECOVERY
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
REJECTION RATIOS
vs
FREQUENCY
90
0
−50
Vn
10
PSRR+
80
70
Rejection Ratios − dB
50
Hz
100
I n − Current Noise − pA/
Source
Hz
100
VS = ±5 V
60
50
CMMR
PSRR−
40
30
20
In
10
RL = 800 Ω
VS = ±5 V
Sink
0
1
0.01
Case Temperature − °C
0.1
1
10
100
1000
−10
10 k
0.1
1
10
f − Frequency − MHz
f − Frequency − kHz
100
Figure 32.
Figure 33.
Figure 34.
REJECTION RATIOS
vs
CASE TEMPERATURE
OUTPUT BALANCE ERROR
vs
FREQUENCY
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
0
−10
Output Balance Error − dB
CMMR
100
PSRR+
80
60
40
20
RL = 800 Ω
VS = ±5 V
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 35.
60
PIN = 10 dBm
RL = 800 Ω
Rf = 392 Ω
VS = ±5 V
−20
−40
−50
−60
−70
0.1
1
PIN = −30 dBm
RL = 800 Ω
VS = ±5 V
50
−30
−80
30
Gain
Open-Loop Gain − dB
120
Rejection Ratios − dB
3
t − Time − ns
−150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
12
2.5
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
Figure 29.
150
Output Drive − mA
0.2
Vn − Voltage Noise − nV/
−2
−100
−100
0.3
4
−0.3
−1.5
200
5
10
f − Frequency − MHz
Figure 36.
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100
40
0
−30
−60
30
Phase
Phase − °
VO − Output Voltage − V
VO − Output Voltage − V
1.5
OVERDRIVE RECOVERY
0.4
Single-Ended Output Voltage − V
2
VI − Input Voltage − V
LARGE-SIGNAL TRANSIENT
RESPONSE
20
−90
10
−120
0
0.01
0.1
1
10
100
−150
1000
f − Frequency − MHz
Figure 37.
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SLOS832 – JUNE 2013
TYPICAL CHARACTERISTICS: ±5 V (continued)
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
RL = 800 Ω
VS = ±5 V
Open-Loop Gain − dB
56
55
54
53
52
51
50
35
0
VS = ±5 V
3.3
I IB − Input Bias Current − µ A
57
IIB−
−0.01
−0.02
3.2
IIB+
3.1
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
−0.03
3
−0.04
2.9
−0.05
2.8
−0.06
IOS
2.7
−0.07
2.6
−0.08
TA = 85°C
30
Quiescent Current − mA
3.4
58
I OS − Input Offset Current − µ A
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
25
TA = −40°C
20
15
10
5
−0.09
2.5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
49
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
Case Temperature − °C
1
1.5
2
2.5
3
3.5
4 4.5
Figure 39.
Figure 40.
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
OUTPUT DRIVE
vs
CASE TEMPERATURE
5
4
3
2
1
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
200
110
VS = ±5 V
100
VS = ±5 V
5
Source
150
90
80
100
Output Drive − mA
6
CMRR − Common-Mode Rejection Ratio − dB
Figure 38.
VS = ±5 V
70
60
50
40
30
50
0
−50
20
10
−100
0
−10
−6 −5 −4 −3 −2 −1 0
Case Temperature − °C
1
2
3
4
5
6
Sink
−150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 42.
Figure 43.
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
SMALL-SIGNAL FREQUENCY
RESPONSE AT VOCM
OUTPUT OFFSET VOLTAGE AT VOCM
vs
OUTPUT COMMON-MODE VOLTAGE
0
Single-Ended and Differential
Input to Differential Output
Gain = 1, VO = 2 VPP
f= 8 MHz, Rf = 392 Ω
VS = ±5 V
−10
−20
−30
−40
HD2-SE
−50
HD2
-Diff
−60
−70
HD3-SE
HD3-Diff
−80
−90
−100
−3.5
−2.5 −1.5 −0.5
0.5
1.5
2.5
3.5
VOC − Output Common-Mode Voltage − V
Figure 44.
Small Signal Frequency Response at VOCM − dB
Input Common-Mode Voltage Range − V
Figure 41.
600
3
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN= −20 dBm
VS = ±5 V
2
1
VOS − Output Offset Voltage − mV
VOS − Input Offset Voltage − mV
0 0.5
VS − Supply Voltage − ±V
7
Harmonic Distortion − dBc
TA = 25°C
0
400
200
0
−200
−1
−400
−2
−600
−3
1
10
100
f − Frequency − MHz
Figure 45.
1000
−5 −4 −3 −2 −1
0
1
2
3
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Figure 46.
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VOC − Output Common-Mode Voltage − V
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TYPICAL CHARACTERISTICS: ±5 V (continued)
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
30
800
15
10
5
0
Quiescent Current − mA
Powerdown Voltage Signal − V
20
0.02
0.01
Current
0
0
−1
−2
−3
−4
−5
−5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0
Power-Down Voltage − V
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
102
103
500
400
300
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −1 dBm
VS = ±5 V
200
100
1
10
100
1000
f − Frequency − MHz
Figure 49.
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
1000
1000
RL = 800 Ω
VS = ±5 V
Power-Down Quiescent Current − µ A
Power-Down Quiescent Current − µ A
600
Figure 48.
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
800
700
600
500
400
300
200
100
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
RL = 800 Ω
900
800
700
600
500
400
300
200
100
0
0
0.5 1
1.5 2
2.5 3
3.5 4
4.5 5
VS − Supply Voltage − ±V
Case Temperature − °C
Figure 50.
14
700
0
0.1
−6
Figure 47.
900
ZO− Single-Ended Output Impedance
in Powerdown − Ω
0.03
25
Quiescent Current − mA
SINGLE-ENDED OUTPUT
IMPEDANCE IN POWER-DOWN
vs
FREQUENCY
TURN-ON AND TURN-OFF DELAY
TIME
Figure 51.
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TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNITY-GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
1
0.2
22
Gain = 10, Rf = 5.1 kΩ
−1
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = 5 V
−3
0.1
1
16
Gain = 5, Rf = 2.4 kΩ
14
12
10
8
Gain = 2, Rf = 1 kΩ
6
4
2
10
100
0
−2
0.1
1000
0.1 dB Gain Flatness − dB
0
−4
f − Frequency − MHz
RL = 800 Ω
PIN = −30 dBm
VS = 5 V
1
0
Rf = 392 Ω
−0.1
−0.2
−0.3
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = 5 V
−0.4
−0.5
10
100
10
1
1000
100
1000
f − Frequency − MHz
f − Frequency − MHz
Figure 52.
Figure 53.
Figure 54.
LARGE-SIGNAL FREQUENCY
RESPONSE
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
0
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = 5 V
−10
Harmonic Distortion − dBc
0
−1
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = 10 dBm
VS = 5 V
−3
−20
−30
−40
−50
−60
HD2
−70
−80
1
10
100
1000
−30
−40
−60
HD2
−70
−80
HD3
−100
0.1
Figure 55.
Figure 56.
Figure 57.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = 5 V
−10
−50
−60
−70
HD3
HD2
−80
−90
−100
0.1
−50
1
10
f − Frequency − MHz
−20
−30
−40
100
−60
HD3
HD2
−80
10
100
−100
0.1
−20
−30
−40
−50
−60
HD3
−70
−80
HD2
−90
1
100
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = 5 V
−10
−50
−70
1
10
f − Frequency − MHz
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
Harmonic Distortion − dBc
0.1
Harmonic Distortion − dBc
−20
−40
f − Frequency − MHz
0
−10
−30
−90
−100
0.1
−20
HD3
−90
−4
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = 5 V
−10
Harmonic Distortion − dBc
1
Large Signal Gain − dB
Rf = 499 Ω
0.1
18
Small Signal Gain − dB
Small Signal Unity Gain − dB
20
Harmonic Distortion − dBc
0.1-dB GAIN FLATNESS FREQUENCY
RESPONSE
−90
−100
f − Frequency − MHz
1
10
f − Frequency − MHz
Figure 58.
Figure 59.
100
0
0.5
1
1.5
2
2.5
Figure 60.
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TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = 5 V
−20
−30
−40
−50
−60
HD3
−70
−80
HD2
−90
−100
0
0.5
1
1.5
2
2.5
−20
−30
−40
HD2
−60
−70
−80
−30
−40
−70
−80
−90
−100
1
1.5
2
2.5
3
0
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
HD2
−80
−20
−30
−40
−50
HD2
−60
−70
−80
−20
−30
−40
−50
−60
10
−80
HD3
1
10
f − Frequency − MHz
f − Frequency − MHz
100
−100
0.1
Figure 66.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
HD3
HD2
−80
−90
−20
−30
−40
−50
−60
HD3
−70
−80
HD2
−90
−100
0.1
10
100
20
30
40
50
60
HD3
70
80
HD2
90
−100
1
Differential Input to
Differential Output
Gain = 2
RL = 800 W
RF = 1 kW
f = 8 MHz
VS = 5 V
10
Harmonic Distortion - dBc
−60
−70
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f = 8 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
−50
100
Figure 65.
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = 5 V
−40
1
10
f − Frequency − MHz
Figure 64.
0
−30
HD2
−90
−100
0.1
100
HD3
−70
−90
1
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = 5 V
−10
Harmonic Distortion − dBc
−70
3
0
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = 5 V
−10
HD3
−20
2.5
HARMONIC DISTORTION
vs
FREQUENCY
−60
−10
2
Figure 63.
−50
0.1
1.5
Figure 62.
Harmonic Distortion − dBc
−40
1
Figure 61.
0
−30
0.5
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = 5 V
−20
HD2
−60
−90
0.5
HD3
−50
VO − Output Voltage Swing − V
−100
Harmonic Distortion − dBc
−20
−100
0
−90
16
HD3
−50
3
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = 5 V
−10
VO − Output Voltage Swing − V
0
−10
Harmonic Distortion − dBc
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f = 30 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−10
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
100
0
0.5
1
1.5
2
2.5
f − Frequency − MHz
VO − Output Voltage Swing − V
Figure 67.
Figure 68.
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3
0
0.5
1
1.5
2
2.5
3
VO - Output Voltage Swing - V
Figure 69.
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TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
−30
−40
−50
HD2
−60
HD3
−70
−80
20
30
40
60
HD3
70
80
−30
−40
−60
−80
−90
100
−100
1
1.5
2
2.5
3
0
0.5
800
1200
1600
HARMONIC DISTORTION
vs
LOAD RESISTANCE
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
HD2
-60
HD3
-70
-80
-90
0
400
RL − Load Resistance − Ω
Figure 72.
-50
400
800
1200
1600
−50
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
RL = 800 Ω
VS = 5 V
−60
−70
−80
−90
−100
10
RL - Load Resistance - W
55
Gain = 1
VO = 2 VPP
RF = 392 W
RL = 800 W
VS = 5 V
50
45
40
35
30
0
100
20
f − Frequency − MHz
40
60
80
100
120
f - Frequency - MHz
Figure 73.
Figure 74.
Figure 75.
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP
LARGE-SIGNAL TRANSIENT
RESPONSE
SMALL-SIGNAL TRANSIENT
RESPONSE
1400
1200
1000
VO − Output Voltage − V
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VS = 5 V
800
600
400
200
2
0.4
1.5
0.3
VO − Output Voltage − V
-100
0
3
Third-Order Output Intercept Point - dBm
-40
2.5
Figure 71.
Third-Order Intermodulation Distortion − dBc
-30
2
Figure 70.
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
RF = 392 W
f = 30 MHz
VS = 5 V
-20
1.5
VO - Output Voltage Swing - V
0
-10
1
HD3
−70
−100
0.5
HD2
−50
90
VO − Output Voltage Swing − V
Harmonic Distortion - dBc
HD2
50
−20
−90
0
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
−20
Differential Input to
Differential Output
Gain = 2
RL = 800 W
RF = 1 kW
f = 30 MHz
VS = 5 V
10
Harmonic Distortion - dBc
Harmonic Distortion − dBc
0
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f = 30 MHz
VS = 5 V
−10
SR − Slew Rate − V/ µ s
HARMONIC DISTORTION
vs
LOAD RESISTANCE
1
Gain = 1
RL = 800 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = 5 V
0.5
0
−0.5
−1
0
0.5
1
1.5
2
2.5
3
VO − Differential Output Voltage Step − V
Figure 76.
Gain = 1
RL = 800 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = 5 V
0.1
0
−0.1
−0.2
−0.3
−1.5
0
0.2
−2
−100
0
100
200
300
t − Time − ns
400
Figure 77.
500
−0.4
−100
0
100
200
300
400
Figure 78.
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TYPICAL CHARACTERISTICS: 5 V (continued)
REJECTION RATIOS
vs
FREQUENCY
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
90
60
50
CMMR
PSRR−
40
30
20
In
10
0.1
1
10
100
1000
0.1
1
10
f − Frequency − MHz
f − Frequency − kHz
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
60
30
−60
Phase
−90
20
Open-Loop Gain − dB
−30
Phase − °
Open-Loop Gain − dB
55
40
54
53
52
51
50
49
48
−120
1
10
f − Frequency − MHz
0
0.01
100
0.1
1
10
46
−150
1000
100
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
f − Frequency − MHz
Figure 82.
Figure 83.
Figure 84.
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
0
35
4
TA = 85°C
IIB+
I OS − Input Offset Current − µ A
−0.01
30
−0.02
IIB−
−0.03
2.75
−0.04
2.5
−0.05
IOS
−0.06
2
−0.07
1.75
−0.08
1.5
−0.09
−0.1
1.25
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 85.
TA = 25°C
VOS − Input Offset Voltage − mV
VS = 5 V
Quiescent Current − mA
Output Balance Error − dB
0
47
3.75
I IB − Input Bias Current − µ A
RL = 800 Ω
VS = 5 V
56
10
−70
0.1
18
PIN = −30 dBm
RL = 800 Ω
VS = 5 V
50
−60
57
30
Gain
−50
2.25
Case Temperature − °C
OUTPUT BALANCE ERROR
vs
FREQUENCY
−40
3
100
Figure 81.
−30
3.25
RL = 800 Ω
VS = 5 V
Figure 80.
PIN = −20 dBm
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
−20
40
Figure 79.
0
−10
PSRR+
60
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−10
10 k
PSRR−
80
20
RL = 800 Ω
VS = 5 V
0
1
0.01
CMMR
100
70
Rejection Ratios − dB
Hz
I n − Current Noise − pA/
Vn
10
120
PSRR+
80
Rejection Ratios − dB
Hz
Vn − Voltage Noise − nV/
100
3.5
REJECTION RATIOS
vs
CASE TEMPERATURE
25
TA = −40°C
20
15
10
5
0
0 0.5
1
1.5
2
2.5
3
3.5
4 4.5
5
3.5
VS = 5 V
3
2.5
2
1.5
1
0.5
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
VS − Supply Voltage − ±V
Case Temperature − °C
Figure 86.
Figure 87.
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TYPICAL CHARACTERISTICS: 5 V (continued)
OUTPUT DRIVE
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
0
150
VS = 5 V
VS = 5 V
90
Source
100
Output Drive − mA
80
70
60
50
40
30
50
0
−50
20
−100
10
0
−10
0
1
2
3
4
Sink
5
−20
−30
−40
−50
HD3-SE
and Diff
−60
−70
−80
−90
HD2-SE
1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
Input Common-Mode Range − V
Case Temperature − °C
VOCM − Output Common-Mode Voltage − V
Figure 88.
Figure 89.
Figure 90.
SMALL-SIGNAL FREQUENCY
RESPONSE AT VOCM
OUTPUT OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE VOLTAGE
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
800
25
4
2
1
VS = 5 V
600
Quiescent Current − mA
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN= −20 dBm
VS = 5 V
3
HD2-Diff
−100
−150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
VOS − Output Offset Voltage − mV
Small Signal Frequency Response at VOCM − dB
−1
Single-Ended and
Differential Input
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 8 MHz, VS = 5 V
−10
Harmonic Distortion − dBc
CMRR − Common-Mode Rejection Ratio − dB
110
100
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
400
200
0
−200
0
−400
−1
20
15
10
5
−600
−2
−800
0
0 0.5
−3
0.1
1
10
100
1000
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage − V
VOC − Output Common-Mode Voltage − V
f − Frequency − MHz
Figure 91.
Figure 92.
Figure 93.
TURN-ON AND TURN-OFF DELAY
TIME
SINGLE-ENDED OUTPUT
IMPEDANCE IN POWER-DOWN
vs
FREQUENCY
POWER-DOWN QUIESCENT
CURRENT
vs
CASE TEMPERATURE
0
−1
−2
−3
−4
−5
−6
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
102
103
Figure 94.
Power-Down Quiescent Current − µ A
0
Quiescent Current − mA
0.01
ZO− Single-Ended Output Impedance
in Power Down − Ω
Power-Down Voltage Signal − V
1000
0.02
Current
800
1100
0.03
900
800
700
600
500
400
300
200
100
0
0.1
Gain = 1
RL = 400 Ω
Rf = 499 Ω
PIN = −1 dBm
VS = 5 V
1
10
100
f − Frequency − MHz
Figure 95.
1000
700
RL = 800 Ω
VS = 5 V
600
500
400
300
200
100
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 96.
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TYPICAL CHARACTERISTICS: 5 V (continued)
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
Power-Down Quiescent Current − µ A
1000
900
800
700
600
500
400
300
200
100
0
0
0.5 1
1.5 2
2.5 3
3.5 4
4.5 5
VS − Supply Voltage − V
Figure 97.
20
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIERS
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external commonmode noise, suppression of even-order nonlinearities,
and increased dynamic range. Fully differential
amplifiers not only serve as the primary means of
providing gain to a differential signal chain, but also
provide a monolithic solution for converting singleended signals into differential signals for easier,
higher performance processing. The THS4500 family
of amplifiers contains products in Texas Instruments'
expanding line of high-performance, fully differential
amplifiers. Information on fully differential amplifier
fundamentals, as well as implementation specific
information, is presented in the Applications Section
of this data sheet to provide a better understanding of
the operation of the THS4500 family of devices, and
to simplify the design process for designs using these
amplifiers.
Fully differential amplifiers are typically packaged in
eight-pin packages, as shown in Figure 98. The
device pins include two inputs (VIN+, VIN–), two
outputs (VOUT–, VOUT+), two power supplies (VS+, VS–),
an output common-mode control pin (VOCM), and an
optional power-down pin (PD).
APPLICATIONS SECTION
A standard configuration for the device is shown in
Figure 98. The functionality of a fully differential
amplifier can be imagined as two inverting amplifiers
that share a common noninverting terminal (though
the voltage is not necessarily fixed). For more
information on the basic theory of operation for fully
differential amplifiers, refer to the Texas Instruments
application note Fully Differential Amplifiers, literature
number SLOA054.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential
Amplifiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
Setting the Output Common-Mode Voltage With
the VOCM Input
Saving Power with Power-Down Functionality
Linearity:
Definitions,
Terminology,
Circuit
Techniques, and Design Tradeoffs
An Abbreviated Analysis of Noise in Fully
Differential Amplifiers
Printed-Circuit Board Layout Techniques for
Optimal Performance
Power Dissipation and Thermal Considerations
Power Supply Decoupling Techniques and
Recommendations
Evaluation
Fixtures,
Spice
Models,
and
Applications Support
Additional Reference Material
VIN- 1
8 VIN+
VOCM 2
7 PD
VS+ 3
6 VS-
VOUT+ 4
5 VOUT-
Figure 98. Fully Differential Amplifier Pin Diagram
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the
four devices. The THS4502 and THS4503 have an
input common-mode range that is centered around
midrail, and the THS4500 and THS4501 have an
input common-mode range that is shifted to include
the negative power-supply rail. Selection of one or
the other amplifier is determined by the nature of the
application. Specifically, the THS4500 and THS4501
are designed for use in single-supply applications
where the input signal is ground-referenced, as
depicted in Figure 99. The THS4502 and THS4503
are designed for use in single-supply or split-supply
applications where the input signal is centered
between the power-supply voltages, as depicted in
Figure 100.
xxx
xxx
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RF1
RG1
RS
+VS
RT
VS
V OUT) +
V OUT–
+ - +
VOCM
RG2
RF2
Figure 99. Application Circuit for the THS4500
and THS4501, Featuring Single-Supply Operation
With a Ground-Reference Input Signal
V IN)(1–β)–V IN–(1–β) ) 2V OCMβ
2β
(3)
Where:
RG
β+
RF ) RG
(4)
V P + V IN)(1–β) ) V OUT–β
NOTE: The equations denote the device inputs as VN and VP, and
the circuit inputs as VIN+ and VIN–.
(5)
RF
RG
VIN+
+VS
RT
VS
VP
VOCM
+ - +
VOCM
VN
+ - +
VOUTVOUT+
VIN-
-VS
RG
RG2
(2)
V N + V IN–(1–β) ) V OUT)β
RF1
RG1
RS
(1)
–V IN)(1–β) ) V IN–(1–β) ) 2V OCMβ
+
2β
RF
RF2
Figure 100. Application Circuit for the THS4500
and THS4501, Featuring Split-Supply Operation
With an Input Signal Referenced at the Midrail
Equation 1 through Equation 5 are used to calculate
the required input common-mode range for a given
set of input conditions.
The equations allow calculation of the input commonmode range requirements, given information about
the input signal, the output voltage swing, the gain,
and the output common-mode voltage. Calculating
the maximum and minimum voltage required for VN
and VP (the amplifier input nodes) determines
whether or not the input common-mode range is
violated or not. Four equations are required: two
calculate the output voltages and two calculate the
node voltages at VN and VP (note that only one of
these nodes needs calculation, because the amplifier
forces a virtual short between the two nodes).
Figure 101. Diagram For Input Common-Mode
Range Equations
Table 1 and Table 2 depict the input common-mode
range requirements for two different input scenarios,
an input referenced around the negative rail and an
input referenced around midrail. The tables highlight
the differing requirements on input common-mode
range, and illustrate the reasoning to choose either
the THS4500/1 or the THS4502/3. For signals
referenced around the negative power supply, the
THS4500/1 should be chosen because its input
common-mode range includes the negative supply
rail. For all other situations, the THS4502/3 offers
slightly improved distortion and noise performance for
applications with input signals centered between the
power-supply rails.
Table 1. Negative-Rail Referenced
22
Gain
(V/V)
VIN+
(V)
VIN–
(V)
VIN
(VPP)
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
1
–2.0 to 2.0
0
4
2.5
4
0.75
1.75
2
–1.0 to 1.0
0
2
2.5
4
0.5
1.167
4
–0.5 to 0.5
0
1
2.5
4
0.3
0.7
8
–0.25 to 0.25
0
0.5
2.5
4
0.167
0.389
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Table 2. Midrail Referenced
Gain
(V/V)
VIN+
(V)
VIN–
(V)
VIN
(VPP)
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
1
0.5 to 4.5
2.5
4
2.5
4
2
3
2
1.5 to 3.5
2.5
2
2.5
4
2.16
2.83
4
2.0 to 3.0
2.5
1
2.5
4
2.3
2.7
8
2.25 to 2.75
2.5
0.5
2.5
4
2.389
2.61
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values
presented in this section provide the optimum highfrequency performance (lowest distortion, flat
frequency response). Since the THS4500 family of
amplifiers is developed with a voltage feedback
architecture, the choice of resistor values does not
have a dominant effect on bandwidth, unlike a
current-feedback amplifier. However, resistor choices
do have second-order effects. For optimal
performance, the following feedback resistor values
are recommended. In higher gain configurations (gain
greater than two), the feedback resistor values have
much less effect on the high-frequency performance.
Example feedback and gain resistor values are given
in the section on basic design considerations
(Table 3).
Amplifier loading, noise, and the flatness of the
frequency response are three design parameters that
should be considered when selecting feedback
resistors. Larger resistor values contribute more noise
and can induce peaking in the ac response in low
gain configurations; smaller resistor values can load
the amplifier more heavily, resulting in a reduction in
distortion performance. In addition, feedback resistor
values, coupled with gain requirements, determine
the value of the gain resistors and directly impact the
input impedance of the entire circuit. While there are
no strict rules about resistor selection, these trends
can provide qualitative design guidance.
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers provide designers with a
great deal of flexibility in a wide variety of
applications. This section provides an overview of
some common circuit configurations and gives some
design guidelines. Designing the interface to an
analog-to-digital converter (ADC), driving lines
differentially, and filtering with fully differential
amplifiers are a few of the circuits that are covered.
BASIC DESIGN CONSIDERATIONS
Table 3. Resistor Values for Balanced Operation
in Various Gain Configurations
Gain
R2 and R4
(Ω)
R1 (Ω)
R3 (Ω)
RT (Ω)
1
392
412
383
54.9
1
499
523
487
53.6
2
392
215
187
60.4
2
1.3 k
665
634
52.3
5
1.3 k
274
249
56.2
5
3.32 k
681
649
52.3
10
1.3 k
147
118
64.9
10
6.81 k
698
681
52.3
ǒ Ǔ
VOD
VIN
R2
R1
Vn
Vout+
R3
RS
+
+
-
VP
VS
VoutVOCM
RT
R4
Figure 102. Diagram for Design Calculations
Equations for calculating fully differential amplifier
resistor values in order to obtain balanced operation
in the presence of a 50-Ω source impedance are
given in Equation 6 through Equation 9.
1
K + R2 R2 + R4
RT +
R1
K
1–
2(1)K)
1 –
RS
R3
R3 + R1 * ǒRs || R TǓ
(6)
β1 +
R3 ) RT || R S
R1
β +
R1 ) R2 2
R3 ) RT || R S ) R4
ǒ Ǔǒ
1–β
Ǔ
+ 2ǒ
β )β
V OD
1–β 2
+2
β1 ) β 2
VS
V OD
V IN
RT
RT ) RS
Ǔ
(7)
(8)
2
1
2
(9)
The circuits in Figure 99 through Figure 102 are used
to highlight basic design considerations for fully
differential amplifier circuit designs.
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For more detailed information about balance in fully
differential amplifiers, see the application report, Fully
Differential Amplifiers (SLOA054), referenced at the
end of this data sheet.
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
The THS4500 family of amplifiers are designed
specifically to interface to today's highestperformance ADCs. This section highlights the key
concerns when interfacing to an ADC and provides
example interface circuits.
There are several key design concerns when
interfacing to an analog-to-digital converter:
• Terminate the input source properly. In highfrequency receiver chains, the source that feeds
the fully differential amplifier requires a specific
load impedance (that is, 50 Ω).
• Design a symmetric printed circuit board (PCB)
layout. Even-order distortion products are heavily
influenced by layout, and careful attention to a
symmetric layout minimizes these distortion
products.
• Minimize inductance in power-supply decoupling
traces and components. Poor power-supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power-supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the
current loop.
• Use separate analog and digital power supplies
and grounds. Noise (bounce) in the power
supplies (created by digital switching currents) can
couple directly into the signal path, and powersupply noise can create higher distortion products
as well.
• Use care when filtering. While an RC low-pass
filter may be desirable on the output of the
amplifier to filter broadband noise, the excess
loading can negatively impact the amplifier
linearity. Filtering in the feedback path does not
have this effect.
• AC-coupling allows easier circuit design. If dccoupling is required, be aware of the excess
power dissipation that can occur due to levelshifting the output through the output commonmode voltage control.
• Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop
fully differential amplifiers drive a specific output
24
•
•
•
•
•
voltage regardless of the load impedance present.
Terminating the output of a fully differential
amplifier with a heavy load adversely affects the
amplifier linearity.
Comprehend the VOCM input drive requirements.
Determine if the ADC voltage reference can
provide the required amount of current to move
VOCM to the desired value. A buffer may be
needed.
Decouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can
act as an antenna. A large decoupling capacitor
on this node eliminates this problem.
Know the input common-mode range. If the input
signal is referenced around the negative powersupply rail (for example, around ground on a
single 5 V supply), then the THS4500/1
accommodates the input signal. If the input signal
is referenced around midrail, choose the
THS4502/3 for the best operation.
Packaging makes a difference at higher
frequencies. If possible, choose the smaller,
thermally-enhanced MSOP package for the best
performance. As a rule, lower junction
temperatures provide better performance. If
possible, use a thermally-enhanced package,
even if the power dissipation is relatively small
compared to the maximum power dissipation
rating to achieve the best results.
Understand the effect of the load impedance seen
by the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level
of intermodulation distortion performance.
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at
the output of the data converter. Two representative
circuits shown below highlight single-supply operation
and split supply operation, respectively. Specific
feedback resistor, gain resistor, and feedback
capacitor values are not shown, as these values
depend on the frequency of interest. Information on
calculating these values can be found in the
applications material above.
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CF
RS
VS
RG
CG
RS
RF
RF
15 V
RT
VS
5V
RT
RG
RISO
+
VOCM
1 mF
+
VOCM
+
-
0.1 mF
THS4503
RISO
RISO
-
0.1 mF
IN ADS5410
12-Bit/80 MSPS
IN
CM
RL
+
RISO
RF
RG
CS
VDD
THS4500/2
5V
10 mF
-
CS
VOD = 26 VPP
CG
5 V
RG
10 mF 0.1 mF
0.1 mF
RF
Figure 105. Fully Differential Line Driver With
High Output Swing
CF
Figure 103. Using the THS4503 With the ADS5410
CF
RS
VS
RG
RF
5V
RT
5V
10 mF
1 mF
0.1 mF
+
VOCM
+
-
RISO
IN ADS5421
14-Bit/40 MSPS
IN
CM
THS4501
RISO
RG
RF
CF
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
Similar to single-ended counterparts, fully differential
amplifiers have the ability to couple filtering
functionality with voltage gain. Numerous filter
topologies can be based on fully differential
amplifiers. Several of these are outlined in the
application report A Differential Circuit Collection
(literature number SLOA064), referenced at the end
of this data sheet. The circuit below depicts a simple,
two-pole, low-pass filter applicable to many different
types of systems. The first pole is set by the resistors
and capacitors in the feedback paths, and the second
pole is set by the isolation resistors and the capacitor
across the outputs of the isolation resistors.
0.1 mF
CF1
Figure 104. Using the THS4501 With the ADS5421
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers.
The high power-supply voltage rating (16.5 V
absolute maximum) allows operation on a single 12-V
or a single 15-V supply. The high supply voltage,
coupled with the ability to provide differential outputs,
enables the ability to drive 26 VPP into reasonably
heavy loads (250 Ω or greater). The circuit in
Figure 105 illustrates the THS4500 family of devices
used as high-speed line drivers. For line driver
applications, close attention must be paid to thermal
design constraints because of the typically high level
of power dissipation.
RG1
RS
VS
RF1
RISO
RT
+
-
-
C
VO
+
RG2
RISO
RF2
CF2
Figure 106. A Two-Pole, Low-Pass Filter Design
Using a Fully Differential Amplifier With Poles
Located at: P1 = (2πRFCF)–1 in Hz and
P2 = (4πRISOC)–1 in Hz
Often, filters like these are used to eliminate
broadband noise and out-of-band distortion products
in signal acquisition systems. It should be noted that
the increased load placed on the output of the
amplifier by the second low-pass filter has a
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detrimental effect on the distortion performance. The
preferred method of filtering is to use the feedback
network, as the typically smaller capacitances
required at these points in the circuit do not load the
amplifier nearly as heavily in the passband.
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
The output common-mode voltage pin provides a
critical function to the fully differential amplifier; it
accepts an input voltage and reproduces that input
voltage as the output common-mode voltage. In other
words, the VOCM input provides the ability to level-shift
the outputs to any voltage inside the output voltage
swing of the amplifier.
A description of the input circuitry of the VOCM pin is
shown in Figure 107 to facilitate an easier
understanding of the VOCM interface requirements.
The VOCM pin has two 50-kΩ resistors between the
power supply rails to set the default output commonmode voltage to midrail. A voltage applied to the
VOCM pin alters the output common-mode voltage as
long as the source has the ability to provide enough
current to overdrive the two 50-kΩ resistors. This
phenomenon is depicted in the VOCM equivalent
circuit diagram. Current drive is especially important
when using the reference voltage of an analog-todigital converter to drive VOCM. Output current drive
capabilities differ from part to part, so a voltage buffer
may be necessary in some applications.
frequency noise that could couple into the signal path
through the VOCM circuitry. A 0.1-μF or 1-μF
capacitance is a reasonable value for eliminating a
great deal of broadband interference, but additional,
tuned decoupling capacitors should be considered if a
specific source of electromagnetic or radio frequency
interference is present elsewhere in the system.
Information on the ac performance (bandwidth, slew
rate) of the VOCM circuitry is included in the
ELECTRICAL CHARACTERISTICS and TYPICAL
CHARACTERISTICS sections.
Since the VOCM pin provides the ability to set an
output common-mode voltage, the ability for
increased power dissipation exists. While this
possibility does not pose a performance problem for
the amplifier, it can cause additional power
dissipation of which the system designer should be
aware. The circuit shown in Figure 108 demonstrates
an example of this phenomenon. For a device
operating on a single 5-V supply with an input signal
referenced around ground and an output commonmode voltage of 2.5 V, a dc potential exists between
the outputs and the inputs of the device. The amplifier
sources current into the feedback network in order to
provide the circuit with the proper operating point.
While there are no serious effects on the circuit
performance, the extra power dissipation may need to
be included in the system power budget.
I1 =
VOCM
RF1+ RG1 + RS || RT
DC Current Path to Ground
VS+
RF1
RG1
RS
R = 50 kW
IIN =
VOCM
IIN
2 VOCM - V S+ - VSR
VS
5V
RT
VOCM = 2.5 V
R = 50 kW
+ -
RG2
26
RF2
2.5-V DC
DC Current Path to Ground
I2 =
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal.
As shown in Figure 107, the VOCM input has a high
impedance associated with it, dictated by the two 50kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and
any associated PCB traces to act as an antenna. For
this reason, a decoupling capacitor is recommended
on this node for the sole purpose of filtering any high-
RL
+
VS-
Figure 107. Equivalent Input Circuit for VOCM
2.5-V DC
VOCM
RF2 + RG2
Figure 108. Depiction of DC Power Dissipation
Caused By Output Level-Shifting in a DC-Coupled
Circuit
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The THS4500 family of fully differential amplifiers
contains devices that come with and without the
power-down option. Even-numbered devices have
power-down capability, which is described in detail
here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (that is, an internal pull-up resistor is present),
putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
enable threshold voltage, the device is on. Below the
disable threshold voltage, the device is off. Behavior
between these threshold voltages is not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The
THS4500
family
of
devices
features
unprecedented distortion performance for monolithic
fully differential amplifiers. This section focuses on
the fundamentals of distortion, circuit techniques for
reducing nonlinearity, and methods for equating
distortion of fully differential amplifiers to desired
linearity specifications in RF receiver chains.
Amplifiers are generally thought of as linear devices.
In other words, the output of an amplifier is a linearly
scaled version of the input signal applied to it. In
reality, however, amplifier transfer functions are
nonlinear. Minimizing amplifier nonlinearity is a
primary design goal in many applications.
Intercept points are specifications that have long
been used as key design criteria in the RF
communications world as a metric for the
intermodulation distortion performance of a device in
the signal chain (for example, amplifiers, mixers,
etc.). Use of the intercept point, rather than strictly the
intermodulation distortion, allows for simpler systemlevel calculations. Intercept points, like noise figures,
can be easily cascaded back and forth through a
signal chain to determine the overall receiver chain
intermodulation
distortion
performance.
The
relationship between intermodulation distortion and
intercept point is depicted in Figure 109 and
Figure 110.
PO
PO
∆fc = fc − f1
Power
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
∆fc = f2 − fc
IMD3 = PS − PO
PS
fc − 3∆f
PS
f1 fc
f2
fc + 3∆f
f − Frequency − MHz
Figure 109. 2-Tone and 3rd-Order
Intermodulation Products
POUT
(dBm)
1X
OIP3
PO
IMD3
IIP3
3X
PIN
(dBm)
PS
Figure 110. Graphical Representation of 2-Tone
and 3rd-Order Intercept Point
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Due to the intercept point ease-of-use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related
design decisions. Traditionally, these systems use
primarily class-A, single-ended RF amplifiers as gain
blocks. These RF amplifiers are typically designed to
operate in a 50-Ω environment, just like the rest of
the receiver chain. Since intercept points are given in
dBm, this implies an associated impedance (50 Ω).
However, with a fully differential amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to the outputs regardless of the impedance present, it
is important to comprehend this feature when
evaluating the intercept point of a fully differential
amplifier. The THS4500 series of devices yields
optimum distortion performance when loaded with
200 Ω to 1 kΩ, very similar to the input impedance of
an analog-to-digital converter over its input frequency
band. As a result, terminating the input of the ADC to
50 Ω can actually be detrimental to system
performance.
This discontinuity between open-loop, class-A
amplifiers and closed-loop, class-AB amplifiers
becomes apparent when comparing the intercept
points of the two types of devices. Equation 10 gives
the definition of an intercept point, relative to the
intermodulation distortion.
ŤIMD 3Ť
OIP 3 + P O )
where
2
(10)
ǒ
ǒ
P O + 10 log
Ǔ
Ǔ
V 2Pdiff
2RL 0.001
NOTE: Po is the output power of a single tone, RL is the
differential load resistance, and VP(diff) is the differential
peak voltage for a single tone.
(11)
As can be seen in the equations, when a higher
impedance is used, the same level of intermodulation
distortion performance results in a lower intercept
point. Therefore, it is important to understand the
impedance seen by the output of the fully differential
amplifier when selecting a minimum intercept point.
Figure 111 shows the relationship between the strict
definition of an intercept point with a normalized, or
equivalent, intercept point for the THS4500.
28
OIP 3 − Third-Order Output Intercept Point − dBm
SLOS832 – JUNE 2013
60
Normalized to 200 Ω
55
Normalized to 50 Ω
50
45
40
35
OIP3 RL= 800 Ω
30
Gain = 1
Rf = 392 Ω
VS = ± 5 V
Tone Spacing = 200 kHz
25
20
15
0
10 20 30 40 50 60 70 80 90 100
f − Frequency − MHz
Figure 111. Equivalent 3rd-Order Intercept Point
for the THS4500
Comparing specifications between different device
types becomes easier when a common impedance
level is assumed. For this reason, the intercept points
on the THS4500 family of devices are reported
normalized to a 50-Ω load impedance.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is
analogous to noise analysis in single-ended
amplifiers; the same concepts apply. Figure 112
shows a generic circuit diagram consisting of a
voltage source, a termination resistor, two gain
setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the
relevant noise sources. From this circuit, the noise
factor (F) and noise figure (NF) are calculated. The
figures indicate the appropriate scaling factor for each
of the noise sources in two different cases. The first
case includes the termination resistor, and the
second, simplified case assumes that the voltage
source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier
input noise power (NA) can be calculated by summing
each individual noise source with its scaling factor.
The noise delivered to the amplifier by the source (NI)
and input noise power are used to calculate the noise
factor and noise figure as shown in Equation 23
through Equation 27.
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Ni
eg
NA
Rg
Rf
Si
ef
Scaling Factors for Individual Noise Sources
Asseming No Termination Resistance is Used
(that is, RT is Open)
en
Ni
No
Rs
+
Rt
So
fully-diff
amp
−
ini
es
NA: Fully Differential Amplifier; termination = 2Rg
Noise
Source
No
et
eg
(ini)2
Rg
Rf
ef
ȡR )
ȧR R
Ȣ
(iii)2
f
s
2
(18)
(19)
Rg2
(20)
ǒ Ǔ
Rg
Rf
2
Figure 112. Noise Sources in a Fully Differential
Amplifier Circuit
2
(21)
2
ȡ R ȣ
ȧR ) R ȧ
Ȣ 2Ȥ
g
2
4kTRg
NA: Fully Differential Amplifier
Noise
Source Scale Factor
g
Rg2
4kTRf
Scaling Factors for Individual Noise Sources
Assuming a Finite Value Termination Resistor
2
ȣ
Rȧ
) Ȥ
Rg
g
(eni)2
iii
Scale Factor
s
g
(22)
Input Noise With a Termination Resistor
2
(12)
ȡ 2R R ȣ
ȧ R )2R ȧ
N + 4kTR ȧ
R ȧ
ȧ
ȧR )R2R)2R
Ȥ
Ȣ
(ini)2
Rg2
(13)
Input Noise Assuming No Termination Resistor
(iii)2
Rg2
(14)
4kTRt
R
ȣ
ȡ R2R)2R
ȧR ) 2R R ȧ
Ȣ R )2R Ȥ
Ni = 4kTRS
ȡR
ȧR ) R
Ȣ
g
(eni)2
f
t
2
ȣ
ȧ
Ȥ
Rg
R sR t
g) ǒ
2 Rs)R tǓ
i
2
4kTRf
4kTRg
g
s
t
2
s
ǒ Ǔ
Rg
Rf
ȡ
ȧR
Ȣ
t
t
G
s
g
t
s
s
2
s
g
g
g
(15)
2
(16)
2
ȣ
ȧ
Ȥ
g
g
(23)
2
2RG
RS + 2RG
Noise Factor and Noise Figure Calculations
NA = S(Noise Source ´ Scale Factor)
NA
F=1+
NI
NF + 10 log (F)
(24)
(25)
(26)
(27)
Rg
R sR t
g)
2ǒR s)RtǓ
(17)
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PRINTED CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to PCB layout parasitic and external
component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance (< 0.25”, 6.35 mm) from the
power-supply pins to high frequency 0.1-μF
decoupling capacitors. At the device pins, the
ground and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 μF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PCB. The primary goal is to
minimize the impedance seen in the differentialcurrent return paths.
• Careful selection and placement of external
components
preserve
the
high-frequency
performance of the THS4500 family. Resistors
should be a very low reactance type. Surfacemount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good
high frequency performance. Again, keep the
leads and PCB trace length as short as possible.
Never use wirewound type resistors in a highfrequency application. Since the output pin and
inverting input pins are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed close
to the gain-setting resistors. Even with a low
parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance. Good axial metal-film or surfacemount resistors have approximately 0.2 pF in
shunt with the resistor. For resistor values greater
than 2.0 kΩ, this parasitic capacitance can add a
30
•
•
•
•
pole and/or a zero below 400 MHz that can affect
circuit operation. Keep resistor values as low as
possible,
consistent
with
load
driving
considerations.
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils, or 1.27
mm to 2.54 mm) should be used, preferably with
ground and power planes opened up around
them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are
necessary. Low parasitic capacitive loads (less
than 4 pF) may not need an RS since the
THS4500 family is nominally compensated to
operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded
phase margin). If a long trace is required, and the
6-dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout
techniques).
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance
environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined based onboard
material and trace dimensions, a matching series
resistor into the trace from the output of the
THS4500 family is used as well as a terminating
shunt resistor at the input of the destination
device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device: this
total effective impedance should be set to match
the trace impedance. If the 6-dB attenuation of a
doubly-terminated
transmission
line
is
unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace
as a capacitive load in this case. This
configuration does not preserve signal integrity as
well as a doubly-terminated line. If the input
impedance of the destination device is low, there
is some signal attenuation due to the voltage
divider formed by the series output into the
terminating impedance.
Socketing a high-speed part such as the THS4500
family is not recommended. The additional lead
length and pin-to-pin capacitance introduced by
the socket can create an extremely troublesome
parasitic network that can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
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the THS4500 family parts directly onto the board.
0.205
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in a thermallyenhanced PowerPAD set of packages. These
packages are constructed using a downset leadframe
upon which the die is mounted [see Figure 113(a)
and Figure 113(b)]. This arrangement results in the
lead frame being exposed as a thermal pad on the
underside of the package [see Figure 113(c)].
Because this thermal pad has direct thermal contact
with the die, excellent thermal performance can be
achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 113. Views of PowerPAD, ThermallyEnhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 114. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as
shown in Figure 114. There should be etch for
the leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 13 mils (0.33 mm) in
diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These holes help dissipate the heat
generated by the THS4500 family IC. These
additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad.
They can be larger because they are not in the
thermal pad area to be soldered so that wicking
is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This transfer slowing makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete
connection
around
the
entire
circumference of the plated-through hole.
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POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute
maximum junction temperature of +150°C is
exceeded. For best performance, design for a
maximum junction temperature of +125°C. Between
+125°C and +150°C, damage does not occur, but the
performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated
by the package and the PCB. Maximum power
dissipation for a given package can be calculated
using the following formula.
TMAX - TA
PDmax =
qJA
Where:
PDmax is the maximum power dissipation in the
amplifier (W).
TMAX is the absolute maximum junction
temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
ambient air (°C/W).
(28)
For systems where heat dissipation is more critical,
the THS4500 family of devices is offered in an
MSOP-8 package with PowerPAD. The thermal
coefficient for the MSOP PowerPAD package is
substantially improved over the traditional SOIC.
32
Maximum power dissipation levels are depicted in
Figure 115 for the two packages. The data for the
DGN package assumes a board layout that follows
the PowerPAD layout guidelines referenced above
and detailed in the PowerPAD application notes in
the Additional Reference Material section at the end
of the data sheet.
3.5
PD − Maximum Power Dissipation − W
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard surfacemount component. This process results in a part
that is properly installed.
8-Pin DGN Package
3
2.5
2
8-Pin D Package
1.5
1
0.5
0
−40
−20
0
20
40
60
TA − Ambient Temperature − °C
80
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
Figure 115. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this consideration is difficult to quantify
because the signal pattern is inconsistent; an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however,
the load capacitance should be isolated by two
isolation resistors in series with the output. The
requisite isolation resistor size depends on the value
of the capacitance, but 10 Ω to 25 Ω is a good place
to begin the optimization process. Larger isolation
resistors decrease the amount of peaking in the
frequency response induced by the capacitive load,
but this decreased peaking comes at the expense ofa
larger voltage drop across the resistors, increasing
the output swing requirements of the system.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: THS4500-EP
THS4500-EP
www.ti.com
SLOS832 – JUNE 2013
RF
VS
RG
RS
RISO
+
VS
RT
-
-
CL
+
RISO
-VS
obtained by ordering through the THS4500 or
THS4501 product folder on the Texas Instruments
web site, www.ti.com, or through your local Texas
Instruments sales representative. A schematic for the
evaluation board is shown in Figure 117 with the
default component values. Unpopulated footprints are
shown to provide insight into design flexibility.
Riso = 10 - 25 W
C4
RF
C0805
R4
RG
R0805
VS
J1
C1
Figure 116. Use of Isolation Resistors With a
Capacitive Load
R1
C0805
C2
R1206
C0805
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, an evaluation board
has been developed for the THS4500 family of fully
differential amplifiers. The evaluation board can be
1
R0805
R0805
R3
8
+
2
5
6
VOCM
POWER-SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of
performance.
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along
power-supply return current paths.
4. Recommended
values
for
power-supply
decoupling include 10-μF and 0.1-μF capacitors
for each supply. A 1000-pF capacitor can be
used across the supplies as well for extremely
high frequency return currents, but often is not
required.
R2
PD
U1
THS450X
R6
4
7
R0805
3
_
PwrPad
C5
C0805
C7
C0805
R0805
R7
J2
J2
J3
J3
C6
C0805
-V S
R5 R0805
C3
C0805
J2
R8
R0805
J3
R9
R0805
R0805
R9
J4
4
3
5
R11
R1206
6
1
T1
Figure 117. Simplified Schematic of the
Evaluation Board
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
practice is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the THS4500 family of devices is
available through either the Texas Instruments web
site (www.ti.com) or as one model on a disk from the
Texas Instruments Product Information Center (1800-548-6132). The PIC is also available for design
assistance and detailed product information at this
number. These models do a good job of predicting
small-signal ac and transient performance under a
wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between
the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: THS4500-EP
33
THS4500-EP
SLOS832 – JUNE 2013
www.ti.com
ADDITIONAL REFERENCE MATERIAL
•
•
•
•
•
•
•
34
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
PowerPAD Thermally-Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
Karki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number
SLOA054D.
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and
Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature
Number SLOA064.
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments
Literature Number SLOA072.
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog
Applications Journal, July 2001.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: THS4500-EP
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4500MDGNEP
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SJE
THS4500MDGNREP
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SJE
V62/13610-01XE
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SJE
V62/13610-01XE-T
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SJE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4500-EP :
• Catalog: THS4500
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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