Texas Instruments | Dual Micropower LinCMOS Voltage Comparator (Rev. B) | Datasheet | Texas Instruments Dual Micropower LinCMOS Voltage Comparator (Rev. B) Datasheet

Texas Instruments Dual Micropower LinCMOS Voltage Comparator (Rev. B) Datasheet
TLC393-Q1
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SGLS198B – SEPTEMBER 2004 – REVISED MAY 2013
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATOR
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FEATURES
APPLICATIONS
•
•
•
1
Qualified for Automotive Applications
AEC Q100 Qualified with the Following
Results:
– Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
ESD Protection Exceeds 500 V Per
MIL-STD-883, Method 3015; Exceeds 50 V
Using Machine Model (C = 200 pF, R = 0)
Low Power: 110 µW Typ at 5 V
Fast Response Time: tPLH = 2.5 µs Typ With 5mV Overdrive
Single Supply Operation:
– TLC393Q: 4 V to 16 V
2
•
•
•
•
Automotive Applications
D PACKAGE
(TOP VIEW)
1OUT
1IN í
1IN +
GND
1
8
2
3
4
7
6
5
VDD
2OUT
2IN í
2IN +
symbol (each comparator)
IN +
OUT
IN í
DESCRIPTION
The TLC393 consists of dual independent micropower voltage comparators designed to operate from a single
supply. It is functionally similar to the LM393 but uses one-twentieth the power for similar response times. The
open-drain MOS output stage interfaces to a variety of loads and supplies. For a similar device with a push-pull
output configuration see the TLC3702 data sheet.
Texas Instruments LinCMOS™ process offers superior analog performance to standard CMOS processes. Along
with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and low bias
currents, the LinCMOS™ process offers extremely stable input offset voltages, even with differential input
stresses of several volts. This characteristic makes it possible to build reliable CMOS comparators.
The TLC393Q is characterized for operation over the full automotive temperature range of TA = −40°C to 125°C
ORDERING INFORMATION (1)
TA
VIOmax
AT 25°C
−40°C to 125°C
5 mV
(1)
(2)
PACKAGE (2)
SOIC (D)
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
TLC393QDRQ1
C393Q1
Tape and reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Schematic
OUT
1
2
OPEN-DRAIN CMOS OUTPUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
Supply voltage range, VDD (2)
UNIT
MAX
–0.3
Differential input voltage, VID (3)
18
V
±18
V
V
Input voltage range, VI
–0.3
VDD
Output voltage range, VO
–0.3
16
V
Input current, II
±5
mA
Output current, IO
20
mA
Total supply current into VDD
40
mA
Total current out of GND
40
mA
D Package
126
°C/W
PW Package
149
°C/W
2
kV
750
V
Package thermal impedance, θJA
(4) (5)
,
)
Electrostatic discharge (ESD)
Human Body Model (HBM) AEC-Q100
Classification Level H2
Charge Device Model (CDM) AEC-Q100
Classification Level C4B
Operating free-air temperature range
–40
125
°C
Storage temperature range
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground.
Differential voltages are at IN+ with respect to IN −
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply voltage, VDD
4
5
16
Common-mode input voltage, VIC
0
Low-level output current, IOL
Operating free-air temperature, TA
2
–40
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VDD - 1.5
UNIT
V
V
20
mA
125
°C
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ELECTRICAL CHARACTERISTICS
at specified operating free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1)
VIO
Input offset voltage
VIC = VICRmin,
VDD = 5 V to 10 V,
See (2)
IIO
Input offset current
VIC = 2.5 V
IIB
Input bias current
VICR
Common-mode input voltage
range
CMMR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
MIN
25°C
TYP
1.4
–40°C to 125°C
5
125°C
25°C
–40°C to 125°C
VIC = VICRmin
VDD = 5 V to 10 V
Low-level output voltage
VID = −1 V, IOL = 6 mA
IOH
High-level output current
VID = 1 V, VO = 5 V
IDD
Supply current (both
comparators)
Outputs low, No load
0 to VDD − 1
nA
V
0 to VDD − 1.5
25°C
84
125°C
84
–40°C
84
25°C
85
125°C
84
–40°C
84
25°C
300
125°C
dB
dB
400
800
0.8
125°C
25°C
nA
pA
30
25°C
mV
pA
15
25°C
UNIT
5
1
125°C
VIC = 2.5 V
MAX
10
25°C
VOL
(1)
(2)
TA
22
–40°C to 125°C
mV
40
nA
1
∞A
40
90
∞A
All characteristics are measured with zero common-mode voltage unless otherwise noted.
The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V (with a 2.5-kM load to
VDD).
SWITCHING CHARACTERISTICS
VDD = 5 V, TA = 25°C (see Figure 3)
PARAMETER
tPLH
Propagation delay time, low-tohigh level output
TEST CONDITIONS
f = 10 kHz,
CL = 15 pF
Propagation delay time, high-tolow level output
f = 10 kHz,
CL = 15 pF
Overdrive = 5 mV
2.5
Overdrive = 10 mV
1.7
Overdrive = 20 mV
1.2
Overdrive = 40 mV
1.1
Fall time, output
f = 10 kHz,
CL = 15 pF
MAX
UNIT
∞s
1.1
Overdrive = 2 mV
3.6
Overdrive = 5 mV
2.1
Overdrive = 10 mV
1.3
Overdrive = 20 mV
0.85
Overdrive = 40 mV
0.55
VI = 1.4-V step at IN +
tf
TYP
4.5
VI = 1.4-V step at IN +
tPHL
MIN
Overdrive = 2 mV
∞s
0.1
Overdrive = 50 mV
22
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PARAMETER MEASUREMENT INFORMATION
The TLC393 contains a digital output stage which, if held in the linear region of the transfer curve, can cause
damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo loop
that is designed to force the device output to a level within this linear region. Since the servo-loop method of
testing cannot be used, the following alternatives for testing parameters such as input offset voltage, commonmode rejection ratio, etc., are suggested.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as
shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be
high. With the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages
can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide
greater accuracy.
5V
+
Applied VIO
1V
5.1 kΩ
−
Limit
Applied VIO
VO
5.1 kΩ
+
−
Limit
VO
−4V
(a) VIO WITH VIC = 0 V
(b) VIO WITH VIC = 4 V
Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal,
but opposite in polarity, to the input offset voltage, the output changes states.
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1A generates a
triangular waveform of approximately 20-mV amplitude. U1B acts as a buffer, with C2 and R4 removing any
residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the
noninverting input is driven by the output of the integrator formed by U1C through the voltage divider formed by
R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty
cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the
voltage at the noninverting input exactly equals the input offset voltage.
The voltage divider formed by R9 and R10 provides an increase in input offset voltage by a factor of 100 to make
measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading;
therefore, it is suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current
and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board
leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be
subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the
device.
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PARAMETER MEASUREMENT INFORMATION (continued)
VDD
U1B
1/4 TLC274CN
+
Buffer
C2
1 µF
R6
5.1 kΩ
−
−
C3
0.68 µF
R5
1.8 kΩ, 1%
U1C
1/4 TLC274CN
DUT
R4
47 kΩ
−
R7
1 MΩ
+
VIO
(X100)
R1
240 kΩ
−
+
Integrator
R8
1.8 kΩ, 1%
U1A
1/4 TLC274CN
C4
0.1 µF
C1
0.1 µF
+
Triangle
Generator
R10
100 Ω, 1%
R3
100 Ω
R9
10 kΩ, 1%
R2
10 kΩ
Figure 2. Circuit for Input Offset Voltage Measurement
Propagation delay time is defined as the interval between the application of an input step function and the instant
when the output reaches 50% of its maximum value. Propagation delay time, low-to-high level output, is
measured from the leading edge of the input pulse, while propagation delay time, high-to-low level output, is
measured from the trailing edge of the input pulse. Propagation delay time measurement at low input signal
levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the
adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then a
low signal, for example, 105 mV or 5 mV overdrive, causes the output to change state.
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PARAMETER MEASUREMENT INFORMATION (continued)
VDD
1 µF
5.1 kΩ
Pulse
Generator
50 Ω
1V
Input Offset Voltage
Compensation
Adjustment
DUT
CL
10 Ω
10 Turn
(see Note A)
1 kΩ
−1V
0.1 µF
TEST CIRCUIT
Overdrive
Overdrive
Input
Low-to-HighLevel Output
Input
100 mV
100 mV
90%
90%
High-to-LowLevel Output
50%
10%
50%
10%
tr
tPLH
tf
tPHL
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
Figure 3. Propagation Delay, Rise Time, and Fall Time Circuit and Voltage Waveforms
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Table 1. Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
Figure 4
IIB
Input bias current
vs Free-air temperature
Figure 5
CMRR
Common-mode rejection ratio
vs Free-air temperature
Figure 6
kSVR
Supply-voltage rejection ratio
vs Free-air temperature
Figure 7
vs Low-level output current
Figure 8
VOL
Low-level output voltage
vs Free-air temperature
Figure 9
vs High-level output voltage
Figure 10
vs Free-air temperature
Figure 11
vs Supply voltage
Figure 12
vs Free-air temperature
Figure 13
IOH
Low-level output current
IDD
Supply current
tPLH
Low-to-high level output propagation delay time
vs Supply voltage
Figure 14
tPHL
High-to-low level output propagation delay time
vs Supply voltage
Figure 15
Low-to-high-level output response
Low-to-high level output propagation delay time
Figure 16
High-to-low level output response
High-to-low level output propagation delay time
Figure 17
Fall time
vs Supply voltage
Figure 18
tf
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TYPICAL CHARACTERISTICS
Data at high and low temperatures are applicable only within the reated operating free-air temperature ranges of the various
devices.
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
DISTRIBUTION OF INPUT
OFFSET VOLTAGE
100
Number of Units
80
VDD = 5 V
VIC = 2.5 V
IIB − Input Bias Current − nA
90
10
VDD = 5 V
VIC = 2.5 V
TA = 25°C
70
60
50
40
30
1
0.1
0.01
20
10
0
−5
0.001
−4
−3
−2
−1
0
1
2
3
4
5
25
50
VIO − Input Offset Voltage − mV
Figure 4.
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
90
kSVR − Supply Voltage Rejection Ratio − dB
90
89
VDD = 5 V
CMRR − Common-Mode
Rejection Ratio − dB
88
87
86
85
84
83
82
81
80
− 75
− 50
− 25
0
25
50
75
100
125
89
100
125
SUPPLY VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
VDD = 5 V to 10 V
88
87
86
85
84
83
82
81
80
− 75
TA − Free-Air Temperature − °C
Figure 6.
8
75
TA − Free-Air Temperature − °C
Figure 5.
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−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
Data at high and low temperatures are applicable only within the reated operating free-air temperature ranges of the various
devices.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
600
TA = 25°C
4V
VOL − Low-Level Output Voltage − mV
VOL − Low-Level Output Voltage − V
1.5
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
1.25
VDD = 3 V
1
5V
0.75
10 V
0.5
0.25
VDD = 16 V
2
4
6
8
10
12
14
16
18
500
400
300
200
100
0
− 75
0
0
VDD = 5 V
IOL = 6 mA
20
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
25
50
75
100
125
HIGH-LEVEL OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
1000
I OH − High-Level Output Current − nA
I OH − High-Level Output Current − nA
−25
TA − Free-Air Temperature − °C
Figure 9.
IOL − Low-Level Output Current − mA
Figure 8.
1000
−50
TA = 125°C
100
TA = 85°C
TA = 70°C
10
TA = 25°C
1
VDD = VOH = 5 V
100
10
1
VOH = VDD
0.1
0
2
4
6
8
10
12
14
16
0.1
25
VOH − High-Level Output Voltage − V
Figure 10.
50
75
100
TA − Free-Air Temperature − °C
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
Data at high and low temperatures are applicable only within the reated operating free-air temperature ranges of the various
devices.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
50
40
Outputs Low
No Loads
45
VDD = 5 V
No Load
TA = − 55°C
35
TA = − 40°C
40
IDD − Supply Current −µA
I DD − Supply Current − µ A
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
35
TA = 25°C
30
25
TA = 85°C
20
TA = 125°C
15
30
25
Outputs Low
20
15
10
10
0
Outputs High
5
5
0
2
4
6
8
10
12
14
0
− 75
16
−50
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 13.
VDD − Supply Voltage − V
Figure 12.
LOW-TO-HIGH-LEVEL OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
6
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
5 TA = 25°C
t PHL − High-to-Low Level
Output Propagation Delay Time − µs
t PLH − Low-to-High-Level
Output Propagation Delay Time − µs
− 25
Overdrive = 2 mV
4
5 mV
3
10 mV
2
20 mV
40 mV
1
HIGH-TO-LOW-LEVEL OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
5
CL = 15 pF
4.5 RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
4
3.5
Overdrive = 2 mV
3
2.5
5 mV
2
1.5
10 mV
1
20 mV
0.5
40 mV
0
0
2
4
6
8
10
12
14
16
0
0
VDD − Supply Voltage − V
Figure 14.
10
2
4
6
8
10
12
14
16
VDD − Supply Voltage − V
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
Data at high and low temperatures are applicable only within the reated operating free-air temperature ranges of the various
devices.
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS INPUT OVERDRIVES
5
VO − Output
Voltage − V
40 mV
20 mV
10 mV
5 mV
2 mV
40 mV
20 mV
10 mV
5 mV
2 mV
0
0
100
100
Differential Input
Voltage − mV
Differential Input
Voltage − mV
VO − Output
Voltage − V
5
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS INPUT OVERDRIVES
VDD = 5 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
0
0
1
2
3
4
VDD = 5 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
0
0
5
1
2
3
4
5
tPHL − High-to-Low-Level Output
Propagation Delay Time − µs
Figure 17.
tPLH − Low-to-High-Level Output
Propagation Delay Time − µs
Figure 16.
OUTPUT FALL TIME
vs
SUPPLY VOLTAGE
60
50
CL = 100 pF
t f − Fall Time −ns
40
50 pF
30
15 pF
20
50-mV Overdrive
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
10
0
0
2
4
6
8
10
12
14
16
VDD − Supply Voltage − V
Figure 18.
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APPLICATION INFORMATION
The input should always remain within the supply rails in order to avoid forward biasing the diodes in the
electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device will not be
damaged as long as the input current is limited to less than 5 mA. To maintain the expected output state, the
inputs must remain within the common-mode range. For example, at 25°C with VDD = 5 V, both inputs must
remain between −0.2 V and 4 V to assure proper device operation.
To assure reliable operation, the supply should be decoupled with a capacitor (0.1-µF) positioned as close to the
device as possible.
The TLC393 has internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as
tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices, as
exposure to ESD may result in the degradation of the device parametric performance.
Table 2. Table of Applications
FIGURE
Pulse-Width-Modulated Motor Speed Controller
Figure 19
Enhanced Supply Supervisor
Figure 20
Two-Phase Nonoverlapping Clock Generator
Figure 21
12 V
12 V
SN75603
Half-H Driver
DIR
5V
EN
C2
(see Note A)
5.1 kΩ
+
5.1 kΩ
100 kΩ
+
10 kΩ
−
5V
10 kΩ
1/2 TLC393
C1
0.01 µF
(see Note B)
Motor
−
1/2 TLC393
12 V
DIR
SN75604
Half-H Driver
10 kΩ
5V
10 kΩ
Motor Speed Control
Potentiometer
EN
5V
Direction
Control
S1
SPDT
A.
The recommended minimum capacitance is 10 µF to eliminate common ground switching noise.
B.
Adjust C1 for change in oscillator frequency.
Figure 19. Pulse-Width-Modulated Motor Speed Controller
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5V
12 V
VCC
12-V
Sense
3.3 kΩ
RESIN
−
5V
10 kΩ
5.1 kΩ
+
1 kΩ
SENSE
TL7705A
RESET
To µP
Reset
1/2 TLC393
REF
CT
GND
2.5 V
12 V
1 µF
CT
(see Note B)
5.1 kΩ
+
VUNREG
(see Note A)
To µP Interrupt
Early Power Fail
R1
−
1/2 TLC393
R2
Monitors 5-VDC Rail
Monitors 12-VDC Rail
Early Power Fail Warning
A.
B.
VUNREG = 2.5
(R1 + R2)
R2
The value of CT determines the time delay of reset.
Figure 20. Enhanced Supply Supervisor
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC393-Q1
13
TLC393-Q1
SGLS198B – SEPTEMBER 2004 – REVISED MAY 2013
www.ti.com
12 V
12 V
R1
100 Ω
(see Note B)
5.1 kΩ
−
12 V
5.1 kΩ
−
1OUT
R2
5 kΩ
(see Note C)
+
1/2 TLC393
12 V
100 kΩ
+
1/2 TLC393
100 kΩ
22 kΩ
5.1 kΩ
C1
0.01 µF
(see Note A)
−
2OUT
100 kΩ
+
1/2 TLC393
R3
100 kΩ
(see Note B)
12 V
1OUT
2OUT
A.
Adjust
C1
1/f = 1.85(100 kΩ)C1
for
a
B.
Adjust R1 and R3 to change duty cycle
C.
Adjust R2 to change deadtime
change
in
oscillator
frequency
where:
Figure 21. Two-Phase Nonoverlapping Clock Generator
14
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC393-Q1
TLC393-Q1
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SGLS198B – SEPTEMBER 2004 – REVISED MAY 2013
REVISION HISTORY
Changes from Original (September 2004) to Revision A
Page
•
Deleted Feature: Qualified in Accordance With AEC-Q100 ................................................................................................. 1
•
Deleted Feature: Customer-Specific Configuration Control... ............................................................................................... 1
Changes from Revision A (April 2008) to Revision B
Page
•
Added Feature: AEC Q100 Qualified with the Following Results: ........................................................................................ 1
•
Deleted the TSSOP (PW) Package from the Ordering Information table ............................................................................. 1
•
Added Electrostatic discharge (ESD) to the Absolute Maximum table ................................................................................. 2
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Product Folder Links: TLC393-Q1
15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLC393QDRG4Q1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C393Q1
TLC393QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C393Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
OTHER QUALIFIED VERSIONS OF TLC393-Q1 :
• Catalog: TLC393
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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