Texas Instruments | LMH6505 Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier (Rev. E) | Datasheet | Texas Instruments LMH6505 Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier (Rev. E) Datasheet

Texas Instruments LMH6505 Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier (Rev. E) Datasheet
LMH6505
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SNOSAT4E – DECEMBER 2005 – REVISED APRIL 2013
LMH6505 Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier
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VS = ±5V, TA = 25°C, RF = 1 kΩ, RG = 100Ω, RL =
100Ω, AV = AVMAX = 9.4 V/V, Typical Values
Unless Specified.
−3 dB BW 150 MHz
Gain Control BW 100 MHz
Adjustment Range (<10 MHz) 80 dB
Gain Matching (Limit) ±0.50 dB
Supply Voltage Range 7V to 12V
Slew Rate (Inverting) 1500 V/μs
Supply Current (No Load) 11 mA
Linear Output Current ±60 mA
Output Voltage Swing ±2.4V
Input Noise Voltage 4.4 nV/√Hz
Input Noise Current 2.6 pA/√Hz
THD (20 MHz, RL = 100Ω, VO = 2 VPP) −45 dBc
Near ideal input characteristics (i.e. low input bias
current, low offset, low pin 3 resistance) enable the
device to be easily configured as an inverting
amplifier as well.
To provide ease of use when working with a single
supply, the VG range is set to be from 0V to +2V
relative to the ground pin potential (pin 4). VG input
impedance is high in order to ease drive requirement.
In single supply operation, the ground pin is tied to a
"virtual" half supply.
The LMH6505’s gain control is linear in dB for a large
portion of the total gain control range from 0 dB down
to −85 dB at 25°C, as shown below. This makes the
device suitable for AGC applications. For linear gain
control applications, see the LMH6503 datasheet.
The LMH6505 is available in either the 8-Pin SOIC or
the 8-Pin VSSOP package. The combination of
minimal external components and small outline
packages allows the LMH6505 to be used in spaceconstrained applications.
APPLICATIONS
Variable Attenuator
AGC
Voltage Controlled Filter
Video Imaging Processing
DESCRIPTION
The LMH6505 is a wideband DC coupled voltage
controlled gain stage followed by a high speed
current feedback operational amplifier which can
directly drive a low impedance load. The gain
adjustment range is 80 dB for up to 10 MHz which is
accomplished by varying the gain control input
voltage, VG.
Maximum gain is set by external components, and
the gain can be reduced all the way to cutoff. Power
consumption is 110 mW with a speed of 150 MHz
and a gain control bandwidth (BW) of 100 MHz.
Output referred DC offset voltage is less than 55 mV
over the entire gain control voltage range. Device-todevice gain matching is within ±0.5 dB at maximum
gain. Furthermore, gain is tested and ensured over a
wide range. The output current feedback op amp
allows high frequency large signals (Slew Rate =
1500 V/μs) and can also drive a heavy load current
(60 mA) ensured.
12
11
10
10
9
125°C
-10
8
25°C
-30
125°C
-50
7
-55°C
dB
6
5
V/V
4
25°C
3
-55°C
2
-70
1
-90
-0.5
0
0
0.5
1
1.5
2
VG (V)
Figure 1. Gain vs. VG
Typical Application
VG
1
VIN
2
V
+
8
6
3
7
RG
100:
4
5
V
-
RF
1 k:
RL
100:
Figure 2. AVMAX = 9.4 V/V
1
2
30
GAIN (dB)
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GAIN (V/V)
FEATURES
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
(3)
ESD Tolerance
Human Body Model
2000V
Machine Model
200V
Input Current
Output Current
±10 mA
(4)
120 mA
Supply Voltages (V+ - V−)
12.6V
+
−
Voltage at Input/ Output pins
V +0.8V, V −0.8V
Storage Temperature Range
−65°C to 150°C
Junction Temperature
150°C
Soldering Information:
(1)
(2)
(3)
(4)
Infrared or Convection (20 sec)
235°C
Wave Soldering (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower.
Operating Ratings (1)
Supply Voltages (V+ - V−)
Temperature Range
Thermal Resistance:
(1)
(2)
2
7V to 12V
(2)
−40°C to +85°C
(θJC)
(θJA)
8 -Pin SOIC
60
165
8-Pin VSSOP
65
235
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TJ = 25°C, VS = ±5V, AVMAX = 9.4 V/V, RF = 1 kΩ, RG = 100Ω, VIN =
±0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
Frequency Domain Response
−3 dB Bandwidth
BW
VOUT < 1 VPP
150
VOUT < 4 VPP, AVMAX = 100
38
40
GF
Gain Flatness
VOUT < 1 VPP
0.9V ≤ VG ≤ 2V, ±0.2 dB
Att Range
Flat Band (Relative to Max Gain)
Attenuation Range (4)
±0.2 dB Flatness, f < 30 MHz
26
±0.1 dB Flatness, f < 30 MHz
9.5
BW
Control
Gain control Bandwidth
VG = 1V
CT (dB)
Feed-through
GR
Gain Adjustment Range
(5)
MHz
MHz
dB
100
MHz
VG = 0V, 30 MHz
(Output/Input)
−51
dB
f < 10 MHz
80
f < 30 MHz
71
0.5V Step
2.1
ns
10
%
dB
Time Domain Response
tr, tf
Rise and Fall Time
OS %
Overshoot
SR
Slew Rate
(1)
(2)
(3)
(4)
(5)
(6)
Non Inverting
900
Inverting
1500
V/μs
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the Electrical
Tables under conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2 dB or ±0.1 dB), relative to AVMAX gain. For example, for f < 30 MHz, here are the Flat Band Attenuation
ranges:
±0.2 dB: 19.7 dB down to -6.3 dB = 26 dB range
±0.1 dB: 19.7 dB down to 10.2 dB = 9.5 dB range
Gain control frequency response schematic:
RF
1 k:
+0.2 VDC
+VIN
LMH6505
PORT 2
-
RL
50:
VG
RG
100:
(6)
+5V
C1
0.01 PF
RF IN
PORT 1
ROUT
50:
+
R1
50:
RT
50:
RP1
10 k:
1V DC
-5V
Slew rate is the average of the rising and falling slew rates.
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Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TJ = 25°C, VS = ±5V, AVMAX = 9.4 V/V, RF = 1 kΩ, RG = 100Ω, VIN =
±0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
Distortion & Noise Performance
HD2
2nd Harmonic Distortion
HD3
3rd Harmonic Distortion
–61
THD
Total Harmonic Distortion
−45
En tot
Total Equivalent Input Noise
f > 1 MHz, RSOURCE = 50Ω
4.4
nV/√Hz
IN
Input Noise Current
f > 1 MHz
2.6
pA/√Hz
DG
Differential Gain
f = 4.43 MHz, RL = 100Ω
0.30
%
DP
Differential Phase
0.15
deg
−47
2VPP, 20 MHz
dBc
DC & Miscellaneous Performance
GACCU
G Match
Gain Accuracy
(See Application Information)
VG = 2.0V
Gain Matching
(See Application Information)
VG = 2.0V
—
±0.50
0.8V < VG < 2V
—
+4.2/−4.0
0.890
0.830
0.940
0.990
1.04
RG = 100Ω
±0.60
±0.50
±0.74
V
±6.0
±5.0
±7.4
mA
K
Gain Multiplier
(See Application Information)
VIN NL
Input Voltage Range
VIN L
0.8V < VG < 2V
RG Open
I RG_MAX
RG Current
Pin 3
IBIAS
Bias Current
Pin 2
(7)
TC IBIAS
Bias Current Drift
Pin 2
(8)
RIN
Input Resistance
Pin 2
CIN
Input Capacitance
Pin 2
IVG
VG Bias Current
Pin 1, VG = 2V
TC IVG
VG Bias Drift
Pin 1
R VG
VG Input Resistance
Pin 1
C VG
VG Input Capacitance
Pin 1
VOUT L
Output Voltage Range
RL = 100Ω
VOUT NL
0
±0.50
+0.1/−0.53
+4.3/−3.9
−0.6
(7)
(8)
±2.1
±1.9
RL = Open
µA
nA/°C
MΩ
2.8
pF
0.9
µA
10
pA/°C
25
MΩ
2.8
pF
±2.4
V
±3.1
0.12
Ω
±80
mA
DC
Output Current
VOUT = ±4V from Rails
VO
Output Offset Voltage
0V < VG < 2V
+PSRR
+Power Supply Rejection Ratio
Input Referred, 1V change, VG =
2.2V
–65
–72
−PSRR
−Power Supply Rejection Ratio
(9)
Input Referred, 1V change, VG =
2.2V
–65
–75
IS
Supply Current
No Load
9.5
7.5
11
4
−2.5
−2.6
7
Output Impedance
(7)
(8)
(9)
V/V
1.28
IOUT
(9)
dB
±3
ROUT
OFFSET
dB
±60
±40
±10
±55
±70
mV
dB
dB
14
16
mA
Positive current corresponds to current flowing into the device.
Drift is determined by dividing the change in parameter distribution at temperature extremes by the total temperature change.
+PSRR definition: [|ΔVOUT/ΔV+| / AV], −PSRR definition: [|ΔVOUT/ΔV−| / AV] with 0.1V input voltage. ΔVOUT is the change in output
voltage with offset shift subtracted out.
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Connection Diagram
VG
1
8
2
7
VIN
+
V
I
-
X1
RG
GND
3
4
6
+
VOUT
5
V-
Figure 3. 8-Pin SOIC/VSSOP Top View
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Typical Performance Characteristics
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Frequency Response Over Temperature
85°C
GAIN
100
0
50
-1
0
-2
PHASE
-3
-50
85°C
-4
-100
25°C
-150
-5
-40°C
GAIN (dB)
-40°C
-2
PHASE (°)
25°C
-1
GAIN (dB)
1
150
VG = 2V
GAIN
-3
-50
-100
-4
-5
-250
-7
-8 P = -22 dBm
IN
-300
-8 P = -22 dBm
IN
-9
1M
-350
GAIN
1
0
0
-150
-1
PHASE
-200
-2
-6
VG = 0.8V
-250
PIN = 4 dBm
VG = 2V
0
-40
-3
4 VPP
-4
-240
-8
-400
-9
-280
4 VPP
2 VPP
-320
1 VPP
0
f (50 MHz/DIV)
-360
f (50 MHz/DIV)
Figure 7.
Frequency Response for Various VG (AVMAX = 100)
(Large Signal)
Frequency Response for Various Amplitudes
2
80
50
GAIN
0
-200
1 VPP
PHASE
-7
-350
-120
-160
-5
Gain/Phase normalized to low frequency value at each setting.
Figure 6.
1
-80
2 VPP
-6
-300
VG = 1V
0
GAIN
-2
GAIN (dB)
VG = 0.8V
40
-1
PHASE (°)
GAIN (dB)
1
-100
0
RG = 510:
1G
Inverting Frequency Response
50
VG = 2V -50
-5
-350
100M
FREQUENCY (Hz)
VG = 1V
RF = 1 k:
-300
Gain/Phase normalized to low frequency value at each setting.
Figure 5.
Frequency Response (AVMAX = 2)
-4
-250
VG = 1V
10M
FREQUENCY (Hz)
-3 AVMAX = 2V/V
-200
VG = 2V
VG = 0.9V
-9
1M
Gain/Phase normalized to low frequency value at 25°C.
Figure 4.
2
-150
VG = 0.7V
-7
3
0
PHASE
-6
1G
50
VG = 0.9V
-200
100M
100
VG = 0.7V
-6
10M
VG = 1V
PHASE (°)
0
Frequency Response for Various VG
150
PHASE (°)
1
GAIN
40
0
0
-2
-40
-4
1 VPP
0
0.8V
-1
-50
-80
PHASE
-4
-5
2V
AVMAX = 100V/V
RF = 2.32 k:
-6 RG = 18:
PIN = -24 dBm,
-7
0
f (10 MHz/DIV)
-120
-160
-150
-6
4 VPP
-8
-200
-250
-10
2 VPP
-200
-12
-240
-14
-300
-350
0
f (20 MHz/DIV)
Gain/Phase normalized to low frequency value at each setting.
Figure 8.
6
-100
PHASE
PHASE (°)
-3
GAIN (dB)
-2
PHASE (°)
GAIN (dB)
1V
Gain/Phase normalized to low frequency value at each setting.
Figure 9.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Gain Control Frequency Response
10
80
5
40
40°C
-80
25°C
-120
85°C
-20
-160
14
12
10
-200
6
-240
4
-35 VG = 0.98 AVERAGE
-40
10M
100k
1M
-280
2
-320
-30
VG (AC) = -13.7 dBm
25°C
8
VIN = 0.2V (DC)
-25
RL = OPEN
16
85°C
-40
-15
VG = VG_MIN
18
0
ANGLE
-10
20
IS (mA)
|S21| (dB)
85°C
25°C
0
-5
IS vs. VS
120
40°C
MAGNITUDE
ANGLE S21 (°)
15
-40°C
100M
0
1G
3
3.5
FREQUENCY (Hz)
4
4.5
5
5.5
6
±SUPPLY VOTLAGE (V)
See Electrical Characteristics Note (5).
Figure 10.
Figure 11.
IS vs. VS
Input Bias Current vs. VS
-0.4
20
RL = OPEN
18
16
-0.5
85°C
85°C
12
10
IB (PA)
IS (mA)
14
25°C
8
6
25°C
-0.6
-0.7
-40°C
4
-40°C
2
-0.8
0
3
3.5
4
4.5
5
5.5
2
6
3
4
5
±SUPPLY VOTLAGE (V)
±SUPPLY VOLTAGE (V)
Figure 12.
Figure 13.
PSRR
0
6
AVMAX vs. Supply Voltage
12
-10
10
-30
AVMAX (V/V)
PSRR (dB)
-20
-PSRR
-40
-50
8
85°C
6
25°C
4
-60
-40°C
+PSRR
2
-70
-80
100
0
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
2.5
3
3.5
4
4.5
5
5.5
6
±SUPPLY VOLTAGE
See Electrical Characteristics Note (9)
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Feed through Isolation for Various AVMAX
Gain Variation Over entire Temp Range vs. VG
100
60
TEMP RANGE: -55°C TO 125°C
|GAIN(COLD) ± GAIN (HOT)
OVER TEMP CHANGE (dB)
40
GAIN (dB)
20
0
-20
-40
AVMAX = 100 V/V
AVMAX = 10 V/V
AVMAX = 2 V/V
-60
10
1
0.1
-80
0.01
-100
100k
1M
100M
10M
0
1G
0.5
1
FREQUENCY (Hz)
Figure 16.
2
Figure 17.
IRG vs. VIN
-10
1.5
VG (V)
Gain vs. VG
30
12
11
-8
10
125°C
-10
GAIN (dB)
IR G (mA)
-4
-2
0
+2
10
9
8
25°C
-55°C
dB
-30
125°C
-50
7
6
5
V/V
4
25°C
+4
GAIN (V/V)
-6
3
-55°C
2
-70
+6
1
+8
-1.5
-1
-0.5
0
0.5
1
1.5
-90
-0.5
0
0
0.5
VIN (V)
1
1.5
2
VG (V)
See Electrical Characteristics Note (7).
Figure 18.
Figure 19.
Output Offset Voltage vs. VG (Typical Unit #1)
Output Offset Voltage vs. VG (Typical Unit #2)
30
10
25°C
-40°C
25
VO_OFFSET (mV)
VO_OFFSET (mV)
5
0
25°C
-5
85°C
20
15
10
85°C
85°C
-10
5
-40°C
0
-15
0
0.5
1
1.5
2
2.5
VG (V)
0.5
1
1.5
2
2.5
VG (V)
Figure 20.
8
0
Figure 21.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Output Offset Voltage vs. VG (Typical Unit #3)
Distribution of Output Offset Voltage
24
30
25°C
20
15
-40°C
10
22
20
RELATIVE FREQUENCY (%)
VO_OFFSET (mV)
25
85°C
5
18
16
14
12
10
8
6
4
2
25°C
0
-55 -45 -35 -25 -15 -5
0
0
0.5
1
1.5
2
2.5
5 15 25 35 45 55
OFFSET VOLTAGE (mV)
VG (V)
Figure 22.
Figure 23.
Output Noise Density vs. Frequency
Output Noise Density vs. Frequency
10000
100000
RSOURCE - 50:
AVMAX = 100
RF = 2.4 k:
RG = 22:
VG_MAX
1000
eno (nV/ Hz)
eno (nV/ Hz)
10000
VG_MID
VG_MIN
100
VG_MAX
RSOURCE = 50:
VG_MID
1000
100
VG_MIN
10
1
10
10
1k
100
10k 100k
10M
1M
1
10
100
FREQUENCY (Hz)
1k
10k
100k
1M 10M
FREQUENCY (Hz)
Figure 24.
Figure 25.
Output Noise Density vs. Frequency
Input Referred Noise Density vs. Frequency
10000
1000
1000
AVMAX = 2
RG = 510:
VG_MID
100
100
100
Hz)
VOLTAGE
Ini (pA/
VG_MAX
1000
eni (nV/ Hz)
eno (nV/ Hz)
RSOURCE = 50:
10
10
VG_MIN
CURRENT
10
1
1
10
100
1k
10k 100k
1M
10M
1
1
FREQUENCY (Hz)
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Output Voltage vs. Output Current (Sinking)
5
Output Voltage vs. Output Current (Sourcing)
5
25°C
85°C
-40°C
-40°C
85°C
25°C
+
VOUT FROM V (V)
4
-
VOUT FROM V (V)
4
3
-40°C
2
25°C
85°C
3
-40°C
2
85°C
1
1
0
0
20
0
40
60
80
100
120
20
0
80
Figure 28.
Figure 29.
Distortion vs. Frequency
100
120
HD vs. POUT
-120
VG = VG_MAX
VG = VGMAX
-110
VOUT = 1 VPP
HD3, 100 kHz
-100
-50
HD2, 100 kHz
-90
HD (dBc)
HD (dBc)
60
IOUT (mA)
-30
-40
40
IOUT (mA)
-60
THD
-70
HD2
HD3
-80
-80
-70
-60
-50
HD2, 20 MHz
-40
-90
HD3, 20 MHz
-30
-20
-100
100k
1M
10M
-10
100M
-5
0
FREQUENCY (Hz)
5
10
15
20
15
20
POUT (dBm)
Figure 30.
Figure 31.
THD vs. POUT
THD vs. POUT
-70
-100
VG = VG_MAX
-90
-60
-80
-50
-70
THD (dBc)
THD (dBc)
1 MHz
100 kHz
-60
-50
20 MHz
-40
-30
-20
-40
20 MHz
-10
-30
-20
-10
VG = VGMID = a1V
0
-5
0
5
10
15
20
-5
0
5
10
POUT (dBm)
POUT (dBm)
Figure 32.
10
-10
Figure 33.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
THD vs. Gain
THD vs. Gain
-90
VOUT = 0.25 VPP
-80
-80
100 kHz
100 kHz
VOUT = 1 VPP
VG VARIED
-70
VG VARIED
2 MHz
-70
2 MHz
-60
THD (dBc)
THD (dBc)
-60
-50
20 MHz
-40
-30
-50
-40
-20
-20
-10
-10
0
-15
-10
-5
0
5
10
15
20 MHz
-30
0
20
-5
0
5
GAIN (dB)
Figure 34.
0.1
920
0.05
900
0
DG
0
-0.1
-1.4
-1
-0.6 -0.2
0.2
0.6
1
IG (nA)
DG (%)
DP
0.2
0.1
940
DP (°)
RL = 100:
VG = VGMAX
0.3
20
VG Bias Current vs. VG
0.15
f = 4.43 MHz
0.4
15
Figure 35.
Differential Gain & Phase
0.5
10
GAIN (dB)
880
-0.05
860
-0.1
840
-0.15
1.4
820
0
VOUT DC (V)
0.5
1
1.5
2
3
VG (V)
Figure 36.
Figure 37.
Step Response Plot
Step Response Plot
0.5 VPP SMALL SIGNAL
SS REF
2.5
0.5 VPP SMALL SIGNAL
SS REF
LS REF
LS REF
4 VPP LARGE SIGNAL
4 VPP LARGE SIGNAL
VG = VG_MID
5 ns/DIV
5 ns/DIV
Figure 38.
Figure 39.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Gain vs. VG Step
2.5
10
GAIN
2
8
7
6
1.5
5
1
4
GAIN (V/V)
VG
VG (V)
9
3
0.5
2
VIN = 0.3V
0
1
0
t (10 ns/DIV)
Figure 40.
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APPLICATION INFORMATION
GENERAL DESCRIPTION
The key features of the LMH6505 are:
• Low power
• Broad voltage controlled gain and attenuation range (from AVMAX down to complete cutoff)
• Bandwidth independent, resistor programmable gain range (RG)
• Broad signal and gain control bandwidths
• Frequency response may be adjusted with RF
• High impedance signal and gain control inputs
The LMH6505 combines a closed loop input buffer (“X1” Block in Figure 41), a voltage controlled variable gain
cell (“MULT” Block) and an output amplifier (“CFA” Block). The input buffer is a transconductance stage whose
gain is set by the gain setting resistor, RG. The output amplifier is a current feedback op amp and is configured
as a transimpedance stage whose gain is set by, and is equal to, the feedback resistor, RF. The maximum gain,
AVMAX, of the LMH6505 is defined by the ratio: K · RF/RG where “K” is the gain multiplier with a nominal value of
0.940. As the gain control input (VG) changes over its 0 to 2V range, the gain is adjusted over a range of about
80 dB relative to the maximum set gain.
INPUT
SIGNAL
GAIN
CONTROL
5V
+VCC
VG
MULT
VIN
RX
50:
IX1
RIN
50:
-
RO OUTPUT
50:
CFA
GND
0.1 µF
RF
1 k:
VO
RG
+
6.8 µF
-VCC
+
RG
100:
0.1 µF
6.8 µF
+
-5V
Figure 41. LMH6505 Typical Application and Block Diagram
SETTING THE LMH6505 MAXIMUM GAIN
AVMAX =
RF
RG
·K
(1)
Although the LMH6505 is specified at AVMAX = 9.4 V/V, the recommended AVMAX varies between 2 and 100.
Higher gains are possible but usually impractical due to output offsets, noise and distortion. When varying AVMAX
several tradeoffs are made:
RG: determines the input voltage range
RF: determines overall bandwidth
The amount of current which the input buffer can source/sink into RG is limited and is given in the IRG_MAX
specification. This sets the maximum input voltage:
VIN (MAX) = IR G MAX · RG
(2)
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As the IRG_MAX limit is approached with increasing the input voltage or with the lowering of RG, the device's
harmonic distortion will increase. Changes in RF will have a dramatic effect on the small signal bandwidth. The
output amplifier of the LMH6505 is a current feedback amplifier (CFA) and its bandwidth is determined by RF. As
with any CFA, doubling the feedback resistor will roughly cut the bandwidth of the device in half.
For more about CFAs, see the basic tutorial, OA-20, Current Feedback Myths Debunked, (literature number
SNOA376), or a more rigorous analysis, OA-13, Current Feedback Amplifier Loop Gain Analysis and
Performance Enhancements, (literature number SNOA366).
OTHER CONFIGURATIONS
1. Single Supply Operation
The LMH6505 can be configured for use in a single supply environment. Doing so requires the following:
(a) Bias pin 4 and RG to a “virtual half supply” somewhere close to the middle of V+ and V− range. The other
end of RG is tied to pin 3. The “virtual half supply” needs to be capable of sinking and sourcing the
expected current flow through RG.
(b) Ensure that VG can be adjusted from 0V to 2V above the “virtual half supply”.
(c) Bias the input (pin 2) to make sure that it stays within the range of 2V above V− to 2V below V+. See the
Input Voltage Range specification in the Electrical Characteristics table. This can be accomplished by
either DC biasing the input and AC coupling the input signal, or alternatively, by direct coupling if the
output of the driving stage is also biased to half supply.
Arranged this way, the LMH6505 will respond to the current flowing through RG. The gain control relationship
will be similar to the split supply arrangement with VG measured with reference to pin 4. Keep in mind that
the circuit described above will also center the output voltage to the “virtual half supply voltage.”
2. Arbitrarily Referenced Input Signal
Having a wide input voltage range on the input (pin 2) (±3V typical), the LMH6505 can be configured to
control the gain on signals which are not referenced to ground (e.g. Half Supply biased circuits). This node
will be called the “reference node”. In such cases, the other end of RG which is the side not tied to pin 3 can
be tied to this reference node so that RG will “look at” the difference between the signal and this reference
only. Keep in mind that the reference node needs to source and sink the current flowing through RG.
GAIN ACCURACY
Gain accuracy is defined as the actual gain compared against the theoretical gain at a certain VG, the results of
which are expressed in dB. (See Figure 42).
Theoretical gain is given by:
A(V/V) = K x
RF
RG
1
N - VG
x
1+e
VC
where
•
•
K = 0.940 (nominal) N = 1.01V
VC = 79 mV at room temperature
(3)
For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The
"Typical" value would be the difference between the "Typical Gain" and the "Theoretical Gain." The "Max" value
would be the worst case difference between the actual gain and the "Theoretical Gain" for the entire population.
GAIN MATCHING
As Figure 42 shows, gain matching is the limit on gain variation at a certain VG, expressed in dB, and is specified
as "±Max" only. There is no "Typical." For a VG range, the value specified represents the worst case matching
over the entire range. The "Max" value would be the worst case difference between the actual gain and the
typical gain for the entire population.
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MAX GAIN LIMIT
THEORETICAL GAIN
GAIN (dB)
MIN GAIN LIMIT
D
TYPICAL GAIN
C
PARAMETER:
B
GAIN ACCURACY (TYPICAL) = B-C
GAIN ACCURACY (+MAX) = D-C
GAIN ACCURACY (-MAX) = A-C
GAIN MATCHING (+MAX) = D-B
GAIN MATCHING (-MAX) = A-B
A
VG (V)
Figure 42. LMH6505 Gain Accuracy & Gain Matching Defined
GAIN PARTITIONING
If high levels of gain are needed, gain partitioning should be considered:
VG
VIN
+
25:
LMH6624
1
2
RC
-
LMH6505
3
6
VO
7
4
R2
RF
RG
R1
Figure 43. Gain Partitioning
The maximum gain range for this circuit is given by the following equation:
R2
MAXIMUM GAIN =
1+
R1
RF
·
RG
·K
(4)
The LMH6624 is a low noise wideband voltage feedback amplifier. Setting R2 at 909Ω and R1 at 100Ω produces
a gain of 20 dB. Setting RF at 1000Ω as recommended and RG at 50Ω, produces a gain of about 26 dB in the
LMH6505. The total gain of this circuit is therefore approximately 46 dB. It is important to understand that when
partitioning to obtain high levels of gain, very small signal levels will drive the amplifiers to full scale output. For
example, with 46 dB of gain, a 20 mV signal at the input will drive the output of the LMH6624 to 200 mV and the
output of the LMH6505 to 4V. Accordingly, the designer must carefully consider the contributions of each stage
to the overall characteristics. Through gain partitioning the designer is provided with an opportunity to optimize
the frequency response, noise, distortion, settling time, and loading effects of each amplifier to achieve improved
overall performance.
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LMH6505 GAIN CONTROL RANGE AND MINIMUM GAIN
Before discussing Gain Control Range, it is important to understand the issues which limit it. The minimum gain
of the LMH6505 is theoretically zero, but in practical circuits it is limited by the amount of feedthrough, here
defined as the gain when VG = 0V. Capacitive coupling through the board and package, as well as coupling
through the supplies, will determine the amount of feedthrough. Even at DC, the input signal will not be
completely rejected. At high frequencies feedthrough will get worse because of its capacitive nature. At
frequencies below 10 MHz, the feed through will be less than −60 dB and therefore, it can be said that with
AVMAX = 20 dB, the gain control range is 80 dB.
LMH6505 GAIN CONTROL FUNCTION
In the plot, Gain vs. VG (Figure 19), we can see the gain as a function of the control voltage. The “Gain (V/V)”
plot, sometimes referred to as the S-curve, is the linear (V/V) gain. This is a hyperbolic tangent relationship and
is given by Equation 3. The “Gain (dB)” plots the gain in dB and is linear over a wide range of gains. Because of
this, the LMH6505 gain control is referred to as “linear-in-dB.”
For applications where the LMH6505 will be used at the heart of a closed loop AGC circuit, the S-curve control
characteristic provides a broad linear (in dB) control range with soft limiting at the highest gains where large
changes in control voltage result in small changes in gain. For applications requiring a fully linear (in dB) control
characteristic, use the LMH6505 at half gain and below (VG ≤ 1V).
GAIN STABILITY
The LMH6505 architecture allows complete attenuation of the output signal from full gain to complete cutoff. This
is achieved by having the gain control signal VG “throttle” the signal which gets through to the final stage and
which results in the output signal. As a consequence, the RG pin's (pin 3) average current (DC current) influences
the operating point of this “throttle” circuit and affects the LMH6505's gain slightly. Figure 44 below, shows this
effect as a function of the gain set by VG.
4.5
4
DELTA AV (dB)
3.5
3
4.5 mA SOURCING
2.5
2
1.5
1
4.5 mA SINKING
0.5
0
-0.5
-80
-60
-40
-20
0
20
AV (dB)
Figure 44. LMH6505 Gain Variation over RG DC Current Capability vs. Gain
This plot shows the expected gain variation for the maximum RG DC current capability (±4.5 mA). For example,
with gain (AV) set to −60 dB, if the RG pin DC current is increased to 4.5 mA sourcing, one would expect to see
the gain increase by about 3 dB (to −57 dB). Conversely, 4.5 mA DC sinking current through RG would increase
gain by 1.75 dB (to −58.25 dB). As you can see from Figure 44 above, the effect is most pronounced with
reduced gain and is limited to less than 3.75 dB variation maximum.
If the application is expected to experience RG DC current variation and the LMH6505 gain variation is beyond
acceptable limits, please refer to the LMH6502 (Differential Linear in dB variable gain amplifier) datasheet
instead at http://www.ti.com/lit/gpn/LMH6502.
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AVOIDING OVERDRIVE OF THE LMH6505 GAIN CONTROL INPUT
There is an additional requirement for the LMH6505 Gain Control Input (VG): VG must not exceed +2.3V (with
±5V supplies). The gain control circuitry may saturate and the gain may actually be reduced. In applications
where VG is being driven from a DAC, this can easily be addressed in the software. If there is a linear loop
driving VG, such as an AGC loop, other methods of limiting the input voltage should be implemented. One simple
solution is to place a 2.2:1 resistive divider on the VG input. If the device driving this divider is operating off of
±5V supplies as well, its output will not exceed 5V and through the divider VG can not exceed 2.3V.
IMPROVING THE LMH6505 LARGE SIGNAL PERFORMANCE
Figure 45 illustrates an inverting gain scheme for the LMH6505.
VG
1
2
LMH6505
25:
3
VIN
6
VO
7
4
RG
RF
Figure 45. Inverting Amplifier
The input signal is applied through the RG resistor. The VIN pin should be grounded through a 25Ω resistor. The
maximum gain range of this configuration is given in the following equation:
AVMAX = -
RF
·K
RG
(5)
The inverting slew rate of the LMH6505 is much higher than that of the non-inverting slew rate. This ≈ 2X
performance improvement comes about because in the non-inverting configuration the slew rate of the overall
amplifier is limited by the input buffer. In the inverting circuit, the input buffer remains at a fixed voltage and does
not affect slew rate.
TRANSMISSION LINE MATCHING
One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor
at the input or output of the amplifier. Figure 46 shows a typical circuit configuration for matching transmission
lines.
VG
CO
ZO
1
2
SIGNAL
INPUT
ZO
6
RS
RI
+-
OUTPUT
LMH6505
3
RO
7
RT
4
RG
RF
Figure 46. Transmission Line Matching
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The resistors RS, RI, RO, and RT are equal to the characteristic impedance, ZO, of the transmission line or cable.
Use CO to match the output transmission line over a greater frequency range. It compensates for the increase of
the op amp’s output impedance with frequency.
MINIMIZING PARASITIC EFFECTS ON SMALL SIGNAL BANDWIDTH
The best way to minimize parasitic effects is to use surface mount components and to minimize lead lengths and
component distance from the LMH6505. For designs utilizing through-hole components, specifically axial
resistors, resistor self-capacitance should be considered. For example, the average magnitude of parasitic
capacitance of RN55D 1% metal film resistors is about 0.15 pF with variations of as much as 0.1 pF between
lots. Given the LMH6505’s extended bandwidth, these small parasitic reactance variations can cause
measurable frequency response variations in the highest octave. We therefore recommend the use of surface
mount resistors to minimize these parasitic reactance effects.
RECOMMENDATIONS
Here are some recommendations to avoid problems and to get the best performance:
• Do not place a capacitor across RF. However, an appropriately chosen series RC combination can be used to
shape the frequency response.
• Keep traces connecting RF separated and as short as possible.
• Place a small resistor (20-50Ω) between the output and CL.
• Cut away the ground plane, if any, under RG.
• Keep decoupling capacitors as close as possible to the LMH6505.
• Connect pin 2 through a minimum resistance of 25Ω.
ADJUSTING OFFSETS AND DC LEVEL SHIFTING
Offsets can be broken into two parts: an input-referred term and an output-referred term. These errors can be
trimmed using the circuit in Figure 47. First set VG to 0V and adjust the trim pot R4 to null the offset voltage at the
output. This will eliminate the output stage offsets. Next set VG to 2V and adjust the trim pot R1 to null the offset
voltage at the output. This will eliminate the input stage offsets.
VG
VIN
2
1
LMH6505
3
7
+5V
R2
10 k:
R1
10 k:
6
VO
RF
4
RG
+5V
R3
10 k:
R4
10 k:
0.1 µF
0.1 µF
-5V
-5V
Figure 47. Offset Adjust Circuit
DIGITAL GAIN CONTROL
Digitally variable gain control can be easily realized by driving the LMH6505 gain control input with a digital-toanalog converter (DAC). Figure 48 illustrates such an application. This circuit employs TI’s eight-bit DAC0830,
the LMC8101 MOS input op amp (Rail-to-Rail Input/Output), and the LMH6505 VGA. With VREF set to 2V, the
circuit provides up to 80 dB of gain control in 256 steps with up to 0.05% full scale resolution. The maximum gain
of this circuit is 20 dB.
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DIGITAL
INPUT
RFB
Io1
VREF
LMC8101
DAC0830
Io2
+
VIN
1
2
6
VO
LMH6505
3
7
4
RG
100:
RF
1 k:
Figure 48. Digital Gain Control
USING THE LMH6505 IN AGC APPLICATIONS
In AGC applications, the control loop forces the LMH6505 to have a fixed output amplitude. The input amplitude
will vary over a wide range and this can be the issue that limits dynamic range. At high input amplitudes, the
distortion due to the input buffer driving RG may exceed that which is produced by the output amplifier driving the
load. In the plot, THD vs. Gain, total harmonic distortion (THD) is plotted over a gain range of nearly 35 dB for a
fixed output amplitude of 0.25 VPP in the specified configuration, RF = 1 kΩ, RG = 100Ω. When the gain is
adjusted to −15 dB (i.e. 35 dB down from AVMAX), the input amplitude would be 1.41 VPP and we can see the
distortion is at its worst at this gain. If the output amplitude of the AGC were to be raised above 0.25 VPP, the
input amplitudes for gains 40 dB down from AVMAX would be even higher and the distortion would degrade
further. It is for this reason that we recommend lower output amplitudes if wide gain ranges are desired. Using a
post-amp like the LMH6714/LMH6720/LMH6722 family or the LMH6702 would be the best way to preserve
dynamic range and yield output amplitudes much higher than 100 mVPP. Another way of addressing distortion
performance and its limitations on dynamic range, would be to raise the value of RG. Just like any other highspeed amplifier, by increasing the load resistance, and therefore decreasing the demanded load current, the
distortion performance will be improved in most cases. With an increased RG, RF will also have to be increased
to keep the same AVMAX and this will decrease the overall bandwidth. It may be possible to insert a series RC
combination across RF in order to counteract the negative effect on BW when a large RF is used.
AUTOMATIC GAIN CONTROL (AGC)
Fast Response AGC Loop
The AGC circuit shown in Figure 49 will correct a 6 dB input amplitude step in 100 ns. The circuit includes a two
op amp precision rectifier amplitude detector (U1 and U2), and an integrator (U3) to provide high loop gain at low
frequencies. The output amplitude is set by R9. The following are some suggestions for building fast AGC loops:
Precision rectifiers work best with large output signals. Accuracy is improved by blocking DC offsets, as shown in
Figure 49.
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INCLUDES SCOPE
PROBE CAPACITANCE
C3
40 pF
VIN
1
2
+
U4
LMH6505
3
R10
500:
RG
100:
-
OUTPUT
20 MHz,
6
0.1 VPP
7
4
C1
1.0 µF
RF
R1
20:
C2
680 pF
R8
500:
R5
25:
+
-
U2
LMH6714
U3
LMH6609
-
+
R4
300:
R6
300:
R9
4.22 k:
-
R7
300:
-5V
R3
300:
1N5712
SCHOTTKY
U1
LMH6714
+
R2
25:
Figure 49. Automatic Gain Control Circuit
Signal frequencies must not reach the gain control port of the LMH6505, or the output signal will be distorted
(modulated by itself). A fast settling AGC needs additional filtering beyond the integrator stage to block signal
frequencies. This is provided in Figure 49 by a simple R-C filter (R10 and C3); better distortion performance can
be achieved with a more complex filter. These filters should be scaled with the input signal frequency. Loops with
slower response time, which means longer integration time constants, may not need the R10 – C3 filter.
Checking the loop stability can be done by monitoring the VG voltage while applying a step change in input signal
amplitude. Changing the input signal amplitude can be easily done with an arbitrary waveform generator.
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CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARDS
A good high frequency PCB layout including ground plane construction and power supply bypassing close to the
package is critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the Iinput (pin 7) so it is best to keep the node trace area small. Shunt capacitance across the feedback resistor
should not be used to compensate for this effect. Capacitance to ground should be minimized by removing the
ground plane from under the body of RG. Parasitic or load capacitance directly on the output (pin 6) degrades
phase margin leading to frequency response peaking.
The LMH6505 is fully stable when driving a 100Ω load. With reduced load (e.g. 1k.) there is a possibility of
instability at very high frequencies beyond 400 MHz especially with a capacitive load. When the LMH6505 is
connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100Ω and 39
pF in series tied between the LMH6505 output and ground). CL can also be isolated from the output by placing a
small resistor in series with the output (pin 6).
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board
Part Number
LMH6505
SOIC
LMH730066
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SNOSAT4E – DECEMBER 2005 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LMH6505
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH6505MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH65
05MA
LMH6505MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH65
05MA
LMH6505MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
AZ2A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMH6505MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMH6505MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6505MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMH6505MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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