Texas Instruments | LMC6442 Dual Micropower Rail-to-Rail Output Single Supply Operational Amplifier (Rev. E) | Datasheet | Texas Instruments LMC6442 Dual Micropower Rail-to-Rail Output Single Supply Operational Amplifier (Rev. E) Datasheet

Texas Instruments LMC6442 Dual Micropower Rail-to-Rail Output Single Supply Operational Amplifier (Rev. E) Datasheet
LMC6442
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SNOS013E – SEPTEMBER 1997 – REVISED MARCH 2013
LMC6442 Dual Micropower Rail-to-Rail Output Single Supply Operational Amplifier
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FEATURES
DESCRIPTION
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The LMC6442 is ideal for battery powered systems,
where very low supply current (less than one
microamp per amplifier) and Rail-to-Rail output swing
is required. It is characterized for 2.2V to 10V
operation, and at 2.2V supply, the LMC6442 is ideal
for single (Li-Ion) or two cell (NiCad or alkaline)
battery systems.
1
2
(Typical, VS = 2.2V)
Output Swing to Within 30 mV of Supply Rail
High Voltage Gain 103 dB
Gain Bandwidth Product 9.5 KHz
Ensured for: 2.2V, 5V, 10V
Low Supply Current 0.95 µA/Amplifier
Input Voltage Range −0.3V to V+ -0.9V
2.1 µW/Amplifier Power Consumption
Stable for AV ≥ +2 or AV ≤ −1
Operation from single supply is enhanced by the wide
common mode input voltage range which includes the
ground (or negative supply) for ground sensing
applications. Very low (5 fA, typical) input bias current
and near constant supply current over supply voltage
enhance the LMC6442's performance near the endof-life battery voltage.
APPLICATIONS
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The LMC6442 is designed for battery powered
systems that require long service life through low
supply current, such as smoke and gas detectors,
and pager or personal communications systems.
Portable Instruments
Smoke/Gas/CO/Fire Detectors
Pagers/Cell Phones
Instrumentation
Thermostats
Occupancy Sensors
Cameras
Active Badges
Designed for closed loop gains of greater than plus
two (or minus one), the amplifier has typically 9.5
KHz GBWP (Gain Bandwidth Product). Unity gain can
be used with a simple compensation circuit, which
also allows capacitive loads of up to 300 pF to be
driven, as described in the Application Information
section.
Connection Diagram
Top View
Figure 1. 8-Pin SOIC / PDIP Package
See Package Numbers D0008A, P0008E
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2013, Texas Instruments Incorporated
LMC6442
SNOS013E – SEPTEMBER 1997 – REVISED MARCH 2013
(1) (2)
Absolute Maximum Ratings
ESD Tolerance
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(3)
2 kV
Differential Input Voltage
±Supply Voltages
(V+) + 0.3V, (V−) − 0.3V
Voltage at Input/Output Pin
Supply Voltage (V+ − V−):
Current at Input Pin
16V
(4)
Current at Output Pin (5)
±5 mA
(6)
±30 mA
Lead Temp. (soldering 10 sec)
260°C
−65°C to +150°C
Storage Temp. Range:
Junction Temp.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(7)
150°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Human body model, 1.5 kΩ in series with 100 pF.
Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings
(1)
1.8V ≤ VS ≤ 11V
Supply Voltage
−40°C < TJ < +85°C
Junction Temperature Range: LMC6442AI, LMC6442I
Thermal Resistance (θJA)
(1)
D0008A Package, 8-pin Surface Mount
193°C/W
P0008E Package, 8-pin Molded DIP
115°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
2.2V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.2V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Typ
(1)
LMC6442AI
Limit (2)
LMC6442I
Limit (2)
Units
±3
±4
±7
±8
mV
max
DC Electrical Characteristics
VOS
Input Offset Voltage
TCVOS
Temp. coefficient of input
offset voltage
IB
Input Bias Current
See
(3)
Input Offset Current
See
(3)
CMRR
Common Mode Rejection
Ratio
−0.1V ≤ VCM ≤0.5V
CIN
Common Mode Input
Capacitance
PSRR
Power Supply Rejection
Ratio
IOS
(1)
(2)
(3)
2
−0.75
0.4
µV/°C
0.005
4
4
pA
max
0.0025
2
2
pA
max
92
67
67
67
67
4.7
VS = 2.5 V to 10V
95
dB min
pF
75
75
75
75
dB
min
Typical Values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis unless otherwise specified.
Limits specified by design.
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2.2V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.2V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
VCM
Input Common-Mode
Voltage Range
AV
Large Signal Voltage Gain
Test Conditions
1.3
CMRR ≥ 50 dB
Sourcing
Sinking
−0.3
(4)
Output Swing
Output Short Circuit
Current
IS
Supply Current
(2 amplifiers)
LMC6442I
Limit (2)
Units
1.05
0.95
1.05
0.95
V
min
−0.2
0
−0.2
0
V
max
dB
min
94
VID = 100 mV
103
80
80
2.18
2.15
2.15
2.15
2.15
V
min
22
60
60
60
60
mV
max
(5)
VID = −100 mV
ISC
LMC6442AI
Limit (2)
100
(4)
VO = 0.22V to 2V
VO
(1)
Typ
(5)
Sourcing, VID = 100 mV
(6) (5)
50
18
17
18
17
Sinking, VID = −100 mV
(6) (5)
50
20
19
20
19
1.90
2.4
3.0
2.6
3.2
RL = open
+
V = 1.8V, RL = open
µA
min
µA
max
2.10
AC Electrical Characteristics
SR
Slew Rate
(7)
2.2
V/ms
GBWP
Gain-Bandwidth Product
9.5
KHz
φm
Phase Margin
63
deg
(4)
(5)
(6)
(7)
(8)
See
(8)
RL connected to V+/2. For Sourcing Test, VO > V+/2. For Sinking tests, VO < V+/2.
VID is differential input voltage referenced to inverting input.
Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.
Slew rate is the slower of the rising and falling slew rates.
See the Typical Performance Characteristics and Applications Information sections for more details.
5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Typ
(1)
LMC6442AI
Limit (2)
LMC6442I
Limit (2)
Units
±3
±4
±7
±8
mV
max
DC Electrical Characteristics
VOS
Input Offset Voltage
TCVOS
Temp. coefficient of input
offset voltage
IB
Input Bias Current
See
(3)
Input Offset Current
See
(3)
CMRR
Common Mode Rejection
Ratio
−0.1V ≤ VCM ≤3.5V
CIN
Common Mode Input
Capacitance
PSRR
Power Supply Rejection
Ratio
IOS
(1)
(2)
(3)
−0.75
0.4
µV/°C
0.005
4
4
pA
max
0.0025
2
2
pA
max
102
70
70
70
70
dB min
4.1
VS = 2.5 V to 10V
95
pF
75
75
75
75
dB
min
Typical Values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis unless otherwise specified.
Limits specified by design.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
VCM
Test Conditions
Input Common-Mode
Voltage Range
AV
4.1
CMRR ≥ 50 dB
Large Signal Voltage Gain
Sourcing
Sinking
−0.4
(4)
Output Swing
IS
LMC6442I
Limit (2)
Units
3.85
3.75
3.85
3.75
V
min
−0.2
0
−0.2
0
V
max
dB
min
94
VID = 100 mV
(5)
VID = −100 mV
ISC
LMC6442AI
Limit (2)
100
(4)
VO = 0.5V to 4.5V
VO
(1)
Typ
(5)
103
80
80
4.99
4.95
4.95
4.95
4.95
V
min
20
50
50
50
50
mV
max
Output Short Circuit Current Sourcing, VID = 100 mV
(6) (5)
500
300
200
300
200
Sinking, VID = −100 mV
(6) (5)
350
200
150
200
150
1.90
2.4
3.0
2.6
3.2
µA
max
2.5
2.5
V/ms
Supply Current
(2 amplifiers)
RL = open
µA
min
AC Electrical Characteristics
SR
Slew Rate
(7)
4.1
GBWP
Gain-Bandwidth Product
10
KHz
φm
Phase Margin
See
64
deg
THD
Total Harmonic Distortion
AV = +2, f = 100 Hz,
RL = 10 MΩ, VOUT = 1 VPP
0.08
%
(4)
(5)
(6)
(7)
(8)
(8)
RL connected to V+/2. For Sourcing Test, VO > V+/2. For Sinking tests, VO < V+/2.
VID is differential input voltage referenced to inverting input.
Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.
Slew rate is the slower of the rising and falling slew rates.
See the Typical Performance Characteristics and Applications Information sections for more details.
10V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 10V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Typ
(1)
LMC6442AI
Limit (2)
LMC6442I
Limit (2)
Units
±3
±4
±7
±8
mV
max
DC Electrical Characteristics
VOS
Input Offset Voltage
TCVOS
Temp. coefficient of input
offset voltage
IB
Input Bias Current
See (3)
Input Offset Current
See
CMRR
Common Mode Rejection
Ratio
−0.1V ≤ VCM ≤8.5V
CIN
Common Mode Input
Capacitance
PSRR
Power Supply Rejection
Ratio
IOS
(1)
(2)
(3)
4
−1.5
0.4
µV/°C
0.005
4
4
pA
max
0.0025
2
2
pA
max
105
70
70
70
70
(3)
3.5
VS= 2.5 V to 10V
95
dB min
pF
75
75
75
75
dB
min
Typical Values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis unless otherwise specified.
Limits specified by design.
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10V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 10V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
VCM
Input Common-Mode
Voltage Range
AV
Large Signal Voltage Gain
Test Conditions
Typ
9.1
CMRR ≥ 50 dB
Sourcing
Sinking
−0.4
(4)
Output Swing
Output Short Circuit
Current
IS
Supply Current
(2 amplifiers)
LMC6442I
Limit (2)
Units
8.85
8.75
8.85
8.75
V
min
−0.2
0
−0.2
0
V
max
dB
min
100
VID = 100 mV
(5)
VID = −100 mV
ISC
LMC6442AI
Limit (2)
120
(4)
VO = 0.5V to 9.5V
VO
(1)
(5)
104
80
80
9.99
9.97
9.97
9.97
9.97
V
min
22
50
50
50
50
mV
max
Sourcing, VID = 100 mV
(6) (5)
2100
1200
1000
1200
1000
Sinking, VID = −100 mV
(6) (5)
900
600
500
600
500
1.90
2.4
3.0
2.6
3.2
µA
max
2.5
2.5
V/ms
RL = open
µA
min
AC Electrical Characteristics
SR
Slew Rate (7)
4.1
GBWP
Gain-Bandwidth Product
10.5
φm
Phase Margin
See
en
Input-Referred Voltage
Noise
in
(4)
(5)
(6)
(7)
(8)
(9)
(8)
KHz
68
deg
RL = open
f = 10 Hz
170
nV/√Hz
Input-Referred Current
Noise
RL = open
f = 10 Hz
0.0002
pA/√Hz
Crosstalk Rejection
See
85
dB
(9)
RL connected to V+/2. For Sourcing Test, VO > V+/2. For Sinking tests, VO < V+/2.
VID is differential input voltage referenced to inverting input.
Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.
Slew rate is the slower of the rising and falling slew rates.
See the Typical Performance Characteristics and Applications Information sections for more details.
Input referred, V+ = 10V and RL = 10 MΩ connected to 5V. Each amp excited in turn with 1 KHz to produce about 10 VPP output.
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Typical Performance Characteristics
VS = 5V, Single Supply, TA = 25°C unless otherwise specified
6
Total Supply Current
vs.
Supply Voltage
Total Supply Current
vs.
Supply Voltage (Negative Input Overdrive)
Figure 2.
Figure 3.
Total Supply Current
vs.
Supply Voltage (Positive Input Overdrive)
Input Bias Current
vs.
Temperature
Figure 4.
Figure .
Offset Voltage
vs.
Common Mode Voltage (VS = 2.2V)
Offset Voltage
vs.
Common Mode Voltage (VS = 5V)
Figure 5.
Figure 6.
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Typical Performance Characteristics (continued)
VS = 5V, Single Supply, TA = 25°C unless otherwise specified
Offset Voltage
vs.
Common Mode Voltage (VS = 10V)
Swing Towards V−
vs.
Supply Voltage
Figure 7.
Figure 8.
Swing Towards V+
vs.
Supply Voltage
Swing From Rail(s)
vs.
Temperature
Figure 9.
Figure 10.
Output Source Current
vs.
Output Voltage
Output Sink Current
vs.
Output Voltage
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
VS = 5V, Single Supply, TA = 25°C unless otherwise specified
8
Maximum Output Voltage
vs.
Load Resistance
Large Signal Voltage Gain
vs.
Supply Voltage
Figure 13.
Figure 14.
Open Loop Gain/Phase
vs.
Frequency
Open Loop Gain/Phase
vs.
Frequency For Various CL (ZL = 1 MΩ II CL)
Figure 15.
Figure 16.
Open Loop Gain/Phase
vs.
Frequency For Various CL (ZL = 100 KΩ II CL)
Gain Bandwidth Product
vs.
Supply Voltage
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
VS = 5V, Single Supply, TA = 25°C unless otherwise specified
Phase Margin (Worst Case)
vs.
Supply Voltage
CMRR
vs.
Frequency
Figure 19.
Figure 20.
PSRR
vs.
Frequency
Positive Slew Rate
vs.
Supply Voltage
Figure 21.
Figure 22.
Negative Slew Rate
vs.
Supply Voltage
Cross-Talk Rejection
vs.
Frequency
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
VS = 5V, Single Supply, TA = 25°C unless otherwise specified
10
Input Voltage Noise
vs.
Frequency
Output Impedance
vs.
Frequency
Figure 25.
Figure 26.
THD+N
vs.
Frequency
THD+N
vs.
Amplitude
Figure 27.
Figure 28.
Maximum Output Swing
vs.
Frequency
Small Signal Step Response
(AV = +2) (CL = 12 pF, 100 pF)
Figure 29.
Figure 30.
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Typical Performance Characteristics (continued)
VS = 5V, Single Supply, TA = 25°C unless otherwise specified
Large Signal Step Response
(AV = +2) (CL = 100 pF)
Small Signal Step Response
(AV = −1) (CL= 1MΩ II 100 pF, 200 pF)
Figure 31.
Figure 32.
Small Signal Step Response
(AV = +1) For Various CL
Large Signal Step Response
(AV = +1) (CL = 200 pF)
Figure 33.
Figure 34.
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APPLICATIONS INFORMATION
USING LMC6442 IN UNITY GAIN APPLICATIONS
LMC6442 is optimized for maximum bandwidth and minimal external components when operating at a minimum
closed loop gain of +2 (or −1). However, it is also possible to operate the device in a unity gain configuration by
adding external compensation as shown in Figure 35:
Figure 35. AV = +1 Operation by adding CC and RC
Using this compensation technique it is possible to drive capacitive loads of up to 300 pF without causing
oscillations (see the Typical Performance Characteristics for step response plots). This compensation can also
be used with other gain settings in order to improve stability, especially when driving capacitive loads (for
optimum performance, RC and CC may need to be adjusted).
USING “T” NETWORK
Compromises need to be made whenever high gain inverting stages need to achieve a high input impedance as
well. This is especially important in low current applications which tend to deal with high resistance values. Using
a traditional inverting amplifier, gain is inversely proportional to the resistor value tied between the inverting
terminal and input while the input impedance is equal to this value. For example, in order to build an inverting
amplifier with an input impedance of 10MΩ and a gain of 100, one needs to come up with a feedback resistor of
1000 MΩ -an expensive task.
An alternate solution is to use a “T” Network in the feedback path, as shown in Figure 36.
Closed loop gain, AV is given by:
(1)
Figure 36. “T” Network Used to Replace High Value Resistor
It must be noted, however, that using this scheme, the realizable bandwidth would be less than the theoretical
maximum. With feedback factor, β, defined as:
(2)
(3)
BW(−3 dB) ≈ GBWP • β
In this case, assuming a GBWP of about 10 KHz, the expected BW would be around 50 Hz (vs. 100 Hz with the
conventional inverting amplifier).
12
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Looking at the problem from a different view, with RF defined by AV•Rin, one could select a value for R in the “T”
Network and then determine R1 based on this selection:
(4)
Figure 37. “T” Network Values for Various Values of R
For convenience, Figure 37 shows R1 vs. RF for different values of R.
DESIGN CONSIDERATIONS FOR CAPACITIVE LOADS
As with many other opamps, the LMC6442 is more stable at higher closed loop gains when driving a capacitive
load. Figure 38 shows minimum closed loop gain versus load capacitance, to achieve less than 10% overshoot in
the output small signal response. In addition, the LMC6442 is more stable when it provides more output current
to the load and when its output voltage does not swing close to V−.
The LMC6442 is more tolerant to capacitive loads when the equivalent output load resistance is lowered or when
output voltage is 1V or greater from the V− supply. The capacitive load drive capability is also improved by
adding an isolating resistor in series with the load and the output of the device. Figure 39 shows the value of this
resistor for various capacitive loads (AV = −1), while limiting the output to less than 10 % overshoot.
Referring to the Typical Performance Characteristics plot of Phase Margin (Worst Case) vs. Supply Voltage, note
that Phase Margin increases as the equivalent output load resistance is lowered. This plot shows the expected
Phase Margin when the device output is very close to V−, which is the least stable condition of operation.
Comparing this Phase Margin value to the one read off the Open Loop Gain/Phase vs. Frequency plot, one can
predict the improvement in Phase Margin if the output does not swing close to V−. This dependence of Phase
Margin on output voltage is minimized as long as the output load, RL, is about 1MΩ or less.
Output Phase Reversal: The LMC6442 is immune against this behavior even when the input voltages exceed
the common mode voltage range.
Output Time Delay: Due to the ultra low power consumption of the device, there could be as long as 2.5 ms of
time delay from when power is applied to when the device output reaches its final value.
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Figure 38. Minimum Operating Gain vs. Capacitive Load
Figure 39. Isolating Resistor Value vs Capacitive Load
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Application Circuits
V + = 5V: IS < 10 µA, f/VC = 4.3 (Hz/V)
Figure 40. Micropower Single Supply Voltage to Frequency Converter
Figure 41. Gain Stage with Current Boosting
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Figure 42. Offset Nulling Schemes
16
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SNOS013E – SEPTEMBER 1997 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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Copyright © 1997–2013, Texas Instruments Incorporated
Product Folder Links: LMC6442
17
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMC6442AIM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC64
42AIM
LMC6442AIMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC64
42AIM
LMC6442IM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC64
42IM
LMC6442IMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
-40 to 85
LMC64
42IM
LMC6442IN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LMC6442
IN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMC6442AIMX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMC6442IMX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMC6442AIMX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMC6442IMX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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