Texas Instruments | LMC6032 CMOS Dual Operational Amplifier (Rev. C) | Datasheet | Texas Instruments LMC6032 CMOS Dual Operational Amplifier (Rev. C) Datasheet

Texas Instruments LMC6032 CMOS Dual Operational Amplifier (Rev. C) Datasheet
LMC6032
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SNOS609C – NOVEMBER 1994 – REVISED MARCH 2013
LMC6032 CMOS Dual Operational Amplifier
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FEATURES
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Specified for 2 kΩ and 600 Ω Loads
High Voltage Gain: 12 dB
Low Offset Voltage Drift: 2.3 μV/°C
Ultra Low Input Bias Current: 40 fA
Input Common-mode Range Includes V−
Operating Range From +5V to +15V Supply
ISS = 400 μA/Amplifier; Independent of V+
Low Distortion: 0.01% at 10 kHz
Slew Rate: 1.1 V/μs
Improved Performance Over TLC272
APPLICATIONS
•
•
High-Impedance Buffer or Preamplifier
Current-to-Voltage Converter
•
•
•
Long-Term Integrator
Sample-and-Hold Circuit
Medical Instrumentation
DESCRIPTION
The LMC6032 is a CMOS dual operational amplifier
which can operate from either a single supply or dual
supplies. Its performance features include an input
common-mode range that reaches ground, low input
bias current, and high voltage gain into realistic loads,
such as 2 kΩ and 600 Ω.
This chip is built with TI's advanced Double-Poly
Silicon-Gate CMOS process.
See the LMC6034 datasheet for a CMOS quad
operational amplifier with these same features. For
higher performance characteristics refer to the
LMC662.
CONNECTION DIAGRAMS
8-Pin PDIP/SOIC
Top View
Figure 1. 10 Hz High-Pass Filter
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Differential Input Voltage
±Supply Voltage
Supply Voltage (V+ − V−)
16V
Output Short Circuit to V+
See (2)
Output Short Circuit to V−
See (3)
Lead Temperature (Soldering, 10 sec.)
260°C
−65°C to +150°C
Storage Temperature Range
Junction Temperature
150°C
ESD Tolerance (4)
1000V
Power Dissipation
See (5)
(V+) + 0.3V
Voltage at Output/Input Pin
(V−) − 0.3V
Current at Output Pin
±18 mA
Current at Input Pin
±5 mA
Current at Power Supply Pin
35 mA
(1)
(2)
(3)
(4)
(5)
Absolute Maximum Ratings indicate limits beyond which damage to component may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Do not connect output to V+, when V+ is greater than 13V or reliability may be adversely affected.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) – TA)/θJA.
Operating Ratings (1)
−40°C ≤ TJ ≤ +85°C
Temperature Range
Supply Voltage Range
4.75V to 15.5V
(2)
Power Dissipation
Thermal Resistance (θJA) (3)
(1)
(2)
(3)
2
8-Pin PDIP
101°C/W
8-Pin SOIC
165°C/W
Absolute Maximum Ratings indicate limits beyond which damage to component may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA.
All numbers apply for packages soldered directly into a PC board.
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DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
GND = 0V, VCM = 1.5V, VOUT = 2.5V and RL > 1M unless otherwise specified.
Symbol
Parameter
Conditions
Typical
(1)
LMC6032I
Units
Limit
(2)
VOS
Input Offset Voltage
1
ΔVOS/ΔT
Input Offset Voltage
Average Drift
2.3
IB
Input Bias Current
0.04
IOS
Input Offset Current
Input Resistance
CMRR
Common Mode Rejection
Ratio
0V ≤ VCM ≤ 12V
V+ = 15V
83
Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V
VO = 2.5V
83
Negative Power Supply
Rejection Ratio
0V ≤ V− ≤ −10V
94
Input Common-Mode
Voltage Range
V+ = 5V & 15V
For CMRR ≥ 50 dB
−PSRR
VCM
AV
Large Signal Voltage Gain
μV/°C
pA
200
max
100
max
pA
>1
RL = 2 kΩ (3)
Sourcing
Sinking
RL = 600Ω
(3)
Sourcing
Sinking
(1)
(2)
(3)
mV
max
0.01
RIN
+PSRR
9
11
TeraΩ
63
dB
60
min
63
dB
60
min
74
dB
70
min
−0.4
−0.1
V
0
max
V+ − 1.9
V+ − 2.3
V
V+ − 2.6
min
200
V/mV
2000
500
1000
250
100
min
90
V/mV
40
min
100
V/mV
75
min
50
V/mV
20
min
Typical values represent the most likely parametric normal.
All limits are specified at room temperature (standard type face) or at operating temperature extremes (bold type face).
V+ = 15V, VCM = 7.5V, and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
GND = 0V, VCM = 1.5V, VOUT = 2.5V and RL > 1M unless otherwise specified.
Symbol
Parameter
Conditions
Typical
(1)
LMC6032I
Units
Limit
(2)
VO
Output Voltage Swing
+
V = 5V
RL = 2 kΩ to 2.5V
4.87
0.10
V+ = 5V
RL = 600Ω to 2.5V
4.61
0.30
V+ = 15V
RL = 2 kΩ to 7.5V
14.63
0.26
V+ = 15V
RL = 600Ω to 7.5V
13.90
0.79
IO
IS
(4)
4
Output Current
Supply Current
V+ = 5V
Sourcing, VO = 0V
Sinking, VO = 5V
22
V+ = 15V
Sourcing, VO = 0V
Sinking, VO = 13V (4)
Both Amplifiers
VO = 1.5V
4.20
V
4.00
min
0.25
V
0.35
max
4.00
V
3.80
min
0.63
V
0.75
max
13.50
V
13.00
min
0.45
V
0.55
max
12.50
V
12.00
min
1.45
V
1.75
max
13
mA
9
min
21
13
mA
9
min
40
23
mA
15
min
39
23
mA
15
min
0.75
1.6
mA
1.9
max
Do not connect output to V+, when V+ is greater than 13V or reliability may be adversely affected.
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AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
GND = 0V, VCM = 1.5V, VOUT = 2.5V and RL > 1M unless otherwise specified.
Symbol
Parameter
Conditions
Typical
(1)
LMC6032I
Units
Limit
(2)
SR
Slew Rate
See
(3)
1.1
0.8
0.4
V/μs
min
GBW
Gain-Bandwidth Product
1.4
MHz
φM
Phase Margin
50
Deg
GM
Gain Margin
17
dB
130
dB
Amp-to-Amp Isolation
See (4)
en
Input-Referred Voltage Noise
F = 1 kHz
22
nV/√Hz
in
Input-Referred Current Noise
F = 1 kHz
0.0002
pA/√Hz
Total Harmonic Distortion
F = 10 kHz, AV = −10
RL = 2 kΩ, VO = 8 VPP
±5V Supply
0.01
%
THD
(1)
(2)
(3)
(4)
Typical values represent the most likely parametric normal.
All limits are specified at room temperature (standard type face) or at operating temperature extremes (bold type face).
V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Input referred. V+ = 15V and RL = 10 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP.
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TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±7.5V, TA = 25°C unless otherwise specified
6
Supply Current
vs Supply Voltage
Input Bias Current
Figure 2.
Figure 3.
Output Characteristics
Current Sinking
Output Characteristics
Current Sourcing
Figure 4.
Figure 5.
Input Voltage Noise
vs Frequency
CMRR
vs
Frequency
Figure 6.
Figure 7.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Open-Loop Frequency
Response
Frequency Response
vs Capacitive Load
Figure 8.
Figure 9.
Non-Inverting Large Signal
Pulse Response
Stability vs
Capacitive Load
Figure 10.
Figure 11.
Stability vs
Capacitive Load
Stability vs
Capacitive Load
Figure 12.
Figure 13.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Stability vs
Capacitive Load
Avoid resistive loads of less than 500Ω, as they may cause instability.
Figure 14.
8
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APPLICATION HINTS
AMPLIFIER TOPOLOGY
The topology chosen for the LMC6032, shown in Figure 15, is unconventional (compared to general-purpose op
amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from
the output of the integrator, to allow a larger output swing. Since the buffer traditionally delivers the power to the
load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now
fall to the integrator.
As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed
forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the
integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path
consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain
stages with two fed forward.
Figure 15. LMC6032 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600Ω load.
The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, under
heavy load (600Ω) the gain will be reduced as indicated in the Electrical Characteristics.
COMPENSATING INPUT CAPACITANCE
The high input resistance of the LMC6032 op amps allows the use of large feedback and source resistor values
without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when
these large-value resistors are used.
Every amplifier has some capacitance between each input and AC ground, and also some differential
capacitance between the inputs. When the feedback network around an amplifier is resistive, this input
capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback
resistors create a pole in the feedback path. In the following General Operational Amplifier Circuit, Figure 16, the
frequency of this pole is
where CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray
capacitance from the IC socket (if one is used), circuit board traces, etc., and RPis the parallel combination of RF
and RIN. This formula, as well as all formulae derived below, apply to inverting and non-inverting op-amp
configurations.
When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole will be quite high,
since CSis generally less than 10 pF. If the frequency of the feedback pole is much higher than the “ideal” closedloop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible effect
on stability, as it will add only a small amount of phase shift.
However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3 dB frequency, a feedback
capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can
also be stated in terms of the amplifier's low-frequency noise gain: To maintain stability, a feedback capacitor will
probably be needed if
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where
is the amplifier's low-frequency noise gain and GBW is the amplifier's gain bandwidth product. An amplifier's lowfrequency noise gain is represented by the formula
regardless of whether the amplifier is being used in an inverting or non-inverting mode. Note that a feedback
capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is
large enough that:
the following value of feedback capacitor is recommended:
If
the feedback capacitor should be:
Note that these capacitor values are usually significantly smaller than those given by the older, more
conservative formula:
CS consists of the amplifier's input capacitance plus any stray capacitance from the circuit board and socket. CF
compensates for the pole caused by CS and the feedback resistor.
Figure 16. General Operational Amplifier Circuit
Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may
be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected
stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease
the noise or bandwidth, or simply because the particular circuit implementation needs more feedback
capacitance to be sufficiently stable. For example, a printed circuit board's stray capacitance may be larger or
smaller than the breadboard's, so the actual optimum value for CF may be different from the one estimated using
the breadboard. In most cases, the value of CF should be checked on the actual circuit, starting with the
computed value.
10
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CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC6032 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain
follower. See the Typical Performance Characteristics.
The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole
frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at
low gains. As shown in Figure 17, the addition of a small resistor (50Ω to 100Ω) in series with the op amp's
output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe
value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be
tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near
the threshold for oscillation.
Figure 17. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 18). Typically a pull up
resistor conducting 500 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see DC Electrical
Characteristics).
Figure 18. Compensating for Large Capacitive
Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6032, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6032's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs. See Figure 19. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the
LMC6032's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ω would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the
amplifier's performance. See Figure 20, Figure 21, Figure 22 for typical connections of guard rings for standard
op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still
provide some protection; see Figure 23.
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Figure 19. Example of Guard Ring in
P.C. Board Layout
Figure 20. Inverting Amplifier Guard Ring Connections
Figure 21. Non-Inverting Amplifier Guard Ring Connections
Figure 22. Follower Guard Ring Connections
12
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Figure 23. Howland Current Pump Guard Ring Connections
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 24.
Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.
Figure 24. Air Wiring
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BIAS CURRENT TESTING
The test method of Figure 25 is appropriate for bench-testing bias current with reasonable accuracy. To
understand its operation, first close switch S2 momentarily. When S2 is opened, then
Figure 25. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When
determining the magnitude of Ib−, the leakage of the capacitor and socket must be taken into account. Switch S2
should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2 shorted)
where Cx is the stray capacitance at the + input.
14
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TYPICAL SINGLE-SUPPLY APPLICATIONS
(V+ = 5.0 VDC)
Additional single-supply applications ideas can be found in the LM358 datasheet. The LMC6032 is pin-for-pin
compatible with the LM358 and offers greater bandwidth and input resistance over the LM358. These features
will improve the performance of many existing single-supply applications. Note, however, that the supply voltage
range of the LMC6032 is smaller than that of the LM358.
Figure 26. Instrumentation Amplifier
if R1 = R5;
R3 = R6,
and R4 = R7.
= 100 for circuit shown.
For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects
CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
Figure 27. Sine-Wave Oscillator
This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.0V.
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TYPICAL SINGLE-SUPPLY APPLICATIONS (continued)
+
(V = 5.0 VDC)
Figure 28. Low-Leakage Sample-and-Hold
Figure 29. 1 Hz Square-Wave Oscillator
Figure 30. Power Amplifier
fO = 10 Hz
Q = 2.1
Gain = −8.8
Figure 31. 10 Hz Bandpass Filter
16
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TYPICAL SINGLE-SUPPLY APPLICATIONS (continued)
+
(V = 5.0 VDC)
Figure 32. 1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
fc = 10 Hz
d = 0.895
Gain = 1
2 dB passband ripple
Figure 33. 10 Hz High-Pass Filter
Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV).
Figure 34. High Gain Amplifier with Offset Voltage Reduction
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
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26-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMC6032IM
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 85
LMC60
32IM
LMC6032IM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC60
32IM
LMC6032IMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC60
32IM
LMC6032IN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LMC
6032IN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMC6032IMX/NOPB
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.4
2.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMC6032IMX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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