Texas Instruments | LM148QML Quad 741 Op Amps (Rev. A) | Datasheet | Texas Instruments LM148QML Quad 741 Op Amps (Rev. A) Datasheet

Texas Instruments LM148QML Quad 741 Op Amps (Rev. A) Datasheet
LM148QML
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SNOSAH3A – FEBRUARY 2005 – REVISED MARCH 2013
LM148QML Quad 741 Op Amps
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FEATURES
DESCRIPTION
•
•
The LM148 is a true quad LM741. It consists of four
independent, high gain, internally compensated, low
power operational amplifiers which have been
designed to provide functional characteristics
identical to those of the familiar LM741 operational
amplifier. In addition the total supply current for all
four amplifiers is comparable to the supply current of
a single LM741 type op amp. Other features include
input offset currents and input bias current which are
much less than those of a standard LM741. Also,
excellent isolation between amplifiers has been
achieved by independently biasing each amplifier and
using layout techniques which minimize thermal
coupling.
1
2
•
•
•
•
•
•
•
•
741 Op Amp Operating Characteristics
Class AB Output Stage—No Crossover
Distortion
Pin Compatible with the LM124
Overload Protection for Inputs and Outputs
Low Supply Current Drain: 0.6 mA/Amplifier
Low Input Offset Voltage: 1 mV
Low Input Offset Current: 4 nA
Low Input Bias Current 30 nA
High Degree of Isolation between Amplifiers:
120 dB
Gain Bandwidth Product (Unity Gain): 1.0 MHz
The LM148 can be used anywhere multiple LM741 or
LM1558 type amplifiers are being used and in
applications where amplifier matching or high packing
density is required.
Connection Diagram
Figure 1. Top View
See Package Number J0014A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM148QML
1OUT
N/C
4OUT
4IN-
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1IN-
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3
2
1
20
19
4
18
4IN+
N/C
5
17
N/C
VCC+
6
16
VCC-
1IN+
10
11
12
13
3IN-
3IN+
9
3OUT
N/C
N/C
15
14
2OUT
7
8
2IN-
N/C
2IN+
Figure 2. Top View
See Package Number NAJ0020A
Schematic Diagram
* 1 pF in the LM149
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1)
Supply Voltage
±22V
Differential Input Voltage
±44V
Output Short Circuit Duration (2)
Continuous
Power Dissipation (Pd at 25°C) (3)
1100mW
θJA
Thermal Resistance
θJC
CDIP (Still Air)
103°C/W
CDIP (500LF/ Min Air flow)
52°C/W
LCCC (Still Air)
90°C/W
LCCC (500LF/ Min Air flow)
66°C/W
CDIP
19°C/W
LCCC
21°C/W
Maximum Junction Temperature (TjMAX)
150°C
Operating Temperature Range
−55°C ≤ TA ≤ +125°C
Storage Temperature Range
−65°C ≤ TA ≤ +150°C
Lead Temperature (Soldering, 10 sec.) Ceramic
ESD tolerance
(1)
(2)
(3)
(4)
300°C
(4)
500V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Any of the amplifier outputs can be shorted to ground indefinitely; however, more than one should not be simultaneously shorted as the
maximum junction temperature will be exceeded.
The maximum power dissipation for these devices must be derated at elevated temperatures and is dicated by TJMAX, θJA, and the
ambient temperature, TA. The maximum available power dissipation at any temperature is Pd = (TJMAX − TA)/θJA or the number given in
the Absolute Maximum Ratings, whichever is less.
Human body model, 1.5 kΩ in series with 100 pF
Quality Conformance Inspection
MIL-STD-883, Method 5005 — Group A
Subgroup
Description
1
Static tests at
Temp ( °C)
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
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Electrical Characteristics
DC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.)
VCC = ±15V, RS = 0Ω
Symbol
VIO
IIO
Input Offset Voltage
Input Offset Current
±IIB
Rin
(1)
Parameter
Input Bias Current
Conditions
Notes
VCM = 0V, RS = 50 Ω
VCM = 0V
VCM = 0V
See (1)
Input Resistance
Subgroups
Min
Max
Units
−5
+5
mV
1
−6
+6
mV
2,3
−25
+25
nA
1
−75
+75
nA
2,3
1
100
nA
1
1
325
nA
2,3
0.8
MΩ
1
PSRR+
Power Supply Rejection Ratio
+VCC = +15V and +5V, −VCC = −15V,
RS = 50Ω
77
dB
1, 2, 3
PSRR−
Power Supply Rejection Ratio
+VCC = +15V, −VCC = −15V and −5V,
RS = 50Ω
77
dB
1, 2, 3
CMRR
Common Mode Rejection Ratio
+VCM = ±12V, RS = 50Ω
dB
1, 2, 3
IOS+
Short Circuit Current
−55
−14
mA
1
IOS−
Short Circuit Current
14
55
mA
1
ICC
Power Supply Current
0.4
3.6
mA
1
0.4
4.5
mA
2, 3
50
V/mV
4
25
V/mV
5, 6
50
V/mV
4
25
V/mV
5, 6
RL = 10 kΩ
+12
V
4, 5, 6
RL = 2kΩ
+10
AVS+
Large Signal Voltage Gain
VOUT = 0V to +10V, RL > 2 kΩ
AVS−
Large Signal Voltage Gain
VOUT = 0V to −10V, RL > 2 kΩ
Vout+
Output Voltage Swing
Vout−
Output Voltage Swing
70
V
4, 5, 6
RL = 10 kΩ
−12
V
4, 5, 6
RL = 2kΩ
−10
V
4, 5, 6
Max
Units
Subgroups
V/μs
7, 8A, 8B
MHz
7, 8A, 8B
Parameter specified, Not Tested.
Electrical Characteristics
AC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.)
VCC = ±15V, AV = 1, RS = 0Ω
Symbol
4
Parameter
Conditions
Notes
Min
±SR
Slew Rate
0.2
GBW
Gain Bandwidth Product
0.4
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Cross Talk Test Circuit
VS = ±15V
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Typical Performance Characteristics
6
Supply Current
Input Bias Current
Figure 3.
Figure 4.
Voltage Swing
Positive Current Limit
Figure 5.
Figure 6.
Negative Current Limit
Output Impedance
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Common-Mode Rejection Ratio
Open Loop Frequency Response
Figure 9.
Figure 10.
Bode Plot LM148
Large Signal Pulse Response (LM148)
Figure 11.
Figure 12.
Small Signal Pulse Response (LM148)
Undistorted Output Voltage Swing
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
8
Gain Bandwidth
Slew Rate
Figure 15.
Figure 16.
Inverting Large Signal Pulse Response (LM148)
Input Noise Voltage and Noise Current
Figure 17.
Figure 18.
Positive Common-Mode Input Voltage Limit
Negative Common-Mode Input Voltage Limit
Figure 19.
Figure 20.
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APPLICATION HINTS
The LM148 series are quad low power LM741 op amps. In the proliferation of quad op amps, these are the first
to offer the convenience of familiar, easy to use operating characteristics of the LM741 op amp. In those
applications where LM741 op amps have been employed, the LM148 series op amps can be employed directly
with no change in circuit performance.
The package pin-outs are such that the inverting input of each amplifier is adjacent to its output. In addition, the
amplifier outputs are located in the corners of the package which simplifies PC board layout and minimizes
package related capacitive coupling between amplifiers.
The input characteristics of these amplifiers allow differential input voltages which can exceed the supply
voltages. In addition, if either of the input voltages is within the operating common-mode range, the phase of the
output remains correct. If the negative limit of the operating common-mode range is exceeded at both inputs, the
output voltage will be positive. For input voltages which greatly exceed the maximum supply voltages, either
differentially or common-mode, resistors should be placed in series with the inputs to limit the current.
Like the LM741, these amplifiers can easily drive a 100 pF capacitive load throughout the entire dynamic output
voltage and current range. However, if very large capacitive loads must be driven by a non-inverting unity gain
amplifier, a resistor should be placed between the output (and feedback connection) and the capacitance to
reduce the phase shift resulting from the capacitive loading.
The output current of each amplifier in the package is limited. Short circuits from an output to either ground or the
power supplies will not destroy the unit. However, if multiple output shorts occur simultaneously, the time
duration should be short to prevent the unit from being destroyed as a result of excessive power dissipation in
the IC chip.
As with most amplifiers, care should be taken lead dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to an input should be placed with the body close to the
input to minimize “pickup” and maximize the frequency of the feedback pole which capacitance from the input to
ground creates.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.
In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed
loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less
than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to
the input of the op amp. The value of the added capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.
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Typical Applications—LM148
fMAX = 5 kHz, THD ≤ 0.03%
R1 = 100k pot. C1 = 0.0047 μF, C2 = 0.01 μF, C3 = 0.1 μF, R2 = R6 = R7 = 1M,
R3 = 5.1k, R4 = 12Ω, R5 = 240Ω, Q = NS5102, D1 = 1N914, D2 = 3.6V avalanche
diode (ex. LM103), VS = ±15V
A simpler version with some distortion degradation at high frequencies can be made by using A1 as a simple inverting
amplifier, and by putting back to back zeners in the feedback loop of A3.
Figure 21. One Decade Low Distortion Sinewave Generator
VS = ±15V
R = R2, trim R2 to boost CMRR
Figure 22. Low Cost Instrumentation Amplifier
10
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Adjust R for minimum drift
D3 low leakage diode
D1 added to improve speed
VS = ±15V
Figure 23. Low Drift Peak Detector with Bias Current Compensation
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Tune Q through R0,
For predictable results: fO Q ≤ 4 × 104
Use Band Pass output to tune for Q
Figure 24. Universal State-Variable Filter
12
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Use general equations, and tune each section separately
Q1stSECTION = 0.541, Q2ndSECTION = 1.306
The response should have 0 dB peaking
Figure 25. A 1 kHz 4 Pole Butterworth
Figure 26.
Ex: fNOTCH = 3 kHz, Q = 5, R1 = 270k, R2 = R3 = 20k, R4 = 27k, R5 = 20k, R6 = R8 = 10k, R7 = 100k, C1 = C2 =
0.001 μF
Better noise performance than the state-space approach.
Figure 27. A 3 Amplifier Bi-Quad Notch Filter
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R1C1 = R2C2 = t
R′1C′1 = R′2C′2 = t′
fC = 1 kHz, fS = 2 kHz, fp = 0.543, fZ = 2.14, Q = 0.841, f′ P = 0.987, f′ Z = 4.92, Q′ = 4.403, normalized to ripple BW
Use the BP outputs to tune Q, Q′, tune the 2 sections separately
R1 = R2 = 92.6k, R3 = R4 = R5 = 100k, R6 = 10k, R0 = 107.8k, RL = 100k, RH = 155.1k,
R′1 = R′2 = 50.9k, R′4 = R′5 = 100k, R′6 = 10k, R′0 = 5.78k, R′L = 100k, R′H = 248.12k, R′f = 100k. All capacitors
are 0.001 μF.
Figure 28. A 4th Order 1 kHz Elliptic Filter (4 Poles, 4 Zeros)
Figure 29. Lowpass Response
14
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Typical Simulation
For more details, see IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 6, December 1974
o1
= 112IS = 8 × 10−16
o2
= 144*C2 = 6 pF for LM149
Figure 30. LM148, LM741 Macromodel for Computer Simulation
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REVISION HISTORY SECTION
Date
Released
Revision
Section
Originator
Changes
L. Lytle
1 MDS data sheet converted into one Corp.
data sheet format. MNLM148-X, Rev. 2A2.
MDS data sheet will be archived.
02/08/05
A
New Release, Corporate format
03/20/13
A
All
16
Changed layout of National Data Sheet to TI
format
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PACKAGE OPTION ADDENDUM
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2-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM148 MD8
ACTIVE
DIESALE
Y
0
100
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-55 to 125
LM148J/883
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
-55 to 125
LM148J/883 Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
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EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
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