Texas Instruments | Wideband Low-Distortion Fully Differential Amplifiers (Rev. A) | Datasheet | Texas Instruments Wideband Low-Distortion Fully Differential Amplifiers (Rev. A) Datasheet

Texas Instruments Wideband Low-Distortion Fully Differential Amplifiers (Rev. A) Datasheet
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THS4503−EP
SGLS291A − APRIL 2005 − JANUARY 2012
WIDEBAND, LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIERS
FEATURES
D Controlled Baseline
D One Assembly/Test Site, One Fabrication Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
D
D
D
D
D
D
D
D
Enhanced Product-Change Notification
Qualification Pedigree(1)
Preamplifier
Wireless Communication Receiver Chains
Single-Ended to Differential Conversion
D
D
D Differential Line Driver
D Active Filtering of Differential Signals
VIN−
1
8
VIN+
Bandwidth: 370 MHz
VOCM
2
7
NC
Slew Rate: 2800 V/μs
VS+
3
6
VS−
VOUT+
4
5
VOUT−
Fully Differential Architecture
IMD3: −95 dBc at 30 MHz
OIP3: 51 dBm at 30 MHz
Output Common-Mode Control
Wide Power Supply Voltage Range: 5 V, ±5 V,
12 V, 15 V
D Centered Input Common-Mode Range
D Evaluation Module Available
(1)
APPLICATIONS
D High Linearity Analog-to-Digital Converter
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperaturerange. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life.
RELATED DEVICES
DEVICE(1)
DESCRIPTION
THS4500/1
370 MHz, 2800 V/μs, VICR Includes VS−
THS4502/3
370 MHz, 2800 V/μs, Centered VICR
THS4120/1
3.3 V, 100 MHz, 43 V/μs, 3.7 nV√Hz
THS4130/1
±15 V, 150 MHz, 51 V/μs, 1.3 nV√Hz
THS4140/1
±15 V, 160 MHz, 450 V/μs, 6.5 nV√Hz
THS4150/1
±15 V, 150 MHz, 650 V/μs, 7.6 nV√Hz
(1)
Even numbered devices feature power-down capability
DESCRIPTION
The THS4503 is a high-performance fully differential amplifier from Texas Instruments. The THS4503, without
power-down capability, set new performance standards for fully differential amplifiers with unsurpassed linearity,
supporting 14-bit operation through 40 MHz. Package options include the 8-pin MSOP with PowerPAD™ for a smaller
footprint, enhanced ac performance, and improved thermal dissipation capability.
WARNING:
The THS4503 may have low−level oscillation when the die temperature (also known as the junction
temperature) exceeds 605C. These devices are not recommended for new designs where the die temperature
is expected to exceed 605C. For more information, see Maximum Die Temperature to Oscillation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA
information current as of publication date. Products conform to specifications per
the terms of Texas Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
Copyright © 2005 − 2012, Texas Instruments Incorporated
THS4503−EP
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10 pF
392 Ω
5V
VS
0.1 μF 10 μF
374 Ω
50 Ω
5V
+
56.2 Ω
1 μF
−
VOCM
+
−
402 Ω
24.9 Ω
THS4503
24.9 Ω
−5 V
IN ADC
14 Bit/80 MSps
IN Vref
0.1 μF 10 μF
392 Ω
10 pF
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
16.5 V
Supply voltage, VS
±VS
Input voltage, VI
Output current, IO (2)
150 mA
4V
Differential input voltage, VID
Continuous power dissipation
See Dissipation Rating Table
Maximum junction temperature, TJ (3)
150°C
Maximum junction temperature, continuous
operation, long term reliability TJ (4)
125°C
Maximum junction temperature, to prevent
oscillation TJ (5)
60°C
Operating free-air temperature range, TA
−55°C to 60°C
Storage temperature range, Tstg
−65°C to 150°C
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings:
300°C
HBM
4000 V
CDM
2000 V
MM
100 V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) The THS450x may incorporate a PowerPAD on the underside of
the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See
Texas Instruments technical brief SLMA002 for more information
about utilizing the PowerPAD thermally enhanced package.
(3) The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
(4) Long-term high-temperature storage and/or extended use at
maximum recommended operating conditions may result in a
reduction of overall device life. See Figure 1 for additional
information on thermal derating.
(5)
2
See Maximum Die Temperature to Prevent Oscillation section in
the Application Information of this data sheet.
THIRD-ORDER INTERMODULATION
DISTORTION
−62
10
392 Ω
374 Ω
50 Ω
−68
2.5 V
56.2 Ω
VS
−74
402 Ω
5V
VOUT
+−
VOCM
800 Ω
−+
12
−5 V
392 Ω
Bits
IMD 3 − Third-Order Intermodulation Distortion − dBc
APPLICATION CIRCUIT DIAGRAM
−80
−86
14
−92
−98
0
20
40
60
80
100
16
f − Frequency − MHz
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE DISSIPATION RATINGS
(1)
PACKAGE
θJC
(°C/W)
( )
θJA(1)
(°C/W)
DGN (8 pin)
4.7
58.4
This data was taken using the JEDEC standard High-K test PCB.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage
Dual supply
Single supply
4.5
Operating free-air temperature, TA
−55
NOM
MAX
±5
±7.5
5
15
60
UNIT
V
°C
THS4503−EP
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SGLS291A − APRIL 2005 − JANUARY 2012
WIREBOND LIFE
vs
JUNCTION TEMPERATURE
1G
Time-to-Fail − Hrs
100M
80°C, 74M Hrs
10M
100°C, 5.9M Hrs
1M
120°C, 490K Hrs
100K
140°C, 58K Hrs
10K
80
90
100
110
120
130
140
150
TJ − Junction Temperature − °C
Figure 1. EME−G600 Estimated Wirebond Life
PACKAGE/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER
PLASTIC MSOP(1)
PowerPAD
TEMPERATURE
−55°C to 60°C
(1)
(DGN)
SYMBOL
THS4503MDGNREP
BLB
All packages are available taped and reeled. The R suffix standard quantity is 2500.
PIN ASSIGNMENTS
THS4503
(TOP VIEW)
DGN
V IN−
1
8
V IN+
2
7
NC
V S+
3
6
V S−
V OUT+
4
5
V OUT−
V OCM
3
THS4503−EP
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ELECTRICAL CHARACTERISTICS VS = ±5 V
Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted
THS4503
PARAMETER
TEST CONDITIONS
TYP
25°C
OVER TEMPERATURE(1)
25°C
−55°C
TO 60°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
Small signal bandwidth
Small-signal
G = +1, PIN= −20 dBm, Rf = 392 Ω
370
G = +2, PIN= −30 dBm, Rf = 1 kΩ
175
G = +5, PIN= −30 dBm, Rf = 1.3 kΩ
70
MHz
Typ
G = +10, PIN = −30 dBm, Rf = 1.3 kΩ
30
Gain-bandwidth product
G > +10
300
MHz
Typ
Bandwidth for 0.1dB flatness
PIN = −20 dBm
150
MHz
Typ
Large-signal bandwidth
VP = 2 V
220
MHz
Typ
Slew rate
4 VPP Step
2800
V/μs
Typ
Rise time
2 VPP Step
0.8
ns
Typ
Fall time
2 VPP Step
0.6
ns
Typ
Settling time to 0.01%
VO = 4 VPP
8.3
ns
Typ
Settling time to 0.1%
VO = 4 VPP
6.3
ns
Typ
Harmonic distortion
G = +1, VO = 2 VPP
f = 8 MHz
−83
dBc
Typ
f = 30 MHz
−74
dBc
Typ
f = 8 MHz
−97
dBc
Typ
f = 30 MHz
−78
dBc
Typ
Third-order intermodulation distortion
VO = 2VPP, fc = 30 MHz,
Rf = 392 Ω, 200-kHz tone spacing
−94
dBc
Typ
Third-order output intercept point
fc = 30 MHz, Rf = 392 Ω,
Referenced to 50 Ω
52
dBm
Typ
Input voltage noise
f > 1 MHz
6.8
nV/√Hz
Typ
Input current noise
f > 100 kHz
1.7
pA/√Hz
Typ
Overdrive recovery time
Overdrive = 5.5 V
75
ns
Typ
2nd harmonic
3rd harmonic
Typ
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
VOD = ±4 V, VOCM = 0 V
55
52
48
dB
Min
−1
±6
±7
mV
Max
±10
μV/°C
Typ
4
4.6
5.4
μA
Max
±10
nA/°C
Typ
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
0.5
1
Average offset current drift
2
μA
Max
±40
nA/°C
Typ
V
Min
INPUT
Common-mode input range
Common-mode rejection ratio
Input impedance
VICM = ±0.5 V, VOCM = 0 V
±4.0
±3.7
±3.4
80
74
70
107 || 1
dB
Min
Ω || pF
Typ
OUTPUT
Differential output voltage swing
RL = 399 Ω
±8
±7.6
±7.4
V
Min
Differential output current drive
RL = 20 Ω
120
110
100
mA
Min
Output balance error
PIN = −20 dBm, f = 100 kHz
−58
dB
Typ
Closed-loop output impedance (single-ended)
f = 1 MHz
0.1
Ω
Typ
4
THS4503−EP
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ELECTRICAL CHARACTERISTICS VS = ±5 V
Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted
THS4503
PARAMETER
TEST CONDITIONS
TYP
25°C
OVER TEMPERATURE(1)
−55°C
TO 60°C
25°C
UNITS
MIN/
TYP/
MAX
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
RL = 400 Ω
180
MHz
Typ
Slew rate
2 VPP step
87
V/μs
Typ
Minimum gain
1
0.98
0.98
V/V
Min
Maximum gain
1
1.02
1.02
V/V
Max
Common-mode offset voltage
Input bias current
VOCM = 2.5 V
+2
±7.5
±9.9
mV
Max
100
150
170
μA
Max
±4
±3.7
±3.4
V
Min
kΩ || pF
Typ
Input voltage range
Input impedance
25 || 1
Maximum default voltage
VOCM left floating
0
0.05
0.1
V
Max
Minimum default voltage
VOCM left floating
0
−0.05
−0.1
V
Min
Specified operating voltage
±5
±7.5
±7.5
V
Max
Maximum quiescent current
23
28
34
mA
Max
Minimum quiescent current
23
16
10
mA
Min
80
76
70
dB
Min
POWER SUPPLY
Power supply rejection (±PSRR)
(1)
VS+ = 4 V to 5 V, VS− = −5 V to −4 V
See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet.
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted
THS4503
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
25°C
−55°C
TO 60°C
25°C
UNITS
MIN /
TYP /
MAX
AC PERFORMANCE
Small signal bandwidth
Small-signal
G = +1, PIN = −20 dBm, Rf = 392 Ω
320
G = +2, PIN = −30 dBm, Rf = 1 kΩ
160
G = +5, PIN = −30 dBm, Rf = 1.3 kΩ
60
MHz
Typ
G = +10, PIN = −30 dBm, Rf = 1.3 kΩ
30
Gain-bandwidth product
G > +10
300
MHz
Typ
Bandwidth for 0.1-dB flatness
PIN = −20 dBm
180
MHz
Typ
Large-signal bandwidth
VP = 1 V
200
MHz
Typ
Slew rate
2 VPP Step
1300
V/μs
Typ
Rise time
2 VPP Step
0.6
ns
Typ
Fall time
2 VPP Step
0.8
ns
Typ
Settling time to 0.01%
VO = 2 V Step
13.1
ns
Typ
Settling time to 0.1%
VO = 2 V Step
8.3
ns
Typ
Harmonic distortion
VO = 2 VPP
Typ
f = 8 MHz,
−81
f = 30 MHz
−60
f = 8 MHz
−74
f = 30 MHz
−62
Input voltage noise
f > 1 MHz
Input current noise
f > 100 kHz
Overdrive recovery time
Overdrive = 5.5 V
2nd harmonic
3rd harmonic
dBc
Typ
dBc
Typ
6.8
nV/√Hz
Typ
1.6
pA/√Hz
Typ
75
ns
Typ
5
THS4503−EP
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SGLS291A − APRIL 2005 − JANUARY 2012
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted
THS4503
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
25°C
25°C
−55°C
TO 60°C
UNITS
MIN /
TYP /
MAX
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
VOD = ±1 V, VOCM = 2.5 V
54
51
48
dB
Min
−0.6
±5
±6.5
mV
Max
±10
μV/°C
Typ
4
4.6
5.2
μA
Max
±10
nA/°C
Typ
0.5
0.7
1.2
μA
Max
±20
nA/°C
Typ
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
INPUT
Common-mode input range
Common-mode rejection ratio
Input impedance
VICM = 2.25 V to 2.75 V,
VOCM = 2.5 V
1/4
1.3 / 3.7
1.6 / 3.4
V
Min
80
74
60
dB
Min
Ω || pF
Typ
107 || 1
OUTPUT
Differential output voltage swing
RL = 399 Ω, Referenced to 2.5 V
±3.3
±2.8
±2.6
V
Min
Output current drive
RL = 20 Ω
100
90
80
mA
Min
Output balance error
PIN = −20 dBm, f = 100 kHz
−58
dB
Typ
Closed-loop output impedance (single ended)
f = 1 MHz
0.1
Ω
Typ
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
RL = 400 Ω
180
MHz
Typ
Slew rate
2 VPP Step
80
V/μs
Typ
Minimum gain
1
0.98
0.98
V/V
Min
Maximum gain
1
1.02
1.02
V/V
Max
2
±6.7
±9.2
mV
Max
1
2
3
μA
Max
1/4
1.2/3.8
1.3/3.7
V
Min
Common-mode offset voltage
Input bias current
VOCM = 2.5 V
Input voltage range
Input impedance
25 || 1
kΩ || pF
Typ
Maximum default voltage
VOCM left floating
2.5
2.55
2.6
V
Max
Minimum default voltage
VOCM left floating
2.5
2.45
2.4
V
Min
Specified operating voltage
5
15
15
V
Max
Maximum quiescent current
20
25
31
mA
Max
Minimum quiescent current
20
15
8
mA
Min
75
72
66
dB
Min
POWER SUPPLY
Power supply rejection (+PSRR)
6
VS+ = 4.5 V to 5.5 V
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TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small signal unity gain frequency response
1
Small signal frequency response
2
0.1 dB gain flatness frequency response
3
Harmonic distortion (single-ended input to differential output) vs Frequency
4, 6, 12, 14
Harmonic distortion (differential input to differential output) vs Frequency
5, 7, 13, 15
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
8, 10, 16, 18
Harmonic distortion (differential input to differential output) vs Output voltage swing
9, 11, 17, 19
Harmonic distortion (single-ended input to differential output) vs Load resistance
20
Harmonic distortion (differential input to differential output) vs Load resistance
21
Third order intermodulation distortion (single-ended input to differential output) vs Frequency
22
Third order output intercept point vs Frequency
23
Slew rate vs Differential output voltage step
Settling time
24
25, 26
Large-signal transient response
27
Small-signal transient response
28
Overdrive recovery
29, 30
Voltage and current noise vs Frequency
31
Rejection ratios vs Frequency
32
Rejection ratios vs Case temperature
33
Output balance error vs Frequency
34
Open-loop gain and phase vs Frequency
35
Open-loop gain vs Case temperature
36
Input bias and offset current vs Case temperature
37
Quiescent current vs Supply voltage
38
Input offset voltage vs Case temperature
39
Common-mode rejection ratio vs Input common-mode range
40
Differential output current drive vs Case temperature
41
Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage
42
Small signal frequency response at VOCM
43
Output offset voltage at VOCM vs Output common-mode voltage
44
Quiescent current vs Power-down voltage
45
Turnon and turnoff delay times
46
Single-ended output impedance in power down vs Frequency
47
Power-down quiescent current vs Case temperature
48
Power-down quiescent current vs Supply voltage
49
7
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TYPICAL CHARACTERISTICS
Table of Graphs (5 V)
FIGURE
Small signal unity gain frequency response
50
Small signal frequency response
51
0.1 dB gain flatness frequency response
52
Harmonic distortion (single-ended input to differential output) vs Frequency
53, 54, 61, 63
Harmonic distortion (differential input to differential output) vs Frequency
55, 56, 62, 64
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
57, 58, 65, 67
Harmonic distortion (differential input to differential output) vs Output voltage swing
59, 60, 66, 68
Harmonic distortion (single-ended input to differential output) vs Load resistance
69
Harmonic distortion (differential input to differential output) vs Load resistance
70
Slew rate vs Differential output voltage step
71
Large-signal transient response
72
Small-signal transient response
73
Voltage and current noise vs Frequency
74
Rejection ratios vs Frequency
75
Rejection ratios vs Case temperature
76
Output balance error vs Frequency
77
Open-loop gain and phase vs Frequency
78
Open-loop gain vs Case temperature
79
Input bias and offset current vs Case temperature
80
Quiescent current vs Supply voltage
81
Input offset voltage vs Case temperature
82
Common-mode rejection ratio vs Input common-mode range
83
Output drive vs Case temperature
84
Harmonic distortion (single-ended and differential input) vs Output common-mode range
85
Small signal frequency response at VOCM
86
Output offset voltage vs Output common-mode voltage
87
Quiescent current vs Power-down voltage
88
Turnon and turnoff delay times
89
Single-ended output impedance in power down vs Frequency
90
Power-down quiescent current vs Case temperature
91
Power-down quiescent current vs Supply voltage
92
8
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TYPICAL CHARACTERISTICS (±5 V Graphs)
1
22
0.5
20
−1
−1.5
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = ±5 V
−4
0.1
1
14
12
10
8
Gain = 2, Rf = 1 kΩ
6
4
2
10
100
0
−2
0.1
1000
f − Frequency − MHz
−40
−50
−60
−70
HD2
−80
−90
1
10
f − Frequency − MHz
−20
−30
−40
−50
100
−30
−40
−50
−10
−60
HD2
−80
HD3
−90
−100
0.1
−20
−30
−40
−50
1
10
f − Frequency − MHz
100
Figure 8
−20
−30
−40
−50
−60
−70
100
HD3
1
10
100
Figure 7
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
0
−10
−60
HD2
−80
HD3
−20
−30
−40
−50
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VO − Output Voltage Swing − V
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
−60
−70
HD2
−80
HD3
−90
−100
Figure 9
HD2
−80
f − Frequency − MHz
−100
1
10
f − Frequency − MHz
1000
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
−100
0.1
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−90
100
−90
HD3
−70
10
HARMONIC DISTORTION
vs
FREQUENCY
0
HD2
−80
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
−70
1
Figure 6
Harmonic Distortion − dBc
−20
−0.4
−10
−70
−100
0.1
HARMONIC DISTORTION
vs
FREQUENCY
−10
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = ±5 V
Figure 4
−60
Figure 5
0
−0.3
f − Frequency − MHz
−90
HD3
0.1
Rf = 499 Ω
−0.2
−0.5
1000
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
−10
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−30
100
HARMONIC DISTORTION
vs
FREQUENCY
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
−20
10
Rf = 392 Ω
−0.1
Figure 3
HARMONIC DISTORTION
vs
FREQUENCY
0
1
0
f − Frequency − MHz
Figure 2
−10
RL = 800 Ω
PIN = −30 dBm
VS = ±5 V
Harmonic Distortion − dBc
−3
Gain = 5, Rf = 1.3 kΩ
Harmonic Distortion − dBc
−2.5
16
0.1 dB Gain Flatness − dB
−0.5
−3.5
Harmonic Distortion − dBc
0.1
Gain = 10, Rf = 1.3 kΩ
18
0
−100
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
Small Signal Gain − dB
Small Signal Unity Gain − dB
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VO − Output Voltage Swing − V
Figure 10
9
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
TYPICAL CHARACTERISTICS (±5 V Graphs)
−40
−50
HD3
−60
−70
HD2
−80
−90
−100
0
1
2
3
4
5
VO − Output Voltage Swing − V
−30
−40
−50
HD3
−60
−70
HD2
−80
Harmonic Distortion − dBc
−20
−30
−40
−50
0
1
HD3
−30
−40
−50
6
−70
0
−60
HD3
−70
−80
HD2
1
10
f − Frequency − MHz
3
4
5
6
7
8
VO − Output Voltage Swing − V
Figure 17
−20
−30
−40
−50
−60
HD2
−70
−80
HD3
−100
0.1
100
1
−40
−50
−60
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
9
10
−70
−100
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 30 MHz
VS = ±5 V
−10
HD3
−80
100
Figure 16
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = ±5 V
−30
10
f − Frequency − MHz
HD2
−90
2
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
−90
HD3
−20
100
HARMONIC DISTORTION
vs
FREQUENCY
−10
−80
0
10
Figure 13
HD2
−10
−50
1
1
f − Frequency − MHz
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = ±5 V
0
HD3
0.1
Figure 15
Harmonic Distortion − dBc
Harmonic Distortion − dBc
5
−60
−100
0.1
100
−90
10
4
−90
HD2
1
10
f − Frequency − MHz
−20
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−100
3
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
Figure 14
−40
2
HD2
−80
VO − Output Voltage Swing − V
0
−90
−30
−70
−100
−10
−80
−20
−60
HARMONIC DISTORTION
vs
FREQUENCY
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
−70
0
−50
Figure 12
−60
−10
−40
−90
HARMONIC DISTORTION
vs
FREQUENCY
−100
0.1
−30
−100
6
Harmonic Distortion − dBc
0
−20
−90
Figure 11
−10
Harmonic Distortion − dBc
−30
−20
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
−10
Harmonic Distortion − dBc
−20
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 30 VPP
VS = ±5 V
−10
Harmonic Distortion − dBc
−10
Harmonic Distortion − dBc
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−20
−30
−40
−50
−60
HD3
HD2
−70
−80
−90
0
1
2 3 4
5 6 7 8 9
VO − Output Voltage Swing − V
Figure 18
10
−100
0
1
2
3
4
5
6
7
8
VO − Output Voltage Swing − V
Figure 19
9
10
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
TYPICAL CHARACTERISTICS (±5 V Graphs)
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = ±5 V
−30
−40
−50
HD3
−60
HD2
−70
−20
−80
−30
−40
−50
−60
HD2
−70
−80
−90
HD3
−90
−100
0
1
2
3
4
5
6
7
8
9
−100
10
400
Figure 20
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
VS = ±5 V
Tone Spacing = 200 kHz
−80
−90
−100
10
f − Frequency − MHz
−80
HD3
1600
0
400
40
OIP3 RL= 800 Ω
30
Gain = 1
Rf = 392 Ω
VS = ± 5 V
Tone Spacing = 200 kHz
25
20
3000
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
2000
1500
1000
500
15
0
0
10 20 30 40 50 60 70 80 90 100
0
0.5
VO − Output Voltage − V
Falling Edge
−1
2
2.5
3
3.5
4
Figure 25
LARGE-SIGNAL TRANSIENT RESPONSE
Rising Edge
1.5
−0.5
1.5
3
2
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
1
VO − Differential Output Voltage Step − V
SETTLING TIME
2.5
1600
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
2500
45
35
1200
Figure 22
Normalized to 50 Ω
50
800
RL − Load Resistance − Ω
Figure 24
1
0
1200
HD2
−70
f − Frequency − MHz
SETTLING TIME
0.5
−60
Normalized to 200 Ω
55
100
Rising Edge
VO − Output Voltage − V
800
60
Figure 23
1.5
−50
−90
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Third-Order Output Intersept Point − dBm
Third-Order Intermodulation Distortion − dBc
−70
−40
Figure 21
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
−60
−30
RL − Load Resistance − Ω
VO − Output Voltage Swing − V
−50
−20
−100
0
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
−10
SR − Slew Rate − V/ μ s
−20
HARMONIC DISTORTION
vs
LOAD RESISTANCE
0
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
2
VO − Output Voltage − V
Harmonic Distortion − dBc
−10
0
−10
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
LOAD RESISTANCE
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
1
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
0.5
0
−0.5
−1
−1.5
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
1
0
−1
−2
Falling Edge
−2
−1.5
0
5
10
t − Time − ns
Figure 26
15
20
−2.5
0
5
10
t − Time − ns
Figure 27
15
20
−3
−100
0
100
200
300
400
500
t − Time − ns
Figure 28
11
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
TYPICAL CHARACTERISTICS (±5 V Graphs)
4
0
−0.1
−0.2
−0.3
−0.4
−100
0
100
200
300
400
3
2
1
0
0
−1
−0.5
−2
−1
−3
−1.5
−4
−2
−2.5
0
50
CMMR
PSRR−
40
30
20
10
100
1000
−10
10 k
0.1
60
70
PIN = −30 dBm
RL = 800 Ω
Rf = 100 kΩ
VS = ±5 V
−40
−50
−60
40
PSRR−
60
50
40
30
RL = 800 Ω
VS = ±5 V
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
100
Case Temperature − °C
Figure 34
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
50
PSRR+
10
1
10
f − Frequency − MHz
Gain
PIN = −20 dBm
RL = 800 Ω
Rf = 499 Ω
VS = ±5 V
−3
CMMR
20
RL = 800 Ω
VS = ±5 V
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
30
57
55
−30
−60
30
Phase
RL = 800 Ω
VS = ±5 V
56
0
Phase − °
OUTPUT BALANCE ERROR
vs
FREQUENCY
−30
−70
0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 33
Open-Loop Gain − dB
−20
0
80
Figure 32
−10
−2
90
60
f − Frequency − kHz
0
−4
100
PSRR+
0
10
−1
REJECTION RATIOS
vs
CASE TEMPERATURE
Rejection Ratios − dB
Hz
I n − Current Noise − pA/
In
1
−2
t − Time − μs
70
Rejection Ratios − dB
Hz
Vn − Voltage Noise − nV/
Vn
1
Figure 31
90
10
2
0
REJECTION RATIOS
vs
FREQUENCY
80
3
0
t − Time − μs
100
0.1
2
Figure 30
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
1
0.01
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
4
−6
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − ns
Output Balance Error − dB
1.5
0.5
Figure 29
20
−90
10
−120
54
53
52
51
50
49
1
10
f − Frequency − MHz
Figure 35
12
2
1
−5
500
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
6
Open-Loop Gain − dB
VO − Output Voltage − V
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0.1
2.5
VI − Input Voltage − V
0.3
Single-Ended Output Voltage − V
5
0.2
OVERDRIVE RECOVERY
OVERDRIVE RECOVERY
0.4
VI − Input Voltage − V
Single-Ended Output Voltage − V
SMALL-SIGNAL TRANSIENT RESPONSE
100
0
0.01
0.1
1
10
f − Frequency − MHz
Figure 36
100
−150
1000
48
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 37
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
TYPICAL CHARACTERISTICS (±5 V Graphs)
0.13
IIB−
1.75
0.12
1.5
0.11
IIB+
1.25
0.1
1
0.09
IOS
0.75
0.08
0.5
0.07
0.25
0.06
30
20
TA = −40°C
15
10
5
0
Case Temperature − °C
0 0.5
1
80
70
60
50
40
30
20
10
0
2
4
6
Case Temperature − °C
Figure 40
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
0
−50
0
−1
Sink
−100
−20
−30
−2
−40
−50
100
1000
HD3-SE and Diff
−60
HD2-Diff
−70
HD2-SE
−80
−90
0.5
1.5
2.5
3.5
Figure 43
OUTPUT OFFSET VOLTAGE AT VOCM
vs
OUTPUT COMMON-MODE VOLTAGE
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
600
30
400
25
200
0
−600
−1.5 −0.5
VOC − Output Common-Mode Voltage − V
Case Temperature − °C
−400
f − Frequency − MHz
Single-Ended and Differential
Input to Differential Output
Gain = 1, VO = 2 VPP
f= 8 MHz, Rf = 499 Ω
VS = ±5 V
−100
−3.5 −2.5
−150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−200
Figure 44
0
−10
50
VOS − Output Offset Voltage at VOCM− mV
Small Signal Frequency Response at VOCM − dB
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = ±5 V
10
0.5
Figure 42
3
1
1
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
5
100
SMALL SIGNAL FREQUENCY RESPONSE
AT VOCM
−3
4 4.5
Source
150
Figure 41
1
3.5
Quiescent Current − mA
−2
VS = ±5 V
Input Common-Mode Voltage Range − V
2
3
DIFFERENTIAL OUTPUT CURRENT DRIVE
vs
CASE TEMPERATURE
Differential Output Current Drive − mA
CMRR − Common-Mode Rejection Ratio − dB
90
−4
2.5
200
VS = ±5 V
−6
2
1.5
Figure 39
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
0
−10
1.5
2
VS − Supply Voltage − ±V
Figure 38
110
VS = ±5 V
TA = 25°C
25
0.05
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
100
2.5
TA = 85°C
Harmonic Distortion − dBc
2
Quiescent Current − mA
VS = ±5 V
I OS − Input Offset Current − μ A
I IB − Input Bias Current − μ A
35
0.14
2.25
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
VOS − Input Offset Voltage − mV
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
20
15
10
5
0
−5 −4 −3 −2 −1
0
1
2
3
4
VOC − Output Common-Mode Voltage − V
Figure 45
5
−5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0
Power-Down Voltage − V
Figure 46
13
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
TYPICAL CHARACTERISTICS (±5 V Graphs)
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN
vs
FREQUENCY
1000
0.01
Current
0
0
−1
−2
−3
−4
−5
−6
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
102
1.4
Power-Down Quiescent Current − mA
1100
0.02
Quiescent Current − mA
0.03
ZO− Single-Ended Output Impedance
in Power Down −Ω
Powerdown Voltage Signal − V
TURNON AND TURNOFF DELAY TIMES
900
800
700
600
500
400
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −1 dBm
VS = ±5 V
300
200
100
0
0.1
103
1
10
100
f − Frequency − MHz
Figure 47
1000
Power-Down Quiescent Current − μ A
1000
RL = 800 Ω
800
700
600
500
400
300
200
100
0
0.5 1
1.5 2
2.5 3
3.5 4
VS − Supply Voltage − ±V
Figure 50
14
RL = 800 Ω
VS = ±5 V
1
0.8
0.6
0.4
0.2
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Figure 49
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
0
1.2
Case Temperature − °C
Figure 48
900
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
4.5 5
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
TYPICAL CHARACTERISTICS (5 V Graphs)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
22
1
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = 5 V
0.1
1
12
10
8
Gain = 2, Rf = 1 kΩ
6
4
2
10
100
0
−2
0.1
1000
RL = 800 Ω
PIN = −30 dBm
VS = 5 V
1
Figure 51
0
−40
−50
−60
−70
−80
HD3
HD2
−90
−100
0.1
1
10
−20
−30
−40
−50
−70
−40
−50
−60
−70
HD3
−80
HD2
−90
−100
0.1
1
10
f − Frequency − MHz
Figure 57
0
−20
−30
−40
−50
1
−30
−40
−50
−70
−80
10
100
Figure 55
Figure 56
0
HD2
2.5
3
3.5 4
VO − Output Voltage Swing − V
Figure 58
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = 5 V
−20
−30
−40
−50
HD3
−60
HD2
−70
−80
−90
−100
1.5 2
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−10
−80
1
1
f − Frequency − MHz
−70
0.5
HD3
−100
0.1
100
HD3
0
HD2
−60
f − Frequency − MHz
−60
−100
−20
−90
10
−90
100
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
−10
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
−10
1000
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
100
f − Frequency − MHz
HD2
−100
0.1
100
Harmonic Distortion − dBc
−30
10
1
Figure 53
−90
HARMONIC DISTORTION
vs
FREQUENCY
−20
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = 5 V
−0.5
1000
HD3
−80
Figure 54
−10
100
−60
f − Frequency − MHz
0
10
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
−10
Harmonic Distortion − dBc
−30
−0.3
HARMONIC DISTORTION
vs
FREQUENCY
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
−20
Rf = 392 Ω
−0.2
Figure 52
HARMONIC DISTORTION
vs
FREQUENCY
0
−0.1
f − Frequency − MHz
f − Frequency − MHz
−10
0
−0.4
Harmonic Distortion − dBc
−4
Gain = 5, Rf = 1.3 kΩ
14
Harmonic Distortion − dBc
−3
16
0.1 dB Gain Flatness − dB
Small Signal Gain − dB
Small Signal Unity Gain − dB
−1
Rf = 499 Ω
0.1
18
0
Harmonic Distortion − dBc
0.2
Gain = 10, Rf = 1.3 kΩ
20
Harmonic Distortion − dBc
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
4.5
5
0
0.5
1
1.5 2
2.5
3
3.5 4
4.5
5
VO − Output Voltage Swing − V
Figure 59
15
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
TYPICAL CHARACTERISTICS (5 V Graphs)
−30
−40
−50
HD3
−60
−70
−80
HD2
−90
−100
0
0.5
1
1.5 2
2.5
3
3.5 4
4.5
5
−20
−30
−40
−50
HD2
−70
−80
−40
−50
0
0.5
0
HD3
HD2
1
−20
−30
−40
−50
1
10
f − Frequency − MHz
−70
−50
HD3
−70
0.1
HD2
−50
2.5
3
Figure 66
1
10
f − Frequency − MHz
3.5 4
4.5
5
0
−20
−30
−40
−50
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
−60
HD3
−70
−80
HD2
−100
0.1
100
1
10
f − Frequency − MHz
0
−80
HD2
1
1.5 2
2.5
3
3.5 4
VO − Output Voltage Swing − V
Figure 67
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 30 MHz
VS = 5 V
−10
−70
0.5
100
Figure 65
HD3
0
100
HARMONIC DISTORTION
vs
FREQUENCY
−90
1
10
f − Frequency − MHz
−60
−100
VO − Output Voltage Swing − V
16
−40
−100
1.5 2
0.1
−10
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = 5 V
−30
−90
1
HD2
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−20
−90
0.5
5
HD3
Figure 64
−60
0
4.5
HD2
−10
−80
−80
Figure 62
−80
−100
100
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−40
3.5 4
HD3
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = 5 V
−30
3
−60
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−20
2.5
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
Figure 63
0
1.5 2
−90
−90
−10
−70
−100
−10
−70
−100
0.1
−60
−100
HARMONIC DISTORTION
vs
FREQUENCY
−60
−80
−50
Figure 61
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−30
−40
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
−20
−30
−90
HARMONIC DISTORTION
vs
FREQUENCY
0
−20
−90
Figure 60
−10
HD3
−60
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
−10
Harmonic Distortion − dBc
−20
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
Harmonic Distortion − dBc
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = 5 V
HARMONIC DISTORTION
vs
FREQUENCY
Harmonic Distortion − dBc
0
−10
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−20
−30
−40
−50
HD3
HD2
−60
−70
−80
−90
4.5
5
−100
0
0.5
1
1.5 2
2.5
3
3.5 4
VO − Output Voltage Swing − V
Figure 68
4.5
5
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TYPICAL CHARACTERISTICS (5 V Graphs)
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = 5 V
Harmonic Distortion − dBc
−20
−30
−40
−50
0
HD3
−60
−20
HD2
−70
−80
−30
−40
−50
HD2
HD3
−80
−30
−40
−50
−80
−90
−90
−100
1.5 2
2.5
3
3.5 4
4.5
5
0
400
Figure 69
1200
1000
800
600
400
0.5
1
1.5
2
0.4
1.5
0.3
1
0.2
0.5
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = 5 V
0
−0.5
2.5
3
3.5
−1
Figure 72
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
0
100
200
300
400
Hz
I n − Current Noise − pA/
60
50
CMMR
PSRR−
40
f − Frequency − kHz
Figure 75
10 k
30
20
−10
1
10
f − Frequency − MHz
Figure 76
300
400
500
100
PSRR+
CMMR
80
PSRR−
60
40
20
RL = 800 Ω
VS = 5 V
0.1
200
120
100
10
1000
100
REJECTION RATIOS
vs
CASE TEMPERATURE
70
0
100
0
Figure 74
PSRR+
80
Rejection Ratios − dB
Hz
In
10
−0.2
t − Time − ns
REJECTION RATIOS
vs
FREQUENCY
Vn − Voltage Noise − nV/
10
1
−0.1
−0.4
−100
500
90
0.1
0
Figure 73
Vn
1600
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = 5 V
0.1
t − Time − ns
100
1200
−0.3
−2
−100
4
800
SMALL-SIGNAL TRANSIENT RESPONSE
2
VO − Differential Output Voltage Step − V
1
0.01
400
Figure 71
Rejection Ratios − dB
0
0
RL − Load Resistance − Ω
−1.5
200
0
1600
LARGE-SIGNAL TRANSIENT RESPONSE
VO − Output Voltage − V
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
1400
1200
Figure 70
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
1600
800
RL − Load Resistance − Ω
VO − Output Voltage − V
1
HD3
−70
−100
0.5
HD2
−60
−90
VO − Output Voltage Swing − V
SR − Slew Rate − V/ μ s
−20
−100
0
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = 5 V
−10
−60
−70
HARMONIC DISTORTION
vs
LOAD RESISTANCE
0
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
0
−10
HARMONIC DISTORTION
vs
LOAD RESISTANCE
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
RL = 800 Ω
VS = 5 V
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 77
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TYPICAL CHARACTERISTICS (5 V Graphs)
−20
−30
−40
−50
−60
40
−60
30
1
10
f − Frequency − MHz
Phase
−90
10
−120
0
0.01
100
52
51
50
49
48
0.1
1
0.12
0.11
IIB+
0.1
100
0.09
IOS
Case Temperature − °C
0.08
Figure 80
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
2.5
TA = 85°C
VS = 5 V
TA = 25°C
25
20
TA = −40°C
15
10
0.07
0.25
0.06
5
0.05
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
Case Temperature − °C
0 0.5
1
1.5
2
2.5
3
3.5
4 4.5
90
150
VS = 5 V
0.5
Case Temperature − °C
Output Drive − mA
70
60
50
40
30
20
50
0
−50
Sink
−100
3.5
4
4.5
Input Common-Mode Voltage Range − V
5
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
0
−10
−20
−30
−40
−50
−60
−70
−150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 85
Single-Ended and
Differential Input
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 8 MHz
VS = 5 V
HD3-Diff
HD2-SE
HD2-Diff
−80
−90
10
3
Figure 83
Source
100
Figure 84
1
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
5
OUTPUT DRIVE
vs
CASE TEMPERATURE
VS = 5 V
80
2 2.5
1.5
Figure 82
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
1.5
2
VS − Supply Voltage − ±V
Figure 81
1
−40−30−20−100 10 20 30 40 50 60 70 80 90
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
30
0.5
0 0.5
46
Harmonic Distortion − dBc
1
0.75
35
Quiescent Current − mA
0.13
IIB−
1.5
10
−150
1000
VOS − Input Offset Voltage − mV
0.14
VS = ±5 V
I OS − Input Offset Current − μ A
I IB − Input Bias Current − μ A
53
Figure 79
1.25
CMRR − Common-Mode Rejection Ratio − dB
54
f − Frequency − MHz
1.75
18
55
20
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
0
RL = 800 Ω
VS = 5 V
56
0
−30
Figure 78
2
57
47
−70
0.1
2.25
30
PIN = −30 dBm
RL = 800 Ω
Rf = 100 kΩ
VS = 5 V
50
Open-Loop Gain − dB
−10
Output Balance Error − dB
Gain
PIN = −20 dBm
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
Open-Loop Gain − dB
60
0
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
Phase − °
OUTPUT BALANCE ERROR
vs
FREQUENCY
−100
HD3-SE
1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
VOCM − Output Common-Mode Voltage − V
Figure 86
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TYPICAL CHARACTERISTICS
2
1
VOS − Output Offset Voltage − mV
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = 5 V
0
25
600
400
200
0
−200
−1
−400
−2
10
5
10
100
−800
1000
0 0.5
1
2
2.5
3
3.5
4
4.5
0
5
Figure 88
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN vs FREQUENCY
1000
0.9
−2
−3
−4
−5
Quiescent Current − mA
0.02
ZO− Single-Ended Output Impedance
in Power Down − Ω
1
−1
102
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
1100
0
0
Figure 89
0.03
0.01
Current
900
800
700
600
500
400
300
200
100
Gain = 1
RL = 400 Ω
Rf = 392 Ω
PIN = −1 dBm
VS = 5 V
0
0.1
103
1
10
100
f − Frequency − MHz
1000
RL = 800 Ω
VS = 5 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 91
Figure 90
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage − V
VOC − Output Common-Mode Voltage − V
TURNON AND TURNOFF DELAY TIMES
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
1.5
Power-Down Quiescent Current − mA
1
Figure 87
Figure 92
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
1000
Power-Down Quiescent Current − μ A
Powerdown Voltage Signal − V
15
−600
f − Frequency − MHz
−6
20
Quiescent Current − mA
Small Signal Frequency Response at VOCM − dB
800
3
−3
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
OUTPUT OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE VOLTAGE
SMALL SIGNAL FREQUENCY RESPONSE
at VOCM
900
800
700
600
500
400
300
200
100
0
0
0.5 1
1.5 2
2.5 3
3.5 4
4.5 5
VS − Supply Voltage − V
Figure 93
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APPLICATION INFORMATION
MAXIMUM DIE TEMPERATURE TO PREVENT
OSCILLATION
The THS4503 may have low level oscillation when the die
temperature (also called junction temperature) exceeds
+60°C and is not recommended for new designs where the
die temperature is expected to exceed +60°C.
The oscillation is due to internal design and external
configuration is not expected to mitigate or reduce the
problem. This problem is random due to normal process
variations and normal testing cannot identify problem
units.
The THS4500 and
replacement devices.
THS4501
are recommended
The die temperature depends on the power dissipation
and the thermal resistance of the device and can be
approximated with the following formula:
Die Temperature = PDISS × θJA + TA
Where:
PDISS ≈ (VS(TOTAL) × IQ) + (VS+ − VOUT) × IOUT) × θJA + TA
Table 1 shows the estimated maximum ambient
temperature (TA max) in °C for package option of the
THS4503 using the thermal dissipation rating given in the
PACKAGE DISSIPATION RATINGS table for a JEDEC
standard High−K test PCB. For each case shown,
VS(TOTAL) = 10V, RL = 800 Ω differential, and the quiescent
current = 32mA (the maximum over 0°C to 70°C
temperature range). The last entry for each package
option lists the worst case where the output voltage is 5V
DC.
Table 1. Estimated Maximum Ambient
Temperature Per Package Option
Package/Device
PWR Pad MSOP
THS4503DGN
Vout
20
TA max
0V
41.3°C
2 Vpp
40.8°C
4 Vpp
40.4°C
6 Vpp
Worst Case
qJA
58 4°C/W
58.4°C/W
40.1°C
8 Vpp
39.8°C
5 DC
39.5°C
FULLY DIFFERENTIAL AMPLIFIERS
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external common-mode
noise, suppression of even-order nonlinearities, and
increased dynamic range. Fully differential amplifiers not
only serve as the primary means of providing gain to a
differential signal chain, but also provide a monolithic
solution for converting single-ended signals into
differential signals for easier, higher performance
processing. The THS4500 family of amplifiers contains
products in Texas Instruments’ expanding line of
high-performance fully differential amplifiers. Information
on fully differential amplifier fundamentals, as well as
implementation specific information, is presented in the
applications section of this data sheet to provide a better
understanding of the operation of the THS4500 family of
devices and to simplify the design process for designs
using these amplifiers.
Applications Section
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential
Amplifiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
Setting the Output Common-Mode Voltage With the
VOCM Input
Saving Power With Power-Down Functionality
Linearity: Definitions, Terminology, Circuit
Techniques, and Design Tradeoffs
An Abbreviated Analysis of Noise in Fully
Differential Amplifiers
Printed-Circuit Board Layout Techniques for Optimal
Performance
Power Dissipation and Thermal Considerations
Power Supply Decoupling Techniques and
Recommendations
Evaluation Fixtures, Spice Models, and Applications
Support
Additional Reference Material
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FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
Fully differential amplifiers are typically packaged in 8-pin
packages as shown in the diagram. The device pins
include two inputs (VIN+, VIN−), two outputs (VOUT−,
VOUT+), two power supplies (VS+, VS−), an output
common-mode control pin (VOCM), and an optional
power-down pin (PD).
VIN− 1
8 VIN+
VOCM 2
7 NC
VS+ 3
6 VS−
VOUT+ 4
A standard configuration for the device is shown in the
figure. The functionality of a fully differential amplifier can
be imagined as two inverting amplifiers that share a
common noninverting terminal (though the voltage is not
necessarily fixed). For more information on the basic
theory of operation for fully differential amplifiers, see the
Texas Instruments application note titled Fully Differential
Amplifiers (SLOA054).
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the two
devices. The THS4503 has an input common-mode range
that is centered around midrail, and the THS4500 and
THS4501 have an input common-mode range that is
shifted to include the negative power supply rail. Selection
of one or the other is determined by the nature of the
application. Specifically, the THS4500 and THS4501 are
designed for use in single-supply applications where the
input signal is ground-referenced, as depicted in
Figure 94. The THS4503 is designed for use in
single-supply or split-supply applications where the input
signal is centered between the power supply voltages, as
depicted in Figure 95.
Rf1
+VS
RT
VS
VOCM
Rg2
+ −
− +
Rf2
Application Circuit for the THS4500 and THS4501,
Featuring Single-Supply Operation With a
Ground-Referenced Input Signal
Figure 94
5 VOUT−
Fully Differential Amplifier Pin Diagram
Rg1
RS
Rg1
RS
VS
Rf1
+VS
RT
VOCM
+ −
− +
−VS
Rg2
Rf2
Application Circuit for the THS4500 and THS4501,
Featuring Split-Supply Operation With an Input
Signal Referenced at the Midrail
Figure 95
Equations 1−5 allow for calculation of the required input
common-mode range for a given set of input conditions.
The equations allow calculation of the input commonmode range requirements given information about the
input signal, the output voltage swing, the gain, and the
output common-mode voltage. Calculating the maximum
and minimum voltage required for VN and VP (the
amplifier’s input nodes) determines whether or not the
input common-mode range is violated or not. Four
equations are required. Two calculate the output voltages
and two calculate the node voltages at VN and VP (note
that only one of these needs calculation, as the amplifier
forces a virtual short between the two nodes).
21
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V IN)(1–β)–V IN–(1–β) ) 2V OCMβ
2β
V OUT) +
V OUT– +
–V IN)(1–β) ) V IN–(1–β) ) 2V OCMβ
2β
(2)
V N + V IN–(1–β) ) V OUT)β
(3)
RG
β+
RF ) RG
Where:
(4)
(5)
V P + V IN)(1–β) ) V OUT–β
NOTE:
The equations denote the device inputs as VN and
VP and the circuit inputs as VIN+ and VIN−.
VIN+
Rg
Rf
Vp
VOCM
Vn
VIN−
VOUT−
+ −
− +
Rg
VOUT+
Rf
Diagram For Input Common-Mode Range Equations
Figure 96
The two tables below depict the input common-mode
range requirements for two different input scenarios, an
input referenced around the negative rail and an input
referenced around midrail. The tables highlight the
differing requirements on input common-mode range, and
illustrate reasoning for choosing either the THS4500/1 or
the THS4503. For signals referenced around the negative
power supply, the THS4500/1 should be chosen since its
input common-mode range includes the negative supply
rail. For all other situations, the THS4503 offers slightly
improved distortion and noise performance for
applications with input signals centered between the
power supply rails.
VIN+ (V)
VIN−
(V)
VIN
(VPP)
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
1
−2 to 2
0
4
2.5
4
0.75
1.75
2
−1 to 1
0
2
2.5
4
0.5
1.167
4
−0.5 to
0.5
0
1
2.5
4
0.3
0.7
8
−0.25 to
0.25
0
0.5
2.5
4
0.167
0.389
NOTE: This table assumes a negative-rail referenced, single-ended
input signal on a single 5-V supply as shown in Figure 94.
VNMIN = VPMIN and VNMAX = VPMAX.
22
Gain
(V/V)
VIN+ (V)
VIN−
(V)
VIN
(VPP)
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
1
0.5 to
4.5
2.5
4
2.5
4
2
3
2
1.5 to
3.5
2.5
2
2.5
4
2.16
2.83
4
2 to 3
2.5
1
2.5
4
2.3
2.7
8
2.25 to
2.75
2.5
0.5
2.5
4
2.389
2.61
NOTE: This table assumes a midrail referenced, single-ended input
signal on a single 5-V supply.
VNMIN = VPMIN and VNMAX = VPMAX.
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values in this
section provide the optimum high frequency performance
(lowest distortion, flat frequency response). Since the
THS4500 family of amplifiers is developed with a voltage
feedback architecture, the choice of resistor values does
not have a dominant effect on bandwidth, unlike a current
feedback amplifier. However, resistor choices do have
second-order effects. For optimal performance, the
following feedback resistor values are recommended. In
higher gain configurations (gain greater than two), the
feedback resistor values have much less effect on the high
frequency performance. Example feedback and gain
resistor values are given in the section on basic design
considerations (see Table 4).
Amplifier loading, noise, and the flatness of the frequency
response are three design parameters that should be
considered when selecting feedback resistors. Larger
resistor values contribute more noise and can induce
peaking in the ac response in low gain configurations, and
smaller resistor values can load the amplifier more heavily,
resulting in a reduction in distortion performance. In
addition, feedback resistor values, coupled with gain
requirements, determine the value of the gain resistors,
directly impacting the input impedance of the entire circuit.
While there are no strict rules about resistor selection,
these trends can provide qualitative design guidance.
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Table 2. Negative-Rail Referenced
Gain
(V/V)
Table 3. Midrail Referenced
(1)
Fully differential amplifiers provide designers with a great
deal of flexibility in a wide variety of applications. This
section provides an overview of some common circuit
configurations and gives some design guidelines.
Designing the interface to an ADC, driving lines
differentially, and filtering with fully differential amplifiers
are a few of the circuits that are covered.
BASIC DESIGN CONSIDERATIONS
The circuits in Figure 96 through Figure 100 are used to
highlight basic design considerations for fully differential
amplifier circuit designs.
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Table 4. Resistor Values for Balanced Operation
in Various Gain Configurations
ǒ Ǔ
VOD
VIN
Gain
NOTE:
R2 and R4
(Ω)
R1 (Ω)
R3 (Ω)
RT (Ω)
1
392
412
383
54.9
1
499
523
487
53.6
2
392
215
187
60.4
2
1.3 k
665
634
52.3
5
1.3 k
274
249
56.2
5
3.32 k
681
649
52.3
10
1.3 k
147
118
64.9
10
6.81 k
698
681
52.3
The THS4500 family of amplifiers are designed
specifically to interface to today’s highest-performance
analog-to-digital converters. This section highlights the
key concerns when interfacing to an ADC and provides
example ADC/fully differential amplifier interface circuits.
Key design concerns when
analog-to-digital converter:
Values in the table above assume a 50-Ω source impedance.
R1
R3
VP
RT
VS
+
+ −
Design a symmetric printed-circuit board layout.
Even-order distortion products are heavily influenced
by layout, and careful attention to a symmetric layout
will minimize these distortion products.
D
Minimize inductance in power supply decoupling
traces and components. Poor power supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the current
loop.
D
Use separate analog and digital power supplies and
grounds. Noise (bounce) in the power supplies
(created by digital switching currents) can couple
directly into the signal path, and power supply noise
can create higher distortion products as well.
D
Use care when filtering. While an RC low-pass filter
may be desirable on the output of the amplifier to filter
broadband noise, the excess loading can negatively
impact the amplifier linearity. Filtering in the feedback
path does not have this effect.
D
AC-coupling allows easier circuit design. If
dc-coupling is required, be aware of the excess power
dissipation that can occur due to level-shifting the
output through the output common-mode voltage
control.
D
Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop fully
differential amplifiers drive a specific output voltage
regardless of the load impedance present.
Terminating the output of a fully differential amplifier
with a heavy load adversely effects the amplifier’s
linearity.
Comprehend the VOCM input drive requirements.
Determine if the ADC’s voltage reference can provide
the required amount of current to move VOCM to the
desired value. A buffer may be needed.
VOCM
R4
Equations for calculating fully differential amplifier resistor
values in order to obtain balanced operation in the
presence of a 50-Ω source impedance are given in
equations 6 through 9.
RT +
β1 +
1
K + R2
R1
1– K
1 – 2(1)K)
RS
R3
R2 + R4
(6)
R3 + R1 * ǒRs || R TǓ
R3 ) RT || R S
R1
β +
R1 ) R2 2
R3 ) RT || R S ) R4
(7)
ǒ
Ǔ ǒR R) R Ǔ
(8)
ǒ
Ǔ
(9)
V OD
1–β 2
+2
β1 ) β 2
VS
V OD
1–β 2
+2
β1 ) β 2
V IN
T
T
S
For more detailed information about balance in fully
differential amplifiers, see Fully Differential Amplifiers,
referenced at the end of this data sheet.
an
D
Vout−
Figure 97
to
Terminate the input source properly. In high-frequency
receiver chains, the source feeding the fully
differential amplifier requires a specific load
impedance (e.g., 50 Ω).
Vout+
−
interfacing
D
R2
Vn
RS
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
D
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D
D
D
D
Decouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can act as
an antenna. A large decoupling capacitor on this node
eliminates this problem.
Be cognizant of the input common-mode range. If the
input signal is referenced around the negative power
supply rail (e.g., around ground on a single 5-V
supply), then the THS4500/1 accommodates the
input signal. If the input signal is referenced around
midrail, choose the THS4502/3 for the best operation.
Packaging makes a difference at higher frequencies.
If possible, choose the smaller, thermally enhanced
MSOP package for the best performance. As a rule,
lower junction temperatures provide better
performance. If possible, use a thermally enhanced
package, even if the power dissipation is relatively
small compared to the maximum power dissipation
rating to achieve the best results.
Comprehend the effect of the load impedance seen by
the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level of
intermodulation distortion performance.
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at the
output of the data converter. Two representative circuits
shown below highlight single-supply operation and split
supply operation. Specific feedback resistor, gain resistor,
and feedback capacitor values are not specified, as their
values depend on the frequency of interest. Information on
calculating these values can be found in the applications
material above.
CF
RS
VS
Rg
Rg
−5 V
0.1 μF
RT
10 μF
+ −
VOCM
+
−
1 μF
5V
0.1 μF
Riso
Riso
THS4501
IN ADS5421
14 Bit/40 MSps
IN
CM
Rg
Rf
CF
0.1 μF
Using the THS4501 With the ADS5421
Figure 99
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers. Their
high power supply voltage rating (16.5 V absolute
maximum) allows operation on a single 12-V or a single
15-V supply. The high supply voltage, coupled with the
ability to provide differential outputs enables the ability to
drive 26 VPP into reasonably heavy loads (250 Ω or
greater). The circuit in Figure 100 illustrates the THS4500
family of devices used as high speed line drivers. For line
driver applications, close attention must be paid to thermal
design constraints due to the typically high level of power
dissipation.
RS
VS
CG
Rg
Rf
15 V
RT
VOCM
+
−
THS4500
− +
0.1 μF
Riso
CS
RL
VDD
Riso
Rf
THS4503
Figure 100
5V
Riso
Riso
IN ADS5410
12 Bit/80 MSps
IN
CM
10 μF 0.1 μF
0.1 μF
Rf
CF
Using the THS4503 With the ADS5410
Figure 98
24
Rf
5V
CS
VOD = 26 VPP
Fully Differential Line Driver With High Output Swing
10 μF
1 μF
VS
Rg
CG
Rf
+ −
VOCM
+
−
RS
Rg
5V
RT
CF
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FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
Similar to their single-ended counterparts, fully differential
amplifiers have the ability to couple filtering functionality
with voltage gain. Numerous filter topologies can be based
on fully differential amplifiers. Several of these are outlined
in A Differential Circuit Collection, (SLOA064) referenced
at the end of this data sheet. The circuit below depicts a
simple two-pole low-pass filter applicable to many different
types of systems. The first pole is set by the resistors and
capacitors in the feedback paths, and the second pole is
set by the isolation resistors and the capacitor across the
outputs of the isolation resistors.
applied to the VOCM pin alters the output common-mode
voltage as long as the source has the ability to provide
enough current to overdrive the two 50-kΩ resistors. This
phenomenon is depicted in the VOCM equivalent circuit
diagram. The table contains some representative
examples to aid in determining the current drive
requirement for the VOCM voltage source. This parameter
is especially important when using the reference voltage
of an analog-to-digital converter to drive VOCM. Output
current drive capabilities differ from part to part, so a
voltage buffer may be necessary in some applications.
VS+
R = 50 kΩ
CF1
IIN =
VOCM
Rg1
RS
VS
IIN
Rf1
2 VOCM − VS+ − VS−
R
R = 50 kΩ
Riso
RT
+
−
−
C
+
Rg2
VO
Riso
Rf2
CF2
A Two-Pole, Low-Pass Filter Design Using a Fully
Differential Amplifier With Poles Located at:
P1 = (2πRfCF)−1 in Hz and P2 = (4πRisoC)−1 in Hz
Figure 101
Often times, filters like these are used to eliminate
broadband noise and out-of-band distortion products in
signal acquisition systems. It should be noted that the
increased load placed on the output of the amplifier by the
second low-pass filter has a detrimental effect on the
distortion performance. The preferred method of filtering is
using the feedback network, as the typically smaller
capacitances required at these points in the circuit do not
load the amplifier nearly as heavily in the pass-band.
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
The output common-mode voltage pin provides a critical
function to the fully differential amplifier; it accepts an input
voltage and reproduces that input voltage as the output
common-mode voltage. In other words, the VOCM input
provides the ability to level-shift the outputs to any voltage
inside the output voltage swing of the amplifier.
A description of the input circuitry of the VOCM pin is shown
below to facilitate an easier understanding of the VOCM
interface requirements. The VOCM pin has two 50-kΩ
resistors between the power supply rails to set the default
output common-mode voltage to midrail. A voltage
VS−
Equivalent Input Circuit for VOCM
Figure 102
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal. As
shown in the equivalent circuit diagram, the VOCM input
has a high impedance associated with it, dictated by the
two 50-kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and any
associated printed-circuit board traces to act as an
antenna. For this reason, a decoupling capacitor is
recommended on this node for the sole purpose of filtering
any high frequency noise that could couple into the signal
path through the VOCM circuitry. A 0.1-μF or 1-μF
capacitance is a reasonable value for eliminating a great
deal of broadband interference, but additional, tuned
decoupling capacitors should be considered if a specific
source of electromagnetic or radio frequency interference
is present elsewhere in the system. Information on the ac
performance (bandwidth, slew rate) of the VOCM circuitry
is included in the specification table and graph section.
Since the VOCM pin provides the ability to set an output
common-mode voltage, the ability for increased power
dissipation exists. While this does not pose a performance
problem for the amplifier, it can cause additional power
dissipation of which the system designer should be aware.
The circuit shown in Figure 103 demonstrates an
example of this phenomenon. For a device operating on a
single 5-V supply with an input signal referenced around
ground and an output common-mode voltage of 2.5 V, a
dc potential exists between the outputs and the inputs of
the device. The amplifier sources current into the
feedback network in order to provide the circuit with the
proper operating point. While there are no serious effects
on the circuit performance, the extra power dissipation
may need to be included in the system’s power budget.
25
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I1 =
VOCM
Rf1+ Rg1 + RS || RT
DC Current Path to Ground
Rg1
RS
VS
Rf1
5V
RT
VOCM = 2.5 V
2.5-V DC
+ −
− +
Rg2
Rf2
RL
2.5-V DC
DC Current Path to Ground
I2 =
VOCM
Rf2 + Rg2
Depiction of DC Power Dissipation Caused By
Output Level-Shifting in a DC-Coupled Circuit
Figure 103
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
The THS4500 family of fully differential amplifiers contains
devices that come with and without the power-down
option. Even-numbered devices have power-down
capability, which is described in detail here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (i.e. an internal pullup resistor is present), putting
the amplifier in the power-on mode of operation. To turn off
the amplifier in an effort to conserve power, the
power-down pin can be driven towards the negative rail.
The threshold voltages for power-on and power-down are
relative to the supply rails and given in the specification
tables. Above the enable threshold voltage, the device is
on. Below the disable threshold voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
The time delays associated with turning the device on and
off are specified as the time it takes for the amplifier to
reach 50% of the nominal quiescent current. The time
delays are on the order of microseconds because the
amplifier moves in and out of the linear mode of operation
in these transitions.
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The THS4500 family of devices features unprecedented
distortion performance for monolithic fully differential
amplifiers. This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity, and
methods for equating distortion of fully differential
amplifiers to desired linearity specifications in RF receiver
chains.
Amplifiers are generally thought of as linear devices. In
other words, the output of an amplifier is a linearly scaled
version of the input signal applied to it. In reality, however,
amplifier transfer functions are nonlinear. Minimizing
amplifier nonlinearity is a primary design goal in many
applications.
Intercept points are specifications that have long been
used as key design criteria in the RF communications
world as a metric for the intermodulation distortion
performance of a device in the signal chain (e.g.,
amplifiers, mixers, etc.). Use of the intercept point, rather
than strictly the intermodulation distortion, allows for
simpler system-level calculations. Intercept points, like
noise figures, can be easily cascaded back and forth
through a signal chain to determine the overall receiver
chain’s intermodulation distortion performance. The
relationship between intermodulation distortion and
intercept point is depicted in Figure 104 and Figure 105.
PO
PO
Note that this power-down functionality is just that; the
amplifier consumes less power in power-down mode. The
power-down mode is not intended to provide a
high-impedance output. In other words, the power-down
functionality is not intended to allow use as a 3-state bus
driver. When in power-down mode, the impedance looking
back into the output of the amplifier is dominated by the
feedback and gain setting resistors.
Power
Δfc = fc − f1
Δfc = f2 − fc
IMD3 = PS − PO
PS
fc − 3Δf
PS
f1 fc
f2
fc + 3Δf
f − Frequency − MHz
Figure 104
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As can be seen in the equation, when a higher impedance
is used, the same level of intermodulation distortion
performance results in a lower intercept point. Therefore,
it is important to comprehend the impedance seen by the
output of the fully differential amplifier when selecting a
minimum intercept point. The graphic below shows the
relationship between the strict definition of an intercept
point with a normalized, or equivalent, intercept point for
the THS4503.
1X
OIP3
PO
IMD3
IIP3
3X
THIRD-ORDER OUTPUT INTERCEPT POINT
vs
FREQUENCY
PIN
(dBm)
PS
Figure 105
Due to the intercept point’s ease of use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related design
decisions. Traditionally, these systems use primarily
class-A, single-ended RF amplifiers as gain blocks. These
RF amplifiers are typically designed to operate in a 50-Ω
environment, just like the rest of the receiver chain. Since
intercept points are given in dBm, this implies an
associated impedance (50 Ω).
However, with a fully differential amplifier, the output does
not require termination as an RF amplifier would. Because
closed-loop amplifiers deliver signals to their outputs
regardless of the impedance present, it is important to
comprehend this when evaluating the intercept point of a
fully differential amplifier. The THS4500 series of devices
yields optimum distortion performance when loaded with
200 Ω to 1 kΩ, similar to the input impedance of an
analog-to-digital converter over its input frequency band.
As a result, terminating the input of the ADC to 50 Ω can
actually be detrimental to system performance.
This discontinuity between open-loop, class-A amplifiers
and closed-loop, class-AB amplifiers becomes apparent
when comparing the intercept points of the two types of
devices. Equation 10 gives the definition of an intercept
point, relative to the intermodulation distortion.
OIP 3 + P O )
ǒŤIMD2 ŤǓ where
ǒ
P O + 10 log
3
Ǔ
V 2Pdiff
2RL 0.001
(10)
(11)
NOTE: Po is the output power of a single tone, RL is the differential load
resistance, and VP(diff) is the differential peak voltage for a
single tone.
OIP 3 − Third-Order Output Intercept Point − dBm
POUT
(dBm)
60
Normalized to 200 Ω
55
Normalized to 50 Ω
50
45
40
35
OIP3 RL= 800 Ω
30
Gain = 1
Rf = 392 Ω
VS = ± 5 V
Tone Spacing = 200 kHz
25
20
15
0
10 20 30 40 50 60 70 80 90 100
f − Frequency − MHz
Figure 106
Comparing specifications between different device types
becomes easier when a common impedance level is
assumed. For this reason, the intercept points on the
THS4500 family of devices are reported normalized to a
50-Ω load impedance.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is analogous
to noise analysis in single-ended amplifiers. The same
concepts apply. Below, a generic circuit diagram
consisting of a voltage source, a termination resistor, two
gain setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the relevant
noise sources. From this circuit, the noise factor (F) and
noise figure (NF) are calculated. The figures indicate the
appropriate scaling factor for each of the noise sources in
two different cases. The first case includes the termination
resistor, and the second, simplified case assumes that the
voltage source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier’s input
noise power (NA) can be calculated by summing each
individual noise source with its scaling factor. The noise
delivered to the amplifier by the source (NI) and input noise
power are used to calculate the noise factor and noise
figure as shown in equations 23 through 27.
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Ni
eg
NA
Rg
Rf
Si
NA: Fully Differential Amplifier; termination = 2Rg
ef
Noise
Source
en
No
+
Rt
So
fully-diff
amp
−
ini
es
No
et
iii
eg
Rg
Rf
ȡR )
ȧR R
Ȣ
2
(eni)2
f
(ini)2
Rg2
(iii)2
Rg2
ef
g
2
(18)
s
(19)
ǒ Ǔ
Rg
Rf
2
4kTRf
ȣ
Rȧ
) Ȥ
Rg
g
Ni
Rs
Scale Factor
(20)
2
(21)
2
NA: Fully Differential Amplifier
Noise
Source
2
g
g
(eni)2
f
(ini)2
Rg2
(iii)2
Rg2
g
s
t
t
G
s
2
2
g
s
s
ǒ Ǔ
Rg
Rf
ȡ
ȧR
Ȣ
(15)
g
i
g
s
(23)
g
t
s
t
g
g
t
Figure 110. Input Noise With a
Termination Resistor
g
Ni + 4kTR s
ǒ
2R g
Rs ) 2Rg
Ǔ
2
(24)
2
(16)
Figure 111. Input Noise Assuming No Termination
Resistor
2
ȣ
ȧ
Ȥ
Rg
R sR t
g)
ǒ
2 R s)RtǓ
Figure 108. Scaling Factors for Individual
Noise Sources Assuming a Finite Value
Termination Resistor
28
2
ȡ 2R R ȣ
ȧ R )2R ȧ
N + 4kTR ȧ
R ȧ
ȧR )R2R)2R
ȧ
Ȣ
Ȥ
t
2
R
ȡ R2R)2R
ȣ
ȧR ) 2R R ȧ
Ȣ R )2R Ȥ
4kTRf
(12)
(14)
t
4kTRg
s
(13)
s
4kTRt
ȣ
R
R R ȧ
)
2ǒR )R ǓȤ
(22)
s
g
Figure 109. Scaling Factors for Individual Noise
Sources Assuming No termination Resistance is
Used (e.g., RT is open)
Scale Factor
ȡR
ȧR ) R
Ȣ
g
2
4kTRg
Figure 107. Noise Sources in a Fully
Differential Amplifier Circuit
ȡ R ȣ
ȧR ) R ȧ
Ȣ 2Ȥ
(17)
Noise Factor and Noise Figure Calculations
N A + SǒNoise Source
F+1)
NA
NI
NF + 10 log (F)
Scale FactorǓ
(25)
(26)
(27)
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PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to board layout parasitic and external
component types.
below 400 MHz that can effect circuit operation. Keep
resistor values as low as possible, consistent with
load driving considerations.
D
Recommendations that optimize performance include:
D
Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce
unwanted capacitance, a window around the signal
I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground
and power planes should be unbroken elsewhere on
the board.
D
Minimize the distance (< 0.25”) from the power supply
pins to high frequency 0.1-μF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors. Larger
(6.8 μF or more) tantalum decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board. The
primary goal is to minimize the impedance seen in the
differential-current return paths.
D
Careful selection and placement of external
components preserve
the
high
frequency
performance of the THS4500 family. Resistors should
be a low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep their leads and PC board trace length as
short as possible. Never use wirewound type resistors
in a high frequency application. Since the output pin
and inverting input pins are the most sensitive to
parasitic capacitance, always position the feedback
and series output resistors, if any, as close as possible
to the inverting input pins and output pins. Other
network components, such as input termination
resistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time constants
that can degrade performance. Good axial metal-film
or surface-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values > 2 kΩ,
this parasitic capacitance can add a pole and/or a zero
Connections to other wideband devices on the board
may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as
a lumped capacitive load. Relatively wide traces
(50 mils to 100 mils) should be used, preferably with
ground and power planes opened up around them.
Estimate the total capacitive load and determine if
isolation resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need an RS
since the THS4500 family is nominally compensated
to operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB signal
loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance environment
improves distortion as shown in the distortion versus
load plots. With a characteristic board trace
impedance defined based on board material and trace
dimensions, a matching series resistor into the trace
from the output of the THS4500 family is used as well
as a terminating shunt resistor at the input of the
destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there is some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
D
Socketing a high speed part like the THS4500 family
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the THS4500 family parts
directly onto the board.
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PowerPAD DESIGN CONSIDERATIONS
PowerPAD PCB LAYOUT CONSIDERATIONS
The THS4500 family is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die
is mounted [see Figure 112(a) and Figure 112(b)]. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see
Figure 112(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal
path away from the thermal pad.
1.
Prepare the PCB with a top side etch pattern as shown
in Figure 113. There should be etch for the leads as
well as etch for the thermal pad.
2.
Place five holes in the area of the thermal pad. These
holes should be 13 mils in diameter. Keep the holes
small so that solder wicking through the holes is not a
problem during reflow.
3.
Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the THS4500
family IC. These additional vias may be larger than the
13-mil diameter vias directly under the thermal pad.
They can be larger because they are not in the thermal
pad area to be soldered so that wicking is not a
problem.
4.
Connect all holes to the internal ground plane.
5.
When connecting these holes to the ground plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete connection around the entire circumference
of the plated-through hole.
6.
The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7.
Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8.
With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation as any standard surface-mount component.
This results in a part that is properly installed.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in
combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods
of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 112. Views of Thermally Enhanced
Package
Although there are many ways to properly heatsink the
PowerPAD package, the following steps illustrate the
recommended approach.
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 113. PowerPAD PCB Etch and Via Pattern
30
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 150°C is exceeded. For best performance,
design for a maximum junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur, but
the performance of the amplifier begins to degrade.
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
P Dmax +
Tmax–T A
q JA
(28)
Where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
For systems where heat dissipation is more critical, the
THS4500 family of devices is offered in an 8-pin MSOP
with PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over the
traditional SOIC. Maximum power dissipation levels are
depicted in the graph for the two packages. The data for
the DGN package assumes a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application notes in the
Additional Reference Material section at the end of the
data sheet.
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however, the
load capacitance should be isolated by two isolation
resistors in series with the output. The requisite isolation
resistor size depends on the value of the capacitance, but
10 Ω to 25 Ω is a good place to begin the optimization
process. Larger isolation resistors decrease the amount of
peaking in the frequency response induced by the
capacitive load, but this comes at the expense of larger
voltage drop across the resistors, increasing the output
swing requirements of the system.
Rf
VS
VS
Rg
RS
Riso
+ −
RT
−
CL
+
Riso
−VS
Riso = 10 − 25 Ω
Rf
Rg
Use of Isolation Resistors With a Capacitive Load.
Figure 115
PD − Maximum Power Dissipation − W
3.5
3
8-Pin DGN Package
POWER SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
2.5
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
2
1.5
8-Pin D Package
1
0.5
0
−40
−20
0
20
40
60
TA − Ambient Temperature − °C
1.
Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
2.
Placement priority should be as follows: smaller
capacitors should be closer to the device.
3.
Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths.
4.
Recommended values for power supply decoupling
include 10-μF and 0.1-μF capacitors for each supply.
A 1000-pF capacitor can be used across the supplies
as well for extremely high frequency return currents,
but often is not required.
80
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
Figure 114. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
not only consider quiescent power dissipation, but also
dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
31
THS4503−EP
www.ti.com
SGLS291A − APRIL 2005 − JANUARY 2012
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its customers
with the highest quality of applications support. To support
this goal, an evaluation board has been developed for the
THS4500 family of fully differential amplifiers. The
evaluation board can be obtained by ordering through the
Texas Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative. Schematic
for the evaluation board is shown below with their default
component values. Unpopulated footprints are shown to
provide insight into design flexibility.
C4
C0805
R4
R0805
VS
J1
C1
R1
C0805
C2
R1206
C0805
R2
1
PD
U1
THS450X
R6
4
7
R0805
3
_
R0805
R0805
R3
8
+
2
5
6
VOCM
PwrPad
C5
C0805
C7
C0805
R0805
R7
J2
J3
J2
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the THS4500 family of devices is
available through the Texas Instruments web site
(www.ti.com). The PIC is also available for design
assistance and detailed product information. These
models do a good job of predicting small-signal ac and
transient performance under a wide variety of operating
conditions. They are not intended to model the distortion
characteristics of the amplifier, nor do they attempt to
distinguish between the package types in their
small-signal ac performance. Detailed information about
what is and is not modeled is contained in the model file
itself.
J3
C6
C0805
−VS
R5 R0805
C3
C0805
J2
R8
R0805
J3
R9
R0805
R0805
R9
4
5
6
J4
3
R11
R1206
T1
1
Simplified Schematic of the Evaluation Board. Power
Supply Decoupling, VOCM, and Power Down Circuitry
Not Shown
Figure 116
ADDITIONAL REFERENCE MATERIAL
D
D
D
D
D
D
D
32
PowerPAD Made Easy, application brief, Texas Instruments (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief, Texas Instruments (SLMA002)
Karki, James. Fully Differential Amplifiers. application report, Texas Instruments (SLOA054D)
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and Differential
Transmission Lines. Texas Instruments Analog Applications Journal, February 2001
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments (SLOA064)
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments
(SLOA072)
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog Applications
Journal, July 2001
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4503MDGNREP
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 60
BLB
V62/05608-02YE
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
BLB
V62/05608-03YE
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 60
BLB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4503-EP :
• Catalog: THS4503
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS4503MDGNREP
Package Package Pins
Type Drawing
SPQ
HVSSOP
2500
DGN
8
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4503MDGNREP
HVSSOP
DGN
8
2500
358.0
335.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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