Texas Instruments | 3-Ch RGBHV Video Buffer w/I2C Ctrl, Selectable Filters, Monitor Pass-Thru (Rev. C) | Datasheet | Texas Instruments 3-Ch RGBHV Video Buffer w/I2C Ctrl, Selectable Filters, Monitor Pass-Thru (Rev. C) Datasheet

Texas Instruments 3-Ch RGBHV Video Buffer w/I2C Ctrl, Selectable Filters, Monitor Pass-Thru (Rev. C) Datasheet
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
2
3-Channel RGBHV Video Buffer with I C Control, Selectable Filters, Monitor Pass-Thru,
2:1 Input MUX, and Selectable Input Bias Modes
Check for Samples: THS7327
FEATURES
•
1
• 3-Video Amplifiers for CVBS, S-Video,
SD/ED/HD Y'P'BP'R, G'B'R', and R'G'B' Video
• HV Sync Paths With Adj. Schmitt Trigger
• 2:1 Input MUX
• I2C™ Control of All Functions
• Integrated Low-Pass Filters on ADC Buffers
– 5th Order Butterworth Characteristics
– Selectable Corner Frequencies of 9-MHz,
16-MHz, 35-MHz, and 75-MHz with Bypass
(500-MHz)
• Selectable Input Bias Modes:
– AC-Coupled with Sync-Tip Clamp
– AC-Coupled with Bias
– DC-Coupled with Offset Shift
– DC-Coupled
• Monitor Pass-Thru Function:
– Passes the Input Signal With no Filtering
– 500-MHz BW and 1300 V/μs Slew Rate
– 6-dB Gain With SAG Correction Capable
– High Output Impedance in Disable State
• 2.7-V to 5-V Single Supply Operation
• Low 330 mW at 3.3-V Power Consumption
• Disable Function Reduces Current to < 1 μA
2345
Input 1
2:1
X1
75 W
Input 2
0.1 mF
APPLICATIONS
•
•
•
Projectors
Professional Video Systems
LCD/DLP/LOCS Input Buffering
DESCRIPTION
Fabricated
using
the
new
complementary
silicon-germanium (SiGe) BiCom-III process, the
THS7327 is a low-power, single-supply 2.7-V to 5-V,
3-channel integrated video buffer with H and V Sync
signal paths. It incorporates a selectable 5th order
Butterworth anti-aliasing filter on each channel. The
9-MHz is a perfect choice for SDTV video including
composite, S-Video™, and 480i/576i. The 16-MHz
filter is ideal for EDTV 480p/576p and VGA signals.
The 35-MHz filter is useful for HDTV 720p/1080i and
SVGA signals. The 75-MHz filter is ideal for HDTV
1080p and XGA/SXGA signals. For UXGA/QXGA
R’G’B’ signals, the filter can be bypassed allowing a
500-MHz bandwidth, 1150-V/μs amplifier to buffer the
signal.
3.3 V
Bypass
0.1 mF
In A
In B
•
Rail-to-Rail Output:
– Output Swings Within 0.1 V From the Rails
Which Allows AC or DC Output Coupling
RoHS TQFP Package
DC
+Offset
DC
ACBIAS
75 W
AC
Sync
TIP
Clamp
LPF
9/16/35/
75 MHz
0.1 mF
+
ADC
-
+
Disable
= OPEN
-
Out
75 W
675 W
SAG
1 kW
SDA
SCL
878 W
150 W
47 mF
33 mF
Monitor
Output
75 W
3.3 V
Figure 1. 3.3 V Single-Supply AC-Input/AC-Video Output System w/SAG Correction
(1 of 3 Channels Shown)
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
S-Video is a trademark of its respective owner.
I2C is a trademark of Philips Electronics.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
Each channel of the THS7327 is individually I2C configurable for all functions including controlling the 2:1 input
MUX. Its rail-to-rail output stage allows for both ac and dc coupling applications. The monitor pass-thru path
allows for passing the input signal, with no filtering, on to other systems. This path has a 6-dB Gain, 500-MHz
bandwidth, 1300V/μs slew rate, SAG correction capability, and a high output impedance while disabled to add to
the flexibility of the THS7327.
As part of the THS7327 flexibility, the input can be selected for ac or dc coupled inputs. The ac-coupled modes
include a sync-tip clamp option for CVBS/Y’/G’B’R’ with sync or a fixed bias for the C’/P’B/P’R/R’G’B’ channels
without sync. The dc input options include a dc input or a dc+Offset shift to allow for a full sync dynamic range at
the output with 0-V input.
The THS7327 is available in a RoHS-compliant TQFP package.
PACKAGING/ORDERING INFORMATION (1)
PACKAGED DEVICES
PACKAGE TYPE
THS7327PHP
HTQFP-48 PowerPAD™
THS7327PHPR
(1)
TRANSPORT MEDIA, QUANTITY
Tray, 250
Tape and reel, 1000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
THS7327
UNIT
5.5
V
–0.4 to VA or VDD
V
Output current
±100
mA
Continuous power dissipation
See Dissipation Rating Table
TJ
Maximum junction temperature, any condition (2)
+150
°C
TJ
Maximum junction temperature, continuous operation, long term reliability (3)
+125
°C
Tstg
Storage temperature range
VSS
Supply voltage, GND to VA or GND to VDD
VI
Input voltage
IO
ESD ratings
(1)
(2)
(3)
2
–65 to +150
°C
HBM
1500
V
CDM
1500
V
MM
100
V
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
DISSIPATION RATINGS
(1)
(2)
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
HTQFP-48 with PowerPAD (PHP)
1.1
35
POWER RATING (1)
(TJ = +125°C)
(2)
TA = +25°C
TA = +85°C
2.85 W
1.14 W
This data was taken with a PowerPAD standard 3 inch by 3 inch, 4-layer PCB with internal ground plane connections to the PowerPAD.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase and
long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VDD
Digital supply voltage
2.7
5
VA
Analog supply voltage. Must be equal to or greater than VDD.
VDD
5
V
TA
Ambient temperature
–40
+85
°C
Copyright © 2006–2011, Texas Instruments Incorporated
V
3
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V
RL = 150 Ω || 5 pF to GND for monitor output, 19 kΩ || 8 pF load to GND for ADC buffer, ADC buffer filter = 9 MHz, and SAG
pin shorted to monitor output pin (unless otherwise noted).
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNITS
MIN/MAX/
TYP
AC PERFORMANCE
Small-signal bandwidth
(–3 dB)
Filter select = 9 MHz (1)
9
7/10.4
6.9/10.5
6.8/10.5
MHz
Min/Max
Filter select = 16 MHz (1)
16
13.1/9.6
12.9/19.7
12.8/19.7
MHz
Min/Max
Filter select = 35 MHz (1)
35
28/40.5
27.8/41.3
27.7/41.3
MHz
Min/Max
Filter select = 75 MHz (1)
75
61/86.8
60.5/90.3
60.4/90.3
MHz
Min/Max
Filter select = bypass
500
MHz
Typ
450
MHz
Typ
Filter select = 9 MHz
9
MHz
Typ
Filter select = 16 MHz
16
MHz
Typ
Filter select = 35 MHz
35
MHz
Typ
Filter select = 75 MHz
75
MHz
Typ
Filter select = bypass
500
MHz
Typ
Monitor output
VO = 2 VPP
300
MHz
Typ
Buffer output
Filter select = bypass: VO = 1 VPP
1050
V/μs
Typ
Monitor output
VO = 2 VPP
1050
V/μs
Typ
Filter select = 9 MHz
56
ns
Typ
Filter select = 16 MHz
31
ns
Typ
Filter select = 35 MHz
16
ns
Typ
Filter select = 75 MHz
8
ns
Typ
Filter select = bypass
1.3
ns
Typ
1.3
ns
Typ
Filter select = 9 MHz: at 5.1 MHz
10.5
ns
Typ
Filter select = 16 MHz: at 11 MHz
7.2
ns
Typ
Filter select = 35 MHz: at 27 MHz
4
ns
Typ
Filter select = 75 MHz: at 54 MHz
2
ns
Typ
Filter select = 9 MHz: at 5.75 MHz
0.4
–0.4/1.6
dB
Min/Max
Buffer output
VO = 0.2 VPP
Monitor output
Large-signal bandwidth
(–3 dB)
Buffer output
VO = 1 VPP
Slew rate
Buffer output
Group delay at 100 kHz
Monitor output
Group delay variation
with respect to 100 kHz
Attenuation with respect
to 100 kHz
Buffer output
–0.3/1.5
–0.35/1.55
Filter select = 9 MHz: at 27 MHz
39
31
30.5
30
dB
Min
Filter select = 16 MHz: at 11 MHz
0.5
–0.3/1.5
–0.35/1.55
–0.4/1.6
dB
Min/Max
Filter select = 16 MHz: at 54 MHz
40
32
31.5
31
dB
Min
Filter select = 35 MHz: at 27 MHz
1
–0.3/2.7
-0.35/2.75
–0.4/2.8
dB
Min/Max
Buffer output
Filter select = 35 MHz: at 74 MHz
27
19
18.5
18
dB
Min
Filter select = 75 MHz: at 54 MHz
0.6
–0.3/1.8
–0.4/1.9
–0.45/2
dB
Min/Max
25
17
16.5
16
dB
Min
Buffer output
Filter select = 75 MHz: at 148 MHz
Filter select = 9 MHz: NTSC/PAL
0.3/0.45
%
Typ
Monitor output
NTSC/PAL
0.07/0.08
%
Typ
Buffer output
Filter select = 9 MHz: NTSC/PAL
0.45/0.5
°
Typ
Monitor output
NTSC/PAL
0.07/0.08
°
Typ
Filter select = 9 MHz
–61
dB
Typ
Filter select = 16 MHz
–60
dB
Typ
Filter select = 35 MHz
–57
dB
Typ
Filter select = 75 MHz
–55
dB
Typ
Filter select = bypass
–60
dB
Typ
VO = 2 VPP
–60
dB
Typ
Filter select = 9 MHz
80
dB
Typ
Filter select = 16 MHz
77
dB
Typ
Filter select = 35 MHz
75
dB
Typ
Filter select = 75 MHz
73
dB
Typ
Filter select = bypass (2)
66
dB
Typ
71
dB
Typ
Differential gain
Differential phase
Total harmonic
distortion
f = 1 MHz
Buffer output
VO = 1 VPP
Monitor output
Signal to noise ratio
(unified weighting)
Buffer output
Monitor output
(1)
(2)
4
See
(2)
Min/Max values listed are specified by design only.
Bandwidth up to 100-MHz, no weighting, tilt null.
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V (continued)
RL = 150 Ω || 5 pF to GND for monitor output, 19 kΩ || 8 pF load to GND for ADC buffer, ADC buffer filter = 9 MHz, and SAG
pin shorted to monitor output pin (unless otherwise noted).
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNITS
MIN/MAX/
TYP
AC PERFORMANCE (continued)
Channel-to-channel
crosstalk
Filter select = 9 MHz: at 5 MHz
–58
dB
Typ
Filter select = 16 MHz: at 10 MHz
–65
dB
Typ
Filter select = 35 MHz: at 27 MHz
–58
dB
Typ
Filter select = 75 MHz: at 60 MHz
–58
dB
Typ
Filter select = bypass: at 100 MHz
–47
dB
Typ
F = 100 MHz
–35
dB
Typ
Filter select = 9 MHz: at 5.5 MHz
65
dB
Typ
Filter select = 16 MHz: at 11 MHz
65
dB
Typ
Filter select = 35 MHz: at 27 MHz
65
dB
Typ
Filter select = bypass: at 60 MHz
65
dB
Typ
Monitor output
f = 100 MHz
66
dB
Typ
Buffer output
f = 100 kHz; VO = 1 VPP
0
dB
Typ
Monitor output
f = 100 kHz; VO = 2 VPP
6
dB
Min/Max
6
ns
Typ
6
ns
Typ
Buffer output
Monitor output
Buffer output
MUX isolation
Gain
Buffer output
Settling time
Monitor output
VIN = 1 VPP; 0.5% Settling
5.8/6.25
5.75/6.3
5.75/6.35
Buffer output
f = 10 MHz
2
Ω
Typ
Monitor output
f = 10 MHz
0.4
Ω
Typ
Buffer output
Bias = dc, filter = 16 MHz
65
130
135
135
mV
Max
Monitor output
Bias = dc
20
90
95
95
mV
Max
Buffer output
Bias = dc
20
μV/°C
Typ
Monitor output
Bias = dc
20
μV/°C
Typ
240/450
mV
Min/Max
Output impedance
DC PERFORMANCE
Output offset voltage
Average offset voltage
drift
Buffer output
Bias = dc + shift, VIN = 0 V
340
260/430
250/440
Bias = ac-bias
1.1
0.95/1.25
0.9/1.3
0.9/1.3
V
Min/Max
Bias = dc + Shift, VIN = 0 V
230
160/350
155/370
150/375
mV
Min/Max
Bias = ac-bias
1.7
1.55/1.85
1.5/1.9
1.5/1.9
V
Min/Max
345
260/500
255/505
250/510
mV
Min/Max
305
210/400
205/405
200/410
mV
Min/Max
–1.4
–3
–3.5
–3.5
μA
Max
10
nA/°C
Typ
0.7/3.8
μA
Min/Max
Bias output voltage
Monitor output
Buffer output
Sync tip clamp voltage
Bias = ac STC, clamp voltage
Monitor output
Input bias current
Bias = dc – implies Ib out of the pin
Average bias current drift
Bias = dc
Sync tip clamp bias current
Bias = ac STC, low bias
2.3
0.9/3.5
0.8/3.7
Bias = ac STC, mid bias
Bias = ac STC, high bias
5.9
4.2/8
4/8.2
3.9/8.3
μA
Min/Max
8.2
6.1/10.8
6/1
5.9/11.1
μA
Min/Max
INPUT CHARACTERISTICS
Input voltage range
Bias = dc
0/1.8
V
Typ
Bias = ac-bias mode
25
kΩ
Typ
Bias = dc, dc + shift, ac STC
3
MΩ
Typ
1.5
pF
Typ
Input resistance
Input capacitance
OUTPUT CHARACTERISTICS – MONITOR OUTPUT
High output voltage swing
Low output voltage swing
RL = 150 Ω to 1.65 V
3.15
2.9
2.8
2.8
V
Min
RL = 150 Ω to GND
3.05
2.85
2.75
2.75
V
Min
RL = 75 Ω to 1.65 V
3.05
V
Min
RL = 75 Ω to GND
2.9
V
Min
RL = 150 Ω to 1.65 V
0.15
0.25
0.28
0.29
V
Min
RL = 150 Ω to GND
0.1
0.18
0.21
0.22
V
Min
RL = 75 Ω to 1.65 V
0.25
V
Min
RL = 75 Ω to GND
0.08
V
Min
Sourcing
RL = 10 Ω to 1.65 V
80
50
47
45
mA
Min
Sinking
RL = 10 Ω to 1.65 V
75
50
47
45
mA
Min
Output current
Copyright © 2006–2011, Texas Instruments Incorporated
5
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V (continued)
RL = 150 Ω || 5 pF to GND for monitor output, 19 kΩ || 8 pF load to GND for ADC buffer, ADC buffer filter = 9 MHz, and SAG
pin shorted to monitor output pin (unless otherwise noted).
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
–40°C to
+85°C
UNITS
MIN/MAX/
TYP
+25°C
+25°C
0°C to
+70°C
2
1.8
1.75
1.75
V
Min
0.14
0.24
0.27
0.28
V
Max
OUTPUT CHARACTERISTICS – BUFFER OUTPUT
High output voltage swing (limited by input
range and G = 0 dB)
Load = 19 kΩ || 8 pF to 1.65 V
Low output voltage swing (limited by input
range and G = 0 dB)
Sourcing
RL = 10 Ω to GND
80
50
47
45
mA
Min
Sinking
RL = 10 Ω to 1.65 V
75
50
47
45
mA
Min
Maximum operating voltage
VA
3.3
5.5
5.5
5.5
V
Max
Minimum operating voltage
VA
3.3
2.7
2.7
2.7
V
Min
Maximum quiescent current
VA, dc + shift mode, VIN = 100 mV
100
120
123
125
mA
Max
Minimum quiescent current
VA, dc + shift mode, VIN = 100 mV
100
80
77
75
mA
Min
Power-supply rejection (+PSRR)
Buffer output
50
dB
Typ
Maximum operating voltage
VDD
3.3
5.5
5.5
5.5
V
Max
Minimum operating voltage
VDD
3.3
2.7
2.7
2.7
V
Min
Maximum quiescent current
VDD, VIN = 0 V
0.65
1.2
1.3
1.4
mA
Max
Minimum quiescent current
VDD, VIN = 0 V
0.65
0.35
0.3
0.25
mA
Min
0.1
μA
Typ
5
μs
Typ
2
μs
Typ
Output current
POWER SUPPLY – ANALOG
POWER SUPPLY – DIGITAL
DISABLE CHARACTERISTICS – ALL CHANNELS DISABLED
(3)
Quiescent current
All 3 channels disabled
Turn-on time delay (tON)
Time for ls to reach 50% of final value after I2C control
is initiated
Turn-on time delay (tOFF)
DIGITAL CHARACTERISTICS (4)
High level input voltage
VIH
2.3
V
Typ
Low level input voltage
VIL
1.0
V
Typ
HV SYNC CHARACTERISTICS – RLOAD = 1 kΩ To GND
Schmitt trigger adj. pin voltage
Reference for Schmitt trigger
Schmitt trigger threshold range
Allowable range for Schmitt trigger adj.
V
Min/Max
0.9 to 2
V
Typ
Schmitt trigger VT+
Positive going input voltage threshold relative to
Schmitt trigger threshold
0.25
V
Typ
Schmitt trigger VT–
Negative going input voltage threshold relative to
Schmitt trigger threshold
–0.3
V
Typ
Schmitt trigger threshold pin input resistance
Input Resistance into Control Pin
10
kΩ
Typ
10
MΩ
Typ
H V sync input impedance
1.48
1.35/1.6
1.3/1.65
1.27/1.68
H V sync high output voltage
1 kΩ to GND
3.15
3.05
3
3
V
Min
H V sync low output voltage
1 kΩ to GND
0.01
0.05
0.1
0.1
V
Max
H V sync source current
10 Ω to GND
50
35
30
30
mA
Min
H V sync sink current
10 Ω to 3.3V
35
25
23
21
mA
Min
H V delay
Delay from input to output
6.5
ns
Typ
No filter on buffer channel
5
ns
Typ
H V to buffer output skew
(3)
(4)
6
2
Note that the I C circuitry is still active while in disable mode. The current shown is while there is no activity with the THS7327 circuitry.
Standard CMOS logic.
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V
RL = 150 Ω || 5 pF to GND for monitor output, 19 kΩ || 8 pF load to GND for ADC buffer, ADC buffer filter = 9 MHz, and SAG
pin shorted to monitor output pin (unless otherwise noted).
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
–40°C to
+85°C
UNITS
MIN/MAX/
TYP
6.7/10.5
6.7/10.5
MHz
Min/Max
12.9/19.7
12.8/19.7
MHz
Min/Max
27.8/41.3
27.7/41.3
MHz
Min/Max
63.5/92.3
63.4/92.4
MHz
Min/Max
500
MHz
Typ
500
MHz
Typ
Filter select = 9 MHz
9
MHz
Typ
Filter select = 16 MHz
16
MHz
Typ
Filter select = 35 MHz
35
MHz
Typ
Filter select = 75 MHz
78
MHz
Typ
Filter select = bypass
500
MHz
Typ
Monitor output
VO = 2 VPP
425
MHz
Typ
Buffer output
Filter select = bypass: VO = 1 VPP
1150
V/μs
Typ
Monitor output
VO = 2 VPP
1300
V/μs
Typ
Filter select = 9 MHz
56
ns
Typ
Filter select = 16 MHz
31
ns
Typ
Filter select = 35 MHz
16
ns
Typ
Filter select = 75 MHz
8
ns
Typ
Filter select = bypass
1.3
ns
Typ
1.25
ns
Typ
Filter select = 9 MHz: at 5.1 MHz
10.5
ns
Typ
Filter select = 16 MHz: at 11 MHz
7.2
ns
Typ
Filter select = 35 MHz: at 27 MHz
4
ns
Typ
Filter select = 75 MHz: at 54 MHz
2
ns
Typ
Filter select = 9 MHz: at 5.75 MHz
0.4
–0.4/1.6
dB
Min/Max
+25°C
+25°C
Filter select = 9 MHz (1)
9
6.8/10.4
Filter select = 16 MHz (1)
16
13.1/9.6
Filter select = 35 MHz (1)
35
28/40.5
Filter select = 75 MHz (1)
78
64/89
Filter select = bypass
0°C to
+70°C
AC PERFORMANCE
Small-signal bandwidth
(–3 dB)
Buffer output
VO = 0.2 VPP
Monitor output
Large-signal bandwidth
(–3 dB)
Buffer output
VO = 1 VPP
Slew rate
Buffer output
Group delay at 100 kHz
Monitor output
Group delay variation
with respect to 100 kHz
Attenuation with respect
to 100 kHz
Buffer output
Buffer output
(2)
–0.3/1.5
–0.35/1.55
Filter select = 9 MHz: at 27 MHz
39
31
30.5
30
dB
Min
Filter select = 16 MHz: at 11 MHz
0.5
–0.3/1.5
–0.35/1.55
–0.4/1.6
dB
Min/Max
Filter select = 16 MHz: at 54 MHz
40
32
31.5
31
dB
Min
Filter select = 35 MHz: at 27 MHz
1
–0.3/2.7
–0.35/2.75
–0.4/2.8
dB
Min/Max
Filter select = 35 MHz: at 74 MHz
27
19
18.5
18
dB
Min
Filter select = 75 MHz: at 54 MHz
0.6
–0.3/1.8
–0.4/1.9
–0.45/2
dB
Min/Max
25
17
16.5
16
dB
Min
Buffer output
Filter select = 75 MHz: at 148 MHz
Filter select = 9 MHz: NTSC/PAL
0.3/0.45
%
Typ
Monitor output
NTSC/PAL
0.07/0.08
%
Typ
Buffer output
Filter select = 9 MHz: NTSC/PAL
0.45/0.5
°
Typ
Monitor output
NTSC/PAL
0.07/0.08
°
Typ
Filter select = 9 MHz
–61
dB
Typ
Filter select = 16 MHz
–60
dB
Typ
Filter select = 35 MHz
–57
dB
Typ
Filter select = 75 MHz
–55
dB
Typ
Filter select = bypass
–60
dB
Typ
VO = 2 VPP
–60
dB
Typ
Filter select = 9 MHz
80
dB
Typ
Filter select = 16 MHz
77
dB
Typ
Filter select = 35 MHz
75
dB
Typ
Filter select = 75 MHz
73
dB
Typ
Filter select = bypass (3)
66
dB
Typ
71
dB
Typ
Differential gain
Differential phase
Total harmonic
distortion
f = 1 MHz
Buffer output
VO = 1 VPP
Monitor output
Signal to noise ratio
(unified weighting)
Buffer output
Monitor output
(1)
(2)
(3)
See
(3)
Min/Max values listed are specified by design only.
Performance specified by design, characterization, and 3.3-V testing only.
Bandwidth up to 100-MHz, no weighting, tilt null.
Copyright © 2006–2011, Texas Instruments Incorporated
7
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V (continued)
RL = 150 Ω || 5 pF to GND for monitor output, 19 kΩ || 8 pF load to GND for ADC buffer, ADC buffer filter = 9 MHz, and SAG
pin shorted to monitor output pin (unless otherwise noted).
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNITS
MIN/MAX/
TYP
AC PERFORMANCE (continued)
Channel-to-channel
crosstalk
Filter select = 9 MHz: at 5 MHz
–58
dB
Typ
Filter select = 16 MHz: at 10 MHz
–65
dB
Typ
Filter select = 35 MHz: at 27 MHz
–58
dB
Typ
Filter select = 75 MHz: at 60 MHz
–58
dB
Typ
Filter select = bypass: at 100 MHz
–47
dB
Typ
F = 100 MHz
–35
dB
Typ
Filter select = 9 MHz: at 5.5 MHz
65
dB
Typ
Filter select = 16 MHz: at 11 MHz
65
dB
Typ
Filter select = 35 MHz: at 27 MHz
65
dB
Typ
Filter select = bypass: at 60 MHz
65
dB
Typ
Monitor output
f = 100 MHz
66
dB
Typ
Buffer output
f = 100 kHz; VO = 1 VPP
0
dB
Typ
Monitor output
f = 100 kHz; VO = 2 VPP
6
dB
Min/Max
6
ns
Typ
6
ns
Typ
Buffer output
Monitor output
Buffer output
MUX isolation
Gain
Buffer output
Settling time
Monitor output
VIN = 1 VPP; 0.5% settling
5.8/6.25
5.75/6.3
5.75/6.35
Buffer output
f = 10 MHz
2
Ω
Typ
Monitor output
f = 10 MHz
0.4
Ω
Typ
Buffer output
Bias = dc, filter = 16 MHz
50
120
125
125
mV
Max
Monitor output
Bias = dc
5
80
85
85
mV
Max
Buffer output
Bias = dc
20
μV/°C
Typ
Monitor output
Bias = dc
20
μV/°C
Typ
mV
Min/Max
Output impedance
DC PERFORMANCE
Output offset voltage
Average offset voltage
drift
Buffer output
Bias = dc + shift, VIN = 0 V
345
265/450
255/455
250/460
Bias = ac-bias
Bias = dc + shift, VIN = 0 V
1.55
1.4/1.7
1.35/1.75
1.35/1.75
V
Min/Max
230
150/340
145/345
140/350
mV
Bias = ac-bias
Min/Max
2.65
2.5/2.8
2.45/2.85
2.45/2.85
V
Min/Max
350
265/500
260/505
255/510
mV
Min/Max
305
210/400
205/405
200/410
mV
Min/Max
–1.4
–3
–3.5
–3.5
μA
Max
10
nA/°C
Typ
0.8/4.1
μA
Min/Max
Bias output voltage
Monitor output
Sync tip clamp output
voltage
Buffer output
Bias = ac STC, clamp voltage
Monitor output
Input bias current
Bias = dc – implies Ib out of the pin
Average bias current drift
Bias = dc
Sync tip clamp bias current
Bias = ac STC, low bias
2.45
1/3.9
0.9/4
Bias = ac STC, mid bias
6.35
4.3/8.4
4.1/8.6
4/8.7
μA
Min/Max
Bias = ac STC, high bias
8.75
6.4/11.2
6.2/11.4
6.1/11.5
μA
Min/Max
Bias = dc
0/2.5
0/2.45
0/2.4
0/2.4
INPUT CHARACTERISTICS
Input voltage range
V
Typ
Bias = ac-bias mode
20
kΩ
Typ
Bias = dc, dc + shift, ac STC
3
MΩ
Typ
2
pF
Typ
Input resistance
Input capacitance
OUTPUT CHARACTERISTICS – MONITOR OUTPUT
RL = 150 Ω to 2.5 V
4.8
4.65
4.6
4.6
V
Min
RL = 150 Ω to GND
4.7
4.55
4.5
4.5
V
Min
RL = 75 Ω to 2.5 V
4.7
V
Min
RL = 75 Ω to GND
4.6
V
Min
RL = 150 Ω to 2.5 V
0.19
0.25
0.28
0.3
V
Min
RL = 150 Ω to GND
0.11
0.19
0.23
0.24
V
Min
RL = 75 Ω to 2.5 V
0.24
V
Min
RL = 75 Ω to GND
0.085
V
Min
Sourcing
RL = 10 Ω to 2.5 V
110
85
80
75
mA
Min
Sinking
RL = 10 Ω to 2.5 V
115
85
80
75
mA
Min
High output voltage swing
Low output voltage swing
Output current
8
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V (continued)
RL = 150 Ω || 5 pF to GND for monitor output, 19 kΩ || 8 pF load to GND for ADC buffer, ADC buffer filter = 9 MHz, and SAG
pin shorted to monitor output pin (unless otherwise noted).
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
–40°C to
+85°C
UNITS
MIN/MAX/
TYP
+25°C
+25°C
0°C to
+70°C
3.4
3.1
3
3
V
Min
0.14
0.24
0.27
0.28
V
Max
OUTPUT CHARACTERISTICS – BUFFER OUTPUT
High output voltage swing (limited by input
range and G = 0 dB)
Load = 19 kΩ || 8 pF to 2.5 V
Low output voltage swing (limited by input
range and G = 0 dB)
Sourcing
RL = 10 Ω to GND
110
85
80
75
mA
Min
Sinking
RL = 10 Ω to 2.5V
80
85
80
75
mA
Min
Maximum operating voltage
VA
5
5.5
5.5
5.5
V
Max
Minimum operating voltage
VA
5
2.7
2.7
2.7
V
Min
Maximum quiescent current
VA, dc + shift mode, VIN = 100 mV
118
145
148
150
mA
Max
Minimum quiescent current
VA, dc + shift mode, VIN = 100 mV
118
95
92
90
mA
Min
Power-supply rejection (+PSRR)
Buffer output
46
dB
Typ
Maximum operating voltage
VDD
5
5.5
5.5
5.5
V
Max
Minimum operating voltage
VDD
5
2.7
2.7
2.7
V
Min
Maximum quiescent current
VDD, VIN = 0 V
1
2
3
3
mA
Max
Minimum quiescent current
VDD, VIN = 0 V
1
0.5
0.4
0.4
mA
Min
1
μA
Typ
5
μs
Typ
2
μs
Typ
Output current
POWER SUPPLY – ANALOG
POWER SUPPLY – DIGITAL
DISABLE CHARACTERISTICS – ALL CHANNELS DISABLED
(4)
Quiescent current
All channels disabled
Turn-on time delay (tON)
Time for ls to reach 50% of final value after I2C control
is initiated
Turn-on time delay (tOFF)
DIGITAL CHARACTERISTICS (5)
High level input voltage
VIH
3.5
V
Typ
Low level input voltage
VIL
1.5
V
Typ
HV SYNC CHARACTERISTICS (6)
Schmitt trigger adj. pin voltage
Reference for Schmitt trigger
Schmitt trigger threshold range
Allowable range for Schmitt trigger adj.
V
Min/Max
0.9 to 2
V
Typ
Schmitt trigger VT+
Positive going input voltage threshold relative to
Schmitt trigger threshold
0.25
V
Typ
Schmitt trigger VT–
Negative going input voltage threshold relative to
Schmitt trigger threshold
–0.3
V
Typ
Schmitt trigger threshold pin input resistance
Input resistance into control pin
10
kΩ
Typ
10
MΩ
Typ
H V sync input impedance
1.55
1.45/1.65
1.4/1.7
1.37/1.73
H V sync high output voltage
1 kΩ to GND
4.8
4.7
4.6
4.6
V
Min
H V sync low output voltage
1 kΩ to GND
0.01
0.05
0.1
0.1
V
Max
H V sync source current
10 Ω to GND
90
60
55
55
mA
Min
H V sync sink current
10 Ω to 5 V
50
30
27
25
mA
Min
H V delay
Delay from input to output
6.5
ns
Typ
No filter on buffer channel
5
ns
H V to buffer output skew
(4)
(5)
(6)
2
Typ
2
Note that the I C circuitry is still active while in disable mode. The current shown is while there is no activity with the THS7327 I C
circuitry.
Standard CMOS logic.
Schmitt trigger threshold is defined by (VT+ – VT–)/2.
Copyright © 2006–2011, Texas Instruments Incorporated
9
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
TIMING REQUIREMENTS FOR I2C INTERFACE (1) (2)
At VDD = 2.7 V to 5 V.
STANDARD MODE
PARAMETER
MIN
MAX
100
FAST MODE
MIN
MAX
0
400
UNIT
fSCL
Clock frequency, SCL
0
tw(H)
Pulse duration, SCL high
4
0.6
μs
tw(L)
Pulse duration, SCL low
4.7
1.3
μs
tr
Rise time, SCL and SDA
1000
300
ns
tf
Fall time, SCL and SDA
300
300
ns
tsu(1)
Setup time, SDA to SCL
th(1)
Hold time, SCL to SDA
0
0
ns
t(buf)
Bus free time between stop and start conditions
4.7
1.3
μs
tsu(2)
Setup time, SCL to start condition
4.7
0.6
μs
th(2)
Hold time, start condition to SCL
4
0.6
μs
tsu(3)
Setup time, SCL to stop condition
4
0.6
Cb
Capacitive load for each bus line
(1)
(2)
250
100
400
kHz
ns
μs
400
pF
The THS7327 I2C address = 01011(A1)(A0)(R/W). See the Application Information section for more information.
The THS7327 was designed to comply with Version 2.1 of the I2C specification.
t w(H)
t w(L)
tr
tf
SCL
t su(1)
t h(1)
SDA
Figure 2. SCL and SDA Timing
SCL
t su(2)
t h(2)
t su(3)
t (buf)
SDA
Start Condition
Stop Condition
Figure 3. Start and Stop Conditions
10
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
FUNCTIONAL DIAGRAM
Bypass
Channel 1
Input A
2:1
X1
Channel 2
Input A
DC
+Offset
Channel 3
Input A
AC
Sync
TIP
Clamp
DC
ACBIAS
H-Sync
Input A
+
LPF
9/16/35/
75MHz
Channel 1 Buffer
Output (To ADC)
-
+
Disable
= OPEN
-
675 W
V-Sync
Input A
Channel 1 Monitor
Output
Channel 1 SAG
1 kW
878 W
150 W
Bypass
2:1
X1
DC
+Offset
AC
Sync
TIP
Clamp
DC
ACBIAS
+
LPF
9/16/35/
75MHz
Channel 2 Buffer
Output (To ADC)
-
+
Disable
= OPEN
-
675 W
Channel 2 Monitor
Output
Channel 2 SAG
1 kW
878 W
150 W
Bypass
X1
2:1
DC
+Offset
DC
ACBIAS
AC
Sync
TIP
Clamp
+
LPF
9/16/35/
75MHz
Channel 3 Buffer
Output (To ADC)
-
+
Disable
= OPEN
-
675 W
Channel 3 Monitor
Output
Channel 3 SAG
1 kW
Channel 1
Input B
2:1
878 W
150 W
+
Channel 2
Input B
Horizontal Sync
Buffer OUTPUT
-
Channel 3
Input B
Horizontal Sync
Monitor OUTPUT
H-Sync
Input B
V-Sync
Input B
2:1
+
Vertical Sync
Buffer OUTPUT
10 kW
Vertical Sync
Monitor OUTPUT
+1.4 V
MUX
MODE
MUX
SELECT
SCHMITT SDA SCL I2C- I2C- PUC
A1 A0
TRIGGER
ADJUST
+VDD DGND +VA
AGND
NOTE: The I2C address of the THS7327 is 01011(A1)(A0)(R/W).
Copyright © 2006–2011, Texas Instruments Incorporated
11
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
PIN CONFIGURATION
1
2
CH. 1 - INPUT A
CH. 2 - INPUT A
CH. 3 - INPUT A
H-SYNC - INPUT A
V-SYNC - INPUT A
AGND
CH. 1 - INPUT B
V-Sync - INPUT B
+VA
AGND
V - SYNC MON. OUTPUT
CH. 3 - SAG
H - SYNC MON. OUTPUT
CH. 2 - SAG
CH. 3 - MONITOR OUTPUT
35
CH. 1 - BUFFER OUTPUT
CH. 1 - BUFFER OUTPUT
3
34
AGND
4
5
33
+VA
CH. 2 - BUFFER OUTPUT
32
31
THS7327
PowerPAD
7
8
CH. 3 - INPUT B
H-Sync - INPUT B
CH. 1 - MONITOR OUTPUT
48 47 46 45 44 43 42 41 40 39 38 37
36
6
CH. 2 - INPUT B
CH. 1 - SAG
CH. 2 - MONITOR OUTPUT
+VA
AGND
THS7327PHP
HTQFP-48 (PHP)
(Top View)
30
29
9
28
10
11
27
26
VDD
AGND
+VA
CH. 3 - BUFFER OUTPUT
CH. 3 - BUFFER OUTPUT
AGND
H-SYNC BUFFER OUTPUT
DGND
V-SYNC BUFFER OUTPUT
PUC
I2C - SCL
I2C - A1
I2C - A0
I2C - SDA
AGND
SCHMITT-TRIGGER ADJ.
MUX MODE
MUX SELECT
12
25
13 14 15 16 17 18 19 20 21 22 23 24
AGND
CH. 2 - BUFFER OUTPUT
TERMINAL FUNCTIONS
TERMINAL
NO.
HTQFP-48
I/O
CH. 1 – input A
1
I
Video input channel 1 – input A
CH. 2 – input A
2
I
Video input channel 2 – input A
CH. 3 – input A
3
I
Video input channel 3 – input A
H-sync – input A
4
I
Horizontal sync – input A
V-sync – input A
5
I
Vertical sync – input A
CH. 1 – input B
7
I
Video input channel 1 – input B
CH. 2 – input B
8
I
Video input channel 2 – input B
CH. 3 – input B
9
I
Video input channel 3 – input B
H-sync – input B
10
I
Horizontal sync – input B
V-sync – input B
11
I
Vertical sync – input B
I2C-A1
17
I
I2C slave address control bit A1 – connect to VS+ for a Logic 1 preset value or GND for a
logic 0 preset value.
I2C-A0
18
I
I2C slave address control bit A0 – connect to VS+ for a Logic 1 preset value or GND for a
logic 0 preset value.
NAME
12
DESCRIPTION
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
HTQFP-48
I/O
I2C-SDA
19
I/O
I2C-SCL
20
I
I2C bus clock line. Pull-up resistor should have a minimum value = 2-kΩ and a maximum
value = 19-kΩ. Pull up to VS+.
PUC
21
I
Power-up condition – connect to GND for all channels disabled upon power-up. Connect to
VDD (logic high) to set buffer outputs to OFF and monitor outputs ON with ac-bias
configuration on channels 1 to 3 and HV syncs are enabled.
MUX MODE
15
I
Sets the MUX configuration control – connect to logic low for MUX select (pin 16) control of
the MUX. Connect to logic high for I2C control of the MUX.
MUX select
16
I
Controls the MUX selection when MUX MODE (pin 15) is set to logic low. Connect to logic
low for MUX selector set to input A. Connect to logic high for MUX selector set to input B.
CH. 1 – buffer output
35, 36
O
Output channel 1 from either CH. 1 – input A or CH. 1 – input B – connect to ADC / Scalar /
Decoder
CH. 2 – buffer output
31, 32
O
Output channel 1 from either CH. 2 – input A or CH. 2 – input B – connect to ADC / Scalar /
Decoder
CH. 3 – buffer output
27, 28
O
Output channel 3 from either CH. 3 – input A or CH. 3 – input B – connect to ADC / Scalar /
Decoder
Horizontal sync output
25
O
Horizontal sync output – Connect to ADC / Scalar H-sync input
Vertical sync output
24
O
Vertical sync output – Connect to ADC / Scalar V-sync input
CH. 1 - SAG
45
O
Video monitor pass-thru output channel 1 SAG correction pin. If SAG is not used, connect
directly to CH. 1 – output pin 46.
CH. 1 – output
46
O
Video monitor pass-thru output channel 1 from either CH. 1 – input A or CH. 1 – input B
CH. 2 - SAG
43
O
Video monitor pass-thru output channel 2 SAG correction pin. If SAG is not used, connect
directly to CH. 2 – output pin 44.
CH. 2 – output
44
O
Video monitor pass-thru output channel 2 from either CH. 2 – input A or CH. 2 – input B
CH. 3 - SAG
41
O
Video monitor pass-thru output channel 3 SAG correction pin. If SAG is not used, connect
directly to CH. 3 – output pin 42.
CH. 3 – output
42
O
Video monitor pass-thru output channel 3 from either CH. 3 – input A or CH. 3 – input B
Horizontal sync
monitor output
40
O
Horizontal sync monitor pass-thru output
Vertical sync monitor
output
39
O
Vertical sync monitor pass-thru output
AGND
6, 12, 13,
26, 30, 34,
37, 47
I
Ground reference pin for analog signals. Internally these pins connect to DGND. Although it
is recommended to have the AGND and DGND connected to the proper signals for best
results.
+VA
29, 33, 38,
48
I
Analog positive power-supply input pins – connect to 2.7 V to 5 V. Must be equal to or
greater than VDD.
VDD
22
I
Digital positive supply pin for I2C circuitry and HV sync outputs – connect to 2.7 V to 5 V.
DGND
23
I
Digital GND pin for HV circuitry and I2C circuitry.
Schmitt trigger adjust
14
I
Defaults to 1.45V (TTL compatible). Connect to external voltage reference to adjust HV sync
input thresholds from 0.9-V to 2-V range.
NAME
DESCRIPTION
Serial data line of the I2C bus. Pull-up resistor should have a minimum value = 2-kΩ and a
maximum value = 19-kΩ. Pull up to VS+.
Copyright © 2006–2011, Texas Instruments Incorporated
13
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS: 3.3 V
SLEW RATE
vs
OUTPUT VOLTAGE
SLEW RATE
vs
OUTPUT VOLTAGE
250
1300
VA = 3.3 V
VA = 3.3 V
1200
Buffer LPF = Bypass
200
SR − Slew Rate − V/ms
SR − Slew Rate − V/ms
1100
Buffer LPF = 75 MHz
150
Buffer LPF = 35 MHz
Buffer LPF = 16 MHz
100
Buffer LPF = 9 MHz
1000
900
Monitor Output
800
700
50
600
500
0.5
0
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
0.9
0.7
1.1
1.3
1.5
1.7
1.9
VO − Output Voltage − VPP
VO − Output Voltage − VPP
Figure 4.
Figure 5.
2.1
2.3
2.5
TYPICAL CHARACTERISTICS: 5 V
SLEW RATE
vs
OUTPUT VOLTAGE
SLEW RATE
vs
OUTPUT VOLTAGE
1600
250
VA = 5 V
1500
VA = 5 V
Buffer LPF = Bypass
1400
Buffer LPF = 75 MHz
SR − Slew Rate − V/ms
SR − Slew Rate − V/ms
200
150
Buffer LPF = 35 MHz
Buffer LPF = 16 MHz
100
Buffer LPF = 9 MHz
50
1300
1200
Monitor Output
1100
1000
900
800
700
0
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VO − Output Voltage − VPP
Figure 6.
14
1.3
1.4
1.5
600
0.5
1
1.5
2
2.5
3
3.5
4
VO − Output Voltage − VPP
Figure 7.
Copyright © 2006–2011, Texas Instruments Incorporated
THS7327
SLOS502C – SEPTEMBER 2006 – REVISED OCTOBER 2011
www.ti.com
APPLICATION INFORMATION
The THS7327 is targeted for RGB + HV sync video buffer applications. Although it can be used for numerous
other applications, the needs and requirements of the video signal are the most important design parameters of
the THS7327. Built on the complementary Silicon Germanium (SiGe) BiCom-3 process, the THS7327
incorporates many features not typically found in integrated video parts while consuming low power. Each
channel configuration is completely independent of the other channels. This allows for ANY configuration for
each channel to be dictated by the end user rather than the device—resulting in a highly flexible system. The
THS7327 has the following features:
• I2C Interface for easy interfacing to the system
• Single-supply 2.7-V to 5-V operation with low quiescent current of 100-mA at 3.3-V
• 2:1 input MUX
• Input configuration accepting dc, dc + shift, ac bias, or ac sync-tip clamp selection.
• Unity Gain Buffer path to drive analog-to-digital converter (ADC)/Scalar/Decoder.
• Selectable 5th-order low-pass filter on buffer path for digital-to-analog converter (DAC) reconstruction or ADC
image rejection:
– 9-MHz for SDTV NTSC and 480i, PAL/SECAM and 576i, and S-Video signals.
– 16-MHz for EDTV 480p and 576p Y'P'BP'R signals and R'G'B' (G'B'R') VGA signals.
– 35-MHz for HDTV 720p and 1080i Y’P’BP’R signals and R'G'B' SVGA and XGA signals.
– 75-MHz for HDTV 1080p and R’G’B’ SXGA signals.
– Bypass mode for passing R'G'B' UXGA, QXGA or higher signals.
• Monitor Pass-thru path has an internal fixed gain of 2V/V (6 dB) amplifier that can drive two video lines with
dc coupling, traditional ac coupling, or SAG corrected ac coupling.
• While disabled, the Monitor Pass-Thru path has a high output impedance (> 500 kΩ || 8 pF)
• Power Up Control (PUC) allows the THS7327 to be fully disabled or have the Monitor Pass-Thru function
(with AC-Bias mode on all channels) enabled upon initial power-up.
• MUX is controlled by either I2C or GPIO pin based on the MUX Mode pin logic.
• H and V Sync paths have an externally adjustable Schmitt Trigger threshold
• Disable mode which reduces quiescent current to as low as 0.1-μA.
OPERATING VOLTAGE
The THS7327 is designed to operate from 2.7 V to 5 V over a –40°C to +85°C temperature range. The impact on
performance over the entire temperature range is negligible due to the implementation of thin film resistors and
low-temperature coefficient capacitors.
The power supply pins should have a 0.1-μF to 0.01-μF capacitor placed as close as possible to these pins.
Failure to do so may result in the THS7327 outputs ringing or oscillating. Additionally, a large capacitor, such as
22 μF to 100 μF, should be placed on the power-supply line to minimize issues with 50-Hz/60-Hz line
frequencies.
INPUT VOLTAGE
The THS7327 input range allows for an input signal range from ground to about (VS+ – 1.6 V). But, due to the
internal fixed gain of 2V/V (6 dB), the output is generally the limiting factor for the allowable linear input range.
For example, with a 5-V supply, the linear input range is from GND to 3.4 V. But due to the gain, the linear output
range limits the allowable linear input range to be from GND to at most 2.5 V.
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INPUT OVERVOLTAGE PROTECTION
The THS7327 is built using a high-speed complementary bipolar and CMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 8.
VS+
External
Input/
Output
Pin
Internal
Circuitry
Figure 8. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above and below the supplies. The
protection diodes can typically support 30-mA of continuous current when overdriven.
TYPICAL CONFIGURATION
The THS7327 is typically used as a video buffer driving a video ADC (such as the TVP7001) with 0-dB gain and
the monitor output path drives an output line with 6-dB gain along with horizontal (H) and vertical (V) sync
signals. The versatility of the THS7327 allows virtually any video signal to be utilized. This includes
standard-definition (SD), enhanced-definition (ED), and high-definition (HD) Y’P’BP’R (sometimes labeled Y’U’V’
or incorrectly labeled Y’C’BC’R) signals, S-Video Y’/C’ signals, and the composite video baseband signal (CVBS)
of a SD video system. These signals can also be R’G’B’ (or G’B’R’) or other variations on the placement of the
sync signals commonly called R’G’sB’ (sync on Green) or R’sG’sB’s (sync on all signals). Additionally, the
THS7327 handles the digital H and V sync signals with the noise immunity enhancement of a schmitt trigger.
This schmitt trigger defaults to 1.45 V, but can be set externally to be anywhere form 0.9 V to 2.0 V for added
flexibility.
Simple control of the I2C configures the THS7327 for any configuration conceivable. For example, the THS7327
can be configured to have Channel 1 Input connected to input A while Channels 2 and 3 could be connected to
input B. See the multiple application notes sections explaining the I2C interface later in this document on how to
configure these options.
Note that the Y’ term is used for the luma channels throughout this document rather than the more common
luminance (Y) term. This is to account for the true definition of luminance as stipulated by the CIE - International
Commission on Illumination. Video departs from true luminance since a nonlinear term, gamma, is added to the
true RGB signals to form R’G’B’ signals. These R’G’B’ signals are then used to mathematically create luma (Y’).
Thus, true luminance (Y) is not maintained and hence, the difference in terminology.
This rationale is also used for the chroma (C’) term. Chroma is derived from the non-linear R’G’B’ terms and thus
it is non-linear. True chrominance (C) is derived from linear RGB and hence the difference between chroma (C’)
and chrominance (C). The color difference signals (P’B / P’R / U’ / V’) are also referenced this way to denote the
non-linear (gamma corrected) signals.
R’G’B’ (commonly mislabeled RGB) is also called G’B’R’ (again commonly mislabeled as GBR) in professional
video systems. The SMPTE component standard stipulates that the luma information is placed on the first
channel, the blue color difference is placed on the second channel, and the red color difference signal is placed
on the third channel. This is consistent with the Y'P’BP’R nomenclature. Because the luma channel (Y') carries
the sync information and the green channel (G') also carries the sync information, it makes logical sense that G'
16
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be placed first in the system. Since the blue color difference channel (P'B) is next and the red color difference
channel (P'R) is last, then it also makes logical sense to place the B' signal on the second channel and the R'
signal on the third channel respectfully. Thus, hardware compatibility is better achieved when using G'B'R' rather
than R'G'B'. Note that for many G'B'R' systems, sync is embedded on all three channels, but may not always be
the case in all systems.
I2C INTERFACE NOTES
The I2C interface is used to access the internal registers of the THS7327. I2C is a two-wire serial interface
developed by Philips Semiconductor (see the I2C-Bus Specification, Version 2.1, January 2000). The THS7327
was designed to comply with version 2.1 specifications. The bus consists of a data line (SDA) and a clock line
(SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the
I2C-compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device,
usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating
the SCL signal and device addresses. The master also generates specific conditions that indicate the START
and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master
device. The THS7327 works as a slave and supports the standard mode transfer (100 kbps) and fast mode
transfer (400 kbps) as defined in the I2C-Bus specification. The THS7327 has been tested to be fully functional
with the high-speed mode (3.4 Mbps) but it is not specified at this time.
The basic I2C start and stop access cycles are shown in Figure 9.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SCL
S
P
Start
Condition
Stop
Condition
Figure 9. I2C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
•
•
The master initiates data transfer by generating a start condition. The start condition exist when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 9. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data are valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 10). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 11) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So,
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 12).
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To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 9). This releases the bus and stops the communication link with
the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
2
Figure 10. I C Bit Transfer
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
8
2
9
S
Clock Pulse for
Acknowledgement
Start
Condition
Figure 11. I2C Acknowledge
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
Stop
MSB
Acknowledge
Slave Address
Acknowledge
Data
2
Figure 12. I C Address and Data Cycles
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During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 13 and Figure 14.
Note that the THS7327 does not allow multiple write transfers to occur. See the Example— Writing to the
THS7327 section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 15 and Figure 16.
Note that the THS7327 does not allow multiple read transfers to occur. See the Example— Reading from the
THS7327 section for more information.
From Receiver
S
Slave Address
W
A
DATA
A
DATA
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
A
From Transmitter
Figure 13. I2C Write Cycle
Acknowledge
(From Receiver)
Start
Condition
A6
A5
A1
A0
R/W ACK
D7
Acknowledge
(Transmitter)
Acknowledge
(Receiver)
D6
D0
D1
ACK
D6
D7
D1
D0
ACK
SDA
2
First Data
Byte
I C Device Address and
Read/Write Bit
Other
Data Bytes
Stop
Condition
Last Data Byte
Figure 14. Multiple Byte Write Transfer
S
Slave Address
R
A
DATA
A
DATA
A
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
Transmitter
Receiver
Figure 15. I2C Read Cycle
Start
Condition
SDA
Acknowledge
(From
Receiver)
A6
A0
R/W
ACK
I 2 C Device Address and
Read/Write Bit
D7
Not
Acknowledge
(Transmitter)
Acknowledge
(From
Transmitter)
D0
First Data
Byte
ACK
D7
Other
Data Bytes
D6
D1
D0
Last Data Byte
ACK
Stop
Condition
Figure 16. Multiple Byte Read Transfer
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Slave Address
Both the SDA and the SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors
should comply with the I2C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are
high. The address byte is the first byte received following the START condition from the master device. The first
five bits (MSBs) of the address are factory preset to 01011. The next two bits of the THS7327 address are
controlled by the logic levels appearing on the I2C-A1 and I2C-A0 pins. The I2C-A1 and I2C-A0 address inputs
can be connected to VS+ for logic 1, GND for logic 0, or it can be actively driven by TTL/CMOS logic levels. The
device address is set by the state of these pins and is not latched. Thus, a dynamic address control system
could be used to incorporate several devices on the same system. Up to four THS7327 devices can be
connected to the same I2C Bus without requiring additional glue logic. Table 1 lists the possible addresses for the
THS7327.
Table 1. THS7327 Slave Addresses
SELECTABLE WITH
ADDRESS PINS
FIXED ADDRESS
READ/WRITE
BIT
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 (A1)
Bit 1 (A0)
Bit 0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
0
0
1
0
1
1
1
1
1
Channel Selection Register Description (Subaddress) and Power-Up Condition (PUC) Pin
The THS7327 operates using only a single byte transfer protocol similar to Figure 13 and Figure 15. The internal
subaddress registers and the functionality of each are found in Table 2. When writing to the device, it is required
to send one byte of data to the corresponding internal subaddress. If control of all three channels is desired, then
the master has to cycle through all the subaddresses (channels) one at a time, see the Example— Writing to the
THS7327 section for the proper procedure of writing to the THS7327.
During a read cycle, the THS7327 sends the data in its selected subaddress (or channel) in a single transfer to
the master device requesting the information. See the Example— Reading from the THS7327 section for the
proper procedure on reading from the THS7327.
On power up, the THS7327 registers are dictated by the power-up control (PUC) pin. If the PUC pin is tied to
GND, the THS7327 will power-up in a fully disabled state. If the PUC pin is tied to VDD, upon power-up the
THS7327 will be configured with HV sync on, buffer path disabled, monitor path Enabled, and input bias mode
set to AC-Bias on all input channels. It remains in this state until a valid write sequence is made to the THS7327.
A total of 12 bytes of data completely configures all channels of the THS7327. As such, configuring the THS7327
is accomplished quickly and easily.
Table 2. THS7327 Channel Selection Register Bit Assignments
20
REGISTER NAME
BIT ADDRESS
(b7b6b5....b0)
Channel 1
0000 0001
Channel 2
0000 0010
Channel 3
0000 0011
Channel H and V Sync and Disable Controls
0000 0100
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Channel Register Bit Descriptions
Each bit of the subaddress (channel selection) control register as described above allows the user to individually
control the functionality of the THS7327. The benefit of this process allows the user to control the functionality of
each channel independent of the other channels. The bit description is decoded in Table 3 and Table 4.
Table 3. THS7327 Channel Register (Ch. 1 thru 3) Bit Decoder Table – Use with Register Bit Codes
(0000 0001), (0000 0010), and (0000 0011)
BIT
FUNCTION
(MSB)
7
Sync-Tip Clamp Filter
6, 5, 4, 3
2, 1, 0
(LSB)
MUX Selection
+
Low Pass Filter
Input Mode
+
Operation
BIT
VALUE(S)
RESULT
0
500-kHz Filter on the STC circuit
1
5-MHz Filter on the STC circuit
0000
MUX Input A; LPF = 9-MHz
0001
MUX Input A; LPF = 16-MHz
0010
MUX Input A; LPF = 35-MHz
0011
MUX Input A; LPF = 75-MHz
0100
MUX Input A; LPF = Bypass
0101
MUX Input B; LPF = 9-MHz
0110
MUX Input B; LPF = 16-MHz
0111
MUX Input B; LPF = 35-MHz
1000
MUX Input B; LPF = 75-MHz
1001
MUX Input B; LPF = Bypass
1010
Reserved—Do Not Care
1011
Reserved—Do Not Care
1100
Reserved—Do Not Care
1101
Reserved—Do Not Care
1110
Reserved—Do Not Care
1111
Reserved—Do Not Care
000
Disables both Monitor and Buffer Paths of the Respective
Channel/Register
001
Channel Mute
010
Input Mode = DC
011
Input Mode = DC + Shift
100
Input Mode = AC-Bias
101
Input Mode = AC-STC with Low Bias
110
Input Mode = AC-STC with Mid Bias
111
Input Mode = AC-STC with High Bias
Bits 7 (MSB) – Controls the sync-tip clamp filter. Useful only when AC-STC input mode is selected.
Bit 6, 5, 4, 3 – Selects the Input MUX channel and the Buffer low pass filter
Bits 2, 1, and 0 (LSB) – Configures the channel mode and operation. See Table 4, bits 6 and 5 for more
information with respect to enable/disable state
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Table 4. THS7327 Channel Register (HV Sync Channel + ADC State) Bit Decoder Table – Use in
Conjunction With Register Bit Code (0000 0100)
BIT
FUNCTION
BIT
VALUE(S)
(MSB)
7
Reserved – Do Not Care
X
Reserved—Do Not Care
Monitor Pass-Thru Path Disable Mode
(Use in Conjunction with Table 3)
0
Disables All Monitor Channels regardless of Bits 2:0 of Registers 1-3
6
1
Enable Monitor Channels Functions Dictated by each Programmed
Register Code
Buffer Path Disable Mode (Use in
Conjunction with Table 3)
0
Disable All Buffer Channels regardless of Bits 2:0 of Registers 1-3
5
1
Enable Buffer Channel Functions Dictated by each Programmed
Register Code
4, 3
2, 1
0
(LSB)
Vertical Sync Channel MUX Selection
Horizontal Sync Channel MUX
Selection
HV Sync Paths Disable Mode
RESULT
00
MUX Input A
01
MUX Input B
10
Reserved—Do Not Care
11
Reserved—Do Not Care
00
MUX Input A
01
MUX Input B
10
Reserved—Do Not Care
11
Reserved—Do Not Care
0
Disable H and V Sync Channels
1
Enable H and V Sync Channels
Bit (MSB) 7 – Reserved – Do Not Care
Bit 6 – Master Monitor Path Disable. Disables All Monitor Channels regardless of what is programmed into each
Register Channel (1 to 3).
Bit 5 – Master Buffer Path Disable. Disables All Buffer Channels regardless of what is programmed into each
Register Channel (1 to 3).
Bits 4, 3 – Selects the Input MUX channel for the Vertical Sync
Bits 2, 1 – Selects the Input MUX channel for the Horizontal Sync
Bit 0 (LSB) – Enables or Disables the H and V Sync Channels.
22
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EXAMPLE – WRITING TO THE THS7327
The proper way to write to the THS7327 is illustrated as follows:
An I2C master initiates a write operation to the THS7327 by generating a start condition (S) followed by the
THS7327 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the THS7327, the master presents the subaddress (channel) it wants to write
consisting of one byte of data, MSB first. The THS7327 acknowledges the byte after completion of the
transfer. Finally the master presents the data it wants to write to the register (channel) and the THS7327
acknowledges the byte. The I2C master then terminates the write operation by generating a stop condition
(P). Note that the THS7327 does not support multi-byte transfers. To write to all three channels – or
registers – this procedure must be repeated for each register one series at a time (that is, repeat steps 1
through 8 for each channel).
Step 1
2
I C Start (Master)
0
S
Step 2
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
1
X
X
0
Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VS+ or GND.
Step 3
9
I2C Acknowledge (Slave)
A
Step 4
2
I C Write Channel Address (Master)
7
6
5
4
3
2
1
0
0
0
0
0
0
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
I2C Write Data (Master)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the values shown in Table 3 or Table 4.
Step 7
9
I2C Acknowledge (Slave)
A
Step 8
0
2
I C Stop (Master)
P
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EXAMPLE – READING FROM THE THS7327
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master
initiates a write operation to the THS7327 by generating a start condition (S) followed by the THS7327 I2C
address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
THS7327, the master presents the subaddress (channel) of the register it wants to read. After the cycle is
acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the THS7327 by
generating a start condition followed by the THS7327 I2C address (as shown below for a read operation), in MSB
first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the THS7327, the I2C master
receives one byte of data from the THS7327. After the data byte has been transferred from the THS7327 to the
master, the master generates a not acknowledge followed by a stop. Similar to the Write function, to read all
channels Steps 1 through 11 must be repeated for each and every channel desired.
THS7327 Read Phase 1:
Step 1
0
I2C Start (Master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
1
X
X
0
Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VS+ or GND.
Step 3
9
I2C Acknowledge (Slave)
A
Step 4
2
I C Read Channel Address (Master)
7
6
5
4
3
2
1
0
0
0
0
0
0
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
0
I2C Start (Master)
P
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THS7327 Read Phase 2:
Step 7
0
I2C Start (Master)
S
Step 8
2
I C General Address (Master)
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
1
Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VS+ or GND.
Step 9
9
I2C Acknowledge (Slave)
A
Step 10
I2C Read Data (Slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the Logic values contained in the Channel Register.
Step 11
9
I2C Not-Acknowledge (Master)
A
Step 12
0
I2C Stop (Master)
P
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2008) to Revision C
Page
•
Changed first DC Performance, Bias output voltage, Buffer output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 3.3-V Electrical Characteristics table .......................................................................................... 5
•
Changed first DC Performance, Bias output voltage, Monitor output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 3.3-V Electrical Characteristics table .......................................................................................... 5
•
Changed DC Performance, Sync tip clamp voltage, Buffer output parameter +25°C, 0°C to +70°C, and –40°C to
+85°C specifications in 3.3-V Electrical Characteristics table .............................................................................................. 5
•
Changed first DC Performance, Bias output voltage, Buffer output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 5-V Electrical Characteristics table ............................................................................................. 8
•
Changed first DC Performance, Bias output voltage, Monitor output parameter row +25°C, 0°C to +70°C, and –40°C
to +85°C specifications in 5-V Electrical Characteristics table ............................................................................................. 8
•
Changed DC Performance, Sync tip clamp output voltage, Buffer output parameter +25°C, 0°C to +70°C,
and –40°C to +85°C specifications in 5-V Electrical Characteristics table ........................................................................... 8
Changes from Revision A (February 2007) to Revision B
Page
•
Changed the VSS and VI rows of the Absolute Maximum Ratings table ............................................................................... 2
•
Changed the Recommended Operating Conditions table .................................................................................................... 3
•
Added Digital Characteristics section to 3.3V Electrical Characteristics table ..................................................................... 4
•
Added Digital Characteristics section to 5 V Electrical Characteristics table ....................................................................... 7
•
Changed footnote 1 of the Timing Requirements for I2C Interface table ............................................................................ 10
26
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS7327PHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
THS7327
THS7327PHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
THS7327
THS7327PHPRG4
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
THS7327
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS7327PHPR
Package Package Pins
Type Drawing
HTQFP
PHP
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
9.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS7327PHPR
HTQFP
PHP
48
1000
350.0
350.0
43.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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