Texas Instruments | Gated-Class H, Dual-Port, VDSL2 Line Driver (Rev. C) | Datasheet | Texas Instruments Gated-Class H, Dual-Port, VDSL2 Line Driver (Rev. C) Datasheet

Texas Instruments Gated-Class H, Dual-Port, VDSL2 Line Driver (Rev. C) Datasheet
THS6226
SBOS499C – JANUARY 2011 – REVISED APRIL 2011
www.ti.com
Gated-Class H, Dual-Port VDSL2 Line Driver
Check for Samples: THS6226
FEATURES
DESCRIPTION
•
The
THS6226
is
a
dual-port,
class
H,
current-feedback architecture, differential line driver
amplifier system ideal for xDSL systems. The device
is targeted for use in very-high-bit-rate digital
subscriber line 2 (VDSL2) line driver systems that
enable native DTM signals while supporting greater
than +20.5dBm line power (up to 8.5MHz) with good
linearity, supporting the G.993.2 VDSL2 8b profile. It
is also fast enough to support central-office
transmission of +14.5dBm line power up to 30MHz.
1
23
•
•
•
•
•
•
•
•
•
•
•
•
Digitally-Adjustable Quiescent Current:
7.6mA to 23.0mA
1.0mA Bias Current Step
Independent Voltage Boost and Main Line
Driver Disable
Low-Power Line Termination Mode
Full Capacitor Recharge: 3ms
Low Input Voltage Noise Density:
6.3 nV/√Hz Input-Referred Voltage Noise
Low MTPR Distortion:
70dB with +19.8dBm G.993.2—Profile 8b
–91dBc HD3 (1MHz, 60Ω Differential)
High Output Current: (383mA into 60Ω)
Wide Output Swing: 40VPP (+12V, 60Ω
Differential Load with a 1:1.4 Transformer)
Wide Bandwidth: 125MHz
Port-to-Port Separation of 90dB at 1MHz
PSRR: 70dB at 1MHz for Good Isolation
The unique architecture of the THS6226 allows
quiescent current to be minimal while still achieving
very high linearity. Differential distortion, under full
bias conditions, is –91dBc at 1MHz and reduces to
only –75dBc at 5MHz. Fixed multiple bias settings of
the amplifiers offer enhanced power savings for line
lengths where the full performance of the amplifier is
not required. To allow for even more flexibility and
power savings on all profiles, quiescent current is
digitally adjustable from 7.6mA to 23mA with a bias
current step of 1.0mA. For systems where additional
power savings while not transmitting are desired, the
THS6226 can be used in its line termination mode to
maintain impedance matching.
APPLICATIONS
•
•
Ideal for All VDSL2 Profiles
Backwards-Compatible with
ADSL/ADSL2+/ADSL2++ Systems
The wide output swing on +12V power supplies,
coupled with excellent current drive, allows for wide
dynamic headroom, keeping distortion minimal.
The THS6226 is available in a QFN-32 PowerPAD™
package.
1 mF
VLL_CD
CAPL_CD
+12V
FBC
IND
VIN+
OUTD
THS6226
1:1.4
+12V
100kW
10.2W
33nF
Line:
100W
OUTC
VIN-
DATA
CLK
INC
FBD
VHH_CD
CAPH_CD
1mF
Typical VDSL2 Line Driver Circuit Using One Port of the THS6226
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
THS6226
SBOS499C – JANUARY 2011 – REVISED APRIL 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT (2)
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE MARKING
VQFN-32
RHB
THS6226IRHB
THS6226IRHBT
THS6226IRHBR
(1)
(2)
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 250
Tape and Reel, 3000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
The PowerPAD is electrically isolated from all other pins.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
Supply voltage, GND to VS+, class AB only
Supply voltage, GND to VS+, class H only
Input voltage, VI
Output current, IO: static dc (2)
Continuous power dissipation
THS6226
UNIT
15
V
12.5
V
15
V
±100
mA
See Thermal Information table
–40 to +85
°C
Maximum junction temperature, any condition, TJ (3)
+150
°C
Maximum junction temperature, continuous operation, long-term reliability, TJ (4)
+130
°C
Normal storage temperature
–65 to +150
°C
Human body model (HBM)
2000
V
Charged device model (CDM)
500
V
Machine model (MM)
100
V
Storage temperature range, TSTG
ESD
ratings:
(1)
(2)
(3)
(4)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
The THS6226 incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could
permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD
thermally-enhanced package. Under high-frequency ac operation (> 10kHz), the short-term output current capability is much greater
than the continuous dc output current rating. This short-term output current rating is about 8.5x the dc capability, or approximately
±850mA.
The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
THERMAL INFORMATION
THS6226
THERMAL METRIC (1)
RHB
UNITS
32 PINS
θJA
Junction-to-ambient thermal resistance
35.1
θJCtop
Junction-to-case (top) thermal resistance
22.1
θJB
Junction-to-board thermal resistance
7.0
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
6.9
θJCbot
Junction-to-case (bottom) thermal resistance
1.3
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS: VS = +12V
Boldface limits are tested at +25°C.
At TA = +25°C, with RMATCH = 10.2Ω, transformer turn ratio 1:1.4, RL = 100Ω differential at transformer output, Full Bias Mode,
and active impedance circuit configuration, unless otherwise noted. Each port is tested independently.
THS6226IRHB
PARAMETER
CONDITIONS
MIN
UNIT
TEST
LEVEL (1)
125
MHz
C
TYP
MAX
AC PERFORMANCE
Small-signal bandwidth, –3dB
VO = 2VPP, differential at
OUTCD and OUTAB, gain = 19V/V
0.1dB bandwidth flatness
VO = 2VPP
37
MHz
C
Large-signal bandwidth
VO = 10VPP
125
MHz
C
VO = 15V step, differential
1500
V/μs
C
VO = 2VPP
2.8
ns
C
Slew rate (10% to 90% level)
Rise and fall time
Harmonic distortion
VO = 2VPP, RL = 60Ω differential
C
Second harmonic
Full bias, f = 1MHz
–91
dBc
C
Third harmonic
Full bias, f = 1MHz
–91
dBc
C
Full bias, f = 5MHz
–70
dBc
C
Low bias, f = 5MHz
–64
dBc
C
Full bias, f = 5MHz
–75
dBc
C
Low bias, f = 5MHz
–47
dBc
C
f = 1MHz, input-referred
6.3
nV/√Hz
C
Second harmonic
Third harmonic
Differential input voltage noise
DC PERFORMANCE
Differential gain
19
Differential gain error (2)
Input offset voltage
±1
–40°C to +85°C
Input offset voltage drift
Input offset voltage matching
±1
Channels 1 to 2 and 3 to 4 only
V/V
C
±2.5
%
A
±5
mV
A
±6
mV
B
15
μV/°C
B
±5
mV
A
kΩ || pF
C
V
A
INPUT CHARACTERISTICS
Noninverting input resistance
500 || 2
Input bias voltage
5.8
6
6.2
+16/–4
+17.5/–5.5
V
A
V
B
±383
mA
A
mA
B
+10.1/+1.9
V
A
V
B
±137
mA
A
OUTPUT CHARACTERISTICS
Class H output voltage swing
RL = 60Ω differential, class H operation (3) (4),
each output
–40°C to +85°C
Class H output current (sourcing, sinking)
Class AB output voltage swing
(3) (4)
±333
–40°C to +85°C
±323
RL = 60Ω differential, normal operation (3),
each output
+9.9/+2.1
–40°C to +85°C
Class AB output current (sourcing, sinking)
+15.7/–3.7
RL = 60Ω differential, class H operation
(3)
+9.8/+2.2
RL = 60Ω differential, normal operation
±130
–40°C to +85°C
±126
Short-circuit output current
Output impedance
Crosstalk
(1)
(2)
(3)
(4)
1
mA
B
A
C
f = 1MHz, differential
0.2
Ω
C
f = 1MHz, VOUT = 2VPP, port 1 to port 2
–90
dB
C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Negative feedback loop only.
Measured at amplifier output (pin 17, 20, 21, and 24).
Capacitor fully charged, no droop.
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ELECTRICAL CHARACTERISTICS: VS = +12V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, with RMATCH = 10.2Ω, transformer turn ratio 1:1.4, RL = 100Ω differential at transformer output, Full Bias Mode,
and active impedance circuit configuration, unless otherwise noted. Each port is tested independently.
THS6226IRHB
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
+12
+15
V
A
+15
V
B
+12.5
V
B
POWER SUPPLY
Maximum operating voltage
Class AB
+10
–40°C to +85°C
+10
Class H
+10
–40°C to +85°C
+10
Per port, full bias, class H enable
(power supply connected together)
22.5
–40°C to +85°C
21.8
Per port, full bias, class H disable
(power supply connected together)
22.0
–40°C to +85°C
21.3
Bias current step
IS+ quiescent current
+12
+12.5
23.5
23.0
7.2
–40°C to +85°C
6.9
7.6
Per port, line termination mode
(B9 = B8 =B7 = B6 = 0)
(power supply connected together)
4.4
Both ports, main amplifiers and
class H disable
(B9 = B8 = B7 = B6 = 0)
1.7
–40°C to +85°C
Power-supply rejection (PSRR)
24.5
mA
A
25.2
mA
B
24.0
mA
A
24.7
mA
B
mA
C
8
mA
A
8.3
mA
B
mA
C
2.2
mA
A
2.3
mA
B
dB
A
1.0
Per port, low bias, class H disable
(power supply connected together)
B
Differential, from +12V, GND
60
70
–40°C to +85°C
58
dB
B
1.9
V
C
0.8
V
C
25
μA
A
30
μA
B
125
μA
A
130
μA
B
μs
C
1
μs
C
50 || 1
kΩ || pF
C
LOGIC
Logic pin logic threshold
Logic 1, with respect to GND (5)
Logic 0, with respect to GND
(5)
Logic X = 0.5V (logic 0)
Logic pin quiescent current
10
–40°C to +85°C
Logic X = 3.3V (logic 1)
66
–40°C to +85°C
Turn-on time delay (tON)
Time for IS to reach 50% of final value
Turn-off time delay (tOFF)
Time for IS to reach 50% of final value
Logic pin input impedance
(5)
4
1
The GND pin usable range is from VS– to (VS+ – 5V).
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PIN CONFIGURATIONS
VH_ENCD
VLL_CD
CAPL_CD
GND
VSCD
VSCD
CAPH_CD
VHH_CD
QFN-32(1)(2)
RHB PACKAGE
(TOP VIEW)
32
31
30
29
28
27
26
25
INC
3
22
FB_C
DATA
4
21
OUTC
CLK
5
20
OUTB
INB
6
19
FB_B
INA
7
18
FB_A
GND
8
17
OUTA
9
10
11
12
13
14
15
16
VHH_AB
FB_D
CAPH_AB
23
VSAB
2
VSAB
IND
GND
OUTD
CAPL_AB
24
VLL_AB
1
VH_ENAB
GND
(1)
The PowerPAD is electrically isolated from all other pins and can be connected to any potential voltage range from
VS– to VS+. Typically, the PowerPAD is connected to the GND plane because this plane tends to physically be the
largest and is able to dissipate the most amount of heat.
(2)
The THS6226 defaults to the disabled mode at power-up.
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PIN DESCRIPTIONS
NAME
PIN
DESCRIPTION
GND
1
Analog ground
IND
2
Input D of amplifier CD
INC
3
Input C of amplifier CD
DATA
4
Serial interface data pin
CLK
5
Serial interface CLK pin
INB
6
Input B of amplifier AB
INA
7
Input A of amplifier AB
GND
8
Analog ground
VH_ENAB
9
Class H mode control pin for amplifier AB
VLL_AB
10
Amplifier AB low pump supply
CAPL_AB
11
Amplifier AB negative voltage pump capacitor pin
GND
12
Analog ground
VSAB
13
Amplifier AB supply voltage
VSAB
14
Amplifier AB supply voltage
CAPH_AB
15
Amplifier AB positive voltage pump capacitor pin
VHH_AB
16
Amplifier AB high pump supply
OUTA
17
Output A of amplifier AB
FB_A
18
Feedback for active output impedance of amplifier AB
FB_B
19
Feedback for active output impedance of amplifier AB
OUTB
20
Output B of amplifier AB
OUTC
21
Output C of amplifier CD
FB_C
22
Feedback for active output impedance of amplifier CD
FB_D
23
Feedback for active output impedance of amplifier CD
OUTD
24
Output D of amplifier CD
VHH_CD
25
Amplifier CD high pump supply
CAPH_CD
26
Amplifier CD positive voltage pump capacitor pin
VSCD
27
Amplifier CD supply voltage
VSCD
28
Amplifier CD supply voltage
GND
29
Analog ground
CAPL_CD
30
Amplifier CD negative voltage pump capacitor pin
VLL_CD
31
Amplifier CD low pump supply
VH_ENCD
32
Class H mode control pin for amplifier CD
TIMING CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
CLK
tCL
DATA
tHOLD
tSETUP
Figure 1. Serial Interface Timing
THS6226
PARAMETER
tSETUP
tHOLD
tCL
6
DESCRIPTION
MIN
Setup time
3
ns
Hold time
0.5
ns
Clock period
200
ns
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MAX
UNITS
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TYPICAL CHARACTERISTICS: VS = +12V
At TA = +25°C and Full Bias Mode, unless otherwise noted
LARGE-SIGNAL FREQUENCY RESPONSE
3
0
0
−3
−3
Normalized Gain (dB)
−6
−9
−12
Bias 15
Bias 10
Bias 5
Bias 0
−15
VO = 2VPP
RL = 60Ω
−18
−21
1
−6
−9
−12
VO = 10VPP
RL = 60Ω
−18
10
Frequency ( MHz)
100
−21
300
Bias 15
Bias 10
Bias 5
Bias 0
−15
1
10
Frequency ( MHz)
Figure 2.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
POWER CONSUMPTION
650
100W Load Line
50W Load Line
25W Load Line
550
Power Consumption (mW)
VO (V)
1W Internal
Power
Dissipation
1W Internal
Power
Dissipation
4
2
500
450
400
-250
Output Power Into 100W Load
Load Power Included
350
300
250
200
Bias 15
Class AB Mode
0
-350
Prof. 30, Bias 10
Prof. 17, Bias 4
Prof. 8, Bias 2
ADSL, Bias 0
600
8
6
150
-50
50
IO (mA)
-150
150
250
100
-12.5 -9.5 -6.5 -3.5 -0.5 2.5 5.5 8.5 11.5 14.5 17.5 20.5
Output Power (dBm)
350
Figure 4.
Figure 5.
CLASS AB OVERDRIVE RECOVERY
Output Voltage
Right Scale
4
3
0.11
2
Input Voltage
Left Scale
0.05
1
0
0
0.05
-1
0.11
-2
0.16
-3
RL = 60W
AC-Coupled Input and Output
0.21
0.27
0
20
40
60
80
100
-4
120
140
160
180
-5
200
0.64
0.53
Input Voltage (V)
0.16
Output Voltage (V)
Input Voltage (V)
OVERDRIVE RECOVERY
0.75
5
0.27
0.21
300
Figure 3.
12
10
100
14
RL = 60W
AC-Coupled
Input and Output
Positive Excursion Only
12
10
8
0.43
Input Voltage
Left Scale
0.32
Output Voltage
Right Scale
6
4
0.21
0.11
2
0
0
-0.11
-0.21
0.6
Output Voltage (V)
Normalized Gain (dB)
SMALL-SIGNAL FREQUENCY RESPONSE
3
-2
0.7
Time (ns)
Figure 6.
0.8
0.9
1
1.1 1.2
Time (ns)
1.3
1.4
1.5
1.6
-4
Figure 7.
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TYPICAL CHARACTERISTICS: VS = +12V (continued)
At TA = +25°C and Full Bias Mode, unless otherwise noted
INPUT NOISE DENSITY
HARMONIC DISTORTION vs FREQUENCY
−50
Harmonic Distortion (dBc)
10
−60
−65
−70
−75
−80
−85
−90
2nd Harmonic
3rd Harmonic
−95
1
100
1k
10k
Frequency (Hz)
100k
HARMONIC DISTORTION vs LOAD
TWO-TONE, THIRD-ORDER
INTERMODULATION SPURIOUS
−75
−80
2nd Harmonic
3rd Harmonic
70
80
90
100
110
120
130
140
60
70
75
80
85
90
95
100
105
150
2VPP Envelope
RL = 100W
1:1.4 Transformer
65
0
10
5
Load (Ω)
15
20
Frequency (Hz)
Figure 10.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs BIAS CURRENT
f = 5MHz
RL = 100W
1:1.4 Transformer
40
45
50
55
60
65
70
2nd Harmonic
3rd Harmonic
75
0
2
4
6
f = 5MHz
VO = 2VPP
RL = 100Ω
1:1.4 Transformer
−45
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
30
−40
35
10
12
14
8
Output Voltage (VPP)
16
18
−50
−55
−60
−65
−70
−75
20
−80
2nd Harmonic
3rd Harmonic
0
Figure 12.
8
25
Figure 11.
30
80
30
Figure 9.
−70
60
10
Frequency (MHz)
VO = 2VPP
1:1.4 Transformer
f = 5MHz
50
1
Figure 8.
−65
−85
−100
0.5
1M
−60
Harmonic Distortion (dBc)
VO = 2VPP
RL = 100Ω
1:1.4 Transformer
−55
3rd-Order Intermodulation Spurious (dBc)
Input Voltage Noise Density (nV/ÖHz)
100
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15
Bias Current Mode
Figure 13.
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TYPICAL CHARACTERISTICS: VS = +12V (continued)
At TA = +25°C and Full Bias Mode, unless otherwise noted
LARGE-SIGNAL ENABLE/DISABLE RESPONSE
5
DISABLE FEEDTHROUGH vs FREQUENCY
0
Enable
4
Differential at Amplifier Output
VO = 200mVPP
10
20
1
Disable
Disable
Gain (dB)
Disable Voltage (V)
3
2
0
-1
30
40
-2
50
-3
60
-5
0
-5
5
10
15
Time (ns)
20
25
70
30
10M
100M
Frequency (Hz)
1G
6G
Figure 14.
Figure 15.
PSRR AND CMRR vs FREQUENCY
QUIESCENT CURRENT AND OUTPUT
vs TEMPERATURE
24
0
400
Quiescent Current (Bias 15)
Output Current
23.7
−10
Quiescent Current (mA)
Power−Supply Rejection Ratio
Common−Mode Rejection Ratio (dB)
1M
−20
−30
−40
−50
−60
−70
+PSRR
CMRR
−80
100k
1M
10M
398
23.4
396
23.1
394
22.8
392
22.5
390
22.2
388
21.9
386
21.6
384
21.3
382
21
−50
−25
0
100M
25
50
Temperature (°C)
75
Output Current (mA)
-4
380
125
100
Frequency (Hz)
Figure 16.
Figure 17.
INPUT OFFSET VOLTAGE HISTOGRAM
350
1.8
300
1.5
250
1.2
200
Counts
Input Offset Voltage (mV)
INPUT OFFSET VOLTAGE vs TEMPERATURE
2
1
0.8
150
100
0.5
50
0.2
4.62
5.46
2.94
3.78
2.1
0.42
1.26
-1.26
125
-0.42
100
-2.1
75
-2.94
25
50
Temperature (°C)
-3.78
0
-5.46
−25
-4.62
0
0
−50
Population (mV)
Figure 18.
Figure 19.
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APPLICATION INFORMATION
The THS6226 class H line driver provides exceptional ac performance in conjunction with wide output voltage
swing. The class H operation allows voltage swings to exceed the power supply for short intervals limited only by
the charge in the capacitor. In class AB mode, the THS6226 is capable of driving a 60Ω load from +1.9V to
+10.1V. In class H mode, under the same conditions, the output voltage range becomes an impressive –5.5V to
+17.5V, or 46VPP differentially with the capacitor fully charged.
Figure 20 shows a fully-differential, noninverting amplifier configuration with active impedance. In this
configuration, the 10.2Ω matching resistance appears through the transformer as 100Ω, minimizing reflection on
the line, while also minimizing transmission losses. The THS6226 gain is fixed and equal to 19V/V from input of
the amplifier to the output of the amplifier (INCD to OUTCD), not including the transformer-turn ratio.
To simplify the implementation as well as provide design flexibility, the THS6226 contains an integrated
mid-supply buffer that provides the correct biasing to the amplifier core without requiring any external
components. Also present is a two-pin serial interface that provides exceptional design flexibility and allows
minimal power consumption for each xDSL profile.
1 mF
VLL_CD
CAPL_CD
+12V
FBC
IND
VIN+
OUTD
THS6226
1:1.4
+12V
100kW
10.2W
33nF
Line:
100W
OUTC
VIN-
DATA
CLK
INC
FBD
VHH_CD
CAPH_CD
1mF
Figure 20. Multi-Tone Power Ratio (MTPR) Test Circuit
10
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PROGRAMMING THE THS6226
Programming of the THS6226 is realized through a serial interface (pins 4 and 5) and proceeds in the following
sequence.
Two start bits are required B0 = 0 followed by B1 = 1.
B2 through B9 are used to program the THS6226.
Refer to Table 1 for the bit descriptions.
B10 (refer to Table 2) is the parity bit that controls if the word is or is not loaded.
B11 is the stop bit and should be set to B11 = 1. Figure 21 shows the sequence to be adopted.
Table 1. SDATA
PARAMETER
DESCRIPTION
B0, B1
Start bit
B2, B3
Channel select
B4, B5
Power-down features
B6-B9
Quiescent current setting
B10
Parity bit
B11
Stop bit
Table 2. Parity Bit
B10
ODD PARITY BIT
0
If odd, number of high bits in B2 to B9
1
If even, number of high bits in B2 to B9
MSB
DATA
LSB
B0
B1
Start
Bit
Start
Bit
B2
B3
Ch AB Ch CD
Select Select
B4
B5
B6
B7
B8
B9
B10
B11
PD1
PD0
D3
D2
D1
D0
Parity
Stop
Bit
Figure 21. DATA Description
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QUIESCENT CURRENT
The quiescent current of the THS6226 is dissipated in two main modules of the THS6226: the class AB and the
charge pump. B4 and B5 select the mode of operation, class AB operating with or without the charge pump
enabled, powering down the entire port, or operating in a line termination mode. Table 4 lists the details on each
bit functionality and the approximate quiescent current.
The class AB quiescent current is set by bits B6 to B9, using B4 and B5 for the power-down function, and B2 and
B3 for channel select. The approximate quiescent current for the amplifier core is shown in Table 3.
Table 3. Class AB Quiescent Current
QUIESCENT CURRENT SETTING
APPROXIMATE
IQ (mA/Port)
B6 (D3)
B7 (D2)
B8 (D1)
B9 (D0)
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
13
0
1
1
0
14
0
1
1
1
15
1
0
0
0
16
1
0
0
1
17
1
0
1
0
1
0
1
1
19
1
1
0
0
20
1
1
0
1
21
1
1
1
0
22
1
1
1
1
23
ADSL2+ mode
7.6
8.7
Profile 8b mode
9.8
10.9
Profile 17a mode
12
Profile 30a mode
18
The various power modes are shown in Table 4. For all modes, when B6 through B9 are not defined, set B9 =
B8 = B7 = B6 = 0 to achieve the lowest power dissipation possible.
Table 4. Power Modes
12
APPROXIMATE IQ
(mA/Port)
B4 (PD1)
B5 (PD0)
POWER-DOWN MODE
0
0
Power-down (B9, B8, B7, B6 = 0)
0.85
0
1
Line termination mode (B9, B8, B7, B6 = 0)
4.4
1
0
Class AB driver IQ set by B6 to B9, class H disabled
—
1
1
Class AB driver IQ set by B6 to B9, class H enabled
—
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Channel selection is shown in Table 5. Each channel can be programmed independently, or together if both B2
and B3 are set to '1'.
Table 5. Channel Selection
B2 (Channel AB)
B3 (Channel CD)
CHANNEL SELECT
0
0
Bits B4 to B9 are ignored
0
1
Channel B programmed with B4 to B9
1
0
Channel A programmed with B4 to B9
1
1
Channels A and B programmed with B4 to B9
At startup, the internal register is set as shown in Table 6.
Table 6. Internal Register
B2
(Channel AB)
B3
(Channel CD)
B4 (PD1)
B5 (PD0)
B6 (D3)
B7 (D2)
B8 (D1)
B9 (D0)
0
0
0
0
0
0
0
0
In this condition, the total quiescent power dissipation is 10.2mW/port on a +12V supply.
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THS6226
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2011) to Revision C
Page
•
Changed LOGIC, Logic pin input impedance typical specification and unit in Electrical Characteristics table .................... 4
•
Changed Timing Characteristics section .............................................................................................................................. 6
14
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
THS6226IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
THS6226
IRHB
THS6226IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
THS6226
IRHB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
THS6226IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
THS6226IRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS6226IRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
THS6226IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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