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Texas Instruments 4:1 High Speed Multiplexer (Rev. C) Datasheet
OPA4872
SBOS346C – JUNE 2007 – REVISED MARCH 2011
www.ti.com
4:1 High-Speed Multiplexer
Check for Samples: OPA4872
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
The OPA4872 offers a very wideband 4:1 multiplexer
in an SO-14 package. Using only 10.6mA, the
OPA4872 provides a user-settable output amplifier
gain with greater than 500MHz large-signal
bandwidth (2VPP). The switching glitch is improved
over earlier solutions using a new (patented) input
stage switching approach. This technique uses
current steering as the input switch while maintaining
an overall closed-loop design. The OPA4872 exhibits
an off isolation of 88dB in either Disable or Shutdown
mode. With greater than 500MHz small-signal
bandwidth at a gain of 2, the OPA4872 gives a typical
0.1dB gain flatness to greater than 120MHz.
1
2
•
500MHz SMALL-SIGNAL BANDWIDTH
500MHz, 2VPP BANDWIDTH
0.1dB GAIN FLATNESS to 120MHz
10ns CHANNEL SWITCHING TIME
LOW SWITCHING GLITCH: 40mVPP
2300V/μs SLEW RATE
0.035%/0.005° DIFFERENTIAL GAIN, PHASE
QUIESCENT CURRENT = 10.6mA
1.1mA QUIESCENT CURRENT IN SHUTDOWN
MODE
88dB OFF ISOLATION IN DISABLE OR
SHUTDOWN (10MHz)
System power may be optimized using the chip
enable feature for the OPA4872. Taking the chip
enable (EN) line high powers down the OPA4872 to
less than 3.4mA total supply current. Further power
reduction to 1.1mA quiescent current can be
achieved by bringing the shutdown (SD) line high.
Muxing multiple OPA4872s outputs together, then
using the chip enable to select which channels are
active, increases the number of possible inputs.
APPLICATIONS
•
•
•
•
VIDEO ROUTER
LCD AND PLASMA DISPLAY
HIGH SPEED PGA
DROP-IN UPGRADE TO AD8174
+5V
50W
OPA695
G = 1V/V
-5V
+5V
523W
50W
IN0
+5V
OPA4872
SD
EN
50W
OPA695
G = 2V/V
-5V
IN1
511W
50W
511W
IN2
+5V
523W
50W
To 50W Load
523W
OPA695
G = 4V/V
Logic
-5V
453W
IN3
A0 A1
-5V
149W
+5V
50W
OPA695
G = 8V/V
-5V
402W
57.6W
2-Bit, High-Speed PGA, Greater Than 300MHz Channel Bandwidth
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
OPA4872
SBOS346C – JUNE 2007 – REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA4872
SO-14
D
(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +85°C
OPA4872
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA4872ID
Rails, 50
OPA4872IDR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Power supply
OPA4872
UNIT
±6.5
V
Internal power dissipation
See Thermal Characteristics
±VS
V
–65 to +125
°C
Junction temperature (TJ)
+150
°C
Junction temperature: continuous operation, long-term reliability
+140
°C
Human body model (HBM)
1300
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
Input voltage range
Storage temperature range
ESD rating
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
PIN CONFIGURATION
D PACKAGE
SO-14
(TOP VIEW)
OPA4872
2
1
14
V+
GND
2
13
OUT
IN1
3
12
FB
GND
4
11
SD
IN2
5
10
EN
V-
6
9
A1
IN3
7
8
A0
Logic
IN0
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SBOS346C – JUNE 2007 – REVISED MARCH 2011
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ELECTRICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, RF = 523Ω, and RL = 150Ω, unless otherwise noted.
OPA4872
MIN/MAX OVER
TEMPERATURE
TYP
CONDITIONS
+25°C
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
UNITS
MIN/
MAX
Small-signal bandwidth
VO = 500mVPP, RL = 150Ω
500
375
360
355
MHz
min
B
Bandwidth for 0.1dB flatness
VO = 500mVPP, RL = 150Ω
120
MHz
typ
C
PARAMETER
TEST
LEVEL (1)
AC PERFORMANCE
Large-signal bandwidth
VO = 2VPP, RL = 150Ω
500
400
370
350
MHz
min
B
Slew rate
4V step
2300
2150
2025
2000
V/μs
min
B
Rise time and fall time
4V step
1.25
1.4
1.45
1.5
ns
max
B
to 0.05%
2V step
15
ns
typ
C
to 0.1%
2V step
14
17
17.5
18
ns
max
B
10
12
12.5
13
ns
max
B
Settling time
Channel switching time
Harmonic distortion
G = +2V/V, f = 10MHz, VO = 2VPP
2nd-harmonic
RL = 150Ω
–60
–56
–52
–50
dBc
max
B
3rd-harmonic
RL = 150Ω
–78
–75
–72
–70
dBc
max
B
Input voltage noise
f > 100kHz
4.5
5.4
5.8
6.2
nV/√Hz
max
B
Noninverting input current noise
f > 100kHz
4.0
4.8
5.0
5.2
pA/√Hz
max
B
Inverting input current noise
f > 100kHz
19
22
23
24
pA/√Hz
max
B
G = +2V/V, PAL, VO = 1.4VP
0.035
%
typ
C
Differential gain
G = +2V/V, PAL, VO = 1.4VP
0.005
°
typ
C
Three channels driven at 5MHz, 1VPP
–80
dB
typ
C
Three channels driven at 30MHz, 1VPP
–66
dB
typ
C
VO = 0V, RL = 100Ω
103
92
90
86
kΩ
min
A
VCM = 0V
±1
±5
±5.7
±6.3
mV
max
A
±15
±20
μV/°C
max
B
Differential phase
All hostile crosstalk, input-referred
DC PERFORMANCE
Open-loop transimpedance (ZOL)
Input offset voltage
Average Input offset voltage drift
VCM = 0V
Input offset voltage matching
VCM = 0V
±1
±5
±5.5
±6
mV
max
A
VCM = 0V
±4
±14
±14.7
±15.3
μA
max
A
±15
±20
nA/°C
max
B
±21.4
±22.9
μA
max
A
±75
±75
nA/°C
max
B
Noninverting input bias current
Average noninverting input bias current
VCM = 0V
Inverting bias current
VCM = 0V
Average inverting input bias current
±4
±18
VCM = 0V
INPUT
Each noninverting input
±2.7
±2.55
±2.5
±2.45
V
min
A
VCM = 0V, input-referred, noninverting input
56
50
49
48
dB
min
A
Channel enabled
2.5
MΩ
typ
C
open loop
70
Ω
typ
C
Common-mode input range (CMIR)
Common-mode rejection ratio (CMRR)
Input resistance
Noninverting
Inverting
Input capacitance
Noninverting
Channel selected
0.9
pF
typ
C
Channel deselected
0.9
pF
typ
C
Chip disabled
0.9
pF
typ
C
OUTPUT
Output voltage swing
Output current
Short-circuit output current
Closed-Loop output impedance
(1)
(2)
(3)
RL ≥ 1kΩ
±4
±3.9
±3.85
±3.8
V
min
A
RL = 150Ω
±3.7
±3.55
±3.5
±3.45
V
min
A
VO = 0V
±75
±48
±47
±45
mA
min
A
Output shorted to ground
±100
mA
typ
C
G = +2V/V, f ≤ 100kHz
0.03
Ω
typ
C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C tested specifications.
Junction temperature = ambient at low temperature limit; junction temperature = ambient +9°C at high temperature limit for over
temperature specifications.
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ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 523Ω, and RL = 150Ω, unless otherwise noted.
OPA4872
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
CONDITIONS
+25°C
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
UNITS
MIN/
MAX
V EN = 0V
3.4
3.6
3.8
3.9
mA
max
A
VIN = ±0.25VDC
25
ns
typ
C
TEST
LEVEL (1)
ENABLE (EN)
Power-down supply current
Disable time
Enable time
VIN = ±0.25VDC
6
ns
typ
C
Off isolation
G = +2V/V, f = 10MHz
88
dB
typ
C
Output resistance in disable
14
MΩ
typ
C
Output capacitance in disable
2.5
pF
typ
C
DIGITAL INPUTS
Maximum logic 0
A0, A1, EN, SD
0.8
0.8
0.8
V
max
B
Minimum logic 1
A0, A1, EN, SD
2.0
2.0
2.0
V
min
B
40
45
50
μA
max
A
Logic input current
Output switching glitch
A0 , A1, EN, SD, input = 0V each line
32
Channel selection, at matched load
±20
mV
typ
C
Channel disable, at matched load
±40
mV
typ
C
Shutdown, at matched load
±40
mV
typ
C
mA
max
A
ns
typ
C
SHUTDOWN
Shutdown supply current
VSD = 0V
1.1
VIN = ±0.25VDC
75
Enable time
VIN = ±0.25VDC
15
ns
typ
C
Off isolation
G = +2V/V, f = 10MHz
88
dB
typ
C
Output resistance in shutdown
14
MΩ
typ
C
Output capacitance in shutdown
2.5
pF
typ
C
Shutdown time
1.3
1.4
1.5
POWER SUPPLY
±5
Specified operating voltage
V
typ
C
Minimum operating voltage
±3.5
±3.5
±3.5
V
min
B
Maximum operating voltage
±6.0
±6.0
±6.0
V
max
A
Maximum quiescent current
VS = ±5V
10.6
11
11.5
11.7
mA
max
A
Minimum quiescent current
VS = ±5V
10.6
10
9.5
9.3
mA
min
A
(+PSRR)
Input-referred
–56
–50
–49
–48
dB
min
A
(–PSRR)
Input-referred
–57
–51
–50
–49
dB
min
A
–40 to
+85
°C
typ
C
80
°C/W
typ
C
Power-supply rejection ratio
THERMAL CHARACTERISTICS
Specified operating range, D package
Thermal resistance, θ JA
D
4
Junction-to-ambient
SO-14
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TYPICAL CHARACTERISTICS
At TA = +25°C, G = +2V/V, RF = 523Ω, and RL = 150Ω, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
7
SMALL-SIGNAL FREQUENCY RESPONSE
6
0.3
0.1
Normalized
4
0
Flatness
3
-0.1
2
-0.2
VO = 500mVPP
RL = 150W
G = +2V/V
-0.3
3
Normalized Gain (dB)
5
Normalized Gain Flatness (dB)
-3
G = +2V/V
-6
-9
G = +4V/V
0
-12
-0.4
1M
0
10M
100M
1M
1G
10M
100M
Figure 1.
LARGE-SIGNAL FREQUENCY RESPONSE
0.4
Small-Signal Output Voltage (V)
6
VO = 2VPP
4
Gain (dB)
NONINVERTING PULSE RESPONSE
0.5
VO = 1VPP
3
VO = 0.5VPP
2
2G
Figure 2.
7
5
1G
Frequency (Hz)
Frequency (Hz)
1
2.5
RL = 150W
G = +2V/V
2.0
Large-Signal 4VPP
Right Scale
0.3
1.5
0.2
1.0
Small-Signal 0.4VPP
Left Scale
0.1
0.5
0
0
-0.1
-0.5
-0.2
-1.0
-0.3
-1.5
-2
-0.4
-2.0
-3
-0.5
0
VO = 4VPP
-1
0
200M
400M
600M
800M
Large-Signal Output Voltage (V)
Gain (dB)
0.2
1
G = +1V/V
VO = 500mVPP
Bandwidth
6
-2.5
Time (10ns/div)
1G
Frequency (Hz)
Figure 3.
Figure 4.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
8
90
7
Gain to Capacitive Load (dB)
100
80
RS (W)
70
60
50
40
30
20
5
4
3
+
CL = 22pF
RS
VO
-
75W
-1
-3
1000
75W
0
-2
100
75W
1
0
10
VI
2
10
1
CL = 10pF
6
523W
CL
1kW
(1)
CL = 47pF
523W
NOTE: (1) Optional.
75W
1
CL = 100pF
10
Capacitive Load (pF)
Frequency (MHz)
Figure 5.
Figure 6.
100
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, G = +2V/V, RF = 523Ω, and RL = 150Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
-55
VO = 2VPP
f = 5MHz
-60
2nd-Harmonic
-65
-70
-75
-80
3rd-Harmonic
2nd-Harmonic
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-55
-85
-65
-70
-75
3rd-Harmonic
-80
-85
VO = 2VPP
RL = 150W
f = 5MHz
-90
dBc = dB Below Carrier
-90
dBc = dB Below Carrier
-95
100
2.5
1k
3.0
3.5
4.0
Figure 7.
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-55
-50
-55
-60
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
-85
-90
10
-60
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
-85
-90
-100
100
dBc = dB Below Carrier
0.5
1.5
Frequency (MHz)
6
5
3.5
4.5
5.5
6.5
Figure 9.
Figure 10.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
DISABLE AND SHUTDOWN FEEDTHROUGH vs
FREQUENCY
-20
1W Internal
Power Limit
2
1
50W Load
25W Load
-1
-2
1W Internal
-3
Power Limit
-50
Shutdown Feedthrough
-60
-70
-80
Disable Feedthrough
-90
-100
-4
-5
-200
Input-referred
-40
100W Load
3
0
7.5
-30
Feedthrough (dB)
Output Voltage (V)
2.5
Output Voltage Swing (VPP)
4
-100
0
100
200
300
-110
1M
Output Current (mA)
10M
100M
1G
Frequency (Hz)
Figure 11.
6
6.0
RL = 150W
f = 5MHz
-95
dBc = dB Below Carrier
-95
1
5.5
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
VO = 2VPP
RL = 150W
-45
5.0
Figure 8.
HARMONIC DISTORTION vs FREQUENCY
-40
4.5
Supply Voltage (±VS)
Load Resistance (W)
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, G = +2V/V, RF = 523Ω, and RL = 150Ω, unless otherwise noted.
VIN_Ch0 = 200MHz, 0.7VPP
VIN_Ch1 = 0VDC
A0
A0
Time (10ns/div)
Output (mV)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VIN_Ch0 = 200MHz, 0.10VPP
EN
Enable Voltage (V)
Output (V)
DISABLE/ENABLE SWITCHING GLITCH
Output
75
50
25
0
-25
-50
-75
At Matched Load
EN
Time (10ns/div)
Time (10ns/div)
Figure 15.
Figure 16.
Output (mV)
SHUTDOWN GLITCH
Output
SD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Channel Select (V)
Output (V)
SHUTDOWN/START-UP TIME
VIN_Ch0 = 200MHz, 0.7VPP
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 14.
DISABLE/ENABLE TIME
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Time (10ns/div)
Figure 13.
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Channel Select (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
At Matched Load
Enable Voltage (V)
Output Voltage
75
50
25
0
-25
-50
-75
Shutdown Voltage (V)
Output (mV)
CHANNEL-TO-CHANNEL SWITCHING GLITCH
Channel Select (V)
Output (V)
CHANNEL-TO-CHANNEL SWITCHING
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
75
50
25
0
-25
-50
-75
Time (20ns/div)
At Matched Load
SD
Time (20ns/div)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, G = +2V/V, RF = 523Ω, and RL = 150Ω, unless otherwise noted.
OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE vs
FREQUENCY
ALL HOSTILE CROSSTALK vs FREQUENCY
1M
Input-referred
100k
Transimpedance (W)
-20
Crosstalk (dB)
0
< ZOL
-30
-40
-50
-60
-70
-80
-45
½ZOL½
10k
-90
1k
-135
100
-180
Phase (°)
0
-10
-90
-100
10
1M
10M
100M
10k
1G
100k
1M
10M
100M
1G
-225
Frequency (Hz)
Frequency (Hz)
Figure 19.
Figure 20.
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
INPUT IMPEDANCE vs FREQUENCY
1M
100M
100k
10M
Disabled (or Shutdown)
Input Impedance (W)
Output Impedance (W)
Disabled
10k
1k
100
10
1M
Enabled
100k
10k
1k
1
Enabled
100
1M
10M
100M
10k
1G
Figure 22.
100M
1G
OUTPUT AND SUPPLY CURRENT vs TEMPERATURE
Input-referred
Output Current (mA)
Power-Supply Rejection Ratio (dB)
10M
Figure 21.
PSRR vs FREQUENCY
-PSRR
40
30
+PSRR
20
10
78.00
15.00
76.75
13.75
75.50
12.50
Supply Current (IQ)
74.25
11.25
73.00
10.00
71.75
+IOUT
70.50
6.25
-IOUT
68.00
1k
10k
100k
1M
10M
100M
1G
8.75
7.50
69.25
0
5.00
-50
Frequency (Hz)
Figure 23.
8
1M
Frequency (Hz)
60
50
100k
Frequency (Hz)
Supply Current (mA)
0.1
100k
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, G = +2V/V, RF = 523Ω, and RL = 150Ω, unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE
1.5
8
1.0
7
VOS
0.5
6
0
5
Ibn
-0.5
4
-1.0
3
-1.5
2
Ibi
-2.0
1
-2.5
0
-3.0
-1
-50
-25
0
25
50
75
100
125
300
Voltage Noise Density (nV/ÖHz)
Current Noise Density (pA/ÖHz)
9
Input Bias Current (mA)
Output Offset Voltage (mV)
TYPICAL DC DRIFT OVER TEMPERATURE
2.0
100
Inverting Input Current Noise (19pA/ÖHz)
10
Input Voltage Noise (4.5nV/ÖHz)
Noninverting Input Current Noise (4pA/ÖHz)
1
10
Ambient Temperature (°C)
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 25.
Figure 26.
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APPLICATION INFORMATION
input of a current feedback amplifier. Depending on
the logic applied to channel control pins A0 and A1,
one switch is on at all times. Figure 27 represents the
OPA4872 in this configuration. The truth table for
channel selection is shown in Table 2.
WIDEBAND MULTIPLEXER OPERATION
The OPA4872 gives a new level of performance in
wideband multiplexers. Figure 27 shows the
dc-coupled, gain of +2V/V, dual power-supply circuit
used as the basis of the ±5V Electrical
Characteristics and Typical Characteristic curves. For
test purposes, the input impedance is set to 75Ω with
a resistor to ground and the output impedance is set
to 75Ω with a series output resistor. Voltage swings
reported in the specifications are taken directly at the
input and output pins while load powers (in dBm) are
defined at a matched 75Ω load. For the circuit of
Figure 27, the total effective load will be 150Ω ||
1046Ω = 131Ω. Logic pins A0 and A1 control which
of the four inputs is selected while EN and SD allow
for power reduction. One optional component is
included in Figure 27. In addition to the usual
power-supply decoupling capacitors to ground, a
0.01μF capacitor is included between the two
power-supply pins. In practical printed circuit board
(PCB) layouts, this optional added capacitor typically
improves the 2nd-harmonic distortion performance by
3dB to 6dB for bipolar supply operation.
Table 2. TRUTH TABLE
A0
A1
EN
SD
VOUT
0
0
0
0
IN0
1
0
0
0
IN1
0
1
0
0
IN2
1
1
0
0
IN3
X
X
1
0
High-Z, IQ = 3.4mA
X
X
X
1
High-Z, IQ = 1.1mA
The OPA4872 is in disable mode, with a quiescent
current of 3.4mA typical, when the EN pin is set to
0V. After being placed in disable mode, the OPA4872
is fully enabled in 6ns. For further power savings, the
SD pin can be used. Setting the SD pin to 5V places
the device in shutdown mode with a standing
quiescent current of 1.1mA. Note that in this
shutdown mode, the OPA4872 requires 15ns to be
fully powered again. The truth table for disable and
shutdown modes can be found in Table 2.
Even though the internal architecture of the OPA4872
includes current steering, it is advantageous to look
at it as four switches looking into the noninverting
+5V
0.1mF
+
6.8mF
OPA4872
SD
IN0
EN
VIN0
75W
IN1
VIN1
75W
75W
VOUT
IN2
523W
VIN2
To 75W Load
75W
523W
IN3
VIN3
A0
75W
A1
Optional
0.01mF
0.1mF
+
6.8mF
-5V
Figure 27. DC-Coupled, G = +2V/V Bipolar Specification and Test Circuit (Channel 0 Selected)
10
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2-BIT HIGH-SPEED PGA
The OPA4872 can be used as a 2-bit, high-speed
programmable gain amplifier (PGA) when used in
conjunction with another amplifier. Figure 28 shows
one OPA695 used in series with each OPA4876 input
and configured with gains of +1V/V, +2V/V, +4V/V,
and +8V/V, respectively.
When channel 0 is selected, the overall gain to the
matched load of the OPA4872 is 0dB. When channel
1 is selected, this circuit delivers 6dB of gain to the
matched load. When channel 2 is selected, this circuit
delivers 12dB of gain to the matched load. When
channel 3 is selected, this circuit delivers 18dB of
gain to the matched load.
+5V
50W
OPA695
G = 1V/V
-5V
+5V
523W
50W
IN0
+5V
OPA4872
SD
EN
50W
OPA695
G = 2V/V
-5V
IN1
511W
50W
511W
IN2
+5V
523W
50W
To 50W Load
523W
OPA695
G = 4V/V
Logic
-5V
453W
IN3
A0 A1
-5V
149W
+5V
50W
OPA695
G = 8V/V
-5V
402W
57.6W
Figure 28. 2-Bit, High-Speed PGA, Greater Than 300MHz Channel Bandwidth
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2-BIT, HIGH-SPEED ATTENUATOR
8-TO-1 VIDEO MULTIPLEXER
In contrast to the PGA, a two-bit high-speed
attenuator can be implemented by using an R-2R
ladder together with the OPA4872. Figure 29 shows
such an implementation.
Two OPA4872s can be used together to form an
8-input video multiplexer. The multiplexer is shown in
Figure 31.
Channel 0 sees the full input signal amplitude, where
as channel 1 sees 1/2 VIN, channel 2 see 1/4 VIN and
channel 3 sees 1/8 VIN.
OPA4872
EN
SD
VIN
OPA4872
2R
IN0
SD
EN
RO = 69W
R
2R
523W
IN1
VOUT
IN2
523W
R
R
523W
50W
R
2R
To 75W Load
To 50W Load
Logic
523W
IN3
Logic
OPA4872
EN
A0 A1
SD
Figure 29. 2-Bit, High-Speed Attenuator,
500MHz Channel Bandwidth
4-INPUT RGB ROUTER
RO = 69W
Three OPA4872s can be used together to form a
four-input RGB router. The router for the red
component is shown in Figure 30. Identical stages
would be used for the green and blue channels.
523W
523W
Logic
+5V
OPA4872
EN
Figure 31. 8-to-1 Video Multiplexer
SD
R1
When connecting OPA4872 outputs together,
maintain a gain of +1V/V at the load. The OPA4872
configuration shown is a gain of +6dB; thus, the
matching
resistance
must
be
selected
to
achieve –6dB.
R2
75W
Red Out
523W
R3
To 75W Load
523W
The set of equations to solve are shown in
Equation 1 and Equation 2. Here, the impedance of
interest is 75Ω.
RO = ZO || (RO + RF + RG)
R4
Logic
1+
A0 A1
RF
RG
=2
(1)
-5V
Figure 30. 4-Input RGB Router
(Red Channel Shown)
12
RF + RG = 1046W
R F = RG
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Solving for RO, with n devices connected together,
results in Equation 3:
RO =
75 ´ (n - 1) + 804
2
1+
´
241200
[75 ´ (n - 1) + 804]
2
-1
(3)
Results for n varying from 2 to 6 are given in Table 3.
Table 3. Series Resistance versus
Number of Parallel Outputs
NUMBER OF OPA4872s
RO (Ω)
2
69
3
63.94
4
59.49
5
55.59
6
52.15
The two major limitations of this circuit are the device
requirements for each OPA4872 and the acceptable
return loss resulting from the mismatch between the
load and the matching resistor.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE
BANDWIDTH
The output stage of the OPA4872 is a
current-feedback op amp, meaning it can hold an
almost constant bandwidth over signal gain settings
with the proper adjustment of the external resistor
values. This performance is shown in the Typical
Characteristic curves; the small-signal bandwidth
decreases only slightly with increasing gain. These
curves also show that the feedback resistor has been
changed for each gain setting. The resistor values on
the feedback path can be treated as frequency
response compensation elements while the ratio sets
the signal gain of the feedback resistor divided by the
gain resistor. Figure 32 shows the small-signal
frequency response analysis circuit for a current
feedback amplifier.
VI
a
VO
DESIGN-IN TOOLS
RI
Z(S) iERR
DEMONSTRATION FIXTURE
A printed circuit board (PCB) is available to assist in
the initial evaluation of circuit performance using the
OPA4872. The fixture is offered free of charge as an
unpopulated PCB, delivered with a user's guide. The
summary information for this fixture is shown in
Table 4.
Table 4. OPA4872 Demonstration Fixture
PRODUCT
PACKAGE
ORDERING NUMBER
LITERATURE
NUMBER
OPA4872
SO-14
DEM-OPA-SO-1E
SBOU045
iERR
RF
RG
Figure 32. Recommended Feedback Resistor
versus Noise Gain
The key elements of this current-feedback op amp
model are:
The demonstration fixture can be requested at the
Texas Instruments web site at (www.ti.com) through
the OPA4872 product folder.
α → Buffer gain from the noninverting input to the
inverting input
MACROMODELS AND APPLICATIONS SUPPORT
iERR → Feedback error current signal
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
practice is particularly true for video and RF amplifier
circuits, where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the OPA4872 is available through
the Texas Instruments web site at www.ti.com. This
model does a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. It does not do as well in
predicting the harmonic distortion or dG/dP
characteristics.
Z(s)
→
Frequency-dependent
transimpedance gain from iERR to VO
RI → Buffer output impedance
open-loop
The buffer gain is typically very close to 1.00 and is
normally neglected from signal gain considerations. It
will, however, set the CMRR for a single op amp
differential amplifier configuration. For a buffer gain
α < 1.0, the CMRR = –20 × log (1 – α) dB.
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VO
VI
a 1+
=
RF
RG
R
RF + RI 1+ F
RG
1+
Z(S)
=
aNG
RF + RI NG
1+
Z(S)
where:
NG = 1+
RF
RG
(4)
This formula is written in a loop-gain analysis format,
where the errors arising from a noninfinite open-loop
gain are shown in the denominator. If Z(S) were
infinite over all frequencies, the denominator of
Equation 4 would reduce to 1 and the ideal desired
signal gain shown in the numerator would be
achieved. The fraction in the denominator of
Equation 4 determines the frequency response.
Equation 5 shows this as the loop-gain equation:
Z(S)
= Loop Gain
RF + RI NG
(5)
If 20 × log(RF + NG × RI) were drawn on top of the
open-loop transimpedance plot, the difference
between the two calculations would be the loop gain
at a given frequency. Eventually, Z(S) rolls off to equal
the denominator of Equation 5, at which point the
loop gain reduces to 1 (and the curves intersect).
This point of equality is where the amplifier
closed-loop frequency response given by Equation 4
starts to roll off, and is exactly analogous to the
frequency at which the noise gain equals the
open-loop voltage gain for a voltage-feedback op
amp. The difference here is that the total impedance
in the denominator of Equation 5 may be controlled
somewhat separately from the desired signal gain (or
NG).
14
The OPA4872 is internally compensated to give a
maximally flat frequency response for RF = 523Ω at
NG = 2 on ±5V supplies. Evaluating the denominator
of Equation 5 (which is the feedback transimpedance)
gives an optimal target of 663Ω. As the signal gain
changes,
the
contribution
of
the
NG × RI term in the feedback transimpedance will
change, but the total can be held constant by
adjusting RF. Equation 6 gives an approximate
equation for optimum RF over signal gain:
RF = 663W - NG x RI
(6)
As the desired signal gain increases, this equation
will eventually predict a negative RF. A somewhat
subjective limit to this adjustment can also be set by
holding RG to a minimum value of 20Ω. Lower values
load both the buffer stage at the input and the output
stage, if RF gets too low, actually decreasing the
bandwidth. Figure 33 shows the recommended RF
versus NG for ±5V operation. The values for RF
versus gain shown here are approximately equal to
the values used to generate the Typical
Characteristics. They differ in that the optimized
values used in the Typical Characteristics are also
correcting for board parasitics not considered in the
simplified analysis leading to Equation 5. The values
shown in Figure 33 give a good starting point for
design where bandwidth optimization is desired.
600
550
Feedback Resistor (W)
RI, the buffer output impedance, is a critical portion of
the bandwidth control equation. RI for the OPA4872 is
typically about 30Ω. A current-feedback op amp
senses an error current in the inverting node (as
opposed to a differential input error voltage for a
voltage-feedback op amp) and passes this on to the
output through an internal frequency dependent
transimpedance gain. The Typical Characteristics
show this open-loop transimpedance response. This
open-loop response is analogous to the open-loop
voltage gain curve for a voltage-feedback op amp.
Developing the transfer function for the circuit of
Figure 32 gives Equation 4:
500
450
400
350
300
250
200
150
100
0
5
10
15
20
Noise Gain
Figure 33. Feedback Resistor vs Noise Gain
The total impedance going into the inverting input
may be used to adjust the closed-loop signal
bandwidth. Inserting a series resistor between the
inverting input and the summing junction increases
the feedback impedance (denominator of Equation 4),
decreasing the bandwidth.
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DRIVING CAPACITIVE LOADS
VOSO_envelope = VOS ´ G ± Ibi x RF ± (RS ´ Ib) ´ G
One of the most demanding, yet very common load
conditions, is capacitive loading. Often, the capacitive
load is the input of an analog-to-digital converter
(ADC)—including additional external capacitance that
may be recommended to improve ADC linearity. A
high-speed device such as the OPA4872 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
directly on the output pin. When the device open-loop
output resistance is considered, this capacitive load
introduces an additional pole in the signal path that
can decrease the phase margin. Several external
solutions to this problem have been suggested. When
the primary considerations are frequency response
flatness, pulse response fidelity, and/or distortion, the
simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a
series isolation resistor between the amplifier output
and the capacitive load. This isolation resistor does
not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency.
The additional zero acts to cancel the phase lag from
the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Characteristics show the recommended
RS versus capacitive load and the resulting frequency
response at the load; see Figure 5. Parasitic
capacitive loads greater than 2pF can begin to
degrade the performance of the OPA4872. Long PCB
traces, unmatched cables, and connections to
multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and
add the recommended series resistor as close as
possible to the OPA4872 output pin (see the Board
Layout Guidelines section).
DC ACCURACY
The OPA4872 offers excellent dc signal accuracy.
Parameters that influence the output dc offset voltage
are:
• Output offset voltage
• Input bias current
• Gain error
• Power-supply rejection ratio
• Temperature
Leaving both temperature and gain error parameters
aside, the output offset voltage envelope can be
described as shown in Equation 7:
± ½5 - (VS+)½ ´ 10
-
±½-5 - (VS-)½ ´ 10
-
PSRR+
20
PSRR20
(7)
Where:
RS: Input resistance seen by R0, R1, G0, G1, B0,
or B1.
Ib: Noninverting input bias current
Ibi: Inverting input bias current
G: Gain
VS+: Positive supply voltage
VS–: Negative supply voltage
PSRR+: Positive supply PSRR
PSRR–: Negative supply PSRR
VOS : Input Offset Voltage
Evaluating the front-page schematic, using a
worst-case, +25°C offset voltage, bias current and
PSRR specifications and operating at ±6V, gives a
worst-case output equal to Equation 8:
±10mV + 75W ´ ±14mA ´ 2
50
+523W ´ ±18mA ±½5 - 6½ ´ 10 20
±½-5 - (-6)½ ´ 10
-
51
20
= ±29.2mV
(8)
DISTORTION PERFORMANCE
The OPA4872 provides good distortion performance
into a 150Ω load on ±5V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads. Generally, until the
fundamental signal reaches very high frequency or
power levels, the 2nd harmonic dominates the
distortion with a negligible 3rd harmonic component.
Focusing then on the 2nd harmonic, increasing the
load impedance directly improves distortion. Also,
providing an additional supply decoupling capacitor
(0.01μF) between the supply pins (for bipolar
operation) improves the 2nd-order distortion slightly
(3dB to 6dB).
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the 2nd harmonic increasing at
a little less than the expected 2X rate while the 3rd
harmonic increases at a little less than the expected
3X rate. Where the test power doubles, the 2nd
harmonic increases only by less than the expected
6dB, whereas the 3rd harmonic increases by less
than the expected 12dB.
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NOISE PERFORMANCE
The OPA4872 offers an excellent balance between
voltage and current noise terms to achieve low output
noise. The inverting current noise (19pA/√Hz) is
significantly lower than earlier solutions, while the
input voltage noise (4.5nV/√Hz) is lower than most
unity-gain stable, wideband, voltage-feedback op
amps. As long as the ac source impedance looking
out of the noninverting node is less than 100Ω, this
current noise will not contribute significantly to the
total output noise. The op amp input voltage noise
and the two input current noise terms combine to give
low output noise under a wide variety of operating
conditions. Figure 34 shows the OPA4872 noise
analysis model with all the noise terms included. In
this model, all noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
ENI
EO
OPA4872
RS
IBN
ERS
RF
Ö4kTRS
4kT
RG
RG
IBI
Ö4kTRF
4kT = 1.6 x 10
at 290K
- 20
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 9 shows the
general form for the output noise voltage using the
terms shown in Figure 35.
EO =
Ö(
2
2
)
2
2
ENI + (IBNRS) + 4kTRS NG + (IBIRF) + 4kTRFNG
(9)
Dividing this expression by the noise gain (NG = (1 +
RF/RG)) gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 10.
EO =
Ö
2
2
ENI + (IBNRS) + 4kTRS +
2
( INGR ) + 4kTR
NG
BI
F
F
(10)
Evaluating these two equations for the OPA4872
circuit and component values (see Figure 27) gives a
total output spot noise voltage of 14.2nV/√Hz and a
total equivalent input spot noise voltage of 7.1nV/√Hz.
This total input-referred spot noise voltage is higher
than the 4.5nV/√Hz specification for the OPA4872
voltage noise alone. This voltage reflects the noise
added to the output by the inverting current noise
times the feedback resistor. If the feedback resistor is
reduced in high-gain configurations, the total
input-referred voltage noise given by Equation 10
approaches only the 4.5nV/√Hz of the op amp itself.
For example, going to a gain of +10 using RF = 178Ω
gives a total input-referred noise of 4.7nV/√Hz.
J
Figure 34. Op Amp Noise Analysis Model
16
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THERMAL ANALYSIS
Heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired
junction temperature sets the maximum allowed
internal power dissipation as discussed in this
document. In no case should the maximum junction
temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by TA +
PD × θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
en
RS
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load; for a grounded resistive load, PDL is
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
supplies). Under this condition PDL = VS 2/(4 × RL),
where RL includes feedback network loading.
Note that it is the power in the output stage and not in
the load that determines internal power dissipation.
OPA4872
-20
4kT = 1.6 x 10
at 290K
J
ini
VRS = Ö4kTRS
eo
RF
VRF = Ö4kTRF
iin
RG
iRG
Ö
4kT
RG
Figure 35. OPA4872 Noise Analysis Model
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As a worst-case example, compute the maximum TJ
using an OPA4872ID in the circuit of Figure 27
operating at the maximum specified ambient
temperature of +85°C with its output driving a
grounded 100Ω load to +2.5V:
Again, keep their leads and PCB trace length as short
as possible. Never use wirewound type resistors in a
high-frequency
application.
Other
network
components, such as noninverting input termination
resistors, should also be placed close to the package.
PD = 10V ´ 11.7mA + (5 /[4 ´ (150W || 1046W)]) = 165mW
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them.
2
Maximum TJ = +85°C + (165mW ´ 80°C/W) = 98°C
This worst-case condition does not exceed the
maximum junction temperature. Normally, this
extreme case is not encountered.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier such as the OPA4872
requires careful attention to board layout parasitics
and external component types. Recommendations to
optimize performance include:
a) Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output pin can cause instability;
on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To
reduce unwanted capacitance, a window around the
signal I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
b) Minimize the distance (< 0.25") from the
power-supply pins to high frequency 0.1μF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections (on pins 9, 11, 13, and 15)
should always be decoupled with these capacitors.
An optional supply decoupling capacitor across the
two power supplies (for bipolar operation) improves
2nd harmonic distortion performance. Larger (2.2μF
to 6.8μF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These capacitors may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA4872. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high-frequency performance.
18
Estimate the total capacitive load and set RS from the
plot of Figure 5. Low parasitic capacitive loads
(greater than 5pF) may not need an RS because the
OPA4872 is nominally compensated to operate with a
2pF parasitic load. If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook
for microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary on the board,
and in fact, a higher impedance environment
improves distortion as shown in the Distortion versus
Load plot; see Figure 7. With a characteristic board
trace impedance defined based on board material
and trace dimensions, a matching series resistor into
the trace from the output of the OPA4872 is used as
well as a terminating shunt resistor at the input of the
destination device. Remember also that the
terminating impedance will be the parallel
combination of the shunt resistor and the input
impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. The high output voltage and current
capability of the OPA4872 allows multiple destination
devices to be handled as separate transmission lines,
each with its own series and shunt terminations. If the
6dB attenuation of a doubly-terminated transmission
line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the
series resistor value as shown in Figure 5. This
configuration does not preserve signal integrity as
well as a doubly-terminated line. If the input
impedance of the destination device is low, there will
be some signal attenuation because of the voltage
divider formed by the series output into the
terminating impedance.
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Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): OPA4872
OPA4872
SBOS346C – JUNE 2007 – REVISED MARCH 2011
www.ti.com
e) Socketing a high-speed part like the OPA4872
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
that can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA4872 onto the board.
INPUT AND ESD PROTECTION
The OPA4872 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins have limited ESD protection using internal
diodes to the power supplies as shown in Figure 36.
+VCC
External
Pin
Internal
Circuitry
-VCC
Figure 36. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA4872), current-limiting
series resistors should be added into the two inputs.
Keep these resistor values as low as possible
because high values degrade both noise performance
and frequency response.
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Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): OPA4872
19
OPA4872
SBOS346C – JUNE 2007 – REVISED MARCH 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2008) to Revision C
•
Page
Changed the HBM ESD rating specification in Absolute Maximum Ratings table ............................................................... 2
Changes from Revision A (September 2007) to Revision B
Page
•
Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C .................................................................................................................................................................................. 2
•
Changed 0V to 5V in third paragraph of Wideband Multiplexer Operation section ............................................................ 10
20
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Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): OPA4872
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA4872ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4872
OPA4872IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4872
OPA4872IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4872
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA4872 :
• Enhanced Product: OPA4872-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA4872IDR
Package Package Pins
Type Drawing
SOIC
D
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
9.0
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA4872IDR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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