Texas Instruments | 4-Channel SDTV Video Amplifier with 6th-Order Filters and 6-dB Gain (Rev. B) | Datasheet | Texas Instruments 4-Channel SDTV Video Amplifier with 6th-Order Filters and 6-dB Gain (Rev. B) Datasheet

Texas Instruments 4-Channel SDTV Video Amplifier with 6th-Order Filters and 6-dB Gain (Rev. B) Datasheet
TH
S73
THS7374
74
www.ti.com
SLOS590B – JULY 2008 – REVISED JANUARY 2011
4-Channel SDTV Video Amplifier with 6th-Order Filters and 6-dB Gain
Check for Samples: THS7374
FEATURES
DESCRIPTION
•
Fabricated using the revolutionary complementary
Silicon-Germanium (SiGe) BiCom3X process, the
THS7374 is a low-power, single-supply 3 V to 5 V
four-channel integrated video buffer. It incorporates a
sixth-order Butterworth filter (able to be bypassed)
which is useful as a digital-to-analog converter (DAC)
reconstruction filter or an analog-to-digital converter
(ADC) anti-aliasing filter. The 9.5-MHz filter is a
perfect choice for SDTV video that includes
composite (CVBS), s-video, Y'U'V', G'B'R' (R'G'B'),
and Y'P'BP'R 480i/576i.
1
2
•
•
•
•
•
•
•
•
•
•
4-SDTV Video Amplifiers for CVBS, S-Video,
Y'P'BP'R 480i/576i, Y'U'V', or G'B'R' (R'G'B')
Integrated Low-Pass Filters:
– 6th-Order 9.5-MHz (–3 dB) Butterworth
– –1 dB Passband Bandwidth at 8.2-MHz
– 54-dB Attenuation at 27-MHz
150-MHz (–3 dB) Filter Bypass Mode
Versatile Input Biasing
– DC-Coupled with 300-mV Output Shift
– AC-Coupled with Sync-Tip Clamp
– AC-Coupled with Biasing Allowed
Built-in 6-dB Gain (2 V/V)
+3-V to +5-V Single-Supply Operation
Rail-to-Rail Output:
– Output Swings Within 100 mV from the
Rails to Allow AC or DC Output Coupling
– Supports Driving 2 Lines per Channel
Low 9.6-mA at 3.3-V Total Quiescent Current
0.1-mA Disabled Supply Current Function
Low Differential Gain/Phase of 0.15%/0.3°
Lead-Free and Green TSSOP-14 Package
As part of the THS7374 flexibility, the input can be
configured for either ac or dc-coupled inputs. The
300-mV output level shift allows for a full sync
dynamic range at the output with 0-V input. The
ac-coupled modes include a transparent sync-tip
clamp option for CVBS, Y', and G'B'R' signals with
sync. AC-coupled biasing for C'/P'B/P'R channels can
easily be achieved by adding an external resistor.
The THS7374 is the perfect choice for all video buffer
applications. Its rail-to-rail output stage with 6-dB gain
allows for both ac and dc line driving. The ability to
drive two lines per channel, or 75-Ω loads, allows for
maximum flexibility as a video line driver. The 9.6-mA
total quiescent current at 3.3 V and 0.1-mA disabled
current makes it an excellent choice for portable or
other power-sensitive applications.
APPLICATIONS
•
•
•
The THS7374 is available in a TSSOP-14 package
that is lead-free and green (RoHS) compliant.
Low-Cost SCART Systems
Set Top Box Output Video Buffering
Surveillance Systems
+3.3 V
THS7374
CVBS
R
DAC/Encoder
SDTV
CVBS
S-Video
Y'P’BP'R
R'G'B’
CVBS/Sync
75 W
1
CH1 IN
CH1 OUT 14
2
CH2 IN
CH2 OUT 13
3
CH3 IN
CH3 OUT 12
4
CH4 IN
CH4 OUT 11
5
GND
6
DISABLE
7
NC
75 W
Y'/G' Out
75 W
Y'/G'
R
P’B/B'
75 W
VS+ 10
BYPASS
9
NC
8
P'B/B' Out
75 W
R
75 W
P'R/R' Out
P’R/R'
R
75 W
To GPIO Controller
or GND
75 W
+3 V to +5 V
Figure 1. 3.3-V Single-Supply, DC-Input/DC-Output Coupled Video Line Driver
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
THS7374
SLOS590B – JULY 2008 – REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1) (2)
PRODUCT
PACKAGE-LEAD
THS7374IPW
(2)
Rails, 90
TSSOP-14
THS7374IPWR
(1)
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 2000
ECO STATUS (2)
Pb-Free, Green
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content
can be accessed at www.ti.com/leadfree.
GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion
dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that
does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering
processes.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range unless otherwise noted.
Supply voltage, VS+ to GND
Input voltage, VI
Output current, IO
Continuous power dissipation
THS7374
UNIT
5.5
V
–0.4 to VS
V
100
mA
See Dissipation Ratings Table
Maximum junction temperature, any condition (2) TJ
+150
°C
Maximum junction temperature, continuous operation, long-term
reliability (3), TJ
+125
°C
–65 to +150
°C
Human body model (HBM)
2000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
Storage temperature range, TSTG
ESD ratings
(1)
(2)
(3)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
DISSIPATION RATINGS
PACKAGE
qJC
(°C/W)
qJA
(°C/W)
AT TA ≤ +25°C
POWER RATING
AT TA = +85°C
POWER RATING
TSSOP-14 (PW)
35
115
870 mW
348 mW
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VS+
Ambient temperature, TA
2
NOM
MAX
UNIT
3
5
V
–40
+85
°C
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS VS+ = +3.3 V
RL = 150 Ω to GND and dc-coupled input and output, Filter Mode, unless otherwise noted.
THS7374
TYP
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
Small-signal bandwidth (–3 dB)
VO = 0.2 VPP (1)
9.5
7.6/11.4
7.4/11.6
7.3/11.7
Min/
Max
MHz
Large-signal bandwidth (–3 dB)
VO = 2 VPP (1)
9.5
7.6/11.4
7.4/11.6
7.3/11.7
Min/
Max
MHz
8.2
Typ
MHz
PARAMETER
MIN/
–40°C to TYP/
+85°C
MAX
UNITS
AC PERFORMANCE
–1 dB passband bandwidth
Bypass mode bandwidth (–3 dB)
VO = 0.2 VPP
150
Typ
MHz
Slew rate
Bypass mode
130
Typ
V/ms
f = 6.75 MHz (2)
0.25
–0.9/1.1
–1/1.4
–1.1/1.6
Min/
Max
dB
f = 27 MHz (2)
54
42
40
39
Min
dB
Group delay
f = 100 kHz
70
Typ
ns
Group delay variation
with respect to 100 kHz
f = 5.1 MHz
8.5
Typ
ns
0.3
Typ
ns
NTSC/PAL
0.15/0.25
TYP
%
Attenuation
with respect to 500 kHz
Channel-to-channel delay
Differential gain (NTSC/PAL)
Differential phase (NTSC/PAL)
Total harmonic distortion
Signal-to-noise ratio
NTSC/PAL
0.3/0.35
Typ
°
f = 1 MHz; VO = 2 VPP
–65
Typ
dB
100 kHz to 6 MHz: non-weighted/
unified weighting
70/78
Typ
dB
f = 1 MHz
–55
Typ
dB
6
Min/
Max
dB
Typ
Ω
Min/
Max
mV
Channel-to-channel crosstalk
AC gain—all channels
Output impedance
f = 5 MHz; filter mode
0.7
VIN = 0 V
300
DC input, limited by output
–0.1/1.46
VIN = –0.1 V
200
5.7/6.3
5.65/6.35
5.65/6.35
DC PERFORMANCE
Biased output voltage/level shift
Input voltage range
210/390
200/400
190/410
140
130
120
Typ
V
Min
mA
800
Typ
kΩ
2
Typ
pF
RL = 150 Ω to +1.65 V
3.15
Typ
V
Sync tip clamp charge current
Input resistance
Input capacitance
OUTPUT CHARACTERISTICS
High output voltage swing
RL = 150 Ω to GND
3.1
Min
V
RL = 75 Ω to +1.65 V
3.1
Typ
V
RL = 75 Ω to GND
3
Typ
V
RL = 150 Ω to +1.65 V (VIN = –0.2 V)
0.05
RL = 150 Ω to GND (VIN = –0.2 V)
0.03
RL = 75 Ω to +1.65 V (VIN = –0.2 V)
2.85
2.75
2.75
Typ
V
Max
V
0.1
Typ
V
RL = 75 Ω to GND (VIN = –0.2 V)
0.05
Typ
V
Output current (sourcing)
RL = 10 Ω to +1.65 V
80
Typ
mA
Output current (sinking)
RL = 10 Ω to +1.65 V
70
Typ
mA
Low output voltage swing
(1)
(2)
0.12
0.16
0.17
The min/max values listed for this specification are ensured by design and characterization only.
3.3-V supply filter specifications are ensured by 100% testing at 5-V supply along with design and characterization only.
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ELECTRICAL CHARACTERISTICS VS+ = +3.3 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, Filter Mode, unless otherwise noted.
THS7374
PARAMETER
TYP
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
VS+ to GND
3.3
5.5
5.5
5.5
MIN/
–40°C to TYP/
+85°C
MAX
UNITS
POWER SUPPLY
Maximum operating voltage
Minimum operating voltage
VS+ to GND
(3)
Max
V
3.3
2.85
2.85
2.85
Min
V
Maximum total quiescent current
VIN = 0 V; VS+ = 3.3 V
9.6
12
13
14
Max
mA
Minimum total quiescent current
VIN = 0 V; VS+ = 3.3 V
9.6
8
7
6.5
Min
mA
Disabled total quiescent current
Disable pin = 2 V
0.1
10
10
10
Max
mA
Typ
dB
V
Power-supply rejection (+PSRR)
52
LOGIC CHARACTERISTICS (4)
VIH
Disabled or bypass engaged
1.8
2
2
2
Min
VIL
Enabled or bypass disengaged
0.7
0.65
0.6
0.6
Max
V
IIH
0.2
Typ
mA
IIL
0.2
Typ
mA
Disable time
100
Typ
ns
Enable time
100
Typ
ns
5
Typ
ns
20 || 3
Typ
kΩ || pF
Bypass/filter switch time
Disabled output impedance
(3)
(4)
4
Disable pin = 2 V
The min/max values listed for this specification are ensured by design and characterization only.
The logic input pins should not be left floating. They must be connected to logic low (or GND) or logic high (or VS+).
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS VS+ = +5 V
RL = 150 Ω to GND and dc-coupled input and output, Giler Mode, unless otherwise noted.
THS7374
TYP
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
Small-signal bandwidth (–3 dB)
VO = 0.2 VPP (1)
9.5
7.6/11.4
7.4/11.6
7.3/11.7
Min/
Max
MHz
Large-signal bandwidth (–3 dB)
VO = 2 VPP (1)
9.5
7.6/11.4
7.4/11.6
7.3/11.7
Min/
Max
MHz
8.2
Typ
MHz
PARAMETER
MIN/
–40°C to TYP/
+85°C
MAX
UNITS
AC PERFORMANCE
–1 dB passband bandwidth
Bypass mode bandwidth (–3 dB)
VO = 0.2 VPP
150
Typ
MHz
Slew rate
Bypass mode
130
Typ
V/ms
f = 6.75 MHz
0.25
–0.9/1.1
–1/1.4
–1.1/1.6
Min/
Max
dB
42
40
39
Attenuation
with respect to 500 kHz
f = 27 MHz
54
Min
dB
Group delay
f = 100 kHz
70
Typ
ns
Group delay variation
with respect to 100 kHz
f = 5.1 MHz
8.5
Typ
ns
0.3
Typ
ns
NTSC/PAL
0.1/0.25
TYP
%
Channel-to-channel delay
Differential gain (NTSC/PAL)
Differential phase (NTSC/PAL)
Total harmonic distortion
Signal-to-noise ratio
NTSC/PAL
0.3/0.4
Typ
°
f = 1 MHz; VO = 2 VPP
–69
Typ
dB
100 kHz to 6 MHz: non-weighted/
unified weighting
70/78
Typ
dB
f = 1 MHz
–66
Typ
dB
6
Min/
Max
dB
Typ
Ω
Min/
Max
mV
Channel-to-channel crosstalk
AC gain—all channels
Output impedance
f = 5 MHz; filter mode
0.7
VIN = 0 V
310
Limited by output
–0.1/2.3
VIN = –0.1 V
200
5.7/6.3
5.65/6.35
5.65/6.35
DC PERFORMANCE
Biased output voltage/level shift
Input voltage range
210/390
200/400
190/410
140
130
120
Typ
V
Min
mA
800
Typ
kΩ
2
Typ
pF
RL = 150 Ω to +2.5V
4.85
Typ
V
RL = 150 Ω to GND
4.75
Min
V
RL = 75 Ω to +2.5V
4.7
Typ
V
RL = 75 Ω to GND
4.5
Typ
V
RL = 150 Ω to +2.5V (VIN = –0.2 V)
0.05
RL = 150 Ω to GND (VIN = –0.2 V)
0.03
RL = 75 Ω to +2.5 V (VIN = –0.2 V)
Sync tip clamp charge current
Input resistance
Input capacitance
OUTPUT CHARACTERISTICS
High output voltage swing
4.4
4.3
4.3
Typ
V
Max
V
0.1
Typ
V
RL = 75 Ω to GND (VIN = –0.2 V)
0.05
Typ
V
Output current (sourcing)
RL = 10 Ω to +2.5 V
90
Typ
mA
Output current (sinking)
RL = 10 Ω to +2.5 V
85
Typ
mA
Low output voltage swing
(1)
0.12
0.16
0.17
The min/max values listed for this specification are ensured by design and characterization only.
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ELECTRICAL CHARACTERISTICS VS+ = +5 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, Giler Mode, unless otherwise noted.
THS7374
PARAMETER
TYP
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
VS+ to GND
5
5.5
5.5
5.5
MIN/
–40°C to TYP/
+85°C
MAX
UNITS
POWER SUPPLY
Maximum operating voltage
Minimum operating voltage
VS+ to GND
(2)
Max
V
5
2.85
2.85
2.85
Min
V
Maximum total quiescent current
VIN = 0 V, VS+ = 5 V
10
12.5
13.5
14.5
Max
mA
Minimum total quiescent current
VIN = 0 V, VS+ = 5 V
10
8
7.5
7
Min
mA
Disabled total quiescent current
Disable pin = 3 V
1
10
10
10
Max
mA
Typ
dB
V
Power-supply rejection (+PSRR)
52
DISABLE CHARACTERISTICS (3)
VIH
Disabled/bypass engaged (4)
2.1
2.2
2.2
2.2
Min
VIL
Enabled/bypass disengaged
0.8
0.8
0.8
0.8
Max
V
IIH
0.2
Typ
mA
IIL
0.2
Typ
mA
Disable time
80
Typ
ns
Enable time
80
Typ
ns
Bypass/filter switch time
5
Typ
ns
20 || 3
Typ
kΩ || pF
Disabled output impedance
(2)
(3)
(4)
6
Disable pin = 3 V
The min/max values listed for this specification are ensured by design and characterization only.
The logic input pins should not be left floating. They must be connected to logic low (or GND) or logic high (or VS+).
Defined as applied logic voltage to achieve total quiescent current of less than 100 mA.
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
PIN CONFIGURATION
PW PACKAGE
TSSOP-14
TOP VIEW
CH1 IN
1
14 CH1 OUT
CH2 IN
2
13 CH2 OUT
CH3 IN
3
12 CH3 OUT
CH4 IN
4
GND
5
10 VS+
DISABLE
6
9
BYPASS
NC
7
8
NC
THS7374IPW
11 CH4 OUT
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CH1 IN
1
I
Video input; channel 1
CH2 IN
2
I
Video input; channel 2
CH3 IN
3
I
Video input; channel 3
CH4 IN
4
I
Video input; channel 4
GND
5
I
Ground pin for all internal circuitry
DISABLE
6
I
Disable pin. Logic high disables the part; logic low enables the part. This pin must not be left
floating. It must be connected to a defined logic state (or GND or VS+).
NC
7, 8
—
BYPASS
9
I
Internal filter bypass. Logic high bypasses the internal low-pass filter; logic low uses the
internal filters. This pin must not be left floating. It must be connected to a defined logic state
(or GND or VS+).
No internal connection
VS+
10
I
Positive power-supply pin; connect to +3 V to +5 V
CH4 OUT
11
O
Video output; channel 4
CH3 OUT
12
O
Video output; channel 3
CH2 OUT
13
O
Video output; channel 2
CH1 OUT
14
O
Video output; channel 1
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FUNCTIONAL BLOCK DIAGRAM
+VS
gm
Level
Shift
Channel 1
Input
LPF
Sync-Tip Clamp
(DC Restore)
800 kW
Bypass
6 dB
Channel 1
Output
6 dB
Channel 2
Output
6 dB
Channel 3
Output
6 dB
Channel 4
Output
6-Pole
9.5-MHz
+VS
gm
Level
Shift
Channel 2
Input
LPF
Sync-Tip Clamp
(DC Restore)
800 kW
Bypass
6-Pole
9.5-MHz
+VS
gm
Level
Shift
Channel 3
Input
LPF
Sync-Tip Clamp
(DC Restore)
800 kW
Bypass
6-Pole
9.5-MHz
+VS
gm
Level
Shift
Channel 4
Input
800 kW
8
LPF
Sync-Tip Clamp
(DC Restore)
+3.3 V to +5 V
Bypass
6-Pole
9.5-MHz
BYPASS
DISABLE
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: GENERAL
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
TOTAL QUIESCENT CURRENT vs TEMPERATURE
OUTPUT OFFSET VOLTAGE vs TEMPERATURE
11.0
325
Output Offset Voltage (mV)
Total Quiescent Current (mA)
Input = 0 V
10.6
10.2
VS+ = 5 V
9.8
VS+ = 3.3 V
9.4
320
315
VS+ = 5 V
310
305
VS+ = 3.3 V
300
295
290
9.0
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10 0
Ambient Temperature (°C)
10 20 30 40 50 60 70 80 90
Ambient Temperature (°C)
Figure 2.
Figure 3.
INPUT RESISTANCE vs TEMPERATURE
MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE
5.0
815
VS+ = 3.3 V and 5 V
Input = 1 V
VS+ = 5 V
4.8
Maximum Output Voltage (V)
Input Resistance (kW)
810
805
800
795
790
4.6
4.4
4.2
Load = 150 W to GND
DC-Coupled
4.0
3.8
3.6
3.4
VS+ = 3.3 V
3.2
785
3.0
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10 0
Figure 4.
Figure 5.
MINIMUM OUTPUT VOLTAGE vs TEMPERATURE
ATTENUATION AT 6.75MHz vs TEMPERATURE
0.04
1.0
Load = 150 W to GND
DC-Coupled
Attenuation at 6.75 MHz (dB)
Minimum Output Voltage (V)
0.06
0.05
10 20 30 40 50 60 70 80 90
Ambient Temperature (°C)
Ambient Temperature (°C)
VS+ = 5 V
0.03
0.02
VS+ = 3.3 V
0.01
0
VS+ = 5 V
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10 0
Ambient Temperature (°C)
10 20 30 40 50 60 70 80 90
Ambient Temperature (°C)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS: GENERAL (continued)
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
ATTENUATION AT 27MHz vs TEMPERATURE
PSRR vs FREQUENCY
70
VS+ = 5 V
Power-Supply Rejection Ratio (dB)
Attenuation at 27 MHz (dB)
58
57
56
55
54
53
52
51
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
40
Bypass Mode
30
Filter Mode
20
10
VS = +3.3 V and 5 V
0
10 k
100 k
Figure 8.
Figure 9.
10 M
100 M
DISABLED OUTPUT IMPEDANCE vs FREQUENCY
100 k
VS = +3.3 V and +5 V
Disable Mode
Filter Mode and Bypass Mode Show Same Results
-60
-70
-80
-90
-100
100 k
VS = +5 V
VS = +3.3 V
1M
10 M
100 M
10 k
1k
100
100 k
1M
10 M
100 M
1G
Frequency (Hz)
Frequency (Hz)
Figure 10.
10
1M
Frequency (Hz)
ZO, Output Impedance (W)
S12 Reverse Transmission Coefficient (dB)
50
Ambient Temperature (°C)
S12 REVERSE TRANSMISSION COEFFICIENT vs
FREQUENCY
-50
60
Figure 11.
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: VS+ = 3.3 V
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
SMALL-SIGNAL GAIN vs FREQUENCY
10
Bypass
Mode
0
RL = 75 W
-10
RL = 150 W
-20
Filter Mode
-30
-40
-50
RL = 150 W
VS = +3.3 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
-60
100 k
10 M
6.0
5.5
4.5
4.0
3.5
Filter Mode
Figure 13.
6.5
RL = 150 W
Phase (°)
RL = 75 W and 150 W
Filter Mode
-180
-315
Bypass
Mode
RL = 75 W
VS = +3.3 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
-360
100 k
1M
Group Delay (ns)
6.0
-45
5.5
VS = +3.3 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
5.0
4.5
RL = 150 W
Bypass Mode
4.0
RL = 75 W
3.5
3.0
2.5
10 M
2.0
100 k
1G
100 M
1M
10 M
Frequency (Hz)
Figure 15.
GROUP DELAY vs FREQUENCY
120
LARGE-SIGNAL GAIN vs FREQUENCY
10
Filter Mode
110
Large-Signal Gain (dB)
Group Delay (ns)
RL = 75 W and 150 W
80
70
50
Bypass
Mode
0
90
60
VS = +3.3 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
40
100 k
1G
100 M
Frequency (Hz)
Figure 14.
100
1G
100 M
GROUP DELAY vs FREQUENCY
0
-270
10 M
Figure 12.
7.0
-225
1M
Frequency (Hz)
PHASE vs FREQUENCY
-135
RL = 75 W
Frequency (Hz)
45
-90
Bypass
Mode
VS = +3.3 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
2.5
100 k
1G
100 M
RL = 75 W and 150 W
5.0
3.0
RL = 75 W
1M
RL = 150 W
6.5
Small-Signal Gain (dB)
Small-Signal Gain (dB)
SMALL-SIGNAL GAIN vs FREQUENCY
7.0
-10
VS = +3.3 V
AC-Coupled Output
Load = 150 W || 10 pF
-20
-30
-40
-50
VO = 0.2 VPP
Filter
Mode
VO = 1 VPP
VO = 2 VPP
VO = 2 VPP
VO = 0.2 VPP
1M
10 M
100 M
-60
100 k
Frequency (Hz)
1M
10 M
100 M
1G
Frequency (Hz)
Figure 16.
Figure 17.
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TYPICAL CHARACTERISTICS: VS+ = 3.3 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
LARGE-SIGNAL GAIN vs FREQUENCY
VO = 0.2 VPP
Large-Signal Gain (dB)
6.5
SMALL-SIGNAL GAIN vs FREQUENCY
10
Bypass
Mode
6.0
VO = 1 VPP
5.5
Filter Mode
VO = 2 VPP
5.0
4.5
VO = 0.2 VPP and 2 VPP
4.0
3.5
3.0
VS = +3.3 V
AC-Coupled Output
Load = 150 W || 10 pF
2.5
100 k
10 M
AC
Filter Mode
-30
AC
-40
VS = +3.3 V
Load = 150 W || 10 pF
VOUT = 200 mVPP
Figure 18.
Figure 19.
6.0
AC
Filter Mode
5.0
AC or DC
DC
4.5
4.0
3.5
3.0
VS = +3.3 V
Load = 150 W || 10 pF
VOUT = 200 mVPP
2.5
100 k
VS+ = 3.3 V
Bypass Mode
RL = 150 W || 10 pF
DC-Coupled Output
-50
1 VPP - HD3
-80
1 VPP - HD2
-90
0.5 VPP - HD3
1M
10 M
100 M
0
1G
4
12
16
Figure 21.
HARMONIC DISTORTION vs FREQUENCY
-40
2 VPP - HD2
Harmonic Distortion (dB)
Harmonic Distortion (dB)
8
Frequency (MHz)
VS+ = 3.3 V
Filter Mode
RL = 150 W || 10 pF
DC-Coupled Output
-60
-70
2 VPP - HD3
1 VPP - HD2
0.5 VPP - HD2
0.5 VPP - HD3
-90
2 VPP - HD2
-50
2 VPP - HD3
-60
1 VPP - HD3
-70
1 VPP - HD2
-80
0.5 VPP - HD3
VS+ = 3.3 V
Bypass Mode
RL = 150 W || 10 pF
AC-Coupled Output
0.5 VPP - HD2
-90
1 VPP - HD3
-100
-100
1
2
3
4
0
4
8
12
16
Frequency (MHz)
Frequency (MHz)
Figure 22.
12
0.5 VPP - HD2
-100
HARMONIC DISTORTION vs FREQUENCY
-80
2 VPP - HD2
2 VPP - HD3
-70
Figure 20.
-50
1G
-60
Frequency (Hz)
-40
100 M
HARMONIC DISTORTION vs FREQUENCY
-40
Bypass
Mode
AC- versus
DC-Coupled Outputs
5.5
10 M
Frequency (Hz)
Harmonic Distortion (dB)
Small-Signal Gain (dB)
6.5
1M
DC
Frequency (Hz)
SMALL-SIGNAL GAIN vs FREQUENCY
7.0
DC
-20
-60
100 k
1G
100 M
AC- versus
DC-Coupled Outputs
-10
-50
1M
Bypass
Mode
0
Small-Signal Gain (dB)
7.0
Figure 23.
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: VS+ = 3.3 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
-40
-0.02
-50
Differential Gain (%)
Harmonic Distortion (dB)
2 VPP - HD2
1 VPP - HD2
0.5 VPP - HD2
DIFFERENTIAL GAIN
0
-60
2 VPP - HD3
-70
-80
1 VPP - HD3
VS+ = 3.3 V
Filter Mode
RL = 150 W || 10 pF
AC-Coupled Output
-90
0.5 VPP - HD3
-100
1
2
PAL
-0.06
-0.08
-0.10
-0.12
-0.14
-0.16
VS+ = 3.3 V
Filter Mode
AC-Coupled Output
-0.18
4
3
NTSC
-0.04
1st
2nd
4th
3rd
5th
6th
5th
6th
Frequency (MHz)
Figure 24.
Figure 25.
DIFFERENTIAL PHASE
Differential Phase (°)
0.50
DIFFERENTIAL GAIN
0
VS+ = 3.3 V
Filter Mode
AC-Coupled Output
-0.05
PAL
Differential Gain (%)
0.60
0.40
NTSC
0.30
0.20
0.10
-0.10
NTSC
-0.15
-0.20
-0.30
-0.35
0
PAL
-0.25
VS+ = 3.3 V
Filter Mode
DC-Coupled Output
-0.40
1st
2nd
3rd
4th
5th
1st
6th
2nd
Figure 26.
DIFFERENTIAL PHASE
0.45
Differential Phase (°)
0.40
4th
OUTPUT IMPEDANCE vs FREQUENCY
100
VS+ = 3.3 V
Filter Mode
DC-Coupled Output
0.35
ZO, Output Impedance (W)
0.50
3rd
Figure 27.
PAL
0.30
0.25
NTSC
0.20
0.15
0.10
0.05
0
1st
2nd
3rd
4th
5th
6th
10
1
Filter Mode
0.1
Bypass Mode
VS = +3.3 V
0.01
100 k
1M
10 M
100 M
1G
Frequency (Hz)
Figure 28.
Figure 29.
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TYPICAL CHARACTERISTICS: VS+ = 3.3 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
-10
SMALL-SIGNAL GAIN vs FREQUENCY
10
VS = +3.3 V
0
-20
Small-Signal Gain (dB)
S22 Output Reflection Coefficient (dB)
S22 OUTPUT REFLECTION COEFFICIENT vs FREQUENCY
-30
-40
-50
Filter Mode
-60
-10
CL = 2 pF and 5 pF
-20
-30
-40
-50
Bypass Mode
-70
100 k
1M
100 M
10 M
Figure 31.
SMALL-SIGNAL GAIN vs FREQUENCY
SMALL-SIGNAL GAIN vs FREQUENCY
10
9
CL = 2 pF and 5 pF
Small-Signal Gain (dB)
Small-Signal Gain (dB)
-40
-50
CL = 21 pF
8
-10
-30
CL = 15 pF
VS = +3.3 V
RL = 150 W || CL
VO = 200 mVPP
Bypass Mode
AC-Coupled Output
-60
10 M
CL = 10 pF
1G
CL = 15 pF
7
6
CL = 10 pF
5
CL = 2 pF and 5 pF
4
3
2
1
CL = 21 pF
100 M
VS = +3.3 V
RL = 150 W || CL
VO = 200 mVPP
Bypass Mode
AC-Coupled Output
0
10 M
100 M
1G
Frequency (Hz)
Frequency (Hz)
Figure 32.
14
1G
Frequency (Hz)
Figure 30.
-20
100 M
10 M
Frequency (Hz)
0
CL = 21 pF
-60
1M
CL = 10 pF
CL = 15 pF
VS = +3.3 V
RL = 150 W || CL
VO = 200 mVPP
Filter Mode
AC-Coupled Output
Figure 33.
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: VS+ = 5 V
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
SMALL-SIGNAL GAIN vs FREQUENCY
10
Bypass
Mode
0
RL = 75 W
-10
RL = 150 W
-20
Filter Mode
-30
-40
-50
RL = 150 W
VS = +5 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
-60
100 k
10 M
6.0
Filter Mode
5.0
RL = 75 W and 150 W
4.5
4.0
3.5
RL = 75 W
VS = +5 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
2.5
100 k
1G
100 M
RL = 150 W
5.5
3.0
RL = 75 W
1M
Bypass
Mode
6.5
Small-Signal Gain (dB)
Small-Signal Gain (dB)
SMALL-SIGNAL GAIN vs FREQUENCY
7.0
Figure 34.
Figure 35.
PHASE vs FREQUENCY
0
6.5
Phase (°)
RL = 150 W
RL = 75 W and 150 W
-135
-225
-270
-315
Filter Mode
Bypass
Mode
RL = 75 W
VS = +5 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
-360
100 k
1M
Group Delay (ns)
6.0
-45
5.5
VS = +5 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
5.0
RL = 150 W
4.5
4.0
RL = 75 W
3.5
Bypass Mode
3.0
2.5
10 M
100 M
2.0
100 k
1G
1M
10 M
Frequency (Hz)
Figure 37.
GROUP DELAY vs FREQUENCY
10
110
0
RL = 75 W and 150 W
Large-Signal Gain (dB)
Group Delay (ns)
LARGE-SIGNAL GAIN vs FREQUENCY
120
Filter Mode
90
80
70
60
50
VS = +5 V
AC-Coupled Output
CL = 10 pF
VOUT = 200 mVPP
40
100 k
1G
100 M
Frequency (Hz)
Figure 36.
100
1G
100 M
GROUP DELAY vs FREQUENCY
7.0
-180
10 M
Frequency (Hz)
45
-90
1M
Frequency (Hz)
-10
Bypass
Mode
VS = +5 V
AC-Coupled Output
Load = 150 W || 10 pF
-20
-30
-40
-50
VO = 0.2 VPP
VO = 1 VPP
Filter
Mode
VO = 2 VPP
VO = 2 VPP
VO = 0.2 VPP
1M
10 M
100 M
-60
100 k
Frequency (Hz)
1M
10 M
100 M
1G
Frequency (Hz)
Figure 38.
Figure 39.
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TYPICAL CHARACTERISTICS: VS+ = 5 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
LARGE-SIGNAL GAIN vs FREQUENCY
7.0
VO = 0.2 VPP
6.5
6.0
5.5
5.0
VS = +5 V
AC-Coupled Output
Load = 150 W || 10 pF
4.5
4.0
Bypass
Mode
0
Small-Signal Gain (dB)
Large-Signal Gain (dB)
SMALL-SIGNAL GAIN vs FREQUENCY
10
Bypass
Mode
VO = 2 VPP
Filter Mode
VO = 1 VPP
3.5
AC
Filter Mode
1M
10 M
-40
VS = +5 V
Load = 150 W || 10 pF
VOUT = 200 mVPP
-60
100 k
1G
100 M
Figure 41.
Harmonic Distortion (dB)
Small-Signal Gain (dB)
6.0
AC
AC or DC
5.0
DC
Filter Mode
4.0
VS = +5 V
Load = 150 W || 10 pF
VOUT = 200 mVPP
2.5
100 k
VS+ = 5 V
Filter Mode
RL = 150 W || 10 pF
DC-Coupled Output
-50
-60
-70
-80
1 VPP - HD3
-90
0.5 VPP - HD3
10 M
100 M
0
1G
Figure 42.
Figure 43.
1 VPP - HD2
Harmonic Distortion (dB)
Harmonic Distortion (dB)
16
2 VPP - HD2
2 VPP - HD2
-70
2 VPP - HD3
0.5 VPP - HD2
12
HARMONIC DISTORTION vs FREQUENCY
-40
1 VPP - HD3
-90
-50
1 VPP - HD3
2 VPP - HD3
-60
-70
0.5 VPP - HD3
-80
1 VPP - HD2
VS+ = 5 V
Filter Mode
RL = 150 W || 10 pF
AC-Coupled Output
0.5 VPP - HD2
-90
-100
-100
1
2
3
4
0
4
8
12
16
Frequency (MHz)
Frequency (MHz)
Figure 44.
16
8
Frequency (MHz)
-60
-80
4
0.5 VPP - HD2
Frequency (Hz)
VS+ = 5 V
Filter Mode
RL = 150 W || 10 pF
DC-Coupled Output
-50
2 VPP - HD3
2 VPP - HD2
HARMONIC DISTORTION vs FREQUENCY
-40
1G
1 VPP - HD2
-100
1M
100 M
HARMONIC DISTORTION vs FREQUENCY
-40
Bypass
Mode
AC- versus DC-Coupled Outputs
3.0
10 M
Figure 40.
6.5
3.5
1M
Frequency (Hz)
SMALL-SIGNAL GAIN vs FREQUENCY
4.5
DC
Frequency (Hz)
7.0
5.5
AC
-30
VO = 0.2 VPP and 2 VPP
2.5
100 k
DC
-20
-50
3.0
AC- versus
DC-Coupled Outputs
-10
Figure 45.
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: VS+ = 5 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
VS+ = 5 V, Filter Mode
RL = 150 W || 10 pF
AC-Coupled Output
-50
1 VPP - HD2
DIFFERENTIAL GAIN
0
2 VPP - HD2
NTSC
-0.02
Differential Gain (%)
Harmonic Distortion (dB)
-40
-60
2 VPP - HD3
0.5 VPP - HD2
-70
1 VPP - HD3
-80
-90
-0.04
-0.08
-0.10
-0.12
0.5 VPP - HD3
-100
1
2
VS+ = 5 V
Filter Mode
AC-Coupled Output
-0.14
4
3
PAL
-0.06
1st
2nd
3rd
4th
5th
6th
Frequency (MHz)
Figure 46.
Figure 47.
DIFFERENTIAL PHASE
Differential Phase (°)
0.60
DIFFERENTIAL GAIN
0
VS+ = 5 V
Filter Mode
AC-Coupled Output
-0.05
PAL
0.50
Differential Gain (%)
0.70
0.40
NTSC
0.30
0.20
0.10
-0.10
NTSC
-0.15
-0.20
-0.30
-0.35
0
PAL
-0.25
VS+ = 5 V
Filter Mode
DC-Coupled Output
-0.40
1st
2nd
3rd
4th
5th
1st
6th
2nd
Figure 48.
DIFFERENTIAL PHASE
Differential Phase (°)
0.40
0.35
PAL
0.30
0.25
NTSC
0.20
0.15
0.10
0.05
0
2nd
5th
6th
OUTPUT IMPEDANCE vs FREQUENCY
VS+ = 5 V
Filter Mode
DC-Coupled Output
1st
4th
100
ZO, Output Impedance (W)
0.45
3rd
Figure 49.
3rd
4th
5th
6th
10
1
Filter Mode
0.1
Bypass Mode
VS = +5 V
0.01
100 k
1M
10 M
100 M
1G
Frequency (Hz)
Figure 50.
Figure 51.
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TYPICAL CHARACTERISTICS: VS+ = 5 V (continued)
RL = 150 Ω to GND and dc-coupled input and output, unless otherwise noted.
-10
SMALL-SIGNAL GAIN vs FREQUENCY
10
VS = +5 V
0
-20
Small-Signal Gain (dB)
S22 Output Reflection Coefficient (dB)
S22 OUTPUT REFLECTION COEFFICIENT vs FREQUENCY
-30
-40
-50
Filter Mode
-60
-10
CL = 2 pF and 5 pF
-20
CL = 15 pF
-30
-40
-50
Bypass Mode
-70
100 k
1M
100 M
10 M
Figure 53.
SMALL-SIGNAL GAIN vs FREQUENCY
SMALL-SIGNAL GAIN vs FREQUENCY
9
Small-Signal Gain (dB)
Small-Signal Gain (dB)
CL = 2 pF and 5 pF
-10
-40
-50
CL = 21 pF
8
CL = 15 pF
VS = +5 V
RL = 150 W || CL
VO = 200 mVPP
Bypass Mode
AC-Coupled Output
-60
10 M
CL = 10 pF
1G
CL = 15 pF
7
6
CL = 10 pF
5
CL = 2 pF and 5 pF
4
3
2
1
CL = 21 pF
100 M
VS = +5 V
RL = 150 W || CL
VO = 200 mVPP
Bypass Mode
AC-Coupled Output
0
10 M
100 M
1G
Frequency (Hz)
Frequency (Hz)
Figure 54.
18
1G
Frequency (Hz)
10
-20
100 M
10 M
Figure 52.
-30
CL = 21 pF
-60
1M
Frequency (Hz)
0
CL = 10 pF
VS = +5 V
RL = 150 W || CL
VO = 200 mVPP
Filter Mode
AC-Coupled Output
Figure 55.
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
APPLICATION INFORMATION
The THS7374 is targeted for standard definition video
output buffer applications. Although it can be used for
numerous other applications, the needs and
requirements of the video signal are the most
important design parameters of the THS7374. Built
on the revolutionary complementary Silicon
Germanium (SiGe) BiCom3X process, the THS7374
incorporates many features not typically found in
integrated video parts while consuming very low
power. The THS7374 has the following features:
• Single-supply 3 V to 5 V operation with low total
quiescent current of 9.6-mA at 3.3 V and 10-mA at
5 V.
• 0.1mA disable mode allows for shutting down the
THS7374
to
save
system
power
in
power-sensitive applications.
• Input configuration accepts dc + level shift, ac
sync-tip clamp, or ac-bias.
• AC-biasing is allowed with the use of a single
external pull-up resistor to the positive power
supply.
• Sixth-order low-pass filter for DAC reconstruction
or ADC image rejection:
– 9.5-MHz for NTSC, PAL, SECAM, composite
(CVBS), s-video Y’C’, 480i/576i Y’P’BP’R,
G’B’R’, and SCART signals.
• Bypass mode bypasses the low-pass filter with a
150-MHz bandwidth and 130-V/ms slew rate
amplifier
• Internal fixed gain of 2 V/V (+6 dB) buffer that can
drive two video lines per channel with dc-coupling
or traditional ac-coupling.
• Signal flow-through configuration in a TSSOP-14
package that complies with the latest lead-free
(RoHS-compatible) and green manufacturing
requirements.
Place a 0.1-mF to 0.01-mF capacitor as close as
possible to the power-supply pins. Failure to do so
may result in ringing or oscillating at the THS7374
outputs. Additionally, a large capacitor (such as 22 mF
to 100 mF) should be placed on the power-supply line
to minimize interference with 50-Hz/60-Hz line
frequencies.
INPUT VOLTAGE
The THS7374 input range allows for an input signal
range from –0.2 V to about (VS+ – 1.5 V). However,
because of the internal fixed gain of 2 V/V (+6 dB)
and the internal level shift of 150 mV nominal, the
output is generally the limiting factor for the allowable
linear input range. For example, with a 5-V supply,
the linear input range is from –0.2 V to 3.5 V. As a
result of the gain and level shift, the linear output
range limits the allowable linear input range to be
from about –0.1 V to 2.3 V.
INPUT OVERVOLTAGE PROTECTION
The THS7374 is built using a very high-speed
complementary bipolar and CMOS process. The
internal junction breakdown voltages are relatively
low for these very small geometry devices. These
breakdowns are reflected in the Absolute Maximum
Ratings table. All input and output device pins are
protected with internal ESD protection diodes to the
power supplies, as shown in Figure 56.
+VS
External
Input/Output
Pin
Internal
Circuitry
OPERATING VOLTAGE
The THS7374 is designed to operate from 3-V to 5-V
over a –40°C to +85°C temperature range. The
impact on performance over the entire temperature
range is negligible as a result of the implementation
of thin film resistors and high quality, low temperature
coefficient capacitors. The design of the THS7374
allows operation down to 2.85 V, but it is
recommended to use at least a 3-V supply to ensure
no issues with headroom or clipping.
Figure 56. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above and below the supplies as
well. The protection diodes can typically support 30
mA of continuous current when overdriven.
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TYPICAL CONFIGURATION AND VIDEO
TERMINOLOGY
This rationale is also used for the chroma (C') term.
Chroma is derived from the non-linear R'G'B' terms
and thus it is nonlinear. Chominance (C) is derived
from linear RGB, giving the difference between
chroma (C') and chrominance (C). The color
difference signals (P'B/P'R/U'/V') are also referenced
in this way to denote the nonlinear (gamma
corrected) signals.
A typical application circuit that uses the THS7374 as
a video buffer is shown in Figure 57. It shows a DAC
or encoder driving the input channels of the
THS7374. One channel is a composite video (CVBS)
channel of a standard definition (SD) video system.
The other channels are the component video Y'P'BP'R
(sometimes labeled Y'U'V' or incorrectly labeled
Y'C'BC'R) signals of a 480i or 576i system. These
channels could easily be the s-video Y'/C' channels
or the R'G'B' channels of a SCART system.
R'G'B' (commonly mislabeled RGB) is also called
G'B'R' (again commonly mislabeled as GBR) in
professional video systems. The SMPTE component
standard stipulates that the luma information is
placed on the first channel, the blue color difference
is placed on the second channel, and the red color
difference signal is placed on the third channel. This
configuration is consistent with the Y'P'BP'R
nomenclature. Because the luma channel (Y') carries
the sync information and the green channel (G') also
carries the sync information, it makes logical sense
that G' be placed first in the system. Furthermore,
because the blue color difference channel (P'B) is
next and the red color difference channel (P'R) is last,
then it also makes logical sense to place the B' signal
on the second channel and the R' signal on the third
channel respectfully. Thus, hardware compatibility is
better achieved when using G'B'R' rather than R'G'B'.
Note that for many G'B'R' systems, sync is embedded
on all three channels, but this may not always be the
case in all systems.
Note that the Y' term is used for the luma channels
throughout this document rather than the more
common luminance (Y) term. The reason for this
usage is to account for the definition of luminance as
stipulated by the CIE (International Commission on
Illumination). Video departs from true luminance
because a nonlinear term, gamma, is added to the
true RGB signals to form R'G'B' signals. These R'G'B'
signals are then used to mathematically create luma
(Y'). Thus, luminance (Y) is not maintained, providing
a difference in terminology.
+3.3 V
THS7374
CVBS
R
DAC/Encoder
SDTV
CVBS
S-Video
Y'P'BP'R
R'G'B'
CVBS/Sync
75 W
1
CH1 IN
CH1 OUT 14
2
CH2 IN
CH2 OUT 13
3
CH3 IN
CH3 OUT 12
75 W
Y'/G' Out
75 W
Y'/G'
R
P’B/B'
4
CH4 IN
5
GND
6
DISABLE
7
NC
CH4 OUT 11
75 W
VS+ 10
BYPASS
NC
P'B/B' Out
9
75 W
8
R
75 W
P'R/R' Out
P’R/R'
R
75 W
To GPIO Controller
or GND
75 W
+3 V to +5 V
Figure 57. Typical SDTV CVBS/Y'P'BP'R Inputs from DC-Coupled Encoder/DAC
with DC-Coupled Line Driving
20
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INPUT MODE OF OPERATION: DC
The THS7374 allows for both ac-coupled and
dc-coupled inputs. Many DACs or video encoders can
be dc-connected to the THS7374. One of the
drawbacks to dc coupling is when 0 V is applied to
the input. Although the input of the THS7374 allows
for a 0-V input signal with no issues, the output swing
of a traditional amplifier cannot yield a 0-V signal,
resulting in possible clipping. This condition is true for
any single-supply amplifier as a result of the output
transistor limitations. Both CMOS and bipolar
transistors cannot go to 0 V while sinking current.
This characterization of a transistor is also the same
reason why the highest output voltage is always less
than the power-supply voltage when sourcing current.
This output clipping can reduce the sync amplitudes
(both horizontal and vertical sync) on the video
signal. A problem occurs if the receiver of this video
signal uses an AGC loop to account for losses in the
transmission line. Some video AGC circuits derive
gain from the horizontal sync amplitude. If clipping
occurs on the sync amplitude, then the AGC circuit
can increase the gain too much—resulting in too
much luma and/or chroma amplitude gain correction.
This overcorrection may result in a picture with an
overly bright display with too much color saturation.
Other AGC circuits use the chroma burst amplitude
for amplitude control, and a reduction in the sync
signals does not alter the proper gain setting.
However, it is good engineering design practice to
ensure that saturation/clipping does not take place.
Transistors always take a finite amount of time to
come out of saturation. This saturation could possibly
result in timing delays or other aberrations on the
signals.
To eliminate saturation/clipping problems, the
THS7374 has a 150-mV input level shift feature. This
feature takes the input voltage and adds an internal
+150-mV shift to the signal. Since the THS7374 also
has a gain of 6 dB (2 V/V), the resulting output with a
0-V applied input signal is approximately 300 mV.
The THS7374 rail-to-rail output stage can create this
output level while connected to a typical video load.
This feature ensures that no saturation/clipping of the
sync signals occur. This shift is constant, regardless
of the input signal. For example, if a 1-V input is
applied, the output is at 2.3 V.
Because the internal gain is fixed at +6 dB, the gain
dictates what the allowable linear input voltage range
can be without clipping concerns. For example, if the
power supply is set to 3.0 V, the maximum output is
approximately 2.9 V while driving a significant amount
of current. Thus, to avoid clipping, the allowable input
is [(2.9 V/2) – 0.15 V] = 1.3 V. This calculation is true
for up to the maximum recommended 5-V power
supply that allows about a [(4.9 V/2) – 0.15 V] = 2.3 V
input range while avoiding clipping on the output.
The input impedance of the THS7374 in this mode of
operation is dictated by the internal 800-kΩ pull-down
resistor, as shown in Figure 58. Note that the internal
voltage shift does not appear at the input pin, but only
the output pin. This configuration ensures there is no
issue with interfacing to the source.
+VS
Internal
Circuitry
Input
Pin
800 kW
Level
Shift
Figure 58. Equivalent DC Input Mode Circuit
INPUT MODE OF OPERATION: AC SYNC TIP
CLAMP
Some video DACs or encoders are not referenced to
ground but rather to the positive power supply. The
resulting video signals are generally too high of a
voltage for a dc-coupled video buffer to function
properly. To account for this scenario, the THS7374
incorporates a sync-tip clamp (STC) circuit. This
function requires a capacitor (nominally 0.1 mF) to be
in series with the input. Note that while the term
sync-tip-clamp is used throughout this document, it
should be noted that the THS7374 would probably be
better termed to be a dc restoration circuit based on
how this function is performed. This circuit is an
active clamp circuit and not a passive diode clamp
function.
The input to the THS7374 has an internal control loop
that sets the lowest input applied voltage to clamp at
ground (0 V). By setting the reference at 0-V, the
THS7374 allows a dc-coupled input to also function.
Therefore, the STC is considered transparent
because it does not operate unless the input signal
goes below ground. The signal then goes through the
same 150-mV level shifter, resulting in an output
voltage low level of 300 mV. If the input signal tries to
go below 0 V, the internal control loop of the
THS7374 sources up to 3-mA of current to increase
the input voltage level on the THS7374 input side of
the coupling capacitor. As soon as the voltage goes
above the 0-V level, the loop stops sourcing current
and becomes very high impedance.
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One of the concerns about the sync tip clamp level is
how the clamp reacts to a sync edge that has
overshoot—common in VCR signals or reflections
found in poor printed circuit board (PCB) layouts.
Ideally, the STC should not react to the overshoot
voltage of the input signal. Otherwise, this issue could
result in clipping on the rest of the video signal
because it may raise the bias voltage too much.
To help minimize this input signal overshoot problem,
the control loop in the THS7374 has an internal
low-pass filter as shown in Figure 59. This filter
reduces the response time of the STC circuit. This
delay is a function of how far the voltage is below
ground, but in general it is about an 800-ns delay.
This filter slows down the response of the control loop
so as not to clamp on the input overshoot voltage, but
rather the flat portion of the sync signal.
+VS
Internal
Circuitry
STC LPF
+VS
gm
Input
0.1 mF Input
Pin
800 kW
Level
Shift
Figure 59. Equivalent AC Sync Tip Clamp Input
Circuit
As a result of this delay, the sync may have an
apparent voltage shift. The amount of shift depends
on the amount of droop in the signal as dictated by
the input capacitor and the STC current flow.
Because the sync is primarily for timing purposes,
with synchronization occurring on the edge of the
sync signal, this shift is transparent in most systems.
While this feature may not fully eliminate overshoot
issues on the input signal in case of severe overshoot
and/or ringing, the STC system should help minimize
improper clamping levels. As an additional method to
help minimize this issue, an external capacitor (such
as 10 pF to 47 pF) to ground in parallel with the
external termination resistors can help filter overshoot
problems.
It should be noted that this STC system is dynamic
and does not rely upon timing in any way. It only
depends on the voltage appearing at the input pin at
any given point in time. The STC filtering helps
minimize level shift problems associated with
switching noises or very short spikes on the signal
line. This feature helps ensure a very robust STC
system.
22
When the ac STC operation is used, there must also
be some finite amount of discharge bias current. As
previously described, if the input signal goes below
the 0-V clamp level, the internal loop of the THS7374
sources current to increase the voltage appearing at
the input pin. As the difference between the signal
level and the 0-V reference level increases, the
amount
of
source
current
increases
proportionally—supplying up to 3 mA of current.
Thus, the time to re-establish the proper STC voltage
can be very fast. If the difference is very small, then
the source current is also very small to account for
minor voltage droop.
However, if the input signal goes above the 0-V input
level a problem arises. The problem is that the video
signal is always above this level and must not be
altered in any way. But if the sync level of the input
signal is above this 0-V level, then the internal
discharge (sink) current reduces the ac-coupled bias
signal to the proper 0-V level.
This discharge current must not be large enough to
alter the video signal appreciably or picture quality
issues may arise. This issue is often seen by looking
at the tilt (droop) of a constant luma signal being
applied and observing the resulting output level. The
associated change in luma level from the beginning
of the video line to the end of the video line is the
amount of line tilt (droop).
If the discharge current is very small, then the amount
of tilt is very low, which is a generally a good thing.
However, the amount of time for the system to
capture the sync signal could be too long. This effect
is also called hum rejection. Hum arises from the ac
line voltage frequency of 50-Hz or 60-Hz. The value
of the discharge current and the ac-coupling capacitor
combine to dictate the hum rejection and the amount
of line tilt.
To allow for both dc-coupling and ac-coupling in the
same part, the THS7374 incorporates an 800-kΩ
resistor to ground. Although a true constant-current
sink is preferred over a resistor, there are significant
issues when the voltage is near ground. This
condition can cause the current sink transistor to
saturate and cause potential problems with the signal.
Also, this resistor is large enough to not impact a
dc-coupled DAC termination. For discharging an
ac-coupled source, Ohm’s Law is applied. If the video
signal is 1 V, then there is 1 V/800 kΩ = 1.25-mA of
discharge current. If more hum rejection is desired or
there is a loss of sync occurring, simply decrease the
0.1-mF input coupling capacitor. A decrease from 0.1
mF to 0.047 mF increases the hum rejection by a
factor of 2:1. Alternatively, an external pull-down
resistor to ground may be added that decreases the
overall resistance and ultimately increases the
discharge current.
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To ensure proper stability of the ac STC control loop,
the source impedance must be less than 1-kΩ with
the input capacitor in place. Otherwise, there is a
possibility for the control loop to ring; this ringing may
appear on the THS7374 output. Because most DACs
or encoders use resistors to establish the voltage,
which are typically less than 300-Ω, meeting the less
than 1-kΩ requirement is easily done. However, if the
source impedance looking from the THS7374 input
perspective is very high, simply adding a 1-kΩ
resistor to GND ensures proper operation of the
THS7374.
300 mV)/2 = 0.65 V. Thus, the pull-up resistor
calculates to a standard 3.3-MΩ resistor, resulting in
0.644 V. If the output dc-bias point is desired to be
1.6 V with a 5-V power supply, then the pull-up
resistor value calculates to be approximately
5.36-MΩ.
INPUT MODE OF OPERATION: AC BIAS
The value of the output bias is very flexible and is left
to each individual design. It is important to ensure
that the signal does not clip or saturate the video
signal. Thus, it is recommended to ensure the output
bias voltage is between 0.9 V and (VS+ – 1 V). For
100% color saturated CVBS or signals with
Macrovision, the CVBS signal can reach up to 1.23
VPP input, or 2.46 VPP output. In contrast, other
signals are typically 0.7 VPP input, or 1.4 VPP output.
As such, the output bias voltage must account for a
worst-case situation depending on the potential
signals.
Sync tip clamps are ideal for signals that have
horizontal and/or vertical syncs associated with them.
However, some video signals do not have a sync
embedded within the signal. If ac-coupling of these
signals is desired, then a dc bias is required to
properly set the dc operating point within the
THS7374. This function is easily accomplished with
the THS7374 by simply adding an external pull-up
resistor to the positive power supply, as shown in
Figure 60.
+3.3 V
CIN
0.1 mF
Input
+3.3 V
One other issue that must be taken into account is
the dc-bias point as a function of the power supply.
As such, there is an impact on the system PSRR. To
help reduce this impact, the input capacitor combines
with the pull-up resistance to function as a low-pass
filter. Additionally, the time to charge the capacitor to
the final dc bias point is also a function of the pull-up
resistor and the input capacitor. Lastly, the input
capacitor forms a high-pass filter with the parallel
impedance of the pull-up resistor and the 800-kΩ
resistor. In general, it is good to have this high-pass
filter at approximately 3-Hz to minimize any potential
droop on a P’B, P’R, or non-sync B’ or R’ signal. A
0.1-mF input capacitor with a 3.3-MΩ pull-up resistor
equates to a 2.5-Hz high-pass corner frequency.
Internal
Circuitry
RPU
Input
Pin
800 kW
Level
Shift
Figure 60. AC-Bias Input Mode Circuit
Configuration
The dc voltage that appears at the input pin is equal
to Equation 1:
VDC = VS
800 kW
800 kW + RPU
Keep in mind that the internal 800-kΩ resistor has a
±20% variance. As such, the calculations should take
this variance into account. For the 0.644-V input bias
voltage example above using an ideal 3.3-MΩ
resistor, the input dc bias voltage is about 0.644 V
(±0.1 V).
(1)
The THS7374 allowable input range is approximately
0 V to (VS+ – 1.5 V), which allows for a very wide
input voltage range. As such, the input dc bias point
is very flexible; the output dc bias point is the primary
factor. For example, if the output dc bias point is
desired to be mid-rail on a 3.3-V supply, then the
input dc bias point is recommended to be (1.6 V –
This mode of operation is recommended for use with
chroma (C’), P’B, P’R, U’, V’, and non-sync R'G'B’
signals. This method can also be utilized with signals
with sync if desired. The benefit of using the STC
function is that it maintains a constant back porch
voltage as opposed to a back porch voltage that
fluctuates depending on the video content. Because
the corner frequency of the input is a very low 2.5 Hz,
then this is still very good performance, but not as
good relative to a STC configuration.
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OUTPUT MODE OF OPERATION: DC
COUPLED
care must be taken to ensure that the junction
temperature does not exceed this level; otherwise,
long-term reliability could suffer. Although this
configuration only adds less than 10 mW of power
dissipation per channel, the overall low-power
dissipation of the THS7374 design minimizes
potential thermal issues even when using the TSSOP
package at high ambient temperatures.
The THS7374 incorporates a rail-to-rail output stage
that can be used to drive the line directly without the
need for large ac coupling capacitors, as shown in
Figure 61. This approach offers the best line tilt and
field tilt (or droop) performance because no ac
coupling occurs. Keep in mind that if the input is
ac-coupled, then the resulting tilt because of the input
ac coupling is seen on the output regardless of the
output coupling. The 80-mA output current drive
capability of the THS7374 was designed to drive two
video lines simultaneously (essentially, a 75-Ω load)
while maintaining as wide an output dynamic range
as possible.
Note that the THS7374 can drive the line with dc
coupling regardless of the input mode of operation.
The only requirement is to make sure the video line
has proper termination in series with the
output—typically 75-Ω. This termination helps isolate
capacitive loading effects from the THS7374 output.
Failure to isolate capacitive loads may result in
instabilities with the output buffer, potentially causing
ringing or oscillations to appear. The stray
capacitance appearing directly at the THS7374 output
pins should be kept below 20-pF. The best way to
ensure this limit is maintained is to place the 75-Ω
series output resistor as close as possible to the
output pin. If an output capacitor is used, as
discussed in the next section, then it should be
placed after the resistor.
One concern of dc coupling, however, arises if the
line is terminated to ground. If the ac-bias input
configuration is used, the output of the THS7374 has
a dc bias on the output. With two lines terminated to
ground, this configuration creates a dc current path
that results in a slightly decreased high output voltage
swing and an increase in power dissipation of the
THS7374. While the THS7374 was designed to
operate with a junction temperature of up to +125°C,
+3.3 V
THS7374
CVBS
R
DAC/Encoder
SDTV
CVBS
S-Video
Y'P’BP'R
R'G'B’
CVBS/Sync
75 W
1
CH1 IN
CH1 OUT 14
2
CH2 IN
CH2 OUT 13
3
CH3 IN
CH3 OUT 12
75 W
Y'/G' Out
75 W
Y'/G'
R
P'B/B'
4
CH4 IN
5
GND
6
DISABLE
7
NC
CH4 OUT 11
75 W
VS+ 10
BYPASS
NC
P'B/B' Out
9
75 W
8
R
75 W
P'R/R' Out
P'R/R'
R
75 W
To GPIO Controller
or GND
75 W
+3 V to +5 V
Figure 61. Typical SDTV System with DC-Coupled Line Driving
24
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OUTPUT MODE OF OPERATION: AC
COUPLED
This configuration helps ensure line-to-line dc
isolation and avoids the potential problems discussed
above. Using a single 1000-mF capacitor for two lines
can be done, but there is a chance for ground loops
and interference to be created between the two
receivers.
A very common method of coupling the video signal
to the line is the use of a large capacitor. This
capacitor is typically between 220 mF and 1000 mF,
although 470 mF is very common. The value of this
capacitor must be large enough to minimize the line
tilt (droop) and/or field tilt associated with ac coupling
as described previously in this document. AC
coupling is done for several reasons, but most often
to ensure full interoperability with the receiving video
system. AC coupling also ensures adherence to video
standard specifications. It ensures that regardless of
the reference dc voltage used on the transmit side,
the receive side re-establishes the dc reference
voltage to its own requirements.
Lastly, because of the edge rates and frequencies of
operation, it is recommended (but not required) to
place a 0.1-mF to 0.01-mF capacitor in parallel with
the large 220-mF to 1000-mF capacitor. These
large-value capacitors are generally aluminum
electrolytic. It is well-known that these capacitors
have significantly large equivalent series resistance
(ESR), and the impedance at high frequencies is
rather large because of the associated inductances
involved with the leads and construction. The small
0.1-mF to 0.01-mF capacitors help pass these
high-frequency (> 1-MHz) signals with much lower
impedance than the large capacitors.
As with the dc output mode of operation discussed
previously, each line should have a 75-Ω source
termination resistor in series with the ac coupling
capacitor. If two lines are to be driven, it is best to
have each line use its own capacitor and resistor
rather than sharing these components, as shown in
Figure 62.
Although it is common to use the same capacitor
values for all the video lines, the frequency bandwidth
of the chroma signal in a s-video system are not
required to go as low (or as high of a frequency) as
the luma channels. Thus, the capacitor values of the
chroma line(s) can be smaller, such as 0.1 mF.
+3.3 V
THS7374
(1)
0.1 mF
R
(1)
Y'/G'
+3.3 V
R
(1)
RPU
P'B/B'
CH1 OUT 14
2
CH2 IN
CH2 OUT 13
3
CH3 IN
CH3 OUT 12
4
CH4 IN
CH4 OUT 11
5
GND
6
DISABLE
7
NC
(2)
75 W
75 W
(2)
CVBS Out 1
330 mF
75 W
VS+ 10
BYPASS
9
NC
8
Y'/G' Out
75 W
(2)
330 mF
+3.3 V
R
(1)
0.1 mF
RPU
R
75 W
Y' Out 1
(2)
330 mF
+
75 W
P'R/R'
CVBS/Sync
330 mF
+
0.1 mF
CH1 IN
+
0.1 mF
DAC/Encoder
SDTV
CVBS
S-Video
Y'P'BP'R
R'G'B'
1
+
75 W
CVBS
75 W
To GPIO Controller
or GND
75 W
P’B/B' Out
75 W
P'B Out 1
(2)
330 mF
+
75 W
(2)
330 mF
+
+3 V to +5 V
75 W
(2)
75 W
P'R Out 1
330 mF
+
75 W
P’R/R' Out
330 mF
+
75 W
(2)
75 W
(1) An ac-coupled input is shown in this example. DC coupling is also allowed as long as the DAC output voltage is within the allowable
linear input and output voltage range of the THS7374. To dc-couple, remove the 0.1mF input capacitors and RPU.
(2) An ac-coupled output is shown in this example. DC coupling is also allowed by simply removing these capacitors.
Figure 62. Typical SDTV AC-Input System Driving Two AC-Coupled Video Lines
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Low-Cost SCART System
The THS7374 is an ideal device for use in low-cost
SCART systems. SCART is used primarily throughout
Europe and requires four video channels to support
the RGB and timing channel. The timing channel is
also utilized for CVBS signals for systems that do not
have separate RGB video signals. The connector
also adds audio and several other functions.
Figure 63 shows a low-cost application that allows for
a commonly-used SCART switching interface with a
simple CD4053 switch. The relatively high impedance
of this switch is acceptable in this configuration,
because the input impedance of the THS7374 is 800
kΩ and the audio signal impedance requirement is
less than 1 kΩ. Obviously, other switches and
methods could be used, but this alternative is very
low cost compared to fairly expensive SCART
switching ICs. It does not support all possible modes
and configurations, but it is a good fit to meet many
system requirements.
VCR CVBS/
Sync Out
(1)
330 mF
75 W
+
TV CVBS/
Sync Out
75 W
THS7374
R'
Video SOC/DAC
R
G'
R1
1
CH1 IN
CH1 OUT 14
2
CH2 IN
CH2 OUT 13
3
CH3 IN
CH3 OUT 12
4
CH4 IN
CH4 OUT 11
5
GND
6
DISABLE
7
NC
TV R' Out
75 W
TV G' Out
75 W
VS+ 10
BYPASS
9
NC
8
TV B' Out
75 W
TV SCART
(1)
330 mF
+
(1)
330 mF
+
(1)
330 mF
+
R1
CVBS/Sync
+3 V to +5 V
+12 V
15
16
13
14
11
12
NC
9
10
NC
7
8
5
6
3
4
1
2
NC
75 W
Fast Blank
RGB/CVBS
(From GPIO)
10 kW
+12 V
1.5 kW
470 W
STBY/TV
1 kW (From GPIO)
NC
1.5 kW
NC
16:9/4:3
(From GPIO)
1 kW
47 mF
NC
R2
NC
Amp
LPF Bias
Right
VCR SCART
Audio Right Out
47 mF
470 W
Amp
LPF Bias
Left
Audio
18
21
Audio Left Out
470 W
R1
R2
SOC
PCM17xx
20
17
(1)
330 mF
+
B'
To GPIO Controller
or GND
19
NE5532
DRV600
DRV601
INH
VEE
VSS
A
B
C
CD4053
NC
Audio Left Out
470 W
47 mF
Audio Right Out
47 mF
470 W
20
17
18
15
16
13
14
11
12
NC
9
10
NC
7
8
5
6
3
4
1
2
75 W
NC
220 W
VCR Mode
22 kW
22 kW
21
47 mF
0.1 mF
VCR CVBS In
19
22 kW
100 W
100 kW
+VBIAS
100 kW
47 mF
100 W
(1) These capacitors are optional.
Figure 63. Low-Cost SCART Switching System Circuit
26
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LOW-PASS FILTER
Each channel of the THS7374 incorporates a
sixth-order low-pass filter. These video reconstruction
filters minimize DAC images from being passed onto
the video receiver. Depending on the receiver design,
failure to eliminate these DAC images can cause
picture quality problems as a result of ADC aliasing.
Another benefit of the filter is to smooth out
aberrations in the signal which some DACs can have
if the internal device filtering is not very good. This
technique helps with picture quality and helps ensure
that the signal meets video bandwidth requirements.
Each filter has an associated Butterworth
characteristic. The benefit of the Butterworth
response is that the frequency response is flat, with a
relatively steep initial attenuation at the corner
frequency. The problem is that the group delay rises
near the corner frequency. Group delay is defined as
the change in phase (radians/second) divided by a
change in frequency. An increase in group delay
corresponds to a time domain pulse response that
has overshoot and some possible ringing associated
with the overshoot.
The use of other type of filters, such as elliptic or
chebyshev, are not recommended for video
applications because of the very large group delay
variations near the corner frequency, resulting in
significant overshoot and ringing. While these elliptic
or chebyshev filters may help meet the video
standard specifications with respect to amplitude
attenuation, the group delay is well beyond the
standard specifications. When considering these filter
types, keep in mind that video can go from a white
pixel to a black pixel over and over again, and ringing
can easily occur. Ringing typically causes a display to
have ghosting or fuzziness appear on the edges of a
sharp transition. On the other hand, a Bessel filter
has ideal group delay response, but the rate of
attenuation is typically too low for acceptable image
rejection. Thus, the Butterworth filter is a respectable
compromise for both attenuation and group delay.
The THS7374 filters have a nominal corner (–3 dB)
frequency at 9.5-MHz and a –1 dB passband typically
at 8.2-MHz. This 9.5-MHz filter is ideal for standard
definition (SD) NTSC, PAL, and SECAM composite
video (CVBS) signals. It is also useful for s-video
signals (Y'C'), 480i/576i Y'P'BP'R, Y'U'V', broadcast
G'B'R' (R'G'B') signals, and computer video signals.
The 9.5-MHz –3 dB corner frequency was designed
to achieve 54-dB of attenuation at 27-MHz—a
common sampling frequency between the DAC/ADC
second and third Nyquist zones found in many video
systems. This consideration is important because any
signal appearing around this frequency can appear in
the baseband as a result of aliasing effects of an
ADC found in a receiver.
Keep in mind that images do not stop at 27-MHz;
they continue around the sampling frequencies of
54-MHz, 81-MHz, 108-MHz, etc. Because of these
multiple images that an ADC can fold down into the
baseband signal, the low-pass filter must also
eliminate these higher-order images. The THS7374
has 60-dB attenuation at 54-MHz, 55-dB attenuation
at 81-MHz, and 50-dB attenuation at 108-MHz.
Attenuation above 108-MHz is at least 45-dB, which
makes sure that images do not affect the desired
video baseband signal.
The 9.5-MHz filter frequency was chosen to account
for process variations in the THS7374. To ensure that
the required video frequencies are effectively passed,
the filter corner frequency must be high enough to
allow component variations. The other consideration
is the attenuation must be large enough to ensure the
anti-aliasing/reconstruction filtering is enough to meet
the system demands. Thus, the filter frequencies
were not arbitrarily selected and are a good
compromise that should meet the demands of most
systems.
Benefits Over Passive Filtering
Two key benefits of using an integrated filter system,
such as the THS7374, over a passive system is PCB
area and filter variations. The small TSSOP-14
package for four video channels is much smaller over
a passive RLC network, especially a six-pole passive
network. Additionally, consider that inductors have at
best ±10% tolerances (normally ±15% to ±20% are
common) and capacitors typically have ±10%
tolerances. Using a Monte Carlo analysis shows that
the filter corner frequency (–3 dB), flatness (–1 dB), Q
factor (or peaking), and channel-to-channel delay
have wide variations. This approach can lead to
potential performance and quality issues in
mass-production environments. The THS7374 solves
most of these problems with only the corner
frequency being essentially the only variable.
Another concern about passive filters is the use of
inductors. Inductors are magnetic components and
are therefore susceptible to electromagnetic
coupling/interference (EMC/EMI). Some common
coupling can occur because of other nearby video
channels that use inductors for filtering, or it can
come from nearby switch-mode power supplies.
Some other forms of coupling could be from outside
sources with strong EMI radiation which can cause
failure in EMC testing such as required for CE
compliance.
One concern about an active filter in an integrated
circuit is the variation of the filter characteristics when
the ambient temperature and the subsequent die
temperature changes. To minimize temperature
effects, the THS7374 uses low temperature
coefficient
resistors
and
high
quality—low
temperature coefficient capacitors found in the
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BiCom3X process. The filters have been specified by
design to account for process variations and
temperature variations to maintain proper filter
characteristics. This architecture maintains a low
channel-to-channel time delay, which is required for
proper video signal performance.
Another benefit of the THS7374 over a passive RLC
filter is the input and output impedance. The input
impedance presented to the DAC vary significantly,
from 35-Ω to over 1.5-kΩ, with a passive network and
may cause voltage variations over frequency. The
THS7374 input impedance is 800-kΩ and only the
2-pF input capacitance plus the PCB trace
capacitance impacting the input impedance. As such,
the voltage variation appearing at the DAC output is
better controlled with a fixed termination resistor and
the high input impedance buffer of the THS7374.
On the output side of the filter, a passive filter also
has a large impedance variation over frequency,
again from 35-Ω to over 1.5-kΩ. The THS7374 is an
operational amplifier which approximates an ideal
voltage source. A voltage source is desirable
because the output impedance is very low and can
source and sink current. To properly match the
transmission line characteristic impedance of a video
line, a 75-Ω series resistor is placed on the output. To
minimize reflections and to maintain a good return
loss, this output resistor must maintain a 75-Ω
28
impedance. A passive filter impedance variation
cannot ensure this while the THS7374 has about
0.7-Ω of output impedance at 5-MHz. Thus, the
system is matched much better with a THS7374
compared to a passive filter.
One final advantage of the THS7374 over a passive
filter is power dissipation. A DAC driving a video line
must be able to drive a 37.5-Ω load—the receiver
75-Ω resistor and the 75-Ω source impedance
matching resistor next to the DAC to maintain the
source impedance requirement. This approach forces
the DAC to drive at least 1.25 VP (100% saturation
CVBS)/37.5 Ω = 33.3 mA. A DAC is a current
steering element and this amount of current flows
internally to the DAC even if the output is 0-V. Thus,
power dissipation in the DAC may be very high,
especially when four channels are being driven. With
a high input impedance and the capability to drive up
to two video lines, utilizing the THS7374 can reduce
the DAC power dissipation significantly. This occurs
because the resistance the DAC is driving can be
substantially increased. It is common to set this in a
DAC by a current setting resistor on the DAC. Thus,
the resistance can be 300-Ω or more, substantially
reducing the current drive demands from the DAC
and saving a substantial amount of power. For
example, a 3.3-V four-channel DAC dissipates 440
mW just for the steering current capability (four
channels × 33.3 mA × 3.3 V) if it needs to drive
37.5-Ω load. With a 300-Ω load, the DAC power
dissipation as a result of current steering current
would only be 55 mW (four channels × 4.16 mA ×
3.3 V).
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EVALUATION MODULE
To evaluate the THS7374, an evaluation module
(EVM) is available. The EVM allows for testing the
THS7374 in many different configuration. Inputs and
outputs include BNC connectors commonly found in
video systems along with 75-Ω input termination
resistors, 75-Ω series source termination resistors,
and 75-Ω characteristic impedance traces. Several
unpopulated component pads are found on the EVM
to allow for different input and output configurations
as dictated by the user. This EVM is designed to be
used with single supply from 2.85 V up to 5 V.
The EVM default input configuration sets all channels
for dc input coupling. The input signal must be within
0 V to about 1.4 V for proper operation. Failure to be
within this range will saturate and/or clip the output
signal. If the input range is beyond this, or if the
signal voltage is unknown, or coming from a current
sink DAC, then ac input configuration is desired. This
is easily accomplished with the EVM by simply
replacing Z1, Z2, Z3, and Z4 0-Ω resistors with
0.1-mF capacitors.
For ac-coupled input and sync-tip clamp (STC)
functionality commonly used for CVBS, s-video Y',
component Y' signals, and R'G'B' signals with
embedded sync, then no other changes are needed.
However, if a bias voltage is needed after the input
capacitor which is commonly needed for s-video C',
component P'B and P'R, and non-sync embedded
R'G'B' signals, then a pull-up resistor should be
added to the signal on the EVM. This is easily done
by simply adding a resistor to any of the following
resistor pads; RX1, RX3, RX5, or RX7. A common
value to use is 3.3-MΩ. Note that even signals with
embedded sync can also use bias mode if desired.
The EVM default output configuration sets all
channels for ac output coupling. The 470-mF and
0.1-mF capacitors work well for most ac-coupled
systems. However, if dc coupled output is desired,
then replacing the 0.1-mF capacitors—C12, C14, C16,
and C17—with 0-Ω resistors works well. Removing
the 470-mF capacitors is optional, but removing them
from the EVM will eliminate a few picofarads of stray
capacitance on each signal path which may be
desirable.
The THS7374 incorporates an easy method to
configure the bypass mode and the disable mode.
The use of JP1 controls the disable feature while JP4
controls the bypass feature. While there is a space on
the EVM for JP2 and JP3, these are not utilized for
the THS7374. Connection of JP1 to GND applies 0 V
to the disable pin and the THS7374 operates
normally. Moving JP1 to +VS causes the THS7374 to
be in disable mode. Connection of JP4 to GND
places the THS7374 in filter mode while moving JP4
to +VS places the THS7374 in bypass mode.
Figure 64 shows the THS7374EVM schematic.
Figure 65 and Figure 66 illustrate the two layers of
the EVM PCB, incorporating standard high-speed
layout practices. Table 2 lists the bill of materials as
supplied from Texas Instruments.
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Figure 64. THS7374 EVM Schematic
30
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Figure 65. THS7374 EVM PCB Top Layer
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Figure 66. THS7374 EVM PCB Bottom Layer
32
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
THS7374EVM Bill of Materials
Table 2. THS7374 EVM
ITEM
REF DES
QTY
DESCRIPTION
1
FB1
1
Bead, Ferrite, 2.5 A, 330 Ω
SMD SIZE
0805
MANUFACTURER
PART NUMBER
DISTRIBUTOR
PART NUMBER
(TDK) MPZ2012S331A
(Digi-Key) 445-1569-1-ND
(AVX) TPSC107K010R0100
(Digi-Key) 478-1765-1-ND
2
C24
1
Capacitor, 100 mF, Tantalum, 10 V, 10%,
Low-ESR
3
C1–C4,
C7–C10, C19,
C20–C22
12
Open
0805
4
C5
1
Capacitor, 0.01 mF, Ceramic, 100 V, X7R
0805
(AVX) 08051C103KAT2A
(Digi-Key) 478-1358-1-ND
5
C12, C14, C16,
C17, C23, C25,
C26
7
Capacitor, 0.1 mF, Ceramic, 50 V, X7R
0805
(AVX) 08055C104KAT2A
(Digi-Key) 478-1395-1-ND
6
C6
1
Capacitor, 1 mF, Ceramic, 16 V, X7R
0805
(TDK) C2012X7R1C105K
(Digi-Key) 445-1358-1-ND
7
C11, C13, C15,
C18
4
Capacitor, Aluminum, 470 mF, 10 V, 20%
(Cornell) AFK477M10F24B-F
(Newark) 66K0965
8
RX1–RX8
8
Open
0603
9
R6, R7, R14,
R15
4
Open
0805
10
Z1–Z4
4
Resistor, 0 Ω
0805
(ROHM) MCR10EZHJ000
(Digi-Key) RHM0.0ACT-ND
11
R1–R4,
R9–R12
8
Resistor, 75 Ω, 1/8 W, 1%
0805
(ROHM) MCR10EZHF75.0
(Digi-Key)
RHM75.0CCT-ND
12
R17
1
Resistor, 100 Ω, 1/8 W, 1%
0805
(ROHM) MCR10EZHF1000
(Digi-Key)
RHM100CCT-ND
13
R13, R16
2
Resistor, 1 kΩ, 1/8 W, 1%
0805
(ROHM) MCR10EZHF1001
(Digi-Key)
RHM1.00KCCT-ND
14
R5, R8
2
Resistor, 100 kΩ, 1/8 W, 1%
0805
(ROHM) MCR10EZHF1003
(Digi-Key)
RHM100KCCT-ND
15
J9, J10
2
Jack, Banana Receptance, 0.25" dia. hole
(SPC) 813
(Newark) 39N867
16
J1–J8
8
Connector, BNC, Jack, 75 Ω
(Amphenol) 31-5329-72RFX
(Newark) 93F7554
17
TP5, TP6
2
Test Point, Black
(Keystone) 5001
(Digi-Key) 5001K-ND
18
JP2, JP3
2
Open
3 possible
19
JP1, JP4
2
Header, 0.1" CTRS, 0.025" sq. pins
3 possible
(Sullins) PBC36SAAN
(Digi-Key) S1011E-36-ND
20
JP1, JP4
2
Shunts
(Sullins) SSC02SYAN
(Digi-Key) S9002-ND
21
U1
1
IC, THS7374
22
4
Standoff, 4-40 HEX, 0.625" length
(Keystone) 1808
(Digi-Key) 1808K-ND
23
4
Screw, Phillips, 4-40, 0.250"
(BF) PMS 440 0031 PH
(Digi-Key) H343-ND
24
1
Printed Circuit Board
(TI) Edge# 6497066 Rev. B
C
F
PW
(TI) THS7374IPW
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THS7374
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or
safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 2.85 V to 5.5 V single supply and the output voltage range of 0 V to 5.5
V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +85°C. The EVM is designed to operate
properly with certain components above +85°C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
34
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SLOS590B – JULY 2008 – REVISED JANUARY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2010) to Revision B
Page
•
Deleted Lead temperature parameter from Absolute Maximum Ratings table .................................................................... 2
•
Added ESD ratings to Absolute Maximum Ratings table ..................................................................................................... 2
Changes from Original (July 2008) to Revision A
Page
•
Added Figure 9, Figure 10, Figure 11 to the Typical Characteristics: General .................................................................... 9
•
Added Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, Figure 33 to the
Typical Characteristics: VS+ = 3.3 V .................................................................................................................................... 11
•
Added Figure 47, Figure 48, Figure 49, Figure 50, Figure 51, Figure 52, Figure 53, Figure 54, Figure 55 to the
Typical Characteristics: VS+ = 5 V ....................................................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS7374IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS7374
THS7374IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS7374
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS7374IPWR
Package Package Pins
Type Drawing
TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS7374IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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