Texas Instruments | Universal Active Filter (Rev. B) | Datasheet | Texas Instruments Universal Active Filter (Rev. B) Datasheet

Texas Instruments Universal Active Filter (Rev. B) Datasheet
UAF42
UA
F4
2
UA
F4
2
www.ti.com
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
UNIVERSAL ACTIVE FILTER
Check for Samples: UAF42
FEATURES
DESCRIPTION
•
The UAF42 is a universal active filter that can be
configured for a wide range of low-pass, high-pass,
and band-pass filters. It uses a classic state-variable
analog architecture with an inverting amplifier and two
integrators. The integrators include on-chip 1000pF
capacitors trimmed to 0.5%. This architecture solves
one of the most difficult problems of active filter
design—obtaining tight tolerance, low-loss capacitors.
1
2
•
•
VERSATILE:
– Low-Pass, High-Pass
– Band-Pass, Band-Reject
SIMPLE DESIGN PROCEDURE
ACCURATE FREQUENCY AND Q:
– Includes On-Chip 1000pF ±0.5% Capacitors
APPLICATIONS
•
•
•
•
•
A DOS-compatible filter design program allows easy
implementation of many filter types, such as
Butterworth, Bessel, and Chebyshev. A fourth,
uncommitted FET-input op amp (identical to the other
three) can be used to form additional stages, or for
special filters such as band-reject and Inverse
Chebyshev.
TEST EQUIPMENT
COMMUNICATIONS EQUIPMENT
MEDICAL INSTRUMENTATION
DATA ACQUISITION SYSTEMS
MONOLITHIC REPLACEMENT FOR UAF41
The classical topology of the UAF42 forms a
time-continuous filter, free from the anomalies and
switching noise associated with switched-capacitor
filter types.
The UAF42 is available in 14-pin plastic DIP and
SOIC-16 surface-mount packages, specified for the
–25°C to +85°C temperature range.
blank
blank
blank
blank
High-Pass
Out
Band-Pass
Out
Low-Pass
Out
R
R
1000pF
(1)
1000pF
(1)
V+
In1
In2
R
R
V-
In3
R = 50kW ±0.5%
GND
NOTE: (1) ±0.5%.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1992–2010, Texas Instruments Incorporated
UAF42
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range unless otherwise noted.
Power Supply Voltage
Input Voltage
UAF42
UNIT
±18
V
±VS ±0.7
Output Short-Circuit
V
Continuous
Operating Temperature
–40 to +85
°C
Storage Temperature
–40 to +125
°C
Junction Temperature
+125
°C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended period may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
PDIP-14
N
UAF42AP
SOIC-16
DW
UAF42AU
UAF42AP
UAF42APG4
UAF42AU
UAF42AUE4
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
PIN CONFIGURATIONS
P PACKAGE
PDIP-14
(TOP VIEW)
U PACKAGE
SOIC-16
(TOP VIEW)
Low-Pass VO
1
14 Frequency Adj2
VIN3
2
13 High-Pass VO
VIN2
3
12 VIN1
Auxiliary Op Amp, +In
4
11 Ground
Auxiliary Op Amp, -In
5
10 V+
Auxiliary Op Amp, VO
6
9
V-
Bandpass VO
7
8
Frequency Adj1
1
16 Frequency Adj2
2
15
VIN3
3
14 High-Pass VO
VIN2
4
13 VIN1
Auxiliary Op Amp, +In
5
12 Ground
Auxiliary Op Amp, -In
6
11 V+
Auxiliary Op Amp, VO
7
10 V-
Bandpass VO
8
9
Low-Pass VO
NC
(1)
NC
(1)
Frequency Adj1
NOTE: (1) NC = no connection. For best
performance connect all NC pins to ground
to minimize inter-lead capacitance.
2
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Copyright © 1992–2010, Texas Instruments Incorporated
Product Folder Link(s): UAF42
UAF42
www.ti.com
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
ELECTRICAL CHARACTERISTICS
At TA = +25°C, and VS = ±15V, unless otherwise noted.
UAF42AP, AU
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
FILTER PERFORMANCE
Frequency Range, fn
Frequency Accuracy
0 to 100
f = 1kHz
kHz
1
vs Temperature
0.01
%
%/°C
Maximum Q
400
—
Maximum (Q • Frequency) Product
500
kHz
0.01
%/°C
(fO • Q) < 10
0.025
%/°C
(fO • Q) < 105
2
Q vs Temperature
(fO • Q) < 104
5
Q Repeatability
Offset Voltage, Low-Pass Output
Resistor Accuracy
%
±5
mV
0.5
1
%
±0.5
±5
OFFSET VOLTAGE (1)
Input Offset Voltage
vs Temperature
vs Power Supply
VS = ±6V to ±18V
80
mV
±3
mV/°C
96
dB
INPUT BIAS CURRENT (1)
Input Bias Current
VCM = 0V
10
Input Offset Current
VCM = 0V
5
50
pA
pA
Noise Density: f = 10Hz
25
nV/√Hz
Noise Density: f = 10kHz
10
nV/√Hz
Voltage Noise: BW = 0.1Hz to 10Hz
2
mVPP
2
fA/√Hz
NOISE
Input Voltage Noise
Input Bias Current Noise
Noise Density: f = 10kHz
INPUT VOLTAGE RANGE (1)
Common-Mode Input Range
Common-Mode Rejection
VCM = ±10V
80
±11.5
V
96
dB
1013|| 2
Ω || pF
13
10 || 6
Ω || pF
126
dB
INPUT IMPEDANCE (1)
Differential
Common-Mode
OPEN-LOOP GAIN (1)
Open-Loop Voltage Gain
VO = ±10V, RL= 2kΩ
90
FREQUENCY RESPONSE
Slew Rate
10
V/ms
Gain-Bandwidth Product
G = +1
4
MHz
Total Harmonic Distortion
G = +1, f = 1kHz
0.1
%
OUTPUT (1)
Voltage Output
RL = 2kΩ
Short Circuit Current
(1)
±11
±11.5
V
±25
mA
Specifications apply to uncommitted op amp, A4. The three op amps forming the filter are identical to A4 but are tested as a complete
filter.
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Copyright © 1992–2010, Texas Instruments Incorporated
Product Folder Link(s): UAF42
3
UAF42
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
UAF42AP, AU
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Specified Operating Voltage
±15
Operating Voltage Range
±6
Current
±6
V
±18
V
±7
mA
TEMPERATURE RANGE
Specified
–25
+85
°C
Operating
–25
+85
°C
Storage
–40
+125
Thermal Resistance, q JA
4
100
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°C
°C/W
Copyright © 1992–2010, Texas Instruments Incorporated
Product Folder Link(s): UAF42
UAF42
www.ti.com
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
APPLICATION INFORMATION
The UAF42 is a monolithic implementation of the
proven state-variable analog filter topology. This
device is pin-compatible with the popular UAF41
analog filter, and it provides several improvements.
The slew rate of the UAF42 has been increased to
10V/ms,
versus
1.6V/ms
for
the
UAF41.
Frequency • Q product of the UAF42 has been
improved, and the useful natural frequency extended
by a factor of four to 100kHz. FET input op amps on
the UAF42 provide very low input bias current. The
monolithic construction of the UAF42 provides lower
cost and improved reliability.
DESIGN PROGRAM
Application report SBFA002 (available for download
at www.ti.com) and a computer-aided design program
also available from Texas Instruments, make it easy
to design and implement many kinds of active filters.
The DOS-compatible program guides you through the
design process and automatically calculates
component values.
Low-pass, high-pass, band-pass and band-reject
(notch) filters can be designed. The program supports
the three most commonly-used all-pole filter types:
Butterworth, Chebyshev and Bessel. The less-familiar
inverse Chebyshev is also supported, providing a
smooth passband response with ripple in the stop
band.
With each data entry, the program automatically
calculates and displays filter performance. This
feature allows a spreadsheet-like what-if design
approach. For example, a user can quickly determine,
by trial and error, how many poles are required for a
desired attenuation in the stopband. Gain/phase plots
may be viewed for any response type.
The basic building element of the most
commonly-used filter types is the second-order
section. This section provides a complex-conjugate
pair of poles. The natural frequency, wn, and Q of the
pole pair determine the characteristic response of the
section. The low-pass transfer function is shown in
Equation 1:
VO(s)
ALPwn2
= 2
VI(s)
s + s wn/Q + wn2
(1)
The high-pass transfer
Equation 2:
VHP(s)
AHPs2
= 2
VI(s) s + s wn/Q + wn2
function
is
given
by
(2)
The band-pass transfer function is calculated using
Equation 3:
VBP(s)
A (w /Q) s
= 2 BP n
VI(s) s + s wn/Q + wn2
(3)
A band-reject response is obtained by summing the
low-pass and high-pass outputs, yielding the transfer
function shown in Equation 4:
VBR(s)
A (s2 + wn2)
= 2 BR
VI(s) s + s wn/Q + wn2
(4)
The most common filter types are formed with one or
more cascaded second-order sections. Each section
is designed for wn and Q according to the filter type
(Butterworth, Bessel, Chebyshev, etc.) and cutoff
frequency. While tabulated data can be found in
virtually any filter design text, the design program
eliminates this tedious procedure.
Second-order sections may be noninverting
(Figure 1) or inverting (Figure 2). Design equations
for these two basic configurations are shown for
reference. The design program solves these
equations, providing complete results, including
component values.
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Product Folder Link(s): UAF42
5
UAF42
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
www.ti.com
HP Out
BP Out
RF1
12
13
LP Out
RF2
8
7
1
14
R1
50kW
R2
50kW
2
C1
C2
1000pF
1000pF
50kW
RG
VIN
A1
3
A2
A3
R4
50kW
RQ
UAF42
11
Note: If RG = 50kW, the external gain-setting
resistor can be eliminated by connecting VIN to pin 2.
Pin numbers are for DIP
package. SOIC-16 pinout
is different.
Design Equations
1.
2
wn =
1+
R2
4.
R1 RF1 RF2 C1 C2
ALP =
RG
1+
2.
R4 (RG + RQ)
RG RQ
Q=
1+
R1
R2
1
1
1
+
+
RG RQ R 4
1/2
R2 RF1 C1
R2
R1 RF2 C2
5.
R1
AHP =
R2
R1
1+
ALP =
RG
R2
R1
1
1
1
+
+
RG RQ R 4
1/2
3.
QALP = QAHP
R1
R2
= ABP
R1 RF1 C1
R2 RF2 C2
6.
ABP =
R4
RG
Figure 1. Noninverting Pole-Pair
6
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Copyright © 1992–2010, Texas Instruments Incorporated
Product Folder Link(s): UAF42
UAF42
www.ti.com
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
HP Out
BP Out
RF1
RG
LP Out
RF2
VIN
13
12
8
7
14
1
R1
50kW
R2
50kW
2
C1
C2
1000pF
1000pF
50kW
A1
3
A2
A3
R4
50kW
RQ
11
Note: If RQ = 50kW, the external Q-setting resistor
can be eliminated by connecting pin 2 to ground.
Pin numbers are for DIP
package. SOIC-16 pinout
is different.
Design Equations
1.
R2
2
wn =
R1 RF1 RF2 C1 C2
R1
4.
ALP =
5.
AHP =
6.
ABP = 1 +
RG
1/2
2.
Q= 1 +
R4
RQ
RF1 C1
1
1
1
1
+
+
R 1 R 2 RG
R1 R2 RF2 C2
R2
R1
ALP =
R2
RG
1/2
3.
QALP = QAHP
R1
R2
= ABP
R1 RF1 C1
R2 RF2 C2
R4
1
RQ
RG
1
1
1
+
+
R 1 R 2 RG
Figure 2. Inverting Pole-Pair
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Product Folder Link(s): UAF42
7
UAF42
SBFS002B – JULY 1992 – REVISED OCTOBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November, 2007) to Revision B
•
8
Page
Corrected package marking information shown in Ordering Information table .................................................................... 2
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Copyright © 1992–2010, Texas Instruments Incorporated
Product Folder Link(s): UAF42
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UAF42AP
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UAF42AP
UAF42AU
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
UAF42AU
UAF42AUE4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
UAF42AU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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