Texas Instruments | Dual, Wideband, Voltage-Feedback Operational Amplifier with Disable (Rev. G) | Datasheet | Texas Instruments Dual, Wideband, Voltage-Feedback Operational Amplifier with Disable (Rev. G) Datasheet

Texas Instruments Dual, Wideband, Voltage-Feedback Operational Amplifier with Disable (Rev. G) Datasheet
OPA2690
www.ti.com
SBOS238G – JUNE 2002 – REVISED MARCH 2010
Dual, Wideband, Voltage-Feedback
OPERATIONAL AMPLIFIER with Disable
Check for Samples: OPA2690
FEATURES
DESCRIPTION
•
The OPA2690 represents a major step forward in
unity-gain stable, voltage-feedback op amps. A new
internal architecture provides slew rate and full-power
bandwidth previously found only in wideband,
current-feedback op amps. A new output stage
architecture delivers high currents with a minimal
headroom requirement. These give exceptional
single-supply operation. Using a single +5V supply,
the OPA2690 can deliver a 1V to 4V output swing
with over 120mA drive current and 150MHz
bandwidth. This combination of features makes the
OPA2690 an ideal RGB line driver or single-supply
Analog-to-Digital Converter (ADC) input driver.
1
2
•
•
•
•
•
•
FLEXIBLE SUPPLY RANGE:
+5V to +12V Single Supply
±2.5V to ±6V Dual Supply
WIDEBAND +5V OPERATION: 220MHz (G = 2)
HIGH OUTPUT CURRENT: 190mA
OUTPUT VOLTAGE SWING: ±4.0V
HIGH SLEW RATE: 1800V/ms
LOW SUPPLY CURRENT: 5.5mA/ch
LOW DISABLE CURRENT: 100mA/ch
APPLICATIONS
•
•
•
•
•
•
•
VIDEO LINE DRIVING
xDSL LINE DRIVER/RECEIVER
HIGH-SPEED IMAGING CHANNELS
ADC BUFFERS
PORTABLE INSTRUMENTS
TRANSIMPEDANCE AMPLIFIERS
ACTIVE FILTERS
Single-Supply Differential ADC Driver
+5V
100W
The low 5.5mA/ch supply current of the OPA2690 is
precisely trimmed at +25°C. This trim, along with low
temperature drift, provides lower maximum supply
current than competing products. System power may
be reduced further using the optional disable control
pin. Leaving this disable pin open, or holding it HIGH,
will operate the OPA2690I-14D normally. If pulled
LOW, the OPA2690I-14D supply current drops to less
than 200mA/ch while the output goes to a
high-impedance state.
2kW
OPA2690 RELATED PRODUCTS
+2.5V
+2.5V
0.1mF +5V
100pF
1/2
OPA2690
2kW
REFB
499W
REFT
0.1mF
499W
1kW
35W
SINGLES
DUALS
TRIPLES
Voltage-Feedback
OPA690
OPA2690
OPA3690
Current-Feedback
OPA691
OPA2691
OPA3691
Fixed Gain
OPA692
—
OPA3692
IN
10pF
10-Bit
40MSPS
35W
499W
HARMONIC DISTORTION vs FREQUENCY
FOR THE SINGLE-SUPPLY ADC DRIVER
ADS825
2.5VCM
2VPP
VIN
-50
10pF
1/2
OPA2690
+2.5V
499W
Clock
Harmonic Distortion (dBc)
1kW
2VPP Differential Output
-55
IN
-60
-65
-70
-75
-80
3rd-Harmonic
-85
-90
2nd-Harmonic
-95
-100
1
10
20
Frequency (MHz)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
OPA2690
SBOS238G – JUNE 2002 – REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA2690
SO-8
D
–40°C to +85°C
OPA2690
OPA2690
SO-14
D
–40°C to +85°C
OPA2690
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA2690ID
Rails, 100
OPA2690IDR
Tape and Reel, 2500
OPA2690I-14D
Rails, 58
OPA2690I-14DR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
OPA2690
UNIT
±6.5
VDC
Power Supply
Internal Power Dissipation
See Thermal Analysis section
Differential Input Voltage
±1.2
Input Voltage Range
±VS
V
–65 to +125
°C
Storage Temperature Range: D
Junction Temperature (TJ)
ESD Ratings
(1)
V
+150
°C
Human Body Model (HBM)
2000
V
Charge Device Model (CDM)
1500
V
Machine Model (MM)
200
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
D PACKAGE
SO-8
(TOP VIEW)
Out A
-In A
1
2
+In A
3
-VS
4
A
B
D PACKAGE
SO-14
(TOP VIEW)
8
+VS
7
Out B
6
-In B
5
+In B
2
-In A
1
14 Out A
+In A
2
13 NC
DIS A
3
12 NC
-VS
4
11 +VS
DIS B
5
10 NC
+In B
6
9
NC
-In B
7
8
Out B
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
www.ti.com
SBOS238G – JUNE 2002 – REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 36 for ac performance only), unless otherwise noted.
OPA2690ID, I-14D
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
+25°C (2)
0°C to
+70°C (3)
-40°C to
+85°C (3)
220
165
160
150
G = +10, VO = 0.5VPP
30
20
19
G ≥ 10
300
200
190
G = +2, VO < 0.5VPP
30
TEST CONDITIONS
+25°C
G = +1, VO = 0.5VPP, RF = 25Ω
500
G = +2, VO = 0.5VPP
MIN/
MAX
TEST
LEVELS (1)
MHz
typ
C
MHz
min
B
18
MHz
min
B
180
MHz
min
B
MHz
typ
C
UNIT
AC PERFORMANCE (see Figure 36)
Small-Signal Bandwidth
Gain Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
VO < 0.5VPP
4
dB
typ
C
Large-Signal Bandwidth
G = +2, VO < 5VPP
200
MHz
typ
C
G = +2, 4V Step
1800
V/ms
min
B
G = +2, VO = 0.5V Step
1.4
ns
typ
C
Slew Rate
Rise-and-Fall Time
1400
1200
900
G = +2, VO = 5V Step
2.8
ns
typ
C
Settling Time to 0.02%
G = +2, VO = 5V Step
12
ns
typ
C
Settling Time to 0.1%
G = +2, VO = 5V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, VO = 2VPP
xx x 2nd-Harmonic
RL = 100Ω
–68
–64
–62
–60
dBc
max
B
RL ≥ 500Ω
–77
–70
–68
–66
dBc
max
B
RL = 100Ω
–70
–68
–66
–64
dBc
max
B
RL ≥ 500Ω
–81
–78
–76
–75
dBc
max
B
f > 1MHz
5.5
nV/√Hz
typ
C
xx x 3rd-Harmonic
Input Voltage Noise
Input Current Noise
f > 1MHz
3.1
pA/√Hz
typ
C
Differential Gain
G = +2, NTSC, VO = 1.4VP, RL = 150Ω
0.06
%
typ
C
Differential Phase
G = +2, NTSC, VO = 1.4VP, RL = 150Ω
0.03
deg
typ
C
f = 5MHz, Input-Referred
–85
dBc
typ
C
Channel-to-Channel Crosstalk
DC PERFORMANCE (4)
Open-Loop Voltage Gain (AOL)
VO = 0V, RL = 100Ω
69
58
56
54
dB
min
A
Input Offset Voltage
VCM = 0V
±1.0
±4.5
±5.0
±5.2
mV
max
A
xxx Average Offset Voltage Drift
VCM = 0V
±12
±12
mV/°C
max
B
Input Bias Current
VCM = 0V
±12
±13
mA
max
A
xxx Average Bias Current Drift (magnitude)
VCM = 0V
±20
±40
nA/°C
max
B
Input Offset Current
VCM = 0V
±1.4
±1.6
mA
max
A
xxx Average Offset Current Drift
VCM = 0V
±1.0
±1.5
nA/°C
max
B
+5
±0.1
±11
±1.0
INPUT
Common-Mode Input Range (CMIR) (5)
±3.5
±3.4
±3.3
±3.2
V
min
A
VCM = ±1V
65
60
57
56
dB
min
A
xxx Differential Mode
VCM = 0V
190 || 0.6
kΩ || pF
typ
C
xxx Common-Mode
VCM = 0V
3.2 || 0.9
MΩ || pF
typ
C
Common-Mode Rejection Ratio (CMRR)
Input Impedance
(1)
(2)
(3)
(4)
(5)
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over
temperature specifications.
Current is considered positive out of node. VCM is the input common-mode voltage.
Tested < 3dB below minimum specified CMRR at ±CMIR limits.
3
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
SBOS238G – JUNE 2002 – REVISED MARCH 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C.
At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 36 for ac performance only), unless otherwise noted.
OPA2690ID, I-14D
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
+25°C
+25°C (2)
0°C to
+70°C (3)
-40°C to
+85°C (3)
UNIT
MIN/
MAX
TEST
LEVELS (1)
OUTPUT
Voltage Output Swing
No Load
±4.0
±3.8
±3.7
±3.6
V
min
A
100Ω Load
±3.9
±3.7
±3.6
±3.3
V
min
A
Current Output, Sourcing
VO = 0V
+190
+160
+140
+100
mA
min
A
Current Output, Sinking
VO = 0V
–190
–160
–140
–100
mA
min
A
Short-Circuit Current
VO = 0V
±250
mA
typ
C
G = +2, f = 100kHz
0.04
Ω
typ
C
mA
max
A
ns
typ
C
Closed-Loop Output Impedance
DISABLE (SO-14 Only)
Power-Down Supply Current (+VS)
Disabled LOW
VDIS = 0V, Both Channels
–200
VIN = 1VDC
200
Enable Time
VIN = 1VDC
25
ns
typ
C
Off Isolation
G = +2, RL = 150Ω, VIN = 0V
70
dB
typ
C
Output Capacitance in Disable
G = +2, RL = 150Ω, VIN = 0V
4
pF
typ
C
Turn-On Glitch
±50
mV
typ
C
Turn-Off Glitch
±20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
75
130
150
160
mA
max
A
V
typ
C
±6.0
±6.0
±6.0
V
max
A
Disable Time
Control Pin Input BIas Current (VDIS)
VDIS = 0V, Each Channel
–400
–480
–520
POWER SUPPLY
Specified Operating Voltage
±5
Maximum Operating Voltage Range
Maximum Quiescent Current (2 Channels)
VS = ±5V
11
11.6
12.4
13.2
mA
max
A
Minimum Quiescent Current (2 Channels)
VS = ±5V
11
10.6
9.2
8.6
mA
min
A
Input-Referred
75
68
66
64
dB
min
A
–40 to +85
°C
typ
C
xx x D xxx SO-8
125
°C/W
typ
C
xx x D xxx SO-14
100
°C/W
typ
C
Power-Supply Rejection Ratio (+PSRR)
THERMAL CHARACTERISTICS
Specified Operating Range: D
Thermal Resistance, qJA
Junction-to-Ambient
4
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
www.ti.com
SBOS238G – JUNE 2002 – REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At RF = 402Ω, RL = 100Ω to VS/2, and G = +2 (see Figure 37 for ac performance only), unless otherwise noted.
OPA2690ID, I-14D
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
+25°C (2)
0°C to
+70°C (3)
-40°C to
+85°C (3)
190
150
145
140
G = +10, VO < 0.5VPP
25
18
17
G ≥ 10
250
180
170
G = +2, VO < 0.5VPP
20
TEST CONDITIONS
+25°C
G = +1, VO = 0.5VPP, RF = ±25Ω
400
G = +2, VO < 0.5VPP
MIN/
MAX
TEST
LEVELS (1)
MHz
typ
C
MHz
min
B
16
MHz
min
B
160
MHz
min
B
MHz
typ
C
UNIT
AC PERFORMANCE (see Figure 37)
Small-Signal Bandwidth
Gain Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
VO < 0.5VPP
5
dB
typ
C
Large-Signal Bandwidth
G = +2, VO = 2VPP
220
MHz
typ
C
G = +2, 2V Step
1000
V/ms
min
B
G = +2, VO = 0.5V Step
1.6
ns
typ
C
Slew Rate
Rise-and-Fall Time
700
670
550
G = +2, VO = 2V Step
2.0
ns
typ
C
Settling Time to 0.02%
G = +2, VO = 2V Step
12
ns
typ
C
Settling Time to 0.1%
G = +2, VO = 2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, VO = 2VPP
xx x 2nd-Harmonic
RL = 100Ω to VS/2
–65
–60
–59
–56
dBc
max
B
RL ≥ 500Ω to VS/2
–75
–70
–68
–66
dBc
max
B
RL = 100Ω to VS/2
–68
–64
–62
–60
dBc
max
B
RL ≥ 500Ω to VS/2
–77
–73
–71
–70
dBc
max
B
f > 1MHz
5.6
nV/√Hz
typ
C
xx x 3rd-Harmonic
Input Voltage Noise
Input Current Noise
f > 1MHz
3.2
pA/√Hz
typ
C
Differential Gain
G = +2, NTSC, VO = 1.4VP, RL = 150Ω to
VS/2
0.06
%
typ
C
Differential Phase
G = +2, NTSC, VO = 1.4VP, RL = 150Ω to
VS/2
0.02
deg
typ
C
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (AOL)
VO = 2.5V, RL = 100Ω to VS/2
63
56
54
52
dB
min
A
Input Offset Voltage
VCM = 2.5V
±1.0
±4.5
±4.8
±5.2
mV
max
A
xxx Average Offset Voltage Drift
VCM = 2.5V
±10
±10
mV/°C
max
B
Input Bias Current
VCM = 2.5V
±12
±13
mA
max
A
xxx Average Bias Current Drift (magnitude)
VCM = 2.5V
±20
±40
nA/°C
max
B
Input Offset Current
VCM = 2.5V
±1.4
±1.6
mA
max
A
xxx Average Offset Current Drift
VCM = 2.5V
±7
±9
nA/°C
max
B
+5
±0.3
±11
±1.0
INPUT
Least Positive Input Voltage (5)
1.5
1.6
1.7
1.8
V
max
A
Most Positive Input Voltage (5)
3.5
3.4
3.3
3.2
V
min
A
63
58
56
54
dB
min
A
Common-Mode Rejection Ratio (CMRR)
VCM = 2.5V ± 0.5V
Input Impedance
xxx Differential Mode
VCM = 2.5V
92 || 1.4
kΩ || pF
typ
C
xxx Common-Mode
VCM = 2.5V
2.2 || 1.5
MΩ || pF
typ
C
(1)
(2)
(3)
(4)
(5)
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over
temperature specifications.
Current is considered positive out of node. VCM is the input common-mode voltage.
Tested < 3dB below minimum specified CMRR at ±CMIR limits.
5
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
SBOS238G – JUNE 2002 – REVISED MARCH 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At RF = 402Ω, RL = 100Ω to VS/2, and G = +2 (see Figure 37 for ac performance only), unless otherwise noted.
OPA2690ID, I-14D
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
+25°C
+25°C (2)
0°C to
+70°C (3)
-40°C to
+85°C (3)
UNIT
MIN/
MAX
TEST
LEVELS (1)
OUTPUT
Most Positive Output Voltage
No Load
4
3.8
3.6
3.5
V
min
A
RL = 100Ω to 2.5V
3.9
3.7
3.5
3.4
V
min
A
No Load
1
1.2
1.4
1.5
V
max
A
RL = 100Ω to 2.5V
1.1
1.3
1.5
1.7
V
max
A
Current Output, Sourcing
+160
+120
+100
+80
mA
min
A
Current Output, Sinking
–160
–120
–100
–80
mA
min
A
Short-Circuit Current
±250
mA
typ
C
0.04
Ω
typ
C
mA
max
A
dB
typ
C
Least Positive Output Voltage
Closed-Loop Output Impedance
DISABLE (SO-14 only)
Power-Down Supply Current (+VS)
G = +2, f = 100kHz
Disabled LOW
VDIS = 0V, Both Channels
–200
G = +2, 5MHz
65
4
pF
typ
C
Turn-On Glitch
G = +2, RL = 150Ω, VIN = VS/2
±50
mV
typ
C
Turn-Off Glitch
G = +2, RL = 150Ω, VIN = VS/2
±20
mV
typ
C
Off Isolation
Output Capacitance in Disable
–400
–480
–520
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
75
130
150
160
mA
typ
B
V
typ
C
12
12
12
V
max
B
A
Control Pin Input BIas Current (VDIS)
VDIS = 0V, Each Channel
POWER SUPPLY
Specified Single-Supply Operating Voltage
5
Maximum Single-Supply Operating Voltage
Maximum Quiescent Current (2 Channels)
VS = +5V
9.8
10.88
11.44
12.1
mA
max
Minimum Quiescent Current (2 Channels)
VS = +5V
9.8
8.96
8.0
7.72
mA
min
A
Input-Referred
72
dB
typ
C
–40 to +85
°C
typ
C
xx x D xxx SO-8
125
°C/W
typ
C
xx x D xxx SO-14
150
°C/W
typ
C
Power-Supply Rejection Ratio (+PSRR)
THERMAL CHARACTERISTICS
Specification: D
Thermal Resistance, qJA
Junction-to-Ambient
6
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
www.ti.com
SBOS238G – JUNE 2002 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.
SMALL−SIGNAL
FREQUENCY RESPONSE
9
6
VO = 0.5VPP
G = +1
RF = 25W
3
6
0
G=5
-3
-6
VO = 2VPP
Gain (3dB/div)
Normalized Gain (dB)
LARGE−SIGNAL
FREQUENCY RESPONSE
G=2
G = 10
3
VO = 1VPP
0
VO = 4VPP
-9
-3
-12
VO = 7VPP
-6
0.5
-15
0.7 1
10
700
100
1
Frequency (MHz)
Figure 1.
Figure 2.
SMALL-SIGNAL
PULSE RESPONSE
LARGE-SIGNAL
PULSE RESPONSE
G = +2
VO = 0.5VPP
300
500
G = +2
VO = 5VPP
3
200
Output Voltage (V)
Output Voltage (mV)
100
4
400
100
0
-100
-200
2
1
0
-1
-2
-3
-300
-4
-400
Time (5ns/div)
Time (5ns/div)
Figure 3.
Figure 4.
COMPOSITE VIDEO
dG/dP
CHANNEL-TO-CHANNEL
CROSSTALK
+5V
0.175
75W
1/2
OPA2690
0.150
402W
-55
No Pull- Down
With 1.3kW Pull-Down
Video In
-60
-65
Optional
1.3kW
Pull- Down
Crosstalk (5dB/div)
0.200
dG/dP (%/degree)
10
Frequency (MHz)
dG
402W
0.125
dG
0.100
-5V
dP
0.075
0.050
-70
-75
-80
-85
-90
dP
0.025
-95
0
-100
1
2
3
4
Input Referred
1
Number of 150W Loads
10
100
Frequency (MHz)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.
HARMONIC DISTORTION
vs LOAD RESISTANCE
5MHz HARMONIC DISTORTION
vs SUPPLY VOLTAGE
-60
VO = 2VPP
RL = 100W
f = 5MHz
VO = 2VPP
f = 5MHz
-65
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
-70
2nd-Harmonic
-75
3rd-Harmonic
-80
-85
-65
2nd-Harmonic
-70
3rd-Harmonic
-75
-80
-90
2.0
1000
100
2.5
3.0
5.0
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs OUTPUT VOLTAGE
5.5
6.0
-60
RL = 100W
f = 5MHz
-60
2nd-Harmonic
-70
-80
3rd-Harmonic
-90
2nd-Harmonic
-65
-70
3rd-Harmonic
-75
-80
-100
0.1
1
10
0.1
20
5
1
Output Voltage Swing (VPP)
Frequency (MHz)
Figure 9.
Figure 10.
HARMONIC DISTORTION
vs NONINVERTING GAIN
HARMONIC DISTORTION
vs INVERTING GAIN
-40
-40
VO = 2VPP
RL = 100W
f = 5MHz
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
4.5
Figure 8.
VO = 2VPP
RL = 100W
-50
4.0
Figure 7.
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-40
3.5
Supply Voltage (±VS)
Load Resistance (W)
-60
2nd-Harmonic
3rd-Harmonic
-70
-80
VO = 2VPP
RL = 100W
f = 5MHz
RF = 1kW
-50
-60
2nd-Harmonic
3rd-Harmonic
-70
-80
-90
1
10
20
1
10
20
Inverting Gain (V/V)
Noninverting Gain (V/V)
Figure 11.
Figure 12.
8
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.
INPUT VOLTAGE AND CURRENT
NOISE DENSITY
TWO−TONE, 3RD−ORDER
INTERMODULATION SPURIOUS
-30
3rd-Order Spurious Level (dBc)
Voltage Noise (nV/ÖHz)
Current Noise (pA/ÖHz)
100
10
Voltage Noise 5.5nV/ÖHz
Current Noise 3.1pA/ÖHz
1
-35
50MHz
-40
-45
-50
20MHz
-55
-60
-65
10MHz
Load Power at Matched 50W Load,
see Figure 36
-70
-75
100
1k
10k
100k
1M
10M
-8
-6
-4
Frequency (Hz)
0
-2
2
4
Figure 13.
Figure 14.
RECOMMENDED RS
vs CAPACITIVE LOAD
FREQUENCY RESPONSE
vs CAPACITIVE LOAD
8
10
9
80
G = +2
Gain-to-Capacitive Load (dB)
70
60
RS ( W )
6
Single-Tone Load Power (dBm)
50
40
30
20
10
CL = 10pF
6
CL = 100pF
3
CL = 22pF
0
CL = 47pF
-3
VIN
RS
1/2
OPA2690
VOUT
1kW
CL
402W
-6
402W
1kW is optional.
0
-9
10
1000
100
0
20
40
DISABLE FEEDTHROUGH
vs FREQUENCY
2
2.0
Output Voltage
1.6
Each Channel
SO-14
Package
Only
1.2
0.8
G = +2
VIN = +1V
-45
-50
VDIS = 0
-55
Feedthrough (5dB/div)
4
VDIS (2V/div)
LARGE-SIGNAL
ENABLE/DISABLE RESPONSE
0
Output Voltage (0.4V/div)
100 120 140 160 180 200
Figure 16.
VDIS
0
80
Figure 15.
6
0.4
60
Frequency (20MHz/div)
Capacitive Load (pF)
-60
-65
-70
-75
-80
-85
Reverse
-90
-95
Time (50ns/div)
-100
100k
Forward
1M
10M
100M
Frequency (Hz)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.
OUTPUT VOLTAGE
AND CURRENT LIMITATIONS
1
0
25W
Load Line
50W Load Line
-1
-2
100W Load Line
-3
-4
-5
-300
-200
0
-100
100
200
0.5
Input Offset Current (IOS)
0
0
-0.5
-1.0
-10
Input Offset Voltage (VOS)
-20
-2.0
-50
300
-25
0
25
50
75
100
Figure 19.
Figure 20.
COMMON−MODE REJECTION RATIO AND
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
SUPPLY AND OUTPUT CURRENTS
vs TEMPERATURE
100
14
250
-PSRR
90
Sourcing Output Current
80
Supply Current (2mA/div)
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
125
Ambient Temperature (°C)
IO (mA)
CMRR
70
60
+PSRR
50
40
30
20
12
200
Sinking Output Current
10
150
Quiescent Supply Current
8
100
6
50
10
0
4
10k
100k
1M
10M
100M
-50
-25
Frequency (MHz)
10
0
25
50
75
Figure 21.
Figure 22.
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
OPEN−LOOP
GAIN AND PHASE
Open-Loop Gain (dB)
1/2
200W OPA2690
ZO
-5V 402W
402W
0.1
0.01
0
100k
1M
10M
100M
-30
Open-Loop Gain
50
Open-Loop Phase
-60
40
-90
30
-120
20
-150
10
-180
0
-210
-10
-240
-20
10k
0
125
70
+5V
1
100
Ambient Temperature (°C)
60
Output Impedance (W)
10
-1.5
1W Internal
Power Limit
Output Current Limit
Input Bias Current (IB)
1.0
1k
10k
100k
1M
10M
100M
Open-Loop Phase (°)
VO (V)
1.5
One Channel
Only
2
20
Output Current (50mA/div)
3
Input Offset Voltage (mV)
4
2.0
Output Current Limited
1W Internal
Power Limit
Input Bias and Offset Currents (mA)
5
TYPICAL DC DRIFT
OVER TEMPERATURE
-270
1G
Frequency (Hz)
Frequency (Hz)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.
5
10
4
8
3
6
2
4
1
Output Voltage
2
0
0
-1
-2
-2
-4
-3
-4
Input Voltage
-5
Output Voltage (V)
Input Voltage (V)
NONINVERTING
OVERDRIVE RECOVERY
-6
-8
-10
Time (10ns/div)
Figure 25.
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TYPICAL CHARACTERISTICS: +5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 37 for ac performance only), unless otherwise noted.
SMALL−SIGNAL
FREQUENCY RESPONSE
6
LARGE−SIGNAL
FREQUENCY RESPONSE
9
VO = 0.5VPP
3
6
VO = 3VPP
G = +2
0
3
G = +5
Gain (dB)
Normalized Gain (dB)
VO = 2VPP
G = +1
RF = 25W
-3
VO = 1VPP
0
G = +10
-6
-3
-9
-6
0.7 1
100
10
700
0.5
1
Figure 26.
Figure 27.
SMALL-SIGNAL
PULSE RESPONSE
LARGE-SIGNAL
PULSE RESPONSE
4.1
G = +2
VO = 0.5VPP
2.8
Output Voltage (mV)
2.7
2.6
2.5
2.4
2.3
G = +2
VO = 2VPP
3.7
2.2
3.3
2.9
2.5
2.1
1.7
1.3
2.1
0.9
Time (5ns/div)
Time (5ns/div)
Figure 28.
Figure 29.
RECOMMENDED RS
vs CAPACITIVE LOAD
FREQUENCY RESPONSE
vs CAPACITIVE LOAD
9
50
CL = 10pF
Gain-to-Capacitive Load (dB)
45
40
35
RS ( W )
500
Frequency (MHz)
2.9
Output Voltage (mV)
100
10
Frequency (Hz)
30
25
20
15
10
6
CL = 100pF
3
0
+5V
-3
VIN
0.1mF
CL = 22pF
714W
1/2
58W
714W
714W OPA2690
RS V
OUT
CL = 47pF
CL
-6
402W +5V
5
402W
-9
0
1
10
100
1000
0
20
40
60
80
100 120
140 160
180 200
Frequency (20MHz/div)
Capacitive Load (pF)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS: +5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 37 for ac performance only), unless otherwise noted.
HARMONIC DISTORTION
vs LOAD RESISTANCE
HARMONIC DISTORTION
vs FREQUENCY
-40
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2VPP
f = 5MHz
-65
-70
2nd-Harmonic
3rd-Harmonic
-75
-50
VO = 2VPP
RL = 100W to 2.5V
-60
2nd-Harmonic
-70
-80
3rd-Harmonic
-90
-100
-80
1000
100
0.1
1
Figure 32.
Figure 33.
HARMONIC DISTORTION
vs OUTPUT VOLTAGE
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
-60
20
-30
-65
3rd-Order Spurious Level (dBc)
RL = 100W to 2.5V
f = 5MHz
Harmonic Distortion (dBc)
10
Frequency (MHz)
Resistance ( W )
3rd-Harmonic
-70
2nd-Harmonic
-75
-35
50MHz
-40
-45
-50
20MHz
-55
-60
-65
10MHz
-70
Load Power at Matched 50W Load, see Figure 37
-80
-75
0.1
1
3
-14
Output Voltage Swing (VPP)
-12
-10
-8
-6
-4
-2
0
2
Single-Tone Load Power (dBm)
Figure 34.
Figure 35.
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APPLICATION INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The OPA2690 provides an exceptional combination
of high output power capability in a wideband,
unity-gain stable voltage-feedback op amp using a
new high slew rate input stage. Typical differential
input stages used for voltage feedback op amps are
designed to steer a fixed-bias current to the
compensation capacitor, setting a limit to the
achievable slew rate. The OPA2690 uses a new input
stage that places the transconductance element
between two input buffers, using their output currents
as the forward signal. As the error voltage increases
across the two inputs, an increasing current is
delivered to the compensation capacitor. This
provides very high slew rate (1800V/ms) while
consuming
relatively
low
quiescent
current
(5.5mA/ch). This exceptional, full-power performance
comes at the price of a slightly higher input noise
voltage than alternative architectures. The 5.5nV/√Hz
input voltage noise for the OPA2690 is exceptionally
low for this type of input stage.
Figure 36 shows the dc-coupled, gain of +2, dual
power supply circuit configuration used as the basis
of the ±5V Electrical Characteristics and Typical
Characteristics. This is for one channel; the other
channel is connected similarly. For test purposes, the
input impedance is set to 50Ω with a resistor to
ground and the output impedance is set to 50Ω with a
series output resistor. Voltage swings reported in the
Electrical Characteristics are taken directly at the
input and output pins, while output powers (dBm) are
at the matched 50Ω load. For the circuit of Figure 36,
the total effective load will be 100Ω || 804Ω. The
disable control line (SO-14 package only) is typically
left open for normal amplifier operation. Two optional
components are included in Figure 36. An additional
resistor (175Ω) is included in series with the
noninverting input. Combined with the 25Ω dc source
resistance looking back towards the signal generator,
this gives an input bias current cancelling resistance
that matches the 200Ω source resistance seen at the
inverting input (see the DC Accuracy and Offset
Control section). In addition to the usual power-supply
decoupling capacitors to ground, a 0.1mF capacitor is
included between the two power-supply pins. In
practical printed circuit board (PCB) layouts, this
optional-added capacitor will typically improve the
2nd-harmonic distortion performance by 3dB to 6dB.
Figure 37 shows the ac-coupled, gain of +2,
single-supply circuit configuration used as the basis
of the +5V Electrical Characteristics and Typical
Characteristics. Though not a rail-to-rail design, the
OPA2690 requires minimal input and output voltage
headroom compared to other very wideband
voltage-feedback op amps. It will deliver a 3VPP
output swing on a single +5V supply with > 150MHz
bandwidth. The key requirement of broadband
single-supply operation is to maintain input and
output signal swings within the usable voltage ranges
at both the input and the output. The circuit of
Figure 37 establishes an input midpoint bias using a
simple resistive divider from the +5V supply (two
698Ω resistors). Separate bias networks would be
required at each input. The input signal is then
ac-coupled into the midpoint voltage bias. The input
voltage can swing to within 1.5V of either supply pin,
giving a 2VPP input signal range centered between
the supply pins. The input impedance matching
resistor (59Ω) used for testing is adjusted to give a
50Ω input load when the parallel combination of the
biasing divider network is included.
+5V
+VS
0.1mF
50W Source
VI
6.8mF
+
175W
DIS
VD
0.1mF
50W
VO
1/2
OPA2690
50W
50W Load
RF
402W
RG
402W
6.8mF
+
-VS
0.1mF
-5V
Figure 36. DC-Coupled, G = +2, Bipolar-Supply
Specification and Test Circuit
+5V
+VS
+
0.1mF
6.8mF
698W
0.1mF
VI
50W
DIS
VD
59W
698W
1/2
OPA2690
VO
100W
VS/2
RF
402W
RG
402W
0.1mF
Figure 37. AC-Coupled, G = +2, Single-Supply
Specification and Test Circuit
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Again, an additional resistor (50Ω in this case) is
included directly in series with the noninverting input.
This minimum recommended value provides part of
the dc source resistance matching for the
noninverting input bias current. It is also used to form
a simple parasitic pole to roll off the frequency
response at very high frequencies ( > 500MHz) using
the input parasitic capacitance. The gain resistor (RG)
is ac-coupled, giving the circuit a dc gain of +1, which
puts the input dc bias voltage (2.5V) on the output as
well. The output voltage can swing to within 1V of
either supply pin while delivering > 100mA output
current. A demanding 100Ω load to a midpoint bias is
used in this characterization circuit. The new output
stage circuit used in the OPA2690 can deliver large
bipolar output currents into this midpoint load with
minimal crossover distortion, as shown in the +5V
supply harmonic distortion plots.
The OPA2690 in the circuit of Figure 39 provides
> 200MHz bandwidth for a 2VPP output swing.
Minimal 3rd-harmonic distortion or two-tone,
3rd-order intermodulation distortion will be observed
due to the very low crossover distortion in the
OPA2690 output stage. The limit of output
Spurious-Free Dynamic Range (SFDR) will be set by
the 2nd-harmonic distortion. Without RB, the circuit of
Figure 39 measured at 10MHz shows an SFDR of
57dBc. This can be improved by pulling additional dc
bias current (IB) out of the output stage through the
optional RB resistor to ground (the output midpoint is
at 2.5V for Figure 39). Adjusting IB gives the
improvement in SFDR shown in Figure 38. SFDR
improvement is achieved for IB values up to 5mA,
with worse performance for higher values. Using the
dual OPA2690 in an I/Q receiver channel will give
matched ac performance through high frequencies.
SINGLE-SUPPLY ADC INTERFACE
70
Most modern, high-performance ADCs (such as the
TI ADS8xx and ADS9xx series) operate on a single
+5V (or lower) power supply. It has been a
considerable challenge for single-supply op amps to
deliver a low distortion input signal at the ADC input
for signal frequencies exceeding 5MHz. The high
slew rate, exceptional output swing, and high linearity
of the OPA2690 make it an ideal single-supply ADC
driver. The circuit on the front page shows one
possible interface particularly suited to differential I/O,
ac-coupled requirements. Figure 39 shows the test
circuit of Figure 37 modified for a capacitive (ADC)
load and with an optional output pull-down resistor
(RB). This circuit would be suitable to dual-channel
ADC driving with a single-ended I/O.
68
VO = 2VPP, 10MHz
66
SFDR (dBc)
64
62
60
58
56
54
52
50
0
1
2
3
4
5
6
7
8
9
10
Output Pull-Down Current (mA)
Figure 38. SFDR vs IB
+5V
Power- supply decoupling not shown.
698W
0.1mF
50W
VI
RS
30W
1/2
OPA2690
1VPP
59W
698W
2.5V DC
±1V AC
50pF
ADC Input
402W
402W
RB
0.1mF
IB
Figure 39. SFDR versus IB Test Circuit
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HIGH-PERFORMANCE DAC
TRANSIMPEDANCE AMPLIFIER
50W
1/2
OPA2690
High-frequency, direct digital synthesis (DDS)
digital-to-analog converters (DACs) require a low
distortion output amplifier to retain their SFDR
performance into real-world loads. Figure 40 shows a
single-ended output drive implementation. The
diagram shows the signal output current(s) connected
into the virtual ground summing junction(s) of the
OPA2690, which is set up as a transimpedance stage
or I-V converter. If the DAC requires that its outputs
terminate to a compliance voltage other than ground
for operation, the appropriate voltage level may be
applied to the noninverting input of the OPA2690.
The dc gain for this circuit is equal to RF. At high
frequencies, the DAC output capacitance (CD in
Figure 40) will produce a zero in the noise gain for
the OPA2690 that may cause peaking in the
closed-loop frequency response. CF is added across
RF to compensate for this noise gain peaking. To
achieve a flat transimpedance frequency response,
the pole in each feedback network should be set to:
1
=
2pRFCF
which will give
approximately:
f-3dB =
GBP
4pRFCD
a
cutoff
High- Speed
DAC
f−3dB,
GBP
2pRFCD
RF1
CF1
IO
CD1
RF2
CF2
-IO
CD2
1/2
OPA2690
-VO = -IO RF
50W
Figure 40. DAC Transimpedance Amplifier
WIDEBAND VIDEO MULTIPLEXING
(1)
frequency,
VO = IO RF
One common application for video speed amplifiers
that include a disable pin is to wire multiple amplifier
outputs together, then select which one of several
possible video inputs to source onto a single line.
This simple wired-OR video multiplexer can be easily
implemented using the OP2690I-14D (SO-14
package only), as shown in Figure 6.
of
(2)
Where GBP = gain bandwidth product (Hz) for the
OPA2690.
+5V
2kW
VDIS
+5V
146W
DISA
1/2
OPA2690
Video 1
75W
340W
402W
-5V
75W Cable
340W
402W
Video 2
RG-59
75W Load
+5V
146W
82.5W
82.5W
1/2
OPA2690
DISB
75W
2kW
-5V
Figure 41. Two-Channel Video Multiplexer (SO-14 package only)
16
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Typically, channel switching is performed either on
sync or retrace time in the video signal. The two
inputs are approximately equal at this time. The
make-before-break disable characteristic of the
OPA2690 ensures that there is always one amplifier
controlling the line when using a wired-OR circuit like
that shown in Figure 41. As both inputs may be on for
a short period during the transition between channels,
the outputs are combined through the output
impedance matching resistors (82.5Ω in this case).
When one channel is disabled, its feedback network
forms part of the output impedance and slightly
attenuates the signal in getting out onto the cable.
The gain and output matching resistor have been
slightly increased to get a signal gain of +1 at the
matched load and provide a 75Ω output impedance to
the cable. The video multiplexer connection (see
Figure 41) also ensures that the maximum differential
voltage across the inputs of the unselected channel
does not exceed the rated ±1.2V maximum for
standard video signal levels.
See the Disable Operation section for the turn-on and
turn-off switching glitches using a 0V input for a
single channel is typically less than ±50mV. Where
two outputs are switched (see Figure 41), the output
line is always under the control of one amplifier or the
other due to the make-before-break disable timing. In
this case, the switching glitches for two 0V inputs
drops to < 20mV.
HIGH-SPEED DELAY CIRCUIT
The OPA2690 makes an ideal amplifier for a variety
of active filter designs. Shown in Figure 42 is a circuit
that uses the two amplifiers within the dual OPA2690
to design a two-stage analog delay circuit. For
simplicity, the circuit uses a dual-supply (±5V)
operation, but it can also be modified to operate on a
signal supply. The input to the first filter stage is
driven by the OPA692 wideband buffer amplifier to
isolate the signal input from the filter network.
Each of the two filter stages is a 1st-order filter with a
voltage gain of +1. The delay time through one filter
is given by Equation 3:
tGR0 = 2RC
(3)
For a more accurate analysis of the circuit, consider
the group delay for the amplifiers. For example, in the
case of the OPA2690, the group delay in the
bandwidth from 1MHz to 100MHz is approximately
1.0ns. To account for this, modify the transfer
function, which now comes out to be:
tGR = 2(2RC + tD)
(4)
Where tD = (1/360) × (df/df) = delay of the op amp
itself.
The values of resistors RF and RG should be equal
and low to avoid parasitic effects. If the all-pass filter
is designed for very low delay times, include parasitic
board capacitances to calculate the correct delay
time. Simulating this application using the PSPICE
model of the OPA2690 will allow this design to be
tuned to the desired performance.
DIFFERENTIAL RECEIVER/DRIVER
A very versatile application for a dual operational
amplifier is the differential amplifier configuration
detailed in Figure 43. With both amplifiers of the
OPA2690 connected for noninverting operation, the
circuit provides a high input impedance whereas the
gain can easily be set by just one resistor, RG. When
operated in low gains, the output swing may be
limited as a result of the common-mode input swing
limits of the amplifier itself. An interesting modification
of this circuit is to place a capacitor in series with the
RG. Now the dc gain for each side is reduced to +1,
whereas the ac gain still follows the standard transfer
function of G = 1 + 2RF/RG. This might be
advantageous for applications processing only a
frequency band that excludes dc or very low
frequencies. An input dc voltage resulting from input
bias currents is not amplified by the ac gain and can
be kept low. This circuit can be used as a differential
line receiver, driver, or as an interface to a differential
input ADC.
C
VIN
OPA692
1/2
OPA2690
C
1/2
OPA2690
R
VOUT
R
RG
402W
RF
402W
RG
402W
RF
402W
Figure 42. Two-Stage, All-Pass Network
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SINGLE-SUPPLY MFB DIFFERENTIAL
ACTIVE FILTER: 10MHz BUTTERWORTH
CONFIGURATION
50W
VI
1/2
OPA2690
RO
The active filter circuit shown in Figure 44 can be
easily implemented using the OPA2690. In this
configuration, each amplifier of the OPA2690
operates as an integrator. For this reason, this type of
application is also called infinite gain filter
implementation. A Butterworth filter can be
implemented using the following component ratios:
1
fO =
(cutoff frequency)
2´p´R´C
R1 = R2 = 0.65 ´ R
R3 = 0.375 ´ R
C1 = C
C2 = 2 ´ C
(5)
RF
402W
RG
50W
VDIFF = 1 +
RF
402W
1/2
OPA2690
2RF
RG
VI - (-VI)
RO
-VI
Figure 43. High-Speed Differential Receiver
+12V
6kW
50W
VCM
1/2
OPA2690
1000pF
6kW
C1A
100pF
R3A
60W
R1A
102W
R2A
102W
C2
200pF
VIN
R2B
102W
R1B
102W
R3B
60W
50W
VOUT
C1B
100pF
1/2
OPA2690
VCM
Figure 44. Single-Supply, MFB Active Filter, 10MHz LP Butterworth
18
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The frequency response for a 10MHz Butterworth
filter is shown in Figure 45. One advantage for using
this type of filter is the independent setting of wo and
Q. Q can be easily adjusted by changing the R3A, B
resistors without affecting wo.
The circuit shown on the front page has a 195MHz,
−3dB bandwidth that can be easily bandlimited by
using a capacitor in parallel with the feedback
resistors. Refer to Figure 46 for more details. The
−3dB frequency is given by Equation 6.
1
f-3dB =
2pRFCF
(6)
1
0
-1
-2
Gain (dB)
Single-Supply
Differential
ADC
Driver),
the
2nd-harmonic reacts as expected and drops to a
−95dBc at 1MHz and −87dBc at 5MHz—a significant
improvement
in
going
to
differential
from
single-ended.
-3
-4
-5
-6
9
-7
6
-9
0.1
1
10
20
Frequency (MHz)
Figure 45. Multiple Feedback Filter Frequency
Response
Differential Gain (dB)
-8
3
CF = 8.6pF
0
-3
-6
-9
SINGLE-SUPPLY DIFFERENTIAL ADC
DRIVER
The circuit shown on the front page is ideal for driving
high-frequency ADCs. As shown in the plot on the
front page (Harmonic Distortion vs Frequency for the
-12
0.1
1
10
100
500
Frequency (MHz)
Figure 46. Single-Supply Differential ADC Driver
For example, CF = 8.6pF in parallel with RF = 402Ω
will control the –3dB frequency to 18MHz.
19
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DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
MACROMODELS
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA2690 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user’s guide. The summary
information for these fixtures is shown in Table 1.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the OPA2690 (use two OPA690 SPICE models) is
available through the OPA2690 product folder under
Simulation Models. These models do a good job of
predicting small-signal ac and transient performance
under a wide variety of operating conditions. They do
not do as well in predicting the harmonic distortion or
dG/dP characteristics. These models do not attempt
to distinguish between the package types in their
small-signal ac performance.
Table 1. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA2690ID
SO-8
DEM-OPA-SO-2A
SBOU003
OPA2690I14D
SO-14
DEM-OPA-SO-2D
SBOU002
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA2690 product folder.
20
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OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
As the the OPA2690 is a unity-gain stable,
voltage-feedback op amp, a wide range of resistor
values may be used for the feedback and gain setting
resistors. The primary limits on these values are set
by dynamic range (noise and distortion) and parasitic
capacitance considerations. For a noninverting
unity-gain follower application, the feedback
connection should be made with a 25Ω resistor, not a
direct short. This will isolate the inverting input
capacitance from the output pin and improve the
frequency response flatness. Usually, the feedback
resistor value should be between 200Ω and 1.5kΩ.
Below 200Ω, the feedback network will present
additional output loading which can degrade the
harmonic distortion performance of the OPA2690.
Above 1.5kΩ, the typical parasitic capacitance
(approximately 0.2pF) across the feedback resistor
can cause unintentional band-limiting in the amplifier
response.
A good rule of thumb is to target the parallel
combination of RF and RG (see Figure 36) to be less
than approximately 300Ω. The combined impedance
RF || RG interacts with the inverting input capacitance,
placing an additional pole in the feedback network
and thus, a zero in the forward response. Assuming a
2pF total parasitic on the inverting node, holding RF ||
RG < 300Ω will keep this pole above 250MHz. By
itself, this constraint implies that feedback resistor RF
can increase to several kΩ at high gains. This is
acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out
of the frequency range of interest.
BANDWIDTH vs GAIN: NONINVERTING
OPERATION
Voltage-feedback op amps exhibit decreasing
closed-loop bandwidth as the signal gain is
increased. In theory, this relationship is described by
the Gain Bandwidth Product (GBP) shown in the
Electrical Characteristics. Ideally, dividing GBP by the
noninverting signal gain (also called the Noise Gain,
or NG) will predict the closed-loop bandwidth. In
practice, this only holds true when the phase margin
approaches 90°, as it does in high gain
configurations. At low gains (increased feedback
factors), most amplifiers will exhibit a more complex
response with lower phase margin. The OPA2690 is
compensated to give a slightly peaked response in a
noninverting gain of 2 (see Figure 36). This results in
a typical gain of +2 bandwidth of 220MHz, far
exceeding that predicted by dividing the 300MHz
GBP by 2. Increasing the gain will cause the phase
margin to approach 90° and the bandwidth to more
closely approach the predicted value of (GBP/NG). At
a gain of +10, the 30MHz bandwidth shown in the
Electrical Characteristics agrees with that predicted
using the simple formula and the typical GBP of
300MHz.
The frequency response in a gain of +2 may be
modified to achieve exceptional flatness simply by
increasing the noise gain to 2.5. One way to do this,
without affecting the +2 signal gain, is to add an
804Ω resistor across the two inputs in the circuit of
Figure 36. A similar technique may be used to reduce
peaking in unity-gain (voltage follower) applications.
For example, by using a 402Ω feedback resistor
along with a 402Ω resistor across the two op amp
inputs, the voltage follower response will be similar to
the gain of +2 response of Figure 37. Reducing the
value of the resistor across the op amp inputs will
further limit the frequency response due to increased
noise gain.
The OPA2690 exhibits minimal bandwidth reduction
going to single-supply (+5V) operation as compared
with ±5V. This is because the internal bias control
circuitry retains nearly constant quiescent current as
the total supply voltage between the supply pins is
changed.
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INVERTING AMPLIFIER OPERATION
Since the OPA2690 is a general-purpose, wideband
voltage-feedback op amp, all of the familiar op amp
application circuits are available to the designer.
Inverting operation is one of the more common
requirements and offers several performance
benefits. Figure 47 shows a typical inverting
configuration where the I/O impedances and signal
gain from Figure 36 are retained in an inverting circuit
configuration.
+5V
+
0.1mF
6.8mF
0.1mF
RB
146W
50W
Source
VO
1/2
OPA2690
RO
50W
50W Load
RG
200W
VO
= -2
VI
RF
402W
VI
RM
67W
0.1mF
+
6.8mF
-5V
Figure 47. Gain of –2 Example Circuit
In the inverting configuration, three key design
considerations must be noted. The first is that the
gain resistor (RG) becomes part of the signal channel
input impedance. If input impedance matching is
desired (which is beneficial whenever the signal is
coupled through a cable, twisted-pair, long PCB
trace, or other transmission line conductor), RG may
be set equal to the required termination value and RF
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and
noise performance. However, at low inverting gains,
the resultant feedback resistor value can present a
significant load to the amplifier output. For an
inverting gain of –2, setting RG to 50Ω for input
matching eliminates the need for RM but requires a
100Ω feedback resistor. This has the interesting
advantage that the noise gain becomes equal to 2 for
a 50Ω source impedance—the same as the
noninverting circuits considered in the previous
section. The amplifier output, however, will now see
the 100Ω feedback resistor in parallel with the
external load. In general, the feedback resistor should
be limited to the 200Ω to 1.5kΩ range. In this case, it
is preferable to increase both the RF and RG values,
as shown in Figure 47, and then achieve the input
matching impedance with a third resistor (RM) to
ground. The total input impedance becomes the
parallel combination of RG and RM.
The second major consideration, touched on in the
previous paragraph, is that the signal source
impedance becomes part of the noise gain equation
and influences the bandwidth. For the example in
Figure 47, the RM value combines in parallel with the
external 50Ω source impedance, yielding an effective
driving impedance of 50Ω || 67Ω = 28.6Ω. This
impedance is added in series with RG for calculating
the noise gain (NG). The resultant NG is 2.8 for
Figure 47, as opposed to only 2 if RM could be
eliminated as discussed above. The bandwidth will
therefore be slightly lower for the gain of –2 circuit of
Figure 47 than for the gain of +2 circuit of Figure 36.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistor
on the noninverting input (RB). If this resistor is set
equal to the total dc resistance looking out of the
inverting node, the output dc error, due to the input
bias currents, will be reduced to (Input Offset Current)
× RF. If the 50Ω source impedance is dc-coupled in
Figure 47, the total resistance to ground on the
inverting input will be 228Ω. Combining this in parallel
with the feedback resistor gives the RB = 146Ω used
in this example. To reduce the additional
high-frequency noise introduced by this resistor, it is
sometimes bypassed with a capacitor. As long as RB
< 350Ω, the capacitor is not required because the
total noise contribution of all other terms will be less
than that of the op amp input noise voltage. As a
minimum, the OPA2690 requires an RB value of 50Ω
to damp out parasitic-induced peaking—a direct short
to ground on the noninverting input runs the risk of a
very high-frequency instability in the input stage.
22
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OUTPUT CURRENT AND VOLTAGE
The OPA2690 provides output voltage and current
capabilities in a low-cost monolithic op amp. Under
no-load conditions at +25°C, the output voltage
typically swings closer than 1V to either supply rail;
the specified swing limit is within 1.2V of either rail.
Into a 15Ω load (the minimum tested load), it will
deliver more than ±160mA.
The specifications described previously, though
familiar in the industry, consider voltage and current
limits separately. In many applications, it is the
voltage × current, or V-I product, that is more relevant
to circuit operation. Refer to Figure 19, the Output
Voltage and Current Limitations plot in the Typical
Characteristics. The X- and Y-axes of this graph
show the zero-voltage output current limit and the
zero-current output voltage limit, respectively. The
four quadrants give a more detailed view of the
OPA2690 output drive capabilities, noting that the
graph is bounded by a Safe Operating Area of 1W
maximum internal power dissipation for each channel
separately. Superimposing resistor load lines onto the
plot shows that the OPA2690 can drive ±2.5V into
25Ω or ±3.5V into 50Ω without exceeding the output
capabilities or the 1W dissipation limit. A 100Ω load
line (the standard test circuit load) shows the full
±3.9V output swing capability (see the Electrical
Characteristics).
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at
cold startup will the output current and voltage
decrease to the numbers shown in the Electrical
Characteristic tables. As the output transistors deliver
power, their junction temperatures increase,
decreasing their VBEs (increasing the available output
voltage swing) and increasing their current gains
(increasing the available output current). In
steady-state operation, the available output voltage
and current is always greater than that shown in the
over-temperature specifications because the output
stage junction temperatures will be higher than the
minimum specified operating ambient.
To protect the output stage from accidental shorts to
ground and the power supplies, output short-circuit
protection is included in the OPA2690. The circuit
acts to limit the maximum source or sink current to
approximately 250mA.
OPA2690 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier's open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
problem have been suggested. When the primary
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a
series-isolation resistor between the amplifier output
and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and
adds a zero at a higher frequency. The additional
zero acts to cancel the phase lag from the capacitive
load pole, thus increasing the phase margin and
improving stability.
The Typical Characteristics show the recommended
RS versus capacitive load (Figure 15 for ±5V and
Figure 30 for +5V) and the resulting frequency
response at the load. Parasitic capacitive loads
greater than 2pF can begin to degrade the
performance of the OPA2690. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the OPA2690 output pin (see the Board Layout
Guidelines section).
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For
the OPA2690 operating in a gain of +2, the frequency
response at the output pin is already slightly peaked
without the capacitive load requiring relatively high
values of RS to flatten the response at the load.
Increasing the noise gain will reduce the peaking as
described previously. The circuit of Figure 48
demonstrates this technique, allowing lower values of
RS to be used for a given capacitive load.
+5V
50W
175W
50W
RNG
Power-supply decoupling
not shown.
1/2
OPA2690
402W
R
VO
CLOAD
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance which
may be recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier like the
402W
-5V
Figure 48. Capacitive Load Driving with Noise
Gain Tuning
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This gain of +2 circuit includes a noise gain tuning
resistor across the two inputs to increase the noise
gain, increasing the unloaded phase margin for the
op amp. Although this technique will reduce the
required RS resistor for a given capacitive load, it
does increase the noise at the output. It also will
decrease the loop gain, slightly decreasing the
distortion performance. If, however, the dominant
distortion mechanism arises from a high RS value,
significant dynamic range improvement can be
achieved using this technique. Figure 49 shows the
required RS versus CLOAD parametric on noise gain
using this technique. This is the circuit of Figure 48
with RNG adjusted to increase the noise gain
(increasing the phase margin) then sweeping CLOAD
and finding the required RS to get a flat frequency
response. This plot also gives the required RS versus
CLOAD for the OPA2690 operated at higher signal
gains without RNG.
100
90
80
RS (W)
70
NG = 2
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The new
output stage used in the OPA2690 actually holds the
difference between fundamental power and the 2ndand 3rd-harmonic powers relatively constant with
increasing output power until very large output swings
are required ( > 4VPP). This also shows up in the
2-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are
moderately low at low output power levels. The
output stage continues to hold them low even as the
fundamental power reaches very high levels. As the
Typical
Characteristics
show,
the
spurious
intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not
decrease significantly. For two tones centered at
20MHz, with 10dBm/tone into a matched 50Ω load
(that is, 2VPP for each tone at the load, which requires
8VPP for the overall two-tone envelope at the output
pin), the Typical Characteristics show 46dBc
difference between the test tone powers and the
3rd-order intermodulation spurious powers. This
exceptional performance improves further when
operating at lower frequencies or powers.
60
50
NOISE PERFORMANCE
40
30
20
NG = 3
10
NG = 4
0
1
10
100
1000
Capacitive Load (pF)
Figure 49. Required RS vs Noise Gain
DISTORTION PERFORMANCE
The OPA2690 provides good distortion performance
into a 100Ω load on ±5V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads and/or operating on a
single +5V supply. Generally, until the fundamental
signal reaches very high frequency or power levels,
the 2nd-harmonic dominates the distortion with a
negligible 3rd-harmonic component. Focusing then on
the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total
load includes the feedback network; in the
noninverting configuration (see Figure 36), this is sum
of RF + RG, while in the inverting configuration it is
just
RF.
Also,
providing
an
additional
supply-decoupling capacitor (0.1mF) between the
supply pins (for bipolar operation) improves the
2nd-order distortion slightly (3dB to 6dB). Operating
differentially also lowers 2nd-harmonic distortion
terms (see the plot on the front page).
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve their slew rate at the expense
of a higher input noise voltage. The 5.5nV/√Hz input
voltage noise for the OPA2690 is, however, much
lower than comparable amplifiers. The input-referred
voltage noise, and the two input-referred current
noise terms, combine to give low output noise under
a wide variety of operating conditions. Figure 50
shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms
are taken to be noise voltage or current density terms
in either nV/√Hz or pA/√Hz.
ENI
1/2
OPA2690
RS
EO
IBN
ERS
RF
Ö 4kTRS
4kT
RG
RG
IBI
Ö 4kTRF
4kT = 1.6E - 20J
at 290°K
Figure 50. Op Amp Noise Analysis Model
24
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The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 7 shows the
general form for the output noise voltage using the
terms shown in Figure 50.
EO =
ENI2
2
2
2
+ (IBNRS) + 4kTRS NG + (IBIRF) + 4kTRFNG
(7)
Dividing this expression by the noise gain [NG = (1 +
RF/RG)] will give the equivalent input-referred spot
noise voltage at the noninverting input, as shown in
Equation 8.
EN =
ENI2 + (IBNRS)2 + 4kTRS +
IBIRF
NG
2
+
4kTRF
NG
(8)
Evaluating these two equations for the OPA2690
circuit and component values (see Figure 36) gives a
total output spot noise voltage of 12.3nV/√Hz and a
total equivalent input spot noise voltage of 6.1nV/√Hz.
This is including the noise added by the bias current
cancellation resistor (175Ω) on the noninverting input.
This total input-referred spot noise voltage is only
slightly higher than the 5.5nV/√Hz specification for the
op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp
input are limited to the previously recommend
maximum value of 300Ω. Keeping both (RF || RG) and
the noninverting input source impedance less than
300Ω will satisfy both noise and frequency response
flatness considerations. As the resistor-induced noise
is
relatively
negligible,
additional
capacitive
decoupling across the bias current cancellation
resistor (RB) for the inverting op amp configuration of
Figure 47 is not required.
±(NG × VOS(MAX)) ± (RF × IOS(MAX))
= ±(2 × 4.5mV) ± (402Ω × 1mA)
= ±9.4mV – (NG = noninverting signal gain)
A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques eventually
reduce to adding a dc current through the feedback
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
be noninverting, the offset control is best applied as
an inverting summing signal to avoid interaction with
the signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. However, the
dc offset voltage on the summing junction will set up
a dc current back into the source that must be
considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
frequency response flatness. For a dc-coupled
inverting amplifier, Figure 51 shows one example of
an offset adjustment technique that has minimal
impact on the signal frequency response. In this
case, the dc offsetting current is brought into the
inverting input node through resistor values that are
much larger than the signal path resistors. This
ensures that the adjustment circuit has minimal effect
on the loop gain and hence, the frequency response.
+5V
Power-supply
decoupling not shown.
328W
0.1mF
1/2
OPA2690
VO
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband
voltage-feedback op amp allows good output dc
accuracy in a wide variety of applications. The
power-supply current trim for the OPA2690 gives
even tighter control than comparable amplifiers.
Although the high-speed input stage does require
relatively high input bias current (typically 5mA out of
each input terminal), the close matching between
them may be used to reduce the output dc error
caused by this current. The total output offset voltage
may be considerably reduced by matching the dc
source resistances appearing at the two inputs. This
reduces the output dc error due to the input bias
currents to the offset current times the feedback
resistor. Evaluating the configuration of Figure 36,
and using worst-case +25°C input offset voltage and
current specifications, gives a worst-case output
offset voltage equal to:
BLANKSPACE
BLANKSPACE
-5V
RG
500W
+5V
5kW
RF
1kW
VI
20kW
±200mV Output Adjustment
10kW
0.1mF
5kW
VO
VI
=-
RF
RG
= -2
-5V
Figure 51. DC-Coupled, Inverting Gain of -2, with
Offset Adjustment
25
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DISABLE OPERATION (SO-14 Package Only)
The OPA2690-I-14D provides an optional disable
feature that may be used either to reduce system
power or to implement a simple channel multiplexing
operation. If the DIS control pin is left unconnected,
the OPA2690I-14D will operate normally. To disable,
the control pin must be asserted LOW. Figure 52
shows a simplified internal circuit for the disable
control feature.
One key parameter in disable operation is the output
glitch when switching in and out of the disabled
mode. Figure 53 shows these glitches for the circuit
of Figure 36 with the input signal at 0V. The glitch
waveform at the output pin is plotted along with the
DIS pin voltage.
15kW
Q1
VDIS
110kW
IS
Control
-VS
Figure 52. Simplified Disable Control Circuit
The transition edge rate (dV/dt) of the DIS control line
will influence this glitch. For the plot of Figure 53, the
edge rate was reduced until no further reduction in
glitch amplitude was observed. This approximately
1V/ns maximum slew rate may be achieved by
adding a simple RC filter into the DIS pin from a
higher speed logic line. If extremely fast transition
logic is used, a 2kΩ series resistor between the logic
gate and the DIS input pin provides adequate
bandlimiting using just the parasitic input capacitance
on the DIS pin while still ensuring adequate logic
level swing.
6
4
VDIS
2
0
Output Voltage (10mV/div)
In normal operation, base current to Q1 is provided
through the 110kΩ resistor, while the emitter current
through the 15kΩ resistor sets up a voltage drop that
is inadequate to turn on the two diodes in Q1's
emitter. As VDIS is pulled LOW, additional current is
pulled through the 15kΩ resistor, eventually turning
on those two diodes (≈100mA). At this point, any
further current pulled out of VDIS goes through those
diodes holding the emitter-base voltage of Q1 at
approximately 0V. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current
in the disable mode are only those required to
operate the circuit of Figure 52. Additional circuitry
ensures that turn-on time occurs faster than turn-off
time (make-before-break).
VDIS (2V/div)
+VS
25kW
the output and exceptional signal isolation. If
operating at a gain greater than +1, the total
feedback network resistance (RF + RG) will appear as
the impedance looking back into the output, but the
circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the
input and output will be connected through the
feedback network resistance (RF + RG) and the
isolation will be very poor as a result.
30
20
10
Output Voltage
0
VI = 0V
-10
-20
-30
Time (20ns/div)
Figure 53. Disable/Enable Glitch
When disabled, the output and input nodes go to a
high-impedance state. If the OPA2690 is operating at
a gain of +1, this will show a very high impedance at
26
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
www.ti.com
SBOS238G – JUNE 2002 – REVISED MARCH 2010
THERMAL ANALYSIS
Due to the high output power capability of the
OPA2690, heatsinking or forced airflow may be
required under extreme operating conditions.
Maximum desired junction temperature will set the
maximum allowed internal power dissipation as
described below. In no case should the maximum
junction temperature be allowed to exceed 150°C.
Note that it is the power in the output stage and not
into the load that determines internal power
dissipation.
As a worst-case example, compute the maximum TJ
using an OPA2690ID (SO-8 package) in the circuit of
Figure 36 operating at the maximum specified
ambient temperature of +85°C and with both outputs
driving a grounded 20Ω load to +2.5V.
Operating junction temperature (TJ) is given by:
TA + PD × qJA
PD = 10V × 12.6mA + 2 [52/(4 × (20Ω || 804Ω))
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power
dissipated in the output stage (PDL) to deliver load
power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load but, for a grounded resistive load, is
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
supplies). Under this condition, PDL = VS2/(4 × RL)
where RL includes feedback network loading.
Maximum TJ = +85°C + (0.766W × 125°C/W)
PD = 766mW
PD = 180°C
This absolute worst-case condition exceeds the
specified maximum junction temperature. Actual PDL
is normally less than that considered here. Carefully
consider maximum TJ in your application.
27
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
SBOS238G – JUNE 2002 – REVISED MARCH 2010
www.ti.com
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the OPA2690 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
b. Minimize the distance (< 0.25") from the
power-supply pins to high-frequency 0.1mF
decoupling capacitors. At the device pins, the
ground and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power-supply connections should
always be decoupled with these capacitors. An
optional supply decoupling capacitor (0.1mF)
across the two power supplies (for bipolar
operation) will improve 2nd-harmonic distortion
performance. Larger (2.2mF to 6.8mF) decoupling
capacitors, effective at lower frequencies, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PCB.
c. Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA2690. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Metal film or carbon composition
axially-leaded resistors can also provide good
high-frequency performance. Again, keep their
leads and PCB traces as short as possible. Never
use wirewound type resistors in a high-frequency
application. Since the output pin and inverting
input pin are the most sensitive to parasitic
capacitance, always position the feedback and
series output resistor, if any, as close as possible
to the output pin. Other network components,
such as noninverting input termination resistors,
should also be placed close to the package. Even
with a low parasitic capacitance shunting the
external resistors, excessively high resistor
values can create significant time constants that
can degrade performance. Good axial metal film
or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can
add a pole and/or zero below 500MHz that can
affect circuit operation. Keep resistor values as
low as possible consistent with load driving
considerations. The 402Ω feedback used in the
Electrical Characteristics is a good starting point
for design. Note that a 25Ω feedback resistor,
rather than a direct short, is suggested for the
unity-gain follower application. This effectively
isolates the inverting input capacitance from the
output pin that would otherwise cause an
additional peaking in the gain of +1 frequency
response.
d. Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50mils or 1,27mm to
100mils or 2,54mm) should be used, preferably
with ground and power planes opened up around
them. Estimate the total capacitive load and set
RS from the plot of Recommended RS vs
Capacitive Load (Figure 15 for ±5V and Figure 30
for +5V). Low parasitic capacitive loads (< 3pF)
may not need an RS because the OPA2690 is
nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase
margin; see Figure 49). If a long trace is required,
and the 6dB signal loss intrinsic to a
doubly-terminated
transmission
line
is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary on board,
and in fact, a higher impedance environment will
improve distortion as shown in the distortion
versus load plots (Figure 7 for the ±5v and
Figure 32 for the +5V). With a characteristic
board trace impedance defined (based on board
material and trace dimensions), a matching series
resistor into the trace from the output of the
OPA2690 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance
will be the parallel combination of the shunt
resistor and the input impedance of the
destination device; this total effective impedance
should be set to match the trace impedance. The
high output voltage and current capability of the
OPA2690 allows multiple destination devices to
be handled as separate transmission lines, each
with their own series and shunt terminations. If
28
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
www.ti.com
SBOS238G – JUNE 2002 – REVISED MARCH 2010
the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace
can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the
plots of Recommended RS vs Capacitive Load
(Figure 15 for ±5V and Figure 30 for +5V). This
will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there will be some
signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
e. Socketing a high-speed part like the OPA2690
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the OPA2690 onto the board.
INPUT AND ESD PROTECTION
The OPA2690 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 54.
+VCC
External
Pin
Internal
Circuitry
-VCC
Figure 54. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA2690), current-limiting
series resistors should be added into the two inputs.
Keep these resistor values as low as possible since
high values degrade both noise performance and
frequency response.
29
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
OPA2690
SBOS238G – JUNE 2002 – REVISED MARCH 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August 2008) to Revision G
Page
•
Changed data sheet format to current standards ................................................................................................................. 1
•
Changed Related Products table .......................................................................................................................................... 1
•
Deleted Lead Temperature specification from Absolute Maximum Ratings table ................................................................ 2
•
Changed test levels for Slew Rate, 2nd-Harmonic, and Channel-to-Channel Crosstalk parameters .................................. 3
•
Changed test level for Control Pin Input Bias Current parameter ........................................................................................ 5
•
Changed circuit within Figure 5 ............................................................................................................................................ 7
•
Added Figure 25, Noninverting Overdrive Recovery graph ................................................................................................ 11
•
Changed VO to VI in Figure 53 ............................................................................................................................................ 26
Changes from Revision E (May 2006) to Revision F
•
Page
Changed Storage Temperature minimum value from −40°C to −65°C ................................................................................ 2
30
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA2690
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2690I-14D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA2690
OPA2690I-14DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA2690
OPA2690I-14DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA2690
OPA2690ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2690
OPA2690IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2690
OPA2690IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2690
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2690I-14DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
OPA2690IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2690I-14DR
SOIC
D
14
2500
367.0
367.0
38.0
OPA2690IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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