Texas Instruments | Wide Bandwidth, DC Restoration Circuit (Rev. E) | Datasheet | Texas Instruments Wide Bandwidth, DC Restoration Circuit (Rev. E) Datasheet

Texas Instruments Wide Bandwidth, DC Restoration Circuit (Rev. E) Datasheet
OPA615
www.ti.com...................................................................................................................................... SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009
Wide-Bandwidth, DC Restoration Circuit
Check for Samples: OPA615
FEATURES
DESCRIPTION
•
•
The OPA615 is a complete subsystem for very fast
and precise DC restoration, offset clamping, and
low-frequency hum suppression of wideband
amplifiers or buffers. Although it is designed to
stabilize the performance of video signals, the circuit
can also be used as a sample-and-hold amplifier,
high-speed integrator, or peak detector for
nanosecond pulses. The device features a wideband
Operational Transconductance Amplifier (OTA) with a
high-impedance cascode current source output and
fast and precise sampling comparator that together
set a new standard for high-speed applications. Both
the OTA and the sampling comparator can be used
as stand-alone circuits or combined to form a more
complex signal processing stage. The self-biased,
bipolar OTA can be viewed as an ideal
voltage-controlled current source and is optimized for
low input bias current. The sampling comparator has
two identical high-impedance inputs and a current
source output optimized for low output bias current
and offset voltage; it can be controlled by a
TTL-compatible switching stage within a few
nanoseconds. The transconductance of the OTA and
sampling comparator can be adjusted by an external
resistor, allowing bandwidth, quiescent current, and
gain trade-offs to be optimized.
1
2
•
•
•
•
•
•
PROPAGATION DELAY: 1.9ns
BANDWIDTH:
OTA: 710MHz
Comparator: 730MHz
LOW INPUT BIAS CURRENT: ±1μA
SAMPLE-AND-HOLD SWITCHING
TRANSIENTS: ±5mV
SAMPLE-AND-HOLD FEEDTHROUGH
REJECTION: 100dB
CHARGE INJECTION: 40fC
HOLD COMMAND DELAY TIME: 2.5ns
TTL/CMOS HOLD CONTROL
APPLICATIONS
•
•
•
•
•
•
•
•
•
BROADCAST/HDTV EQUIPMENT
TELECOMMUNICATIONS EQUIPMENT
HIGH-SPEED DATA ACQUISITION
CAD MONITORS/CCD IMAGE PROCESSING
NANOSECOND PULSE INTEGRATOR/PEAK
DETECTOR
PULSE CODE MODULATOR/DEMODULATOR
COMPLETE VIDEO DC LEVEL RESTORATION
SAMPLE-AND-HOLD AMPLIFIER
SHC615 UPGRADE
Ground
9
CHOLD
4
The OPA615 is available in both an
surface-mount and an MSOP-10 package.
Base
3
2
Hold
Control
7
Switching
Stage
10
S/H
In−
11
Emitter
OTA
Sampling
Comparator (SC)
S/H
In+
SO-14
12
SOTA ∞
Biasing
Collector
(IOUT)
1
IQ Adjust
OPA615
13
+VCC
5
−VCC
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2009, Texas Instruments Incorporated
OPA615
SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
OPA615
SO-14
D
OPA615
(1)
MSOP-10
DGS
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +85°C
OPA615ID
–40°C to +85°C
BJT
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
OPA615ID
Rails, 50
OPA615IDR
Tape and Reel, 2500
OPA615IDGST
Tape and Reel, 250
OPA615IDGSR
Tape and Reel, 2500
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage
±6.5V
Differential Input Voltage
±VS
Common-Mode Input Voltage Range
±VS
Hold Control Pin Voltage
–VS to +VS
Storage Temperature Range
–65°C to +125°C
Junction Temperature (TJ)
+150°C
ESD Ratings:
Human Body Model (HBM) (2)
1000V
Charge Device Model (CDM)
1000V
Machine Model (MM)
(1)
(2)
2
150V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Pin 2 for the SO-14 package and pin 1 for the MSOP-10 package > 500V HBM.
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OPA615
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BLOCK DIAGRAMS
SO−14
MSOP−10
Ground
9
CHO LD
Base
4
Ground
3
6
2
Hold
Control
7
S/H
In+
10
S/H
In−
11
12
SOTA ∞
1
Biasing
3
2
1
Hold
Control
OTA
Base
Emitter
Switching
Stage
Sampling
Comparator (SC)
CHO LD
5
Sampling
Comparator (SC)
Collector
(IO UT )
IQ Adjust
S/H
In+
7
S/H
In−
8
Emitter
Switching
Stage
9
OTA
SOTA ∞
Collector
(IO U T )
Biasing
OPA615
OPA615
13
5
10
−VC C
+VCC
4
−VC C
+VCC
PIN CONFIGURATIONS
Top View
IQ Adjust
1
14
NC(1)
Emitter, E
1
10
+VCC
Emitter, E
2
13
+VCC
Base, B
2
9
IOUT, Collector, C
Base, B
3
12
IOUT, Collector, C
CHOLD
3
8
S/H In−
11
S/H In−
−VCC
4
7
S/H In+
Hold Control
5
6
Ground
OPA615
CHOLD
4
−VCC
5
10
S/H In+
NC(1)
6
9
Ground
Hold Control
7
8
NC(1)
BJT
MSOP−10
SO−14
NOTE: (1) No Connection.
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OPA615
SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V
RL = 100Ω, RQ = 300Ω, and RIN = 50Ω, unless otherwise noted.
OPA615ID, OPA615IDGS
TYP
PARAMETER
CONDITIONS
AC PERFORMANCE (OTA)
Small-Signal Bandwidth (B to E)
+25°C
MIN/MAX OVER TEMPERATURE
+25°C
(2)
0°C to
70°C (3)
–40°C to
+85°C (3)
UNIT
MIN/
MAX
TEST
LEVEL (1)
See Figure 36b
VO = 200mVPP, RL = 500Ω
710
MHz
min
C
VO = 1.4VPP, RL = 500Ω
770
MHz
min
C
VO = 2.8VPP, RL = 500Ω
230
MHz
min
C
Large-Signal Bandwidth (B to E)
VO = 5VPP, RL = 500Ω
200
MHz
min
C
Small-Signal Bandwidth (B to C)
G = +1, VO = 200mVPP, RL = 100Ω
440
MHz
min
C
G = +1, VO = 1.4VPP, RL = 100Ω
475
MHz
min
C
G = +1, VO = 2.8VPP, RL = 100Ω
230
MHz
min
C
G = +1, VO = 5VPP, RL = 100Ω
230
MHz
min
C
Rise-and-Fall Time (B to E)
VO = 2VPP, RL = 500Ω
2
ns
max
C
Rise-and-Fall Time (B to C)
G = +1, VO = 2VPP, RL = 100Ω
2
ns
max
C
Harmonic Distortion (B to E)
RE = 100Ω
2nd-Harmonic
VO = 1.4VPP, f = 30MHz
–62
–50
–48
–47
dBc
min
B
3rd-Harmonic
VO = 1.4VPP, f = 30MHz
–47
–40
–35
–33
dBc
min
B
Input Voltage Noise
Base Input, f > 100kHz
4.6
6.2
6.9
7.4
nV/√Hz
max
B
Input Current Noise
Base Input, f > 100kHz
2.5
3.1
3.6
3.9
pA/√Hz
max
B
Input Current Noise
Emitter Input, f > 100kHz
21
23
25
27
pA/√Hz
max
B
Large-Signal Bandwidth (B to C)
DC PERFORMANCE (OTA)
Transconductance (V-base to I-collector)
See Figure 37b
VB = ±5mVPP, RC = 0Ω, RE = 0Ω
72
65
63
58
mA/V
min
A
B-Input Offset Voltage
VB = 0V, RC = 0V, RE = 100Ω
±4
±40
±47
±50
mV
max
A
B-Input Offset Voltage Drift
VB = 0V, RC = 0V, RE = 100Ω
±160
±160
μV/°C
max
B
B-Input Bias Current
VB = 0V, RC = 0V, RE = 100Ω
±1.5
±1.7
μA
max
A
B-Input Bias Current Drift
VB = 0V, RC = 0V, RE = 100Ω
±12
±12
nA/°C
max
B
±120
±135
μA
min
A
±200
±250
nA/°C
max
B
±110
±125
μA
max
A
±200
±250
nA/°C
max
B
±3.1
±3.0
E-Input Bias Current
VB = 0V, VC = 0V
E-Input Bias Current Drift
VB = 0V, VC = 0V
C-Output Bias Current
VB = 0V, VC = 0V
C-Output Bias Current
VB = 0V, VC = 0V
±0.5
±35
±35
±0.9
±110
±100
INPUT (OTA Base)
See Figure 37b
Input Voltage Range
RE = 100Ω
±3.4
B-Input
7 || 1.5
±VS to VIO at E-Input
54
49
47
46
Input Impedance
OTA Power-Supply Rejection Ratio
(–PSRR)
±3.2
V
min
B
MΩ || pF
typ
C
dB
min
A
A
OUTPUT (OTA Collector)
See Figure 37b
Output Voltage Compliance
IE = 2mA
±3.5
±3.4
±3.4
±3.4
V
min
Output Current
VC = 0V
±20
±18
±17
±17
mA
min
A
Output Impedance
VC = 0V
1.2 || 2
MΩ || pF
typ
C
B
COMPARATOR PERFORMANCE
AC Performance
Output Current Bandwidth
IO < 4mAPP
730
520
480
400
MHz
min
IIO = ±2mAPP, RL = 50Ω at CHOLD
1.4
1.5
1.7
2
ns
max
B
Control Propagation Delay Time
Hold ≥ Track and Track ≥ Hold
2.5
ns
typ
C
Signal Propagation Delay Time
S/H In+ – S/H In– to CHOLD Current
1.9
C
Input Differential Voltage Noise
S/H In+ – S/H In–
6
Track-to-Hold
Hold Mode, VIN = 1VPP, f < 20MHz
Output Current Rise and Fall Time
Charge Injection
Feedthrough Rejection
(1)
(2)
(3)
4
ns
typ
nV/√Hz
max
B
40
fC
typ
C
100
dB
typ
C
7.5
8
9
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C tested specifications.
Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over
temperature specifications.
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ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
RL = 100Ω, RQ = 300Ω, and RIN = 50Ω, unless otherwise noted.
OPA615ID, OPA615IDGS
TYP
PARAMETER
CONDITIONS
+25°C
MIN/MAX OVER TEMPERATURE
+25°C
(2)
0°C to
70°C (3)
–40°C to
+85°C (3)
UNIT
MIN/
MAX
TEST
LEVEL (1)
A
DC Performance
Input Bias Current
Output Offset Current
Input Impedance
Input Differential Voltage Range
Input Common-Mode Voltage Range
S/H In+ = S/H In– = 0V
±1
±3
±3.5
±4.0
μA
max
S/H In+ = S/H In– = 0V, Track Mode
±10
±50
±70
±80
μA
max
A
S/H In+ and S/H In–
200 || 1.2
kΩ || pF
typ
C
S/H In+ – S/H In–
±3.0
V
typ
C
S/H In+ and S/H In–
±3.2
V
typ
C
μA/V
max
A
V
typ
C
Common-Mode Rejection Ratio (CMRR)
±2
Output Voltage Compliance
CHOLD Pin
Output Current
CHOLD Pin
±5
Output Impedance
CHOLD Pin
0.5 || 1.2
Transconductance
S/H In+ – S/H In– to CHOLD Current
VIN = 300mVPP
35
±50
±55
±60
±3.5
±3
21
±2.5
20
±2.0
mA
min
A
MΩ || pF
typ
C
19
mA/V
min
A
Minimum Hold Logic High Voltage
Tracking High
2
2
2
V
max
A
Maximum Hold Logic Low Voltage
Holding Low
0.8
0.8
0.8
V
min
A
Logic High Input Current
VHOLD = +5V
±0.5
±1
±1
±1.2
μA
max
A
Logic Low Input Current
VHOLD = 0V
140
200
220
230
μA
max
A
±2
±50
±55
±60
μA/V
max
A
V
typ
C
Minimum Operating Voltage
±4
±4
±4
V
min
B
Maximum Operating Voltage
±6.2
±6.2
±6.2
V
max
A
Comparator Power-Supply Rejection
Ratio (PSRR)
S/H In+ = S/H In– = 0V, Track Mode
POWER SUPPLY
Specified Operating Voltage
±5
Maximum Quiescent Current
RQ = 300Ω (4)
13
14
16
17
mA
max
A
Minimum Quiescent Current
RQ = 300Ω (4)
13
12
11
9
mA
min
A
–40 to +85
°C
typ
C
THERMAL CHARACTERISTICS
Specified Operating Range D Package
Thermal Resistance θ JA
Junction-to-Ambient
DGS
MSOP-10
125
°C/W
typ
C
D
SO-14
100
°C/W
typ
C
(4)
SO-14 package only.
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OPA615
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TYPICAL CHARACTERISTICS
TA = +25°C and IQ = 13mA, unless otherwise noted.
OTA
OTA TRANSCONDUCTANCE vs FREQUENCY
120
80
IQ = 13mA (72mA/V), RQ = 300Ω
VIN = 100mVPP
50Ω
50Ω
Transconductance (mA/V)
Transconductance (mA/V)
VIN
IQ = 14.3mA (89mA/V), RQ = 0Ω
120
IOUT
VIN = 10mVPP
100
OTA TRANSCONDUCTANCE vs QUIESCENT CURRENT
60
40
IQ = 9.6mA (28mA/V), RQ = 2kΩ
20
0
100
80
60
IOUT
VIN
40
30
0
10k
1M
10M
100M
1G
8
9
10
Frequency (Hz)
13
14
15
OTA TRANSFER CHARACTERISTICS
100
20
90
15
I O UT
IQ = 14.3mA
OTA Output Current (mA)
Transconductance (mA/V)
12
Figure 2.
OTA TRANSCONDUCTANCE vs INPUT VOLTAGE
80
70
60
IQ = 13mA
50
I Q = 9.6mA
40
VIN
50Ω
10
50Ω
5
0
−5
IQ = 13mA
IQ = 9.6mA
−10
IQ = 14.3mA
−15
30
Small−Signal Around Input Voltage
20
−50 −40 −30 −20 −10 0
10
20
30
40
−20
−200
50
−150
−100
Input Voltage (mV)
0
50
100
150
200
Figure 4.
OTA-C SMALL SIGNAL PULSE RESPONSE
OTA-C LARGE SIGNAL PULSE RESPONSE
0.15
3
fIN = 10MHz
G = +1V/V
VIN = 0.2VPP
2
Output Voltage (V)
0.10
−50
OTA Input Voltage (mV)
Figure 3.
Output Voltage (V)
11
Quiescent Current (mA)
Figure 1.
0.05
0
−0.05
−0.10
fIN = 10MHz
G = +1V/V
VIN = 4VPP
1
0
−1
−2
−0.15
−3
Time (10ns/div)
Time (10ns/div)
Figure 5.
6
50Ω
50Ω
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
TA = +25°C and IQ = 13mA, unless otherwise noted.
OTA B-INPUT RESISTANCE vs QUIESCENT CURRENT
OTA C-OUTPUT RESISTANCE vs QUIESCENT CURRENT
18
OTA C−Output Resistance (MΩ )
OTA B−Input Resistance (MΩ )
140
120
100
80
60
40
20
0
16
14
12
10
8
6
4
2
0
8
9
10
11
12
13
14
15
8
9
10
Quiescent Current (mA)
12
13
14
15
Figure 7.
Figure 8.
OTA E-OUTPUT RESISTANCE vs QUIESCENT CURRENT
OTA INPUT VOLTAGE AND CURRENT NOISE DENSITY
100
160
Voltage Noise Density (nV/√Hz)
Current Noise Density (pA/√Hz)
OTA E−Output Resistance (Ω)
180
140
120
100
80
60
40
20
8
9
10
11
12
13
14
E−Input Current Noise (21.0pA/√Hz)
10
B−Input Voltage Noise (4.6nV/√Hz)
B−Input Current Noise (2.5pA/√Hz)
1
100
0
15
Figure 9.
1.0
0.05
B−Input Bias Current
0
0
−0.5
−0.05
B−Input Offset Voltage
−1.5
−20
0
20
40
60
80
100
−0.10
120
B−Input Bias Current (µV)
1.5
−2.0
−40
100k
1M
10M
OTA TRANSFER CHARACTERISTICS vs INPUT VOLTAGE
0.10
OTA−C Output Current (mA)
2.0
−1.0
10k
Figure 10.
OTA B-INPUT OFFSET VOLTAGE AND BIAS CURRENT
vs TEMPERATURE
0.5
1k
Frequency (Hz)
Quiescent Current (mA)
B−Input Offset Voltage (mV)
11
Quiescent Current (mA)
35
Degenerated E−Input
IQ = 14.3mA
30
RE = RL = 100Ω
25
IO UT
20
100Ω
15 VIN
IQ = 9.6mA
10
100Ω
5
0
IQ = 13mA
−5
−10
−15
−20
−25
−30
−35
−3.5 −3 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5
Ambient Temperature (_ C)
OTA−B Input Voltage (mV)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
TA = +25°C and IQ = 13mA, unless otherwise noted.
OTA-E OUTPUT PULSE RESPONSE
VO = 0.6VPP
VO = 1.4VPP
−3
Gain (dB)
Output Voltage (mV)
0
VO = 5VPP
−6
VO = 2.8VPP
−9
100Ω
V IN
50Ω
−12
VO = 0.2VPP
VO
200
2.0
160
1.6
120
1.2
0.8
80
Large−Signal
±1.6V
Right Scale
40
Small−Signal
±80mV
Left Scale
0
−40
−80
0
−0.4
100Ω
−0.8
VIN
−120
50Ω
VO
500Ω
−160
500Ω
0.4
1M
10M
100M
−1.2
−1.6
−2.0
−200
−15
Output Voltage (V)
OTA-E OUTPUT FREQUENCY RESPONSE
3
Time (20ns/div)
1G
Frequency (Hz)
Figure 13.
Figure 14.
OTA-C OUTPUT FREQUENCY RESPONSE
OTA-E OUTPUT HARMONIC DISTORTION vs FREQUENCY
3
−40
0
−45
VO = 0.6VPP
−3
Gain (dB)
Harmonic Distortion (dBc)
VOUT = 1.4VPP
VO = 1.4VPP
−6
VO = 0.2VPP
VO
−9
V IN
100Ω
VO = 2.8VPP
50Ω
−12
100Ω
−50
3rd−Harmonic
−55
2nd−Harmonic
−60
V IN
−65
50Ω
V OUT
10 0Ω
VO = 5VPP
−70
−15
1M
10M
100M
1
1G
10
Figure 15.
Figure 16.
OTA-C OUTPUT HARMONIC DISTORTION vs FREQUENCY
OTA QUIESCENT CURRENT vs RQ
−20
16
VO U T
VIN
V OUT = 1.4VPP
15
100Ω
50Ω
−30
Quiescent Current (mA)
Harmonic Distortion (dBc)
−25
100Ω
−35
−40
−45
−50
3rd−Harmonic
−55
14
13
12
+IQ
11
10
−IQ
9
2nd−Harmonic
−60
8
1
10
100
0.1
Frequency (MHz)
1
10
100
1k
10k
100k
R Q (Ω)
Figure 17.
8
100
Frequency (MHz)
Frequency (Hz)
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
TA = +25°C and IQ = 13mA, unless otherwise noted.
SOTA (Sampling Operational Transconductance Amplifier)
SOTA TRANSCONDUCTANCE vs FREQUENCY
SOTA TRANSCONDUCTANCE vs QUIESCENT CURRENT
40
40
Transconductance (mA/V)
Transconductance (mA/V)
VIN = 10mVPP
30
20
VIN
10
50Ω
SOTA ∞
IO UT
30
20
10
50Ω
RQ Adjusted
+5V
Hold Control
0
0
1M
10M
100M
8
1G
9
10
Figure 19.
13
14
15
SOTA TRANSFER CHARACTERISTICS
45
8
40
6
SOTA Output Current (mA)
Transconductance (mA/V)
12
Figure 20.
SOTA TRANSCONDUCTANCE vs INPUT VOLTAGE
35
30
25
20
15
10
4
2
0
−2
−4
−6
5
Small−Signal Around Input Voltage
0
−100 −80 −60 −40
−20
0
20
40
60
80
−8
−200
100
−150 −100
Input Voltage (mV)
50
100
150
200
SOTA PULSE RESPONSE
150
fIN = 20MHz
RL = 50Ω
IOUT = 4mAPP
tRISE = 2ns
100
Output Voltage (mV)
100
0
Figure 22.
SOTA PULSE RESPONSE
150
−50
SOTA Input Voltage (mV)
Figure 21.
Output Voltage (mV)
11
Quiescent Current (mA)
Frequency (Hz)
50
0
−50
fIN = 20MHz
RL = 50Ω
IOUT = 4mAPP
tRISE = 10ns
50
0
−50
−100
−100
Hold Control = +5V
−150
Hold Control = +5V
−150
Time (10ns/div)
Time (10ns/div)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
TA = +25°C and IQ = 13mA, unless otherwise noted.
SOTA PROPAGATION DELAY vs OVERDRIVE
SOTA PROPAGATION DELAY vs TEMPERATURE
1.3
2.0
1.8
Propagation Delay (ns)
Propagation Delay (ns)
Negative
1.2
Positive
1.1
1.0
100W
VOD
VOD
SOTA
GND
0.9
VOD
100W
1.6
Falling Edge
1.4
Rising Edge
1.2
1.0
0.8
0.6
0.4
0.2
0
0.8
0
200
400
600
800
1000
−40
1200
−20
0
20
Input Voltage (mV)
40
60
80
100
120
Temperature (_ C)
Figure 25.
Figure 26.
SOTA PROPAGATION DELAY vs SLEW RATE
SOTA SWITCHING TRANSIENTS
1.4
10
100Ω
VOUT
Switching Transient (mV)
Propagation Delay (ns)
1.3
1.2
Negative
1.1
1.0
VIN = 1.2Vpp
+0.6V
0.9
Positive
ON −OFF
50Ω
5
100Ω
TTL
OFF −ON
0
−5
0V
−0.6V
−10
0.8
0
1
2
3
4
5
6
7
8
9
Time (10ns/div)
10
Rise Time (ns)
Figure 28.
SOTA HOLD COMMAND DELAY TIME
SOTA BANDWIDTH vs OUTPUT CURRENT SWING
2.0
1.5
1.0
Output Voltage (mV)
0.5
0
−50
150
100
50
6
IOUT = 0.5mAPP
3
0
Gain (dB)
2.5
Hold Command (V)
Figure 27.
IOUT = 4mAPP
−3
−6
IOUT = 2mAPP
−9
0
−50
−12
−100
−15
−150
Time (10ns/div)
1M
10M
100M
1G
2G
Frequency (Hz)
Figure 29.
10
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
TA = +25°C and IQ = 13mA, unless otherwise noted.
SOTA FEEDTHROUGH REJECTION vs FREQUENCY
SOTA COMMON-MODE REJECTION vs FREQUENCY
−20
0
Hold Control = 0V
(Off−Isolation)
Common−Mode Rejection (dB)
Feedthrough Rejection (dB)
0
−40
−60
−80
−100
−120
1M
10M
100M
−20
Hold Control = 5V
V+ = V−
−40
−60
−80
−100
−120
100k
1G
1M
10M
Frequency (Hz)
1G
Figure 31.
Figure 32.
SOTA INPUT BIAS CURRENT vs TEMPERATURE
SOTA OUTPUT BIAS CURRENT vs TEMPERATURE
50
0.40
40
0.30
Positive Input
0.25
Negative Input
Output Bias Current (µA)
0.35
Input Bias Current (µA)
100M
Frequency (Hz)
0.20
0.15
0.10
Hold Control = 5V
V+ = V− = 0V
30
20
10
0
−10
−20
−30
−40
0.05
0
−40
−20
0
20
40
60
80
100
120
−50
−40
−20
0
20
40
60
80
100
120
Temperature (_ C)
Temperature (_C)
Figure 33.
Figure 34.
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DISCUSSION OF PERFORMANCE
The OPA615, which contains a wideband Operational
Transconductance Amplifier (OTA) and a fast
sampling comparator (SOTA), represents a complete
subsystem for very fast and precise DC restoration,
offset clamping and correction to GND or to an
adjustable reference voltage, and low frequency hum
suppression of wideband operational or buffer
amplifiers.
Although the IC was designed to improve or stabilize
the performance of complex, wideband video signals,
it can also be used as a sample-and-hold amplifier,
high-speed integrator, peak detector for nanosecond
pulses, or as part of a correlated double sampling
system. A wideband Operational Transconductance
Amplifier (OTA) with a high-impedance cascode
current source output and a fast and precise
sampling comparator sets a new standard for
high-speed sampling applications.
Both the OTA and the sampling comparator can be
used as stand-alone circuits or combined to create
more complex signal processing stages such as
sample-and-hold amplifiers. The OPA615 simplifies
the design of input amplifiers with high hum
suppression; clamping or DC-restoration stages in
professional broadcast equipment, high-resolution
CAD monitors and information terminals; and signal
processing stages for the energy and peak value of
nanoseconds pulses. This device also eases the
design of high-speed data acquisition systems behind
a CCD sensor or in front of an analog-to-digital
converter (ADC).
An external resistor on the SO-14 package, RQ,
allows the user to set the quiescent current. RQ is
connected from Pin 1 (IQ adjust) to –VCC. It
determines the operating currents of the OTA section
and controls the bandwidth and AC behavior as well
as the transconductance of the OTA.
Besides the quiescent current setting feature, a
Proportional-to-Absolute-Temperature (PTAT) supply
current control will increase the quiescent current
versus temperature. This variation holds the
transconductance (gm) of the OTA and comparator
relatively constant versus temperature. The circuit
parameters listed in the specification table are
measured with RQ set to 300Ω, giving a nominal
quiescent current at 13mA. While not always shown
in the application circuits, this RQ = 300Ω is required
to get the 13mA quiescent operating current.
12
OPERATIONAL TRANSCONDUCTANCE
AMPLIFIER (OTA) SECTION
OVERVIEW
The symbol for the OTA section is similar to that of a
bipolar transistor, and the self-biased OTA can be
viewed as either a quasi-ideal transistor or as a
voltage-controlled current source. Application circuits
for the OTA look and operate much like transistor
circuits—the
bipolar
transistor
is
also
a
voltage-controlled current source. Like a transistor, it
has three terminals: a high-impedance input (base)
optimized for a low input bias current of 0.3μA, a
low-impedance input/output (emitter), and the
high-impedance current output (collector).
The OTA consists of a complementary buffer
amplifier and a subsequent complementary current
mirror. The buffer amplifier features a Darlington
output stage and the current mirror has a cascoded
output. The addition of this cascode circuitry
increases the current source output resistance to
1.2MΩ. This feature improves the OTA linearity and
drive capabilities. Any bipolar input voltage at the
high impedance base has the same polarity and
signal level at the low impedance buffer or emitter
output. For the open-loop diagrams, the emitter is
connected to GND; the collector current is then
determined by the voltage between base and emitter
times the transconductance. In application circuits
(Figure 36b), a resistor RE between the emitter and
GND is used to set the OTA transfer characteristics.
The following formulas describe the most important
relationships. re is the output impedance of the buffer
amplifier (emitter) or the reciprocal of the OTA
transconductance. Above ±5mA, the collector current,
IC, will be slightly less than indicated by the formula.
IC +
V IN
r E ) RE
or
RE +
V IN
* rE
IC
(1)
The RE resistor may be bypassed by a relatively large
capacitor to maintain high AC gain. The parallel
combination of RE and this large capacitor form a
high-pass filter, enhancing the high frequency gain.
Other cases may require an RC compensation
network in parallel to RE to optimize the
high-frequency response. The large-signal bandwidth
(VO = 1.4VPP) measured at the emitter achieves
770MHz. The frequency response of the collector is
directly related to the resistor value between the
collector and GND; it decreases with increasing
resistor values, because of the low-pass filter formed
with the OTA C-output capacitance.
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Figure 35 shows a simplified block diagram of the
OPA615 OTA. Both the emitter and the collector
outputs offer a drive capability of ±20mA for driving
low impedance loads. The emitter output is not
current-limited or protected. Momentary shorts to
GND should be avoided, but are unlikely to cause
permanent damage.
+VCC
(13)
B
(3)
E
(2)
+1
While the OTA function and labeling appear similar to
those of a transistor, it offers essential distinctive
differences and improvements: 1) The collector
current flows out of the C terminal for a positive
B-to-E input voltage and into it for negative voltages;
2) A common emitter amplifier operates in
non-inverting mode while the common base operates
in inverting mode; 3) The OTA is far more linear than
a bipolar transistor; 4) The transconductance can be
adjusted with an external resistor; 5) As a result of
the PTAT biasing characteristic, the quiescent current
increases as shown in the typical performance curve
vs temperature and keeps the AC performance
constant; 6) The OTA is self-biased and bipolar; and
7) The output current is approximately zero for zero
differential input voltages. AC inputs centered on zero
produce an output current centered on zero.
BASIC APPLICATION CIRCUITS
C
(12)
Most application circuits for the OTA section consist
of a few basic types which are best understood by
analogy to discrete transistor circuits. Just as the
transistor has three basic operating modes—common
emitter, common base, and common collector—the
OTA has three equivalent operating modes;
common-E, common-B, and common-C (see
Figure 36, Figure 37 and Figure 38). Figure 36 shows
the OTA connected as a Common-E amplifier, which
is equivalent to a common emitter transistor amplifier.
Input and output can be ground-referenced without
any biasing. The amplifier is noninverting because a
current flowing out of the emitter will also flow out of
the collector as a result of the current mirror shown in
Figure 35.
+VCC
(5)
Figure 35. Simplified OTA Block Diagram
V+
RB
RL
VO
100Ω
Inverting Gain
VOS ≈ several volts
VI
RB
VI
VO
12
C
3 B
OTA
RL
NoninvertingGain
VOS ≈ 0
E
2
RE
RE
V−
Single Transistor
(b) Common−E Amplifier for OTA
(a) Common Emitter Amplifier
Transconductance varies over temperature.
Transconductance remains constant over temperature.
Figure 36. a) Common Emitter Amplifier Using a Discrete Transistor; b) Common-E Amplifier Using the
OTA Portion of the OPA615
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Figure 37 shows the Common-C amplifier. It
constitutes an open-loop buffer with low offset
voltage. Its gain is approximately 1 and will vary with
the load.
12
C
V+
100Ω
VI
Figure 38 shows the Common-B amplifier. This
configuration produces an inverting gain, and the
input is low-impedance. When a high impedance
input is needed, it can be created by inserting a
buffer amplifier (such as the BUF602) in series.
3 B
V+
OTA
G≈1
VOS ≈ 0
G=−
RL
E
2
VI
VO
RE
V−
Single Transistor
(a) Common Collector Amplifier
(Emitter Follower)
RE
G=
RO =
1
1+
gm x RE
100Ω
RE
≈ 1
3 B
≈ −
RL
RE
12
C
OTA
VO
Inverting Gain
VOS ≈ 0
RL
E
2
VI
Single Transistor
(a) Common−Base
Amplifier
1
gm
Figure 37. a) Common Collector Amplifier Using
a Discrete Transistor; b) Common-C Amplifier
Using the OTA Portion of the OPA615
14
Noninverting Gain
VOS ≈ several volts
(b) Common−C Amplifier for OTA
(Buffer)
1
1
gm
VO
VO
G≈1
VOS ≈ 0.7V
RL
RE +
RE
VI
(b) Common−B Amplifier for OTA
Figure 38. a) Common Base Amplifier Using a
Discrete Transistor; b) Common-B Amplifier
Using the OTA Portion of the OPA615
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SAMPLING COMPARATOR
The OPA615 sampling comparator features a very
short switching (2.5ns) propagation delay and utilizes
a new switching circuit architecture to achieve
excellent speed and precision.
It provides high impedance inverting and noninverting
analog inputs, a high-impedance current source
output and a TTL-CMOS-compatible Hold Control
Input.
The sampling comparator consists of an operational
transconductance amplifier (OTA), a buffer amplifier,
and a subsequent switching circuit. This combination
is subsequently referred to as the Sampling
Operational Transconductance Amplifier (SOTA). The
OTA and buffer amplifier are directly tied together at
the buffer outputs to provide the two identical
high-impedance
inputs
and
high
open-loop
transconductance. Even a small differential input
voltage multiplied with the high transconductance
results
in
an
output
current—positive
or
negative—depending upon the input polarity. This
characteristic is similar to the low or high status of a
conventional comparator. The current source output
features high output impedance, output bias current
compensation, and is optimized for charging a
capacitor in DC restoration, nanosecond integrators,
peak detectors and S/H circuits. The typical
comparator output current is ±5mA and the output
bias current is minimized to typically ±10μA in the
sampling mode.
This innovative circuit achieves the high slew rate
representative of an open-loop design. In addition,
the acquisition slew current for a hold or storage
capacitor is higher than standard diode bridge and
switch configurations, removing a main contributor to
the limits of maximum sampling rate and input
frequency.
The switching circuits in the OPA615 use current
steering (versus voltage switching) to provide
improved isolation between the switch and analog
sections. This design results in low aperture time
sensitivity to the analog input signal, reduced power
supply and analog switching noise. Sample-to-hold
peak switching charge injection is 40fC.
The additional offset voltage or switching transient
induced on a capacitor at the current source output
by the switching charge can be determined by the
following formula:
Offset (V) +
Charge (pC)
CHTotal (pF)
(2)
The switching stage input is insensitive to the low
slew rate performance of the hold control command
and compatible with TTL/CMOS logic levels. With
TTL logic high, the comparator is active, comparing
the two input voltages and varying the output current
accordingly. With TTL logic low, the comparator
output is switched off, showing a very high
impedance to the hold capacitor.
DESIGN-IN TOOLS
Demonstration Fixture
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA615. The demonstration fixture is
offered free of charge as an unpopulated PCB,
delivered with a user's guide. The summary
information for this fixture is shown in Table 2.
Table 2. OPA615 Demonstration Fixtures
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA615ID
SO-14
DEM-OPA-SO-1C
SBOU039
OPA615IDGS
MSOP-10
DEM-OPA-MSOP-1A
SBOU042
The demonstration fixture can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA615 product folder.
Macromodel and Applications Support
Computer simulation of circuit performance using
SPICE is often a quick way to analyze the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the OPA615 is available through the TI web page
(www.ti.com). This model predicts typical small-signal
AC, transient steps, DC performance, and noise
under a wide variety of operating conditions. The
model includes the noise terms found in the electrical
specifications of the data sheet. However, the model
does not attempt to distinguish between package
types in their small-signal AC performance. The
applications department is also available for design
assistance.
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APPLICATION INFORMATION
The OPA615 operates from ±5V power supplies
(±6.2V maximum). Absolute maximum is ±6.5V. Do
not attempt to operate with larger power supply
voltages or permanent damage may occur.
Power-supply bypass capacitors should be located as
close as possible to the device pins. Solid tantalum
capacitors are generally best. See Board Layout at
the end of the applications discussion for further
suggestions on layout.
BASIC CONNECTIONS
Figure 39 shows the basic connections required for
operation. These connections are not shown in
subsequent circuit diagrams.
RB
(25Ω to 200Ω)
CHOLD
9 GND
4
3 Base
2
(20Ω
to
200Ω)
Hold 7
Control
Switching Stage
Emitter
OTA
12
Collector
Sampling Comparator
(SC)
S/H In+
10
SOTA ∞
Biasing
1
IQ Adjust
S/H In−
11
RQ
13
+VCC
+5V
+
2.2µF
10nF
470pF
5
RQ = 300Ω sets approximately
I Q = 13mA
−VCC
−5V
470pF
10nF
+
2.2µF
Solid Tantalum
Figure 39. Basic Connections
16
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DC-RESTORE SYSTEM
Figure 40 and Figure 41 offer two possible
DC-restore systems using the OPA615. Figure 41
implements a DC-restore function as a unity-gain
amplifier. As can be expected from its name, this
DC-restore circuit does not provide any amplification.
HCL
7
SOTA
4
In applications where some amplification is needed,
consider using the circuit design shown in Figure 40.
10
100Ω
11
12
CHOLD
OPA615
100Ω
100Ω
OTA
3
HCL
10
7
VOUT
2
VIN
100Ω
4
SOTA
11
OPA615
12
CHOLD
3
OTA
VOUT
2
VIN
Figure 41. DC Restoration of a Buffer Amplifier
100Ω
100Ω
= VIN x
R1
For either of these circuits to operate properly, the
source impedance needs to be low, such as the one
provided by the output of a closed-loop amplifier or
buffer. Consider the video input signal shown in
Figure 42, and the complete DC restoration system
shown in Figure 40. This signal is amplified by the
OTA section of the OPA615 by a gain of:
R2
R1
R2
Figure 40. Complete DC Restoration System
G+)
100
89
70
59
41
W
Y
CY GRN MAG
30
R
R2
R1
11
0
BLU BLK
100
IRE UNITS
60
40
7.5
20
10
0
40 IRE
1VPP
80
−20
BACK PORCH
−40
BLANKING
LUMINANCE + CHROMINANCE
FRONT PORCH
SYNC TIP
BREEZEWAY
COLOR BURST
Figure 42. NTSC Horizontal Scan Line
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The DC restoration is done by the SOTA section by
sampling the output signal at an appropriate time.
The sampled section of the signal is then compared
to a reference voltage that appears on the
non-inverting input of the SOTA (pin 10), or ground in
Figure 40.
When the SOTA is sampling, it is charging or
discharging the CHOLD capacitor depending on the
level of the output signal sampled. The detail of an
appropriate timing is illustrated in Figure 43.
100
0V
IRE UNITS
Input Voltage
80
60
40
7.5
20
10
0
−20
−40
HCL
Sample
Hold
100
Output Voltage
IRE UNITS
80
0V
60
40
7.5
20
10
0
−20
−40
Figure 43. DC-Restore Timing
18
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CLAMPED VIDEO/RF AMPLIFIER
Another circuit example for the preamplifier and the
clamp circuit is shown in Figure 44. The preamplifier
uses the wideband, low noise OPA656, again
configured in a gain of +2V/V. Here, the OPA656 has
a typical bandwidth of 200MHz with a settling time of
about 21ns (0.02%) and offers a low bias current
JFET input stage.
HCL
100Ω
7
2
11
4
OTA
3
OPA615
SAMPLE-AND-HOLD AMPLIFIER
With a control propagation delay of 2.5ns and
730MHz bandwidth, the OPA615 can be used
advantageously in a high-speed sample-and-hold
amplifier. Figure 45 illustrates this configuration.
CHOLD
RE
The external capacitor (CHOLD) allows for a wide
range of flexibility. By choosing small values, the
circuit can be optimized for a short clamping period or
with high values for a low droop rate. Another
advantage of this circuit is that small clamp peaks at
the output of the switching comparator are integrated
and do not cause glitches in the signal path.
100Ω
VREF
Hold /Track
SOTA
10
12
100Ω
R1
R2
300Ω
150Ω
VIN
100Ω
300Ω
50Ω
CB
11
12
OPA615
10
7
SOTA
100Ω
4
CHOLD
22pF
3
OTA
2
50Ω
VOUT
OPA656
VOUT
300Ω
• Current Control
VIN
RB
• Non−Inverting
300Ω
Figure 44. Clamped Video/RF Amplifier
Figure 45. Sample-and-Hold Amplifier
The video signal passes through the capacitor CB,
blocking the DC component. To restore the DC level
to the desired baseline, the OPA615 is used. The
inverting input (pin 11) is connected to a reference
voltage. During the high time of the clamp pulse, the
switching comparator (SOTA) will compare the output
of the op amp to the reference level. Any voltage
difference between those pins will result in an output
current that either charges or discharges the hold
capacitor, CHOLD. This charge creates a voltage
across the capacitor, which is buffered by the OTA.
Multiplied by the transconductance, the voltage will
cause a current flow in the collector, C, terminal of
the OTA. This current will level-shift the OPA656 up
to the point where its output voltage is equal to the
reference voltage. This level-shift also closes the
control loop. Because of the buffer, the voltage
across the CHOLD stays constant and maintains the
baseline correction during the off-time of the clamp
pulse.
To illustrate how the digitization is realized in the
Figure 45 circuit, Figure 46 shows a 100kHz
sinewave being sampled at a rate of 1MHz. The
output signal used here is the IOUT output driving a
50Ω load.
1MHz SAMPLE−AND−HOLD OF A 100kHz SINEWAVE
5
Output Voltage (V)
3
2
1
+2.5
0
+1.5
+0.5
−0.5
Hold−and−Track Signal (V)
4
−1.5
−2.5
Time (1µs/div)
Figure 46. 1MHz Sample-and-Hold of a 100kHz
Sine Wave
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Integrator for ns-Pulses
Phase Detector for Fast PLL Systems
The integrator for ns-pulses using the OPA615
(shown in Figure 47) makes use of the fast
comparator and its current-mode output. Placing the
hold-control high, a narrow pulse charges the
capacitor, increasing the average output voltage. To
minimize ripples at the inverting input and maximize
the capacitor charge, a T-network is used in the
feedback path.
Figure 49 shows the circuit for a phase detector for
fast PLL systems. Given a reference pulse train fREF
and a pulse train input signal fIN out of phase, the
SOTA of the OPA615 acts in this circuit as a
comparator, either charging or discharging the
capacitor. This voltage is then buffered by the OTA
and fed to the VCO.
Hold Control
150Ω
VIN
10
SOTA
50Ω
4
OTA
10
f IN
50Ω
75Ω
VOUT
620Ω
SOTA
4
7
27pF
2
12
OPA615
100Ω
100Ω
3
11
11
fR EF
12
7
75Ω
OTA
3
C IN T
2
75Ω
VO UT
+5V
820Ω
1µF
f IN
√N
fO UT
fR EF
Figure 47. Integrator for ns-Pulses
fIN
Fast Pulse Peak Detector
I OU T
A circuit similar to that shown in Figure 47 (the
integrator for ns-pulses) can be devised to detect and
isolate positive pulses from negative pulses. This
circuit, shown in Figure 48, uses the OPA615 as well
as the BUF602. This circuit makes use of diodes to
isolate the positive-going pulses from the
negative-going
pulses
and
charge-different
capacitors.
Hold Control
50Ω
100Ω
4
150Ω
50Ω
10
11
VOU T
Phase
fR EF
fO UT = f RE F x N
Figure 49. Phase Detector For Fast PLL-Systems
−VOUT
8
27pF
100Ω
VIN
+1
VOU T
VCO
BUF602
12
7
SOTA
100Ω
4
3
27pF
OPA615
OTA
2
50Ω
+VOUT
300Ω
Figure 48. Fast Bipolar Peak Detector
20
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OPA615
www.ti.com...................................................................................................................................... SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009
CORRELATED DOUBLE SAMPLER
The signal coming from the CCD is applied to the two
sample-and-hold amplifiers, with their outputs
connected to the difference amplifier. The timing
diagram clarifies the operation (see Figure 52). At
time t1, the sample and hold (S/H1) goes into the hold
mode, taking a sample of the reset level including the
noise. This voltage (VRESET) is applied to the
noninverting input of the difference amplifier. At time
t2, the sample-and-hold (S/H2) will take a sample of
the video level, which is VRESET – VVIDEO. The output
voltage of the difference amplifier is defined by the
equation VOUT = VIN+ – VIN–. The sample of the reset
voltage contains the kT/C noise, which is eliminated
by the subtraction of the difference amplifier.
Noise is the limiting factor for the resolution in a CCD
system, where the kT/C noise is dominant (see
Figure 51). To reduce this noise, imaging systems
use a circuit called a Correlated Double Sampler
(CDS). The name comes from the double sampling
technique of the CCD charge signal. A CDS using
two OPA615s and one OPA694 is shown in
Figure 50. The first sample (S1) is taken at the end of
the reset period. When the reset switch opens again,
the effective noise bandwidth changes because of the
large difference in the switch RON and ROFF
resistance. This difference causes the dominating
kT/C noise essentially to freeze in its last point.
The double sampling technique also reduces the
white noise. The white noise is part of the reset
voltage (VRESET) as well as of the video amplitude
(VRESET – VVIDEO). With the assumption that the noise
of the noise of the second sample was unchanged
from the instant of the first sample, the noise
amplitudes are the same and are correlated in time.
Therefore, the noise can be reduced by the CDS
function.
The other sample (S2) is taken during the video
portion of the signal. Ideally, the two samples differ
only by a voltage corresponding to the transferred
charge signal. This is the video level minus the noise
(ΔV).
The CDS function will eliminate the kT/C noise as
well as much of the 1/f and white noise.
Figure 52 is a block diagram of a CDS circuit. Two
sample-and-hold amplifiers and one difference
amplifier constitute the correlated double sampler.
VHOLD1
100Ω
VIN1
50Ω
11
12
7
10
100Ω
SOTA
4
402Ω
3
OTA
27pF
402Ω
2
300Ω
402Ω
OPA694
VOUT
300Ω
402Ω
VHOLD2
100Ω
VIN2
50Ω
11
12
7
10
100Ω
SOTA
4
3
OTA
27pF
2
300Ω
300Ω
Figure 50. Correlated Double Sampler
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Product Folder Link(s): OPA615
21
OPA615
SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
Simplified CCD Output Signal
S1
kT/C −Noise PP
∆V
Reset Level
S2
Video Level
NOTE: Signals are out of scale.
Figure 51. Improving SNR with Correlated Double Sampling
S/H1
VRESET
VOUT = VIN+ − VIN−
VIN
S/H2
t2
Video Hold
VIN
VRESET − VVIDEO
Difference
Amplifier
t1
Reset Hold
S1
t1
S2
t2
0V
Video Out
Figure 52. CDS: Circuit Concept
22
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Product Folder Link(s): OPA615
OPA615
www.ti.com...................................................................................................................................... SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a highfrequency amplifier such as the OPA615 requires
careful attention to printed circuit board (PCB) layout
parasitics
and
external
component
types.
Recommendations that will optimize performance
include:
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them.
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability; on the non-inverting input, it can
react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
e) Socketing a high-speed part such as the
OPA615 is not recommended. The additional lead
length and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome parasitic
network which can make it almost impossible to
achieve a smooth, stable frequency response. Best
results are obtained by soldering the OPA615 directly
onto the PCB.
b) Minimize the distance (< 0.25") from the power
supply pins to high frequency 0.1μF decoupling
capacitors. At the device pins, the ground and power
plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground
traces to minimize inductance between the pins and
the decoupling capacitors. The power-supply
connections should always be decoupled with these
capacitors. An optional supply-decoupling capacitor
across the two power supplies (for bipolar operation)
will improve 2nd-harmonic distortion performance.
Larger (2.2μF to 6.8μF) decoupling capacitors,
effective at a lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PCB.
The OPA615 is built using a very high-speed,
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table
where an absolute maximum ±6.5V supply is
reported. All device pins have limited ESD protection
using internal diodes to the power supplies, as shown
in Figure 53.
c) Careful selection and placement of external
components will preserve the high frequency
performance of the OPA615. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep these leads and PCB trace length as
short as possible. Never use wirewound-type
resistors in a high frequency application. Other
network components, such as noninverting input
termination resistors, should also be placed close to
the package.
INPUT AND ESD PROTECTION
+VCC
External
Pin
Internal
Circuitry
−VCC
Figure 53. Internal ESD Protection
These diodes also provide moderate protection to
input overdrive voltages above the supplies. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA615), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible since high
values degrade both noise performance and
frequency response.
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Product Folder Link(s): OPA615
23
OPA615
SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2008) to Revision E ................................................................................................ Page
•
Corrected y-axis title of Figure 25 ....................................................................................................................................... 10
Changes from Revision C (October 2006) to Revision D ............................................................................................... Page
•
Changed rating for storage temperature range in Absolute Maximum Ratings table from –40°C to +125°C to –65°C
to +125°C .............................................................................................................................................................................. 2
•
Clarified hold control pin voltage rating in Absolute Maximum Ratings table ....................................................................... 2
24
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Copyright © 2004–2009, Texas Instruments Incorporated
Product Folder Link(s): OPA615
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA615ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA615ID
OPA615IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BJT
OPA615IDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BJT
OPA615IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA615ID
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA615IDGSR
VSSOP
DGS
10
OPA615IDGST
VSSOP
DGS
OPA615IDR
SOIC
D
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA615IDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
OPA615IDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
OPA615IDR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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