Texas Instruments | THS4211, THS4215: Low-Distortion High-Speed Voltage Feedback Amplifier (Rev. E) | Datasheet | Texas Instruments THS4211, THS4215: Low-Distortion High-Speed Voltage Feedback Amplifier (Rev. E) Datasheet

Texas Instruments THS4211, THS4215: Low-Distortion High-Speed Voltage Feedback Amplifier (Rev. E) Datasheet
DGN-8
DGK-8
D-8
THS4211
THS4215
DRB-8
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
LOW-DISTORTION, HIGH-SPEED, VOLTAGE FEEDBACK AMPLIFIER
Check for Samples: THS4211 THS4215
FEATURES
1
•
•
•
•
23
•
•
•
•
•
DESCRIPTION
Unity-Gain Stability
Wide Bandwidth: 1 GHz
High Slew Rate: 970 V/µs
Low Distortion:
– –90 dBc THD at 30 MHz
– 130-MHz Bandwidth (0.1 dB, G = 2)
– 0.007% Differential Gain
– 0.003° Differential Phase
High Output Drive, IO = 170 mA
Excellent Video Performance:
– 130-MHz Bandwidth (0.1 dB, G = 2)
– 0.007% Differential Gain
– 0.003° Differential Phase
Supply Voltages
– +5 V, ±5 V, +12 V, +15 V
Power Down Functionality (THS4215)
Evaluation Module Available
The THS4211 and THS4215 are high slew rate,
unity-gain stable, voltage feedback amplifiers
designed to run from supply voltages as low as 5 V
and as high as 15 V. The THS4215 offers the same
performance as the THS4211 with the addition of
power-down capability. The combination of high slew
rate, wide bandwidth, low distortion, and unity-gain
stability make the THS4211 and THS4215
high-performance devices across multiple ac
specifications.
Designers using the THS4211 are rewarded with
higher dynamic range over a wider frequency band
without the stability concerns of decompensated
amplifiers. These devices are available in SOIC,
MSOP with PowerPAD™, and leadless MSOP with
PowerPAD packages.
RELATED DEVICES
DEVICE
APPLICATIONS
•
•
•
•
•
High Linearity ADC Preamplifier
Differential to Single-Ended Conversion
DAC Output Buffer
Active Filtering
Video Applications
DESCRIPTION
THS4271
1.4-GHz voltage feedback amplifier
THS4503
Wideband, fully differential amplifier
THS3202
Dual, wideband current feedback amplifier
THS4211
NC
ININ+
VS-
Low-Distortion, Wideband Application Circuit
7
3
6
4
5
NC
VS+
VOUT
NC
-50
50 Ω
Gain = 2
Rf = 392 Ω
RL = 150 Ω
VO = 2 VPP
VS = ±5 V
-55
49.9 Ω
THS4211
_
-5 V
392 Ω
392 Ω
NOTE: Power supply decoupling capacitors not shown
VO
Harmonic Distortion - dBc
+
VI
8
2
HARMONIC DISTORTION
vs
FREQUENCY
+5 V
50 Ω Source
1
-60
-65
-70
-75
-80
HD2
-85
HD3
-90
-95
-100
1
10
f - Frequency - MHz
100
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2009, Texas Instruments Incorporated
THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted). (1)
UNIT
Supply voltage, VS
16.5 V
Input voltage, VI
±VS
Output current, IO
250 mA
Continuous power dissipation
Maximum junction temperature, TJ
See Dissipation Ratings Table
(2)
+150°C
Maximum junction temperature, continuous operation, long-term reliability TJ
(3)
+125°C
Storage temperature range, Tstg
ESD ratings
(1)
(2)
(3)
–65°C to +150°C
HBM
4000 V
CDM
1500 V
MM
200 V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS (1)
(1)
(2)
(3)
POWER RATING
(3)
PACKAGE
θJC
(°C/W)
θJA (2)
(°C/W)
TA≤ +25°C
TA= +85°C
D (8-pin)
38.3
97.5
1.02 W
410 mW
DGN (8-pin) (1)
4.7
58.4
1.71 W
685 mW
DGK (8-pin)
54.2
260
385 mW
154 mW
DRB (8-pin)
5
45.8
2.18 W
873 mW
The THS4211/5 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long
term reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, (VS+ and VS–)
Dual supply
Single supply
Input common-mode voltage range
2
Submit Documentation Feedback
MIN
MAX
±2.5
±7.5
5
15
VS– + 1.2
VS+ – 1.2
UNIT
V
V
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
PACKAGING/ORDERING INFORMATION (1)
PACKAGED DEVICES
PACKAGE TYPE
PACKAGE MARKING
SOIC-8
—
MSOP-8
BEJ
QFN-8-PP (2)
BET
MSOP-8-PP (2)
BFN
SOIC-8
—
MSOP-8
BEZ
QFN-8-PP (2)
BEU
MSOP-8-PP (2)
BFQ
TRANSPORT MEDIA, QUANTITY
Non-power-down
THS4211D
THS4211DR
THS4211DGK
THS4211DGKR
THS4211DRBT
THS4211DRBR
THS4211DGN
THS4211DGNR
Rails, 75
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Rails, 80
Tape and Reel, 2500
Power-down
THS4215D
THS4215DR
THS4215DGK
THS4215DGKR
THS4215DRBT
THS4215DRBR
THS4215DGN
THS4215DGNR
(1)
(2)
Rails, 75
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Rails, 80
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The PowerPAD is electrically isolated from all other pins.
PIN ASSIGNMENTS
(TOP VIEW)
D, DRB, DGK, DGN
THS4211
NC
1
8
NC
IN-
2
7
IN+
3
VS-
4
(TOP VIEW)
D, DRB, DGK, DGN
THS4215
REF
1
8
PD
VS+
IN-
2
7
VS+
6
VOUT
IN+
3
6
VOUT
5
NC
VS-
4
5
NC
NC = No Connetion
NC = No Connection
See Note A.
NOTE A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
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3
THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5 V
At RF = 392 Ω, RL = 499 Ω, and G = +2, unless otherwise noted.
TYP
OVER TEMPERATURE
UNITS
MIN/
TYP/
MAX
1
GHz
Typ
G = –1, POUT = –16 dBm
325
MHz
Typ
G = 2, POUT = –16 dBm
325
MHz
Typ
G = 5, POUT = –16 dBm
70
MHz
Typ
PARAMETER
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C
to
+85°C
AC PERFORMANCE
G = 1, POUT = –7 dBm
Small-signal bandwidth
G = 10, POUT = –16 dBm
35
MHz
Typ
0.1-dB flat bandwidth
G = 1, POUT = –7 dBm
70
MHz
Typ
Gain bandwidth product
G > 10, f = 1 MHz
350
MHz
Typ
Full-power bandwidth
G = –1, VO = 2 Vp
77
MHz
Typ
G = 1, VO = 2 V Step
970
V/µs
Typ
G = –1, VO = 2 V Step
850
V/µs
Typ
22
ns
Typ
55
ns
Typ
–78
dBc
Typ
RL = 499 Ω
–90
dBc
Typ
RL = 150Ω
–100
dBc
Typ
RL = 499 Ω
–100
dBc
Typ
RL = 150 Ω
–68
dBc
Typ
RL = 499 Ω
–70
dBc
Typ
RL = 150Ω
–80
dBc
Typ
RL = 499 Ω
Slew rate
Settling time to 0.1%
Settling time to 0.01%
G = –1, VO = 4 V Step
Harmonic distortion
RL = 150 Ω
2nd-order harmonic distortion
G = 1, VO = 1 VPP,
f = 30 MHz
3rd-order harmonic distortion
Harmonic distortion
2nd-order harmonic distortion
G = 2, VO = 2 VPP,
f = 30 MHz
3rd-order harmonic distortion
–82
dBc
Typ
3rd-order intermodulation (IMD3)
G = 2, VO = 2 VPP, RL = 150 Ω, f = 70 MHz
–53
dBc
Typ
3rd-order output intercept (OIP3)
G = 2, VO = 2 VPP, RL = 150 Ω, f = 70 MHz
32
dBm
Typ
0.007
%
Typ
0.003
°
Typ
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
G = 2, RL = 150 Ω
Input voltage noise
f = 1 MHz
7
nV/√Hz
Typ
Input current noise
f = 10 MHz
4
pA√Hz
Typ
VO = ±0.3 V, RL = 499 Ω
70
65
62
60
dB
Min
3
12
14
14
mV
Max
±40
±40
µV/°C
Typ
7
15
18
20
µA
Max
±10
±10
nA/°C
Typ
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input offset voltage
Average offset voltage drift
Input bias current
Average bias current drift
VCM = 0 V
Input offset current
0.3
6
Average offset current drift
4
Submit Documentation Feedback
7
8
µA
Max
±10
±10
nA/°C
Typ
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
At RF = 392 Ω, RL = 499 Ω, and G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
–40°C
to
+85°C
UNITS
MIN/
TYP/
MAX
V
Min
+25°C
+25°C
0°C to
+70°C
±4
±3.8
±3.7
±3.6
52
50
48
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
VCM = ± 1 V
56
dB
Min
Input resistance
Common-mode
4
MΩ
Typ
Input capacitance
Common-mode/differential
0.3/0.2
pF
Typ
OUTPUT CHARACTERISTICS
Output voltage swing
±4.0
±3.8
±3.7
±3.6
V
Min
Output current (sourcing)
220
200
190
180
mA
Min
170
140
130
120
mA
Min
Ω
Typ
Output current (sinking)
Output impedance
RL = 10 Ω
f = 1 MHz
0.3
POWER SUPPLY
Specified operating voltage
±5
±7.5
±7.5
±7.5
V
Max
Maximum quiescent current
19
22
23
24
mA
Max
Minimum quiescent current
19
16
15
14
mA
Min
Power-supply rejection (+PSRR)
VS+ = 5.5 V to 4.5 V, VS– = 5 V
64
58
54
54
dB
Min
Power-supply rejection (–PSRR)
VS+ = 5 V, VS– = –5.5 V to –4.5 V
65
60
56
56
dB
Min
POWER-DOWN CHARACTERISTICS (THS4215 ONLY)
REF = 0 V, or VS–
Power-down voltage level
REF = VS+ or Floating
Power-down quiescent current
Enable
Power-down
Enable
Power-down
REF+1.8
V
Min
REF+1
V
Max
REF–1
V
Min
REF–1.5
V
Max
PD = Ref +1.0 V, Ref = 0 V
650
850
900
1000
µA
Max
PD = Ref –1.5 V, Ref = 5 V
450
650
800
900
µA
Max
Turn-on time delay(t(ON))
50% of final supply current value
4
µs
Typ
Turn-off time delay (t(Off))
50% of final supply current value
3
µs
Typ
4
GΩ
Typ
250
kΩ
Typ
Input impedance
Output impedance
f = 1 MHz
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
Submit Documentation Feedback
5
THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = 5 V
At RF = 392 Ω, RL = 499 Ω, and G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
+25°C
+25°C
0°C to
+70°C
–40°C
to
+85°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
Small-signal bandwidth
G = 1, POUT = –7 dBm
980
MHz
Typ
G = –1, POUT = –16 dBm
300
MHz
Typ
G = 2, POUT = –16 dBm
300
MHz
Typ
MHz
Typ
G = 5, POUT = –16 dBm 65
G = 10, POUT = –16 dBm
30
MHz
Typ
0.1-dB flat bandwidth
G = 1, POUT = –7 dBm
90
MHz
Typ
Gain bandwidth product
G > 10, f = 1 MHz
300
MHz
Typ
Full-power bandwidth
G = –1, VO = 2 Vp
64
MHz
Typ
G = 1, VO = 2 V Step
800
V/µs
Typ
G = –1, VO = 2 V Step
750
V/µs
Typ
22
ns
Typ
84
ns
Typ
RL = 150 Ω
–60
dBc
Typ
RL = 499 Ω
–60
dBc
Typ
RL = 150 Ω
–68
dBc
Typ
RL = 499 Ω
–68
dBc
Typ
–70
dBc
Typ
Slew rate
Settling time to 0.1%
Settling time to 0.01%
G = –1, VO = 2 V Step
Harmonic distortion
2nd-order harmonic distortion
G = 1, VO = 1 VPP,
f = 30 MHz
3rd-order harmonic distortion
3rd-order intermodulation (IMD3)
3rd-order output intercept (OIP3)
G = 1, VO = 1 VPP, RL = 150 Ω, f = 70 MHz
34
dBm
Typ
Input-voltage noise
f = 1 MHz
7
nV/√Hz
Typ
Input-current noise
f = 10 MHz
4
pA/√Hz
Typ
VO = ± 0.3 V, RL = 499 Ω
68
63
60
60
dB
Min
3
12
14
14
mV
Max
±40
±40
µV/°C
Typ
7
15
17
18
µA
Max
±10
±10
nA/°C
Typ
0.3
6
7
8
µA
Max
±10
±10
nA/°C
Typ
V
Min
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input offset voltage
Average offset voltage drift
Input bias current
Average bias current drift
VCM = VS/2
Input offset current
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
1/4
1.2/3.8
1.3/3.7
1.4/3.6
50
48
45
Common-mode rejection ratio
VCM = ± 0.5 V, VO = 2.5 V
54
dB
Min
Input resistance
Common-mode
4
MΩ
Typ
Input capacitance
Common-mode/differential
0.3/0.2
pF
Typ
OUTPUT CHARACTERISTICS
Output voltage swing
1/4
1.2/3.8
1.3/3.7
1.4/3.6
V
Min
Output current (sourcing)
230
210
190
180
mA
Min
150
120
100
90
mA
Min
Ω
Typ
Output current (sinking)
Output impedance
6
RL = 10 Ω
f = 1 MHz
Submit Documentation Feedback
0.3
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
At RF = 392 Ω, RL = 499 Ω, and G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
–40°C
to
+85°C
UNITS
MIN/
TYP/
MAX
+25°C
+25°C
0°C to
+70°C
Specified operating voltage
5
15
15
15
V
Max
Maximum quiescent current
19
22
23
24
mA
Max
Minimum quiescent current
19
16
15
14
mA
Min
POWER SUPPLY
Power-supply rejection (+PSRR)
VS+ = 5.5 V to 4.5 V, VS– = 0 V
63
58
54
54
dB
Min
Power-supply rejection (–PSRR)
VS+ = 5 V, VS– = –0.5 V to 0.5 V
65
60
56
56
dB
Min
POWER-DOWN CHARACTERISTICS (THS4215 ONLY)
REF = 0 V, or VS–
Power-down voltage level
REF = VS+ or floating
Enable
Power down
Enable
Power down
REF+1.8
V
Min
REF+1
V
Max
REF–1
V
Min
REF–1.5
V
Max
Power-down quiescent current
PD = Ref +1.0 V, Ref = 0 V
450
650
750
850
µA
Max
Power-down quiescent current
PD = Ref –1.5 V, Ref = 5 V
400
650
750
850
Turn-on-time delay(t(ON))
Turn-off-time delay (t(Off))
50% of final value
Input impedance
Output impedance
f = 1 MHz
µA
Max
4
µs
Typ
3
µs
Typ
6
GΩ
Typ
75
kΩ
Typ
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
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7
THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small-signal unity-gain frequency response
1
Small-signal frequency response
2
0.1-dB gain flatness frequency response
3
Large-signal frequency response
4
Slew rate
vs Output voltage
5
Harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage swing
Third-order intermodulation distortion
vs Frequency
14, 16
Third-order output intercept point
vs Frequency
15, 17
Voltage and current noise
vs Frequency
18
Differential gain
vs Number of loads
19
Differential phase
vs Number of loads
20
6, 7, 8, 9
10, 11, 12, 13
Settling time
21
Quiescent current
vs supply voltage
22
Output voltage
vs Load resistance
23
Frequency response
vs Capacitive load
24
Open-loop gain and phase
vs Frequency
25
Open-loop gain
vs Case temperature
26
Rejection ratios
vs Frequency
27
Rejection ratios
vs Case temperature
28
Common-mode rejection ratio
vs Input common-mode range
29
Input offset voltage
vs Case temperature
30
Input bias and offset current
vs Case temperature
31
Small-signal transient response
32
Large-signal transient response
33
Overdrive recovery
34
Closed-loop output impedance
vs Frequency
35
Power-down quiescent current
vs Supply voltage
36
Power-down output impedance
vs Frequency
37
Turn-on and turn-off delay times
8
Submit Documentation Feedback
38
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
Table of Graphs (5 V)
FIGURE
Small-signal unity-gain frequency response
39
Small-signal frequency response
40
0.1-dB gain flatness frequency response
41
Large-signal frequency response
42
Slew rate
vs Output voltage
Harmonic distortion
vs Frequency
44, 45, 46, 47
Harmonic distortion
vs Output voltage swing
48, 49, 50, 51
Third-order intermodulation distortion
vs Frequency
52, 54
Third-order intercept point
vs Frequency
53, 55
Voltage and current noise
vs Frequency
56
Settling time
43
57
Quiescent current
vs Supply voltage
58
Output voltage
vs Load resistance
59
Frequency response
vs Capacitive load
60
Open-loop gain and phase
vs Frequency
61
Open-loop gain
vs Case temperature
62
Rejection ratios
vs Frequency
63
Rejection ratios
vs Case temperature
64
Common-mode rejection ratio
vs Input common-mode range
65
Input offset voltage
vs Case temperature
66
Input bias and offset current
vs Case temperature
67
Small-signal transient response
68
Large-signal transient response
69
Overdrive recovery
70
Closed-loop output impedance
vs Frequency
71
Power-down quiescent current
vs Supply voltage
72
Power-down output impedance
vs Frequency
73
Turn-on and turn-off delay times
74
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
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THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL UNITY GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
22
Gain = 1
RL = 499 Ω
VO = 250 mV
VS = ±5 V
3
0.1
20
2
1
0
-1
-2
0
Gain = 10
18
Small Signal Gain - dB
4
-0.1
16
Small Signal Gain - dB
5
Small Signal Gain - dB
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
Gain = 5
14
RL = 499 Ω
Rf = 392 Ω
VO = 250 mV
VS = ±5 V
12
10
8
6
Gain = 2
4
2
-4
100 k
1M
10 M
100 M
1G
Gain = -1
-2
-4
100 k
1M
10 G
f - Frequency - Hz
-0.6
-0.7
Gain = 1
RL = 499 Ω
VO = 250 mV
VS = ±5 V
10 M
100 M
f - Frequency - Hz
-1
1M
1G
10 M
100 M
f - Frequency - Hz
Figure 2.
Figure 3.
LARGE-SIGNAL FREQUENCY
RESPONSE
SLEW RATE
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
FREQUENCY
1400
-1
-2
Gain = 1
RL = 499 Ω
VO = 2 VPP
VS = ±5 V
-4
100 k
Fall, Gain = 1
1000
800
Fall, Gain =- 1
Rise, Gain = -1
600
400
RL = 499 Ω
Rf = 392 Ω
VS = ±5 V
200
10 M
100 M
1G
0
f - Frequency - Hz
-60
-90
0.5
1
1.5
2
2.5
3
3.5
4 4.5
1
5
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
Gain = 2
Rf = 392 Ω
VO = 1 VPP
VS = ±5 V
-60
-80
-85
-90
-65
-70
HD3, RL = 150Ω,
and RL = 499 Ω
-75
-80
HD2, RL = 499Ω
-85
HD2, RL = 150Ω
-90
-60
-65
-70
HD2, RL = 499Ω
-75
-90
-95
-100
-100
10
100
HD3, RL = 150Ω,
and RL = 499 Ω
-85
-100
1
HD2, RL = 150Ω
-80
-95
100
Gain = 2
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
-55
-95
10
1
10
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 7.
Figure 8.
Figure 9.
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100
-50
-55
HD3, RL = 150 Ω
and RL = 499 Ω
HD2, RL = 150 Ω
1
10
f - Frequency - MHz
Figure 6.
HD2, RL = 499 Ω
-75
HD2, RL = 499 Ω
-85
Figure 5.
-65
-70
HD2, RL = 150 Ω
-80
Figure 4.
Gain = 1
VO = 2 VPP
VS = ±5 V
-55
-75
VO - Output Voltage - V
Harmonic Distortion - dBc
-50
HD3, RL = 150 Ω
and RL = 499 Ω
-100
0
1M
-70
-95
Harmonic Distortion - dBc
-3
Gain = 1
VO = 1 VPP
VS = ±5 V
-65
Harmonic Distortion - dBc
SR - Slew Rate - V/ µ s
0
1G
-60
1200
Large Signal Gain - dB
-0.5
-0.9
Rise, Gain = 1
Harmonic Distortion - dBc
-0.4
Figure 1.
1
10
-0.3
-0.8
0
-3
-0.2
100
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
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TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
-85
-90
HD2, RL = 499Ω
-95
-65
HD2, RL = 499Ω
-70
HD2, RL = 150Ω
-75
-80
-85
-90
0.5 1
1.5 2
2.5 3
3.5 4
4.5 5
HD3, RL = 499Ω
HD2, RL = 150Ω
-90
-100
0
0.5 1
1.5 2
2.5 3
3.5 4
4.5 5
0
0.5 1
VO - Output Voltage Swing - ±V
1.5 2
2.5 3
3.5 4
Figure 12.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER OUTPUT
INTERCEPT POINT
vs
FREQUENCY
-50
-55
HD3, RL = 150Ω
HD3, RL = 499Ω
-60
HD2, RL = 499Ω
-65
-70
-75
-80
HD2, RL = 150Ω
-85
-90
-95
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
60
-45
Third-Order Output Intersept Point - dBm
Gain = 2
Rf = 249 Ω
f = 32 MHz
VS = ±5 V
Third-Order Intermodulation Distortion - dBc
Figure 11.
-45
Gain = 1
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
-50
-55
-60
-65
-70
VO = 2 VPP
-75
-80
-85
-90
-95
-100
4.5 5
VO - Output Voltage Swing - ±V
Figure 10.
-40
VO = 1 VPP
10
55
50
45
VO = 1 VPP
40
VO = 2 VPP
35
30
0
100
VO - Output Voltage Swing - ±V
Gain = 1
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
20
40
60
80
100
f - Frequency - MHz
f - Frequency - MHz
Figure 13.
Figure 14.
Figure 15.
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER OUTPUT
INTERCEPT POINT
vs
FREQUENCY
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
100
-55
-60
-65
-70
VO = 2 VPP
-75
-80
-85
-90
VO = 1 VPP
-95
-100
10
100
Gain = 2
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
55
50
45
35
VO = 2 VPP
30
In
1
20
20
40
60
80
100
f - Frequency - MHz
Figure 16.
10
25
0
f - Frequency - MHz
Vn
10
VO = 1 VPP
40
100
Hz
-50
Third-Order Output Intersept Point - dBm
60
Gain = 2
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
-45
Hz
-40
nV/
Harmonic Distortion - dBc
-85
HD3, RL = 499Ω
VO - Output Voltage Swing - ±V
Third-Order Intermodulation Distortion - dBc
HD3, RL = 150Ω
-80
-100
0
HD2, RL = 499Ω
-95
-95
-100
-75
I n - Current Noise - pA/
HD2, RL = 150Ω
-60
Gain = 2
Rf = 249 Ω
f = 8 MHz
VS = ±5 V
-70
HD3, RL = 150Ω
Harmonic Distortion - dBc
HD3, RL = 150Ω
HD3, RL = 499Ω
-80
-65
Gain = 1
f= 32 MHz
VS = ±5 V
-55
Vn - Voltage Noise -
Harmonic Distortion - dBc
-75
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
-50
Gain = 1
f= 8 MHz
VS = ±5 V
Harmonic Distortion - dBc
-70
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Figure 17.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
1k
10 k
100 k
1M
10 M
1
100 M
f - Frequency - Hz
Figure 18.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.030
0.015
°
Differential Phase -
0.020
Gain = 2
Rf = 392 Ω
VS = ±5 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0.18
PAL
NTSC
0.010
0.16
0.14
2
VO - Output Voltage - V
Gain = 2
Rf = 392 Ω
VS = ±5 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0.025
Differential Gain - %
SETTLING TIME
3
0.20
0.12
0.10
PAL
0.08
0.06
NTSC
0.04
0.005
Rising Edge
1
-1
Gain = -1
RL = 499 Ω
Rf = 392 Ω
f= 1 MHz
VS = ±5 V
-2
Falling Edge
0
0.02
0
0
0
1
2
3
4
5
6
7
8
0
2
3
4
5
6
7
-3
8
10
15
20
Figure 21.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
TA = 85°C
TA = 25°C
1
4
0.5
14
12
Normalized Gain - dB
VO - Output Voltage - V
TA = -40°C
16
5
3
18
2
1
TA = -40 to 85°C
0
-1
-2
3
3.5
4
4.5
10
5
0
-0.5
R(ISO) = 15 Ω
CL = 50 pF
-1
-1.5
R(ISO) = 25 Ω
CL = 10 pF
-2
-2.5
-5
2.5
VS =±5 V
R(ISO) = 10 Ω
CL = 100 pF
-3
-4
10
100
-3
100 k
1000
RL - Load Resistance - Ω
VS - Supply Voltage - ±V
1M
10 M
100 M
Figure 23.
Figure 24.
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
REJECTION RATIOS
vs
FREQUENCY
70
90
180
70
160
TA = 25°C
50
120
40
100
30
80
20
60
10
40
0
20
Open-Loop Gain - dB
140
Phase - °
85
60
100 k
1M
10 M
100 M
0
1G
f - Frequency - Hz
Figure 25.
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PSRR-
TA = 85°C
80
75
TA = -40°C
70
65
-10
10 k
VS = ±5 V
60
Rejection Ratios - dB
VS = ±5 V
1G
Capacitive Load - Hz
Figure 22.
80
25
t - Time - ns
Figure 20.
20
Open-Loop Gain - dB
5
Figure 19.
22
12
0
Number of Loads - 150 Ω
Number of Loads - 150 Ω
Quiescent Current - mA
1
50
CMRR
40
30
PSRR+
20
10
60
2.5
3
3.5
4
4.5
5
0
100 k
1M
10 M
Case Temperature - °C
f - Frequency - Hz
Figure 26.
Figure 27.
100 M
1G
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
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THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS: ±5 V (continued)
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
VS = ±5 V
PSRR-
70
CMMR
PSRR+
40
30
20
10
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
9
55
8
50
45
40
35
30
25
20
15
10
VS = ±5 V
TA = 25°C
5
0
-4.5
-3
Case Temperature - °C
1
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
4.5
TC - Case Temperature - °C
LARGE-SIGNAL TRANSIENT
RESPONSE
0.65
0.6
0.55
IIB-
0.5
IOS
0.45
0.4
0.35
IIB+
5.8
0.3
5.7
0.25
VO - Output Voltage - V
0.7
VS = ±5 V
I OS - Input Offset Current - µ A
I IB - Input Bias Current - µ A
2
Input Common-Mode Range - V
0.12
0.1
1.5
0.08
1
0.06
0.04
0.02
0
-0.02
Gain = -1
RL = 499 Ω
Rf =392 Ω
tr/tf = 300 ps
VS = ±5 V
-0.04
-0.06
-0.08
-0.1
0.2
-40 -30 -20-10 0 10 20 30 40 50 60 70 80 90
0.5
0
Gain = -1
RL = 499 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = ±5 V
-0.5
-1
-1.5
-0.12
-1
TC - Case Temperature - °C
0
1
2
3 4 5 6
t - Time - ns
7
8
9
-2
10
0
2
4
6
8 10 12 14 16 18 20
t - Time - ns
Figure 31.
Figure 32.
Figure 33.
OVERDRIVE RECOVERY
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
100 k
2.5
4
2
3
1.5
2
1
1
0.5
0
0
-1
-0.5
-2
-1
-3
-1.5
-4
-2
-5
-2.5
-6
-3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Closed-Loop Output Impedance - Ω
3
VS = ±5 V
VI - Input Voltage - V
Single-Ended Output Voltage - V
3
SMALL-SIGNAL TRANSIENT
RESPONSE
6
6
5
VS = 5 V
4
INPUT BIAS AND OFFSET
CURRENT
vs
CASE TEMPERATURE
6.1
5.6
3
5
Figure 30.
6.2
5.9
1.5
VS = ±5 V
6
Figure 29.
6.4
6.3
0
7
Figure 28.
6.6
6.5
-1.5
VO - Output Voltage - V
50
60
10 k
1k
100
10
1
0.1
0.01
100 k
1
t - Time - µs
Figure 34.
800
RL = 499 Ω,
RF = 392 Ω,
PIN = -4 dBm
VS = ±5 V
Power-Down Quiescent Current - µ A
Rejection Ratios - dB
60
CMRR - Common-Mode Rejection Ratio - dB
80
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
VOS - Input Offset Voltage - mV
REJECTION RATIOS
vs
CASE TEMPERATURE
TA = 85°C
700
600
500
TA = 25°C
400
TA = -40°C
300
200
100
0
1M
10 M
100 M
f - Frequency - Hz
1G
Figure 35.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
2.5
3
3.5
4
4.5
VS - Supply Voltage - ±V
5
Figure 36.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
POWER-DOWN
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
0.1
1M
10 M
100 M
1G
4.5
0.03
10
0.001
100 k
6
0.035
VO - Output Voltage Level - V
Power-Down Output Impedance - Ω
0.04
Gain = 1
RL = 499 Ω
PIN = -1 dBm
VS = ±5 V
3
1.5
0.025
0.02
0
0.015
0.01
-3
-4.5
0.005
-6
0
-7.5
-0.005
-0.01
10 G
-1.5
Gain = -1
RL = 499 Ω
VS = ±5 V
V I - Input Voltage Level - V
TURN-ON AND TURN-OFF TIMES
DELAY TIME
0
f - Frequency - Hz
0.01 0.02 0.03 0.04 0.05 0.06 0.07
t - Time - ns
Figure 37.
Figure 38.
TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNITY GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL
FREQUENCY RESPONSE
22
Gain = 1
RL = 499 Ω
VO = 250 mV
VS = 5 V
2
0
-1
-2
10 M
100 M
1G
16
Gain = 5
14
RL = 499 Ω
Rf = 392 Ω
VO = 250 mV
VS = 5 V
12
10
8
6
Gain = 2
4
2
0
Gain = -1
-2
-4
100 k
1M
-3
1M
10 G
f - Frequency - Hz
-0.3
-0.4
-0.5
-0.6
Gain = 1
RL = 499 Ω
VO = 250 mV
VS = 5 V
-0.7
-0.8
-0.9
-1
10 M
100 M
f - Frequency - Hz
1G
1M
10 M
100 M
f - Frequency - Hz
Figure 40.
Figure 41.
LARGE-SIGNAL
FREQUENCY RESPONSE
SLEW RATE
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
FREQUENCY
1000
-1
-2
Gain = 1
RL = 499 Ω
VO = 2 VPP
VS = 5 V
-4
100 K
800
Rise, G = 1
700
600
Rise, G = -1
500
Fall, G = -1
400
300
RL = 499 Ω
Rf = 392 Ω
VS = 5 V
200
100
10 M
100 M
1G
f - Frequency - Hz
Figure 42.
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-60
-65
-70
HD2
-75
-80
HD3
-85
-90
-95
0
1M
Gain = 1
VO = 1 VPP
RL = 150 Ω, and 499 Ω
VS = 5 V
-55
Harmonic Distortion - dBc
SR - Slew Rate - V/ µ s
0
1G
-50
Fall, G = 1
900
Large Signal Gain - dB
-0.2
Figure 39.
1
14
0
-0.1
Gain = 10
18
1
-4
100 k
0.1
20
Small Signal Gain - dB
Small Signal Gain - dB
3
Small Signal Gain - dB
4
-3
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
-100
0.4
0.6
0.8
1
1.2 1.4 1.6
VO - Output Voltage -V
1.8
2
Figure 43.
1
10
f - Frequency - MHz
100
Figure 44.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
-60
HD3
-65
HD2
-70
-75
-80
-30
-50
-40
-60
HD2
-70
HD3
-80
Gain = 2
VO = 1 VPP
Rf = 392 Ω
RL = 150 Ω and 499 Ω
VS = 5 V
-90
-85
-100
-90
10
1
100
1
f - Frequency - MHz
HD3
-60
-70
Gain = 2
VO = 2 VPP
Rf = 392 Ω
RL = 150 Ω and 499 Ω
VS = 5 V
-80
-90
100
1
10
f - Frequency - MHz
100
Figure 47.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Harmonic Distortion - dBc
HD2
-70
-75
HD3
-80
-85
Gain = 1
RL = 150 Ω, and 499 Ω,
f = 8 MHz
VS = 5 V
-90
-95
-100
-45
-50
-50
-55
-55
HD2
-60
-65
HD3
-70
-75
Gain = 1
RL = 150 Ω, and 499 Ω,
f = 32 MHz
VS = 5 V
-80
-85
-90
0.5
1
1.5
2
VO - Output Voltage Swing - V
2.5
0
0.5
1
1.5
2
VO - Output Voltage Swing - V
HD2
-60
-65
HD3
-70
-75
-80
Gain = 2
Rf = 392 Ω
RL = 150 Ω and 499 Ω
f = 8 MHz
VS = 5 V
-85
-90
-95
-100
0
2.5
0.5
1
1.5
2
2.5
VO - Output Voltage Swing - V
Figure 48.
Figure 49.
Figure 50.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
-40
-45
HD2
-50
-55
HD3
-60
-65
Gain = 2
Rf = 392 Ω
RL = 150 Ω and 499 Ω
f = 32 MHz
VS = 5 V
-70
-75
-80
0
0.5
1
1.5
2
2.5
Third-Order Intermodulation Distortion - dBc
Harmonic Distortion - dBc
HD2
Figure 46.
-65
0
-50
Figure 45.
-60
Harmonic Distortion - dBc
10
f - Frequency - MHz
Harmonic Distortion - dBc
-55
-40
-40
50
Gain = 1
RL = 150 Ω
VS = 5 V
200 kHz Tone
Spacing
-45
-50
-55
-60
-65
VO = 2VPP
-70
-75
-80
-85
VO = 1VPP
-90
-95
-100
10
VO - Output Voltage Swing - V
Third-Order Output Intersept Point - dBm
Harmonic Distortion - dBc
-50
Harmonic Distortion - dBc
Gain = 1
VO = 2 VPP
RL = 150 Ω, and 499 Ω
VS = 5 V
-45
Harmonic Distortion - dBc
-40
HARMONIC DISTORTION
vs
FREQUENCY
100
f - Frequency - MHz
Figure 51.
Figure 52.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
Gain = 1
RL = 150 Ω
VS = 5 V
200 kHz Tone Spacing
45
VO = 1VPP
40
VO = 2VPP
35
30
0
10
20
30
40
50
60
70
80
f - Frequency - MHz
Figure 53.
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TYPICAL CHARACTERISTICS: 5 V (continued)
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
100
-60
VO = 2 VPP
-70
-80
VO = 1 VPP
-90
-100
10
100
40
35
Hz
nV/
-50
45
VO = 1 VPP
30
Vn
10
VO = 2 VPP
25
20
10
In
15
0
20
40
60
80
1k
100
10 k
100 k
1M
10 M
f - Frequency - Hz
f - Frequency - MHz
Figure 54.
Figure 55.
Figure 56.
SETTLING TIME
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
1.5
2
22
Rising Edge
-0.5
18
TA = -40°C
16
14
Falling Edge
-1
VO - Output Voltage - V
Gain = -1
RL = 499 Ω
Rf = 392 Ω
f= 1 MHz
VS = 5 V
0
TA = 25°C
Quiescent Current - mA
0.5
1.5
TA = 85°C
20
1
1
100 M
1
10
f - Frequency - MHz
VO - Output Voltage - V
100
Vn - Voltage Noise -
-40
Gain = 2
RL = 150 Ω
VS = 5 V
200 kHz Tone Spacing
Hz
50
Gain = 1
RL = 150 Ω
VS = 5 V
200 kHz Tone
Spacing
I n - Current Noise - pA/
-30
Third-Order Output Intersept Point - dBm
Third-Order Intermodulation Distortion - dBc
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
1
0.5
TA = -40 to 85°C
0
-0.5
-1
12
-1.5
10
-1.5
0
5
10
15
t - Time - ns
20
3.5
4
4.5
5
10
100
RL - Load Resistance - Ω
Figure 57.
Figure 58.
Figure 59.
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
80
R(ISO) = 25 Ω, CL = 10 pF
70
-1
R(ISO) = 10 Ω
CL = 100 pF
-2
140
50
120
40
100
30
80
20
60
10
40
0
20
Open-Loop Gain - dB
Open-Loop Gain - dB
R(ISO) = 15 Ω
CL = 50 pF
-1.5
TA = 25°C
85
0
-0.5
160
60
1000
90
180
VS = 5 V
Phase - °
0.5
Normalized Gain - dB
3
VS - Supply Voltage - ±V
1
TA = 85°C
80
75
TA = -40°C
70
65
-2.5
VS = 5 V
-3
100 k
1M
10 M
100 M
Capacitive Load - Hz
Figure 60.
16
-2
2.5
25
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1G
-10
10 k
100 k
1M
10 M
100 M
60
0
1G
2.5
3
3.5
4
4.5
5
Case Temperature - °C
f - Frequency - Hz
Figure 61.
Figure 62.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS: 5 V (continued)
REJECTION RATIOS
vs
CASE TEMPERATURE
80
70
VS = 5 V
50
CMRR
40
30
PSRR+
20
PSRR-
60
Rejection Ratios - dB
50
CMMR
PSRR+
40
30
20
10
10
0
100 k
1M
10 M
100 M
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
1G
50
45
40
35
30
25
20
15
10
5
0
0
1
2
3
4
Input Common-Mode Voltage Range - V
Figure 64.
Figure 65.
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
INPUT BIAS AND OFFSET
CURRENT
vs
CASE TEMPERATURE
SMALL-SIGNAL TRANSIENT
RESPONSE
VS = ±5 V
6
5
VS = 5 V
4
3
2
0.65
6.4
6.3
0.6
IIB-
0.55
6.2
6.1
0.5
0.45
IIB+
6
0.4
5.9
0.35
IOS
5.8
0.3
5.7
1
LARGE-SIGNAL TRANSIENT
RESPONSE
-1
-1.5
0
2
4
6
-0.02
-0.06
-1
3 4 5 6
t - Time - ns
7
OVERDRIVE RECOVERY
2
1
1
0.5
0
0
-2
-1
-3
-1.5
100 k
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
t - Time - µs
Figure 69.
2
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
1.5
0
1
Figure 68.
-0.5
8 10 12 14 16 18 20
0
Figure 67.
-1
t - Time - ns
Gain = -1
RL = 499 Ω
Rf =392 Ω
tr/tf = 300 ps
VS = 5 V
-0.04
-0.1
VI - Input Voltage - V
Single-Ended Output Voltage - V
Gain = -1
RL = 499 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = 5 V
-0.5
0.02
0
-0.12
VS = 5 V
0
0.04
-0.08
0.25
3
1.5
0.5
0.06
TC - Case Temperature - °C
Figure 66.
1
0.08
0.2
5.6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
TC - Case Temperature - °C
5
0.12
0.1
Figure 70.
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Product Folder Link(s): THS4211 THS4215
Closed-Loop Output Impedance - Ω
7
0.7
VS = 5 V
VO - Output Voltage - V
6.5
I IB - Input Bias Current - µ A
6.6
8
0
-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90
VO - Output Voltage - V
VS = 5 V
55
Figure 63.
9
-2
60
Case Temperature - °C
f - Frequency - Hz
I OS - Input Offset Current - µ A
Rejection Ratios - dB
VS = 5 V
70
PSRR-
60
VOS - Input Offset Voltage - mV
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
CMRR - Common-Mode Rejection Ratio - dB
REJECTION RATIOS
vs
FREQUENCY
10 k
1k
8
9
10
RL = 499 Ω,
RF = 392 Ω,
PIN = -4 dBm
VS = 5 V
100
10
1
0.1
0.01
100 k
1M
10 M
100 M
f - Frequency - Hz
1G
Figure 71.
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THS4211
THS4215
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TYPICAL CHARACTERISTICS: 5 V (continued)
POWER-DOWN OUTPUT
IMPEDANCE
vs
FREQUENCY
1000
TA = 85°C
600
500
TA = 25°C
400
TA = -40°C
300
200
100
0
2.5
3
3.5
4
4.5
VS - Supply Voltage - ±V
Figure 72.
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5
0.035
Gain = 1
RL = 499 Ω
PIN = -1 dBm
VS = 5 V
0.03
10
0.1
0.001
100 k
10 M
100 M
f - Frequency - Hz
1G
3
10 G
Figure 73.
1.5
0
0.02
0.015
-1.5
-3
0.01
Gain = -1
RL = 499 Ω
VS = 5 V
0.005
0
-0.005
-0.01
1M
4.5
0.025
VO - Output Voltage Level - V
700
Power-Down Output Impedance - Ω
Power-Down Quiescent Current - µ A
800
18
TURN-ON AND TURN-OFF TIMES
DELAY TIME
0
V I - Input Voltage Level - V
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
-4.5
-6
-7.5
0.01 0.02 0.03 0.04 0.05 0.06 0.07
t - Time - ns
Figure 74.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
APPLICATION INFORMATION
HIGH-SPEED OPERATIONAL AMPLIFIERS
WIDEBAND, NONINVERTING OPERATION
The THS4211 and the THS4215 operational
amplifiers set new performance levels, combining low
distortion, high slew rates, low noise, and a unity-gain
bandwidth in excess of 1 GHz. To achieve the full
performance of the amplifier, careful attention must
be paid to printed-circuit board (PCB) layout and
component selection.
The THS4211 and the THS4215 are unity-gain
stable,
1-GHz
voltage-feedback
operational
amplifiers, with and without power-down capability,
designed to operate from a single 5-V to 15-V power
supply.
The THS4215 provides a power-down mode,
providing the ability to save power when the amplifier
is inactive. A reference pin is provided to allow the
user the flexibility to control the threshold levels of the
power-down control pin.
Applications Section Contents
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wideband, Noninverting Operation
Wideband, Inverting Gain Operation
Single-Supply Operation
Saving Power with Power-Down Functionality and
Setting Threshold Levels with the Reference Pin
Power Supply Decoupling Techniques and
Recommendations
Using the THS4211 as a DAC Output Buffer
Driving an ADC with the THS4211
Active Filtering with the THS4211
Building a Low-Noise Receiver with the THS4211
Linearity:
Definitions,
Terminology,
Circuit
Techniques and Design Tradeoffs
An Abbreviated Analysis of Noise in Amplifiers
Driving Capacitive Loads
Printed-Circuit Board Layout Techniques for
Optimal Performance
Power Dissipation and Thermal Considerations
Performance vs Package Options
Evaluation
Fixtures,
Spice
Models,
and
Applications Support
Additional Reference Material
Mechanical Package Drawings
Figure 75 shows the noninverting gain configuration
of 2 V/V used to demonstrate the typical performance
curves. Most of the curves were characterized using
signal sources with 50-Ω source impedance, and with
measurement equipment presenting a 50-Ω load
impedance. In Figure 75, the 49.9-Ω shunt resistor at
the VIN terminal matches the source impedance of the
test generator. The total 499-Ω load at the output,
combined with the 784-Ω total feedback-network
load, presents the THS4211 and THS4215 with an
effective output load of 305 Ω for the circuit shown in
Figure 75.
Voltage-feedback amplifiers, unlike current-feedback
designs, can use a wide range of resistors values to
set their gain with minimal impact on their stability
and frequency response. Larger-valued resistors
decrease the loading effect of the feedback network
on the output of the amplifier, but this enhancement
comes at the expense of additional noise and
potentially lower bandwidth. Feedback-resistor values
between 392 Ω and 1 kΩ are recommended for most
applications.
5 V +V
S
+
100 pF
50 Ω Source
0.1 µF 6.8 µF
+
VI
VO
THS4211
49.9 Ω
_
Rf
392 Ω
499 Ω
392 Ω
Rg
0.1 µF 6.8 µF
100 pF
+
space
space
-5 V
space
-VS
Figure 75. Wideband, Noninverting Gain
Configuration
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THS4215
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WIDEBAND, INVERTING GAIN OPERATION
Since
the
THS4211
and
THS4215
are
general-purpose,
wideband
voltage-feedback
amplifiers, several familiar operational-amplifier
applications circuits are available to the designer.
Figure 76 shows a typical inverting configuration
where the input and output impedances and noise
gain from Figure 75 are retained in an inverting circuit
configuration. Inverting operation is a common
requirement and offers several performance benefits.
The inverting configuration shows improved slew
rates and distortion due to the pseudo-static voltage
maintained on the inverting input.
5 V +V
S
+
100 pF
0.1 µF
6.8 µF
+
RT
200 Ω
CT
0.1 µF
VO
THS4211
_
499 Ω
50 Ω Source
VI
Rg
Rf
392 Ω
RM
57.6 Ω
392 Ω
0.1 µF
100 pF
-5 V
6.8 µF
+
-VS
Figure 76. Wideband, Inverting Gain
Configuration
In the inverting configuration, some key design
considerations must be noted. One is that the gain
resistor (Rg) becomes part of the signal-channel input
impedance. If input impedance matching is desired
(beneficial when the signal is coupled through a
cable, twisted pair, long PCB trace, or other
transmission line conductor), Rg may be set equal to
the required termination value and Rf adjusted to give
the desired gain. However, care must be taken when
20
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dealing with low inverting gains, as the resultant
feedback resistor value can present a significant load
to the amplifier output. For an inverting gain of 2,
setting Rg to 49.9 Ω for input matching eliminates the
need for RM but requires a 100-Ω feedback resistor.
This has the advantage that the noise gain becomes
equal to 2 for a 50-Ω source impedance—the same
as the noninverting circuit in Figure 75. However, the
amplifier output now sees the 100-Ω feedback
resistor in parallel with the external load. To eliminate
this excessive loading, it is preferable to increase
both Rg and Rf, values, as shown in Figure 76, and
then achieve the input matching impedance with a
third resistor (RM) to ground. The total input
impedance becomes the parallel combination of Rg
and RM.
The next major consideration is that the signal source
impedance becomes part of the noise gain equation
and hence influences the bandwidth. For example,
the RM value combines in parallel with the external
50-Ω source impedance (at high frequencies),
yielding an effective source impedance of 50 Ω || 57.6
Ω = 26.8 Ω. This impedance is then added in series
with Rg for calculating the noise gain. The result is
1.9 for Figure 76, as opposed to the 1.8 if RM is
eliminated. The bandwidth is lower for the inverting
gain-of-2 circuit in Figure 76 (NG=+1.9), than for the
noninverting gain of 2 circuit in Figure 75.
The last major consideration in inverting amplifier
design is setting the bias-current cancellation resistor
on the noninverting input. If the resistance is set
equal to the total dc resistance looking out of the
inverting terminal, the output dc error, due to the input
bias currents, is reduced to (input offset current) × Rf
in Figure 76, the dc source impedance looking out of
the inverting terminal is 392 Ω || (392 Ω + 26.8 Ω) =
200 Ω. To reduce the additional high-frequency noise
introduced by the resistor at the noninverting input,
and power-supply feedback, RT is bypassed with a
capacitor to ground.
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
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SINGLE-SUPPLY OPERATION
The THS4211 is designed to operate from a single
5-V to 15-V power supply. When operating from a
single power supply, care must be taken to ensure
the input signal and amplifier are biased appropriately
to maximize output voltage swing. The circuits shown
in Figure 77 demonstrate methods to configure an
amplifier for single-supply operation.
+VS
50 Ω Source
+
VI
49.9 Ω
RT
THS4211
VO
_
499 Ω
+VS
Rf
2
Rg
392 Ω
392 Ω
In addition to the power-down pin, the THS4215 also
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. Operation of the
reference pin as it relates to the power-down pin is
described below.
Rf
392 Ω
VS
50 Ω Source
VI
57.6 Ω
Rg
_
392 Ω
THS4211
RT
VO
+
+VS
+VS
2
2
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
Power-Down Reference Pin Operation
+VS
2
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high- impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
499 Ω
Figure 77. DC-Coupled Single Supply Operation
Saving Power with Power-Down
Functionality and Setting Threshold Levels
with the Reference Pin
The THS4215 features a power-down pin (PD) which
lowers the quiescent current from 19-mA down to
650-µA, ideal for reducing system power.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To conserve power, the amplifier is turned
off by driving the power-down pin towards the
negative rail. The threshold voltages for power-on
and power-down are relative to the supply rails, and
are given in the specification tables. Above the
Enable Threshold Voltage, the device is on. Below
the Disable Threshold Voltage, the device is off.
Behavior between these threshold voltages is not
specified.
In most split-supply applications, the reference pin will
be connected to ground. In some cases, the user
may want to connect it to the negative or positive
supply rail. In either case, the user needs to be aware
of the voltage level thresholds that apply to the
power-down pin. The table below illustrates the
relationship between the reference voltage and the
power-down thresholds.
REFERENCE
VOLTAGE
POWER-DOWN PIN VOLTAGE
DEVICE
DISABLED
DEVICE
ENABLED
VS– to 0.5 (VS– + VS+)
≤ Ref + 1.0 V
≥ Ref + 1.8 V
0.5 (VS– + VS+) to VS+
≤ Ref – 1.5 V
≥ Ref – 1 V
The recommended mode of operation is to tie the
reference pin to mid-rail, thus setting the threshold
levels to mid-rail +1.0 V and midrail +1.8 V.
NO. OF CHANNELS
Single (8-pin)
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PACKAGES
THS4215D, THS4215DGN, and
THS4215DRB
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THS4211
THS4215
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Power-Supply Decoupling Techniques and
Recommendations
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably, improved distortion performance). The
following guidelines ensure the highest level of
performance.
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along
power-supply return current paths, with the
exception of the areas underneath the input and
output pins.
4. Recommended
values
for
power-supply
decoupling include a bulk decoupling capacitor
(6.8 µF to 22 µF), a mid-range decoupling
capacitor (0.1 µF) and a high-frequency
decoupling capacitor (1000 pF) for each supply.
A 100-pF capacitor can be used across the
supplies as well for extremely high-frequency
return currents, but often is not required.
APPLICATION CIRCUITS
Driving an Analog-to-Digital Converter with the
THS4211
The THS4211 can be used to drive high-performance
analog-to-digital converters. Two example circuits are
presented below.
The first circuit (in Figure 78) uses a wideband
transformer to convert a single-ended input signal into
a differential signal. The differential signal is then
amplified and filtered by two THS4211 amplifiers.
This circuit provides low intermodulation distortion,
suppressed even-order distortion, 14 dB of voltage
gain, a 50-Ω input impedance, and a single-pole filter
at 100 MHz. For applications without signal content at
dc, this method of driving ADCs can be very useful.
Where dc information content is required, the
THS4500 family of fully differential amplifiers may be
applicable.
22
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5V
+
VCM
THS4211
_
50 Ω
(1:4 Ω)
Source 1:2
196 Ω
-5 V
392 Ω
24.9 Ω
ADS5422
15 pF
14-Bit, 62 Msps
15 pF
196 Ω
24.9 Ω
392 Ω
_
THS4211
+
VCM
Figure 78. A Linear, Low-Noise, High-Gain
ADC Preamplifier
The second circuit depicts single-ended ADC drive.
While not recommended for optimum performance
using converters with differential inputs, satisfactory
performance can sometimes be achieved with
single-ended input drive. An example circuit is shown
in Figure 79 for reference.
50 Ω
Source
+5 V
+
VI
49.9 Ω
RT
RISO
0.1 µF
THS4211
_
-5 V
16.5 Ω
68 pf
12-Bit,
1.82 kΩ
Rg
ADS807
CM 53 Msps
IN
Rf
392 Ω
IN
0.1 µF
392 Ω
NOTE: For best performance, high-speed ADCs should be driven
differentially. See the THS4500 family of devices for more
information.
Figure 79. Driving an ADC With a
Single-Ended Input
Copyright © 2002–2009, Texas Instruments Incorporated
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THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
Using the THS4211 as a DAC Output Buffer
Active Filtering with the THS4211
Two example circuits are presented here showing the
THS4211 buffering the output of a digital-to-analog
converter. The first circuit (Figure 80) performs a
differential to single-ended conversion with the
THS4211 configured as a difference amplifier. The
difference amplifier can double as the termination
mechanism for the DAC outputs as well.
High-frequency active filtering with the THS4211 is
achievable due to the amplifier's high slew-rate, wide
bandwidth, and voltage feedback architecture.
Several options are available for high-pass, low-pass,
bandpass, and bandstop filters of varying orders. A
simple two-pole low pass filter is presented in
Figure 82 as an example, with two poles at 100 MHz.
3.3 V 3.3 V
100 Ω
3.9 pF
392 Ω
100 Ω
50 Ω Source
392 Ω
+5 V
392 Ω
DAC5675
14-Bit,
400 MSps
_
196 Ω
VI
49.9 Ω
392 Ω
RF
5V
57.6 Ω
THS4211
_
+
49.9 Ω
THS4211
392 Ω
-5 V
392 Ω
VO
+
LO
33 pF
-5 V
Figure 80. Differential to Single-Ended
Conversion of a High-Speed DAC Output
Figure 82. A Two-Pole Active Filter With
Two Poles Between 90 MHz and 100 MHz
A Low-Noise Receiver with the THS4211
For cases where a differential signaling path is
desirable, a pair of THS4211 amplifiers can be used
as output buffers. The circuit in Figure 81 depicts a
differential drive into a mixer's IF inputs, coupled with
additional signal gain and filtering.
THS4211
+
3.3 V 3.3 V
A combination of two THS4211 amplifiers can create
a high-speed, low-distortion, low-noise differential
receiver circuit as depicted in Figure 83. With both
amplifiers operating in the noninverting mode of
operation, the circuit presents a high load impedance
to the source. The designer has the option of
controlling the impedance through termination
resistors if a matched termination impedance is
desired.
_
100 Ω
100 Ω
100 Ω
CF
1 nF
VI+
1 nF
+
49.9 Ω
IF+
DAC5675
14-Bit,
400 MSps
392 Ω
100 Ω
392 Ω
392 Ω
49.9 Ω
392 Ω
49.9 Ω
RF(out)
392 Ω
787 Ω
IF1 nF
1 nF
_
VO+
_
100 Ω
392 Ω
CF
_
+
THS4211
VI-
Figure 81. Differential Mixer Drive Circuit
Using the DAC5675 and the THS4211
100 Ω
49.9 Ω
VO-
+
Figure 83. A High Input Impedance, Low-Noise,
Differential Receiver
space
space
space
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THS4215
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A modification on this circuit to include a difference
amplifier turns this circuit into a high-speed
instrumentation amplifier, as shown in Figure 84.
The
THS4211
features
execllent
distortion
performance for monolithic operational amplifiers.
This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity,
and methods for equating distortion of operational
amplifiers to desired linearity specifications in RF
receiver chains.
+
Rg2
Rf2
THS4211
_
Rf1
Rg1
_
100 Ω
_
Rf1
THS4211
+
49.9 Ω
VO
THS4211
Rg2
+
49.9 Ω
Rf2
VI+
Figure 84. A High-Speed Instrumentation
Amplifier
ǒ
Ǔ
ǒ Ǔ
2R f1
ǒV i)–V i–Ǔ R f2
VO + 1 1 )
2
Rg1
Rg2
(1)
THEORY AND GUIDELINES
Distortion Performance
The
THS4211
provides
excellent
distortion
performance into a 150-Ω load. Relative to alternative
solutions, it provides exceptional performance into
lighter loads, as well as exceptional performance on a
single 5-V supply. Generally, until the fundamental
signal reaches very high frequency or power levels,
the 2nd harmonic dominates the total harmonic
distortion with a negligible 3rd harmonic component.
Focusing then on the 2nd harmonic, increasing the
load impedance directly improves distortion. The total
load includes the feedback network; in the
noninverting configuration (Figure 75) this is the sum
of Rf and Rg, while in the inverting configuration
(Figure 76), only Rf needs to be included in parallel
with the actual load.
space
Amplifiers are generally thought of as linear devices.
The output of an amplifier is a linearly-scaled version
of the input signal applied to it. However, amplifier
transfer functions are nonlinear. Minimizing amplifier
nonlinearity is a primary design goal in many
applications.
Intercept points are specifications long used as key
design criteria in the RF communications world as a
metric for the intermodulation distortion performance
of a device in the signal chain (e.g., amplifiers,
mixers, etc.). Use of the intercept point, rather than
strictly the intermodulation distortion, allows simpler
system-level calculations. Intercept points, like noise
figures, can be easily cascaded back and forth
through a signal chain to determine the overall
receiver
chain's
intermodulation
distortion
performance.
The
relationship
between
intermodulation distortion and intercept point is
depicted in Figure 85 and Figure 86.
PO
PO
∆fc = fc - f1
Power
100 Ω
VI-
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
∆fc = f2 - fc
IMD3 = PS - PO
PS
fc - 3∆f
space
PS
f1 fc
f2
fc + 3∆f
f - Frequency - MHz
Figure 85.
24
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OIP 3 + P O )
POUT
(dBm)
ǒ
1X
P O + 10 log
OIP3
ǒŤIMD2 ŤǓ where
3
2RL
(2)
Ǔ
V 2P
0.001
(3)
NOTE: PO is the output power of a single tone, RL is
the load resistance, and VP is the peak voltage for a
single tone.
PO
NOISE ANALYSIS
PIN
(dBm)
IIP3
IMD3
3X
PS
Figure 86.
Due to the intercept point's ease of use in system
level calculations for receiver chains, it has become
the
specification
of
choice
for
guiding
distortion-related design decisions. Traditionally,
these systems use primarily class-A, single-ended RF
amplifiers as gain blocks. These RF amplifiers are
typically designed to operate in a 50-Ω environment.
Giving intercept points in dBm implies an associated
impedance (50 Ω).
However, with an operational amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to their outputs regardless of the impedance present,
it is important to comprehend this when evaluating
the intercept point of an operational amplifier. The
THS4211 yields optimum distortion performance
when loaded with 150 Ω to 1 kΩ, very similar to the
input impedance of an analog-to-digital converter
over its input frequency band.
As a result, terminating the input of the ADC to 50 Ω
can actually be detrimental to system performance.
The discontinuity between open-loop, class-A
amplifiers and closed-loop, class-AB amplifiers
becomes apparent when comparing the intercept
points of the two types of devices. Equation 2 and
Equation 3 define an intercept point, relative to the
intermodulation distortion.
High slew rate, unity-gain stable, voltage-feedback
operational amplifiers usually achieve their slew rate
at the expense of a higher input noise voltage. The
7-nV/√Hz input voltage noise for the THS4211 and
THS4215 is, however, much lower than comparable
amplifiers. The input-referred voltage noise and the
two input-referred current noise terms (4 pA/√Hz)
combine to give low output noise under a wide variety
of operating conditions. Figure 87 shows the amplifier
noise analysis model with all the noise terms
included. In this model, all noise terms are taken to
be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
THS4211/THS4215
ENI
+
RS
ERS
IBN
EO
_
4kTRS
Rf
Rg
4kT
Rg
IBI
ERF
4kTRf
4kT = 1.6E-20J
at 290K
Figure 87. Noise Analysis Model
The total output shot noise voltage can be computed
as the square of all square output noise voltage
contributors. Equation 4 shows the general form for
the output noise voltage using the terms shown in
Equation 4:
EO +
Ǹǒ
2
Ǔ
2
ENI 2 ) ǒIBNRSǓ ) 4kTR S NG 2 ) ǒIBIRfǓ ) 4kTRfNG
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THS4215
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Dividing this expression by the noise gain [NG= (1 +
Rf/Rg) ] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 5:
Ǹ
1
2
2
E NI 2 ) ǒI BNRSǓ ) 4kTR S )
ǒINGR Ǔ ) 4kTR
NG
BI
f
0.5
VS =±5 V
R(ISO) = 10 Ω
CL = 100 pF
f
(5)
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4211 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier's open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. When the primary considerations
are frequency response flatness, pulse response
fidelity, or distortion, the simplest and most effective
solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a
higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4211. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4211 output pin (see Board Layout
Guidelines).
The criterion for setting this R(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load. For a gain of +2, the frequency response at the
output pin is already slightly peaked without the
capacitive load, requiring relatively high values of
R(ISO) to flatten the response at the load. Increasing
the noise gain also reduces the peaking.
Normalized Gain - dB
EO +
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
0
-0.5
R(ISO) = 15 Ω
CL = 50 pF
-1
-1.5
R(ISO) = 25 Ω
CL = 10 pF
-2
-2.5
-3
100 k
1M
10 M
100 M
1G
Capacitive Load - Hz
Figure 88. Isolation Resistor Diagram
BOARD LAYOUT
Achieving optimum performance with a high
frequency amplifier like the THS4211 requires careful
attention to board layout parasitics and external
component types.
Recommendations that optimize performance include
the following:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the PCB.
space
space
26
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3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4211. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good
high frequency performance. Again, keep their
leads and PCB trace length as short as possible.
Never use wire-wound type resistors in a
high-frequency application. Since the output pin
and inverting input pin are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistor, if any, as
close as possible to the output pin. Other network
components,
such
as
noninverting
input-termination resistors, should also be placed
close to the package. Where double-side
component mounting is allowed, place the
feedback resistor directly under the package on
the other side of the board between the output
and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create
significant time constants that can degrade
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values >
2.0 kΩ, this parasitic capacitance can add a pole
and/or a zero below 400 MHz that can effect
circuit operation. Keep resistor values as low as
possible,
consistent
with
load
driving
considerations. A good starting point for design is
to set the Rf to 249 Ω for low-gain, noninverting
applications. This setting automatically keeps the
resistor noise terms low and minimizes the effect
of their parasitic capacitance.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set RISO from the
plot of recommended RISO vs capacitive load
(See Figure 88). Low parasitic capacitive loads (<
4 pF) may not need an R(ISO), since the THS4211
is nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an R(ISO) are allowed as the signal gain
increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB
signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline
layout techniques). A 50-Ω environment is
normally not necessary onboard, and in fact a
higher
impedance
environment
improves
distortion as shown in the distortion versus load
plots. With a characteristic board trace
impedance defined on the basis of board material
and trace dimensions, a matching series resistor
into the trace from the output of the THS4211 is
used as well as a terminating shunt resistor at the
input of the destination device. Remember also
that the terminating impedance is the parallel
combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the
trace impedance. If the 6-dB attenuation of a
doubly-terminated
transmission
line
is
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of
R(ISO) vs capacitive load (See Figure 88). This
setting does not preserve signal integrity or a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
5. Socketing a high speed part like the THS4211
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create a troublesome parasitic
network which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
THS4211 onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS4211 and THS4215 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 89(a) and Figure 89(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 89(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also
be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
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THS4215
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The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the heretofore awkward
mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 89. Views of Thermally
Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as
shown in Figure 90. There should be etching for
the leads as well as etch for the thermal pad.
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
Single or Dual
68 Mils x 70 Mils
(Via Diameter = 13 Mils)
Figure 90. PowerPAD PCB Etch and
Via Pattern
2. Place five holes in the area of the thermal pad.
These holes should be 13 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. They help dissipate the heat generated by
the THS4211 and THS4215 IC. These additional
vias may be larger than the 13-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered, so wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This resistance makes the
soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
28
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transfer. Therefore, the holes under the THS4211
and THS4215 PowerPAD package should make
their connection to the internal ground plane, with
a complete connection around the entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
For a given θJA, the maximum power dissipation is
shown in Figure 91 and is calculated by Equation 6:
Tmax * T A
PD +
q JA
where
PD = Maximum power dissipation of THS4211 (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to the case
θCA = Thermal coefficient from the case to ambient air
(°C/W).
(6)
The next consideration is the package constraints.
The two sources of heat within an amplifier are
quiescent power and output power. The designer
should never forget about the quiescent heat
generated within the device, especially multi-amplifier
devices. Because these devices have linear output
stages (Class AB), most of the heat dissipation is at
low output voltages with high output currents.
The other key factor when dealing with power
dissipation is how the devices are mounted on the
PCB. The PowerPAD devices are extremely useful
for heat dissipation. But, the device should always be
soldered to a copper plane to fully use the heat
dissipation properties of the PowerPAD. The SOIC
package, on the other hand, is highly dependent on
how it is mounted on the PCB. As more trace and
copper area is placed around the device, θJA
decreases and the heat dissipation capability
increases. For a single package, the sum of the RMS
output currents and voltages should be used to
choose the proper package.
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The THS4211 device does not incorporate automatic
thermal shutoff protection, so the designer must take
care to ensure that the design does not violate the
absolute maximum junction temperature of the
device. Failure may result if the absolute maximum
junction temperature of 150°C is exceeded.
The thermal characteristics of the device are dictated
by the package and the PCB. Maximum power
dissipation for a given package can be calculated
using Equation 7:
Tmax–T A
P Dmax +
q JA
where
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
(7)
For systems where heat dissipation is more critical,
the THS4211 is offered in an 8-pin MSOP with
PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over
the traditional SOIC. Maximum power dissipation
levels are depicted in the graph for the two packages.
The data for the DGN package assumes a board
layout that follows the PowerPAD layout guidelines
referenced above and detailed in the PowerPAD
application notes in the Additional Reference Material
section at the end of the data sheet.
PD - Maximum Power Dissipation - W
3.5
8-Pin DGN Package
3
2.5
2
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power
dissipation, but also dynamic power dissipation. Often
maximum power dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
DESIGN TOOLS
Performance vs Package Options
The THS4211 and THS4215 are offered in a different
package options. However, performance may be
limited due to package parasitics and lead inductance
in some packages. In order to achieve maximum
performance of the THS4211 and THS4215, Texas
Instruments recommends using the leadless MSOP
(DRB) or MSOP (DGN) packages, in addition to
proper high-speed PCB layout. Figure 92 shows the
unity-gain frequency response of the THS4211 using
the leadless MSOP, MSOP, and SOIC package for
comparison. Using the THS4211 and THS4215 in a
unity-gain with the SOIC package may result in the
device becoming unstable. In higher gain
configurations, this effect is mitigated by the reduced
bandwidth. As such, the SOIC is suitable for
application with gains equal to or higher than +2 V/V
or (–1 V/V).
12
_
10
499 Ω
49.9 Ω
6
4
SOIC, Rf = 100 Ω
2
0
-2
8-Pin D Package
PIN = -7 dB
VS =±5 V
-4
1.5
SOIC, Rf = 0 Ω
Rf
+
8
Normalized Gain - dB
THERMAL ANALYSIS
10 M
Leadless MSOP, &
MSOP Rf = 0 Ω
100 M
1G
f - Frequency - Hz
1
Figure 92. Effects of Unity-Gain Frequency
Response for Differential Packages
0.5
0
-40
-20
0
20
40
60
TA - Ambient Temperature - °C
80
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
TJ= 150°C, No Airflow
Figure 91. Maximum Power Dissipation vs
Ambient Temperature
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THS4215
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Evaluation Fixtures, SPICE Models, and
Applications Support
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, evaluation boards have
been developed for the THS4211 operational
amplifier. Three evaluation boards are available: one
THS4211 and one THS4215, both configurable for
different gains, and a third for untiy gain (THS4211
only). These boards are easy to use, allowing for
straightforward evaluation of the device. These
evaluation boards can be ordered through the Texas
Instruments web site at www.ti.com, or through your
local Texas Instruments sales representative.
Schematics for the evaluation boards are shown
below.
The THS4211/THS4215 EVM board shown in
Figure 95 through Figure 99 accommodates different
gain configurations. Its default component values are
set to give a gain of 2. The EVM can be configured
for unity-gain; however, it is strongly not
recommended. Evaluating the THS4211/THS4215 in
unity-gain using this EVM may cause the device to
become unstable. The stability of the device can be
controlled by adding a large resistor in the feedback
path, but performance is sacrificed. Figure 93 shows
the small-signal frequency response of the THS4211
with different feedback resistors in the feedback path.
Figure 94 is the small frequency response of the
THS4211 using the unity-gain EVM.
Small Signal Gain - dB
17
15
_
13
+
Rf
Rf = 50 Ω
9
7
Rf = 200 Ω
3
1
-1
-3
-5
PIN = -7 dBm
VS = ±5 V
10 M
100 M
1G
10 G
f - Frequency - Hz
Figure 93. Frequency Response vs Feedback
Resistor Using the EDGE #6439527 EVM
30
_
3
+
499 Ω
49.9 Ω
2
1
0
-1
-2
PIN = -7 dBm
VS = ±5 V
-3
-4
100 k
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1M
10 M
100 M
f - Frequency - Hz
1G
10 G
Figure 94. Frequency Response Using the
EDGE #6443547 G = +1 EVM
The frequency-response peaking is due to the lead
inductance in the feedback path. Each pad and trace
on a PCB has an inductance associated with it, which
in conjunction with the inductance associated with the
package may cause frequency-response peaking,
causing the device to become unstable.
In order to achieve the maximum performance of the
device, PCB layout is very critical. Texas Instruments
has developed an EVM for the evaluation of the
THS4211 configured for a gain of 1. The EVM is
shown in Figure 100 through Figure 104. This EVM is
designed to minimize peaking in the unity-gain
configuration.
ƪ
Rf = 100 Ω
5
4
Minimizing the inductance in the feedback path is
critical for reducing the peaking of the frequency
response in unity-gain. The recommended maximum
inductance allowed in the feedback path is 4 nH. This
inductance can be calculated using Equation 8:
L(nH) + Kȏ ln 2ȏ ) 0.223 W ) T ) 0.5
ȏ
W)T
Rf = 0 Ω
499 Ω
49.9 Ω
11
Small Signal Gain - dB
5
ƫ
where
W = Width of trace in inches.
ȏ = Length of the trace in inches.
T = Thickness of the trace in inches.
K = 5.08 for dimensions in inches, and K = 2 for dimensions
in cm.
(8)
space
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THS4215
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Vs+
J9
Power Down
R8
C8
R9
R5
Vs -
Vs+
7 8
2 _
R3
J1
Vin -
U1
R6
6
J4
Vout
3 +
R2
R7
4 1
Vs -
J2
Vin+
J8
Power Down Ref
C7
R1
R4
J7
VS-
J6
GND
J5
VS+
TP1
FB1
FB2
VS-
C5
C6
Figure 96. THS4211/THS4215 EVM Board Layout
(Top Layer)
VS+
C1
C2
+
C3
+
C4
Figure 95. THS4211/THS4215 EVM
Circuit Configuration
Figure 97. THS4211/THS4215 EVM Board Layout
(Second Layer, Ground)
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THS4215
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Vs+
7 8
2 _
U1
R6
6
J4
Vout
3 +
R7
4 1
J2
Vin+
Vs R4
J7
VS-
J6
GND
J5
VS+
TP1
FB1
FB2
VS-
C5
VS+
C1
C6
+
C2
+
C3
C4
Figure 100. THS4211 Unity-Gain EVM
Circuit Configuration
Figure 98. THS4211/THS4215 EVM Board Layout
(Third Layer, Power)
Figure 101. THS4211 Unity-Gain EVM Board
Layout (Top Layer)
Figure 99. THS4211/THS4215 EVM Board Layout
(Bottom Layer)
32
Submit Documentation Feedback
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com ................................................................................................................................... SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009
Figure 102. THS4211 Unity-Gain EVM Board
Layout (Second Layer, Ground)
Figure 103. THS4211 Unity-Gain EVM Board
Layout (Third Layer, Power)
Figure 104. THS4211 Unity-Gain EVM
Board Layout (Bottom Layer)
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
Submit Documentation Feedback
33
THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits,
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the THS4500 family of devices is available
through the Texas Instruments web site (www.ti.com).
The Product Information Center (PIC) is available for
design assistance and detailed product information.
These models do a good job of predicting
small-signal ac and transient performance under a
wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between
the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
ADDITIONAL REFERENCE MATERIAL
•
•
PowerPAD Made Easy, application brief
(SLMA004)
PowerPAD
Thermally-Enhanced
Package,
technical brief (SLMA002)
space
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November, 2004) to Revision E .......................................................................................... Page
•
Updated document format to current standards ................................................................................................................... 1
•
Changed high output drive (IO) bullet in Features list from 200 mA to 170 mA ................................................................... 1
•
Changed Absolute Maximum Ratings table; increased output current specification, deleted lead temperature
specification .......................................................................................................................................................................... 2
•
Corrected typo in Turn-off-time delay parametric units; changed to µs ............................................................................... 7
34
Submit Documentation Feedback
Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4211D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4211
THS4211DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BEJ
THS4211DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BFN
THS4211DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BFN
THS4211DGNRG4
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BFN
THS4211DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4211
THS4211DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4211
THS4211DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4211
THS4211DRBTG4
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4211
THS4215D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4215
THS4215DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BEZ
THS4215DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BEQ
THS4215DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4215
THS4215DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4215
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
THS4211DGNR
HVSSOP
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4211DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THS4211DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
THS4211DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
THS4215DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
THS4215DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4211DGNR
HVSSOP
DGN
8
2500
364.0
364.0
27.0
THS4211DR
SOIC
D
8
2500
350.0
350.0
43.0
THS4211DRBR
SON
DRB
8
3000
350.0
350.0
43.0
THS4211DRBT
SON
DRB
8
250
210.0
185.0
35.0
THS4215DRBR
SON
DRB
8
3000
350.0
350.0
43.0
THS4215DRBT
SON
DRB
8
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.5 0.1
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
(0.65)
8X
0.37
0.25
0.1
0.05
C A B
C
0.5
0.3
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31) 1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.23)
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
8X (0.31)
4X
(0.725)
8
1
(2.674)
SYMM
(1.55)
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.846
1.646
TYPICAL
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.846)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(2.15)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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