Texas Instruments | Dual Low-Noise High-Speed Precision Operational Amplifier | Datasheet | Texas Instruments Dual Low-Noise High-Speed Precision Operational Amplifier Datasheet

Texas Instruments Dual Low-Noise High-Speed Precision Operational Amplifier Datasheet
TLE2142-Q1
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Excalibur™ LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIER
FEATURES
1
• Qualified for Automotive Applications
• Low Noise
– 10 Hz: 15 nV/√Hz
– 1 kHz: 10.5 nV/√Hz
• 10000-pF Load Capability
• 20-mA Short-Circuit Output Current (Min)
• 27-V/µs Slew Rate (Min)
• High Gain-Bandwidth Product: 5.9 MHz
• Single or Split Supply: 4 V to 44 V
• Fast Settling Time
– 340 ns to 0.1%
– 400 ns to 0.01%
• Large Output Swing:
VCC– + 0.1 V to VCC+ – 1 V
D PACKAGE
(TOP VIEW)
2
1OUT
1IN1IN+
VCC-
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN2IN+
DESCRIPTION/ORDERING INFORMATION
The TLE2142 device is a high-performance, internally compensated operational amplifier built using the Texas
Instruments complementary bipolar Excalibur™ process. It is a pin-compatible upgrade to standard industry
products.
The design incorporates an input stage that simultaneously achieves low audio-band noise of 10.5 nV/√Hz with a
10-Hz 1/f corner and symmetrical 40-V/µs slew rate typically with loads up to 800 pF. The resulting low distortion
and high power bandwidth are important in high-fidelity audio applications. A fast settling time of 340 ns to 0.1%
of a 10-V step with a 2-kΩ/100-pF load is useful in fast actuator/positioning drivers. Under similar test conditions,
settling time to 0.01% is 400 ns.
The device is stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHz at
this high loading level. As such, the TLE2142 is useful for low-droop sample-and-holds and direct buffering of
long cables, including 4-mA to 20-mA current loops.
The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches as
is evidenced by a 500-µV maximum offset voltage and 1.7-µV/°C typical drift. Minimum common-mode rejection
ratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.
Device performance is relatively independent of supply voltage over the ±2-V to ±22-V range. Inputs can operate
between VCC– – 0.3 V to VCC+ – 1.8 V without inducing phase reversal, although excessive input current may flow
out of each input exceeding the lower common-mode input range. The all-npn output stage provides a nearly
rail-to-rail output swing of VCC– + 0.1 V to VCC+ – 1 V under light current-loading conditions. The device can
sustain shorts to either supply, because output current is internally limited, but care must be taken to ensure that
maximum package power dissipation is not exceeded.
The TLE2142 can also be used as a comparator. Differential inputs of VCC± can be maintained without damage
to the device. Open-loop propagation delay with TTL supply levels is typically 200 ns. This gives a good
indication as to output stage saturation recovery when the device is driven beyond the limits of recommended
output swing.
The TLE2142 device is available in industry-standard 8-pin small-outline (D) packages. The device is
characterized for operation from –40°C to 125°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excalibur is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TLE2142-Q1
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SYMBOL (EACH AMPLIFIER)
IN+
+
IN-
-
OUT
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
2
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
TLE2142QDRQ1
TOP-SIDE MARKING
2142Q
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Q33
Q32
Q31
Q29
D7
D6
Q28
65
43
14
8
1
Transistors
Resistors
Diodes
Capacitors
Epi-FET
TLE2142
COMPONENT
DEVICE COMPONENT COUNT
VCC Q17
Q7
R5
C1
Q9
Q12
Q11
Q4
Q2
Q6
IN +
IN -
Q1
R2
D1
Q3
R1
R10
Q16
Q15
Q14
R8
R3
Q5 Q8
R4
R6
Q10
D2
Q13
R7
R9
C2
R11
Q18
VCC +
Q19
R12
Q20
Q21
C3
C4
Q24
D5
Q25
R13
D3
D4
Q22
R14
R16
R17
Q23
R15
Q27
Q26
R18
D8
Q30
R20
R22
Q35
R23
Q36
Q37
R19
Q34
R21
R24
OUT
EQUIVALENT SCHEMATIC
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC+
Supply voltage (2)
22 V
VCC–
Supply voltage
–22 V
VID
Differential input voltage (3)
±44 V
VI
Input voltage range (any input)
II
Input current (each input)
±1 mA
IO
Output current
±80 mA
Total current into VCC+
80 mA
VCC+ to (VCC– – 0.3) V
Total current out of VCC–
80 mA
Duration of short-circuit current at (or below) 25°C (4)
Unlimited
θJA
Package thermal impedance (5) (6)
TA
Operating free-air temperature range
–40°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
ESD
(1)
(2)
(3)
(4)
(5)
(6)
97.1°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
Electrostatic discharge rating, Human-body model
500 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
Differential voltages are at IN+ with respect to IN–. Excessive current flows, if input, are brought below VCC– – 0.3 V.
The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
VCC±
Supply voltage
VIC
Common-mode input voltage
TA
Operating free-air temperature
4
VCC = 5 V
VCC± = ±15 V
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MIN
MAX
UNIT
±2
±22
V
0
2.7
–15
12.7
–40
125
V
°C
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ELECTRICAL CHARACTERISTICS
VCC = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
αVIO
Temperature coefficient of
input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIO
Input offset current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIB
Input bias current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
VICR
Common-mode input
voltage range
TA (1)
MIN
25°C
High-level output voltage
25°C
8
Full range
25°C
–0.8
Full range
25°C
0 to 3
–0.3 to
3.2
0 to 2.7
–0.3 to
2.9
3.9
4.1
4
IOH = –15 mA
3.4
3.7
IOH = –100 µA
3.75
Full range
Low-level output voltage
µA
V
V
25°C
75
125
150
225
1.2
IOL = 100 µA
1.4
200
Full range
250
IOL = 10 mA
1.25
25°C
50
Full range
5
220
mV
V
mV
V
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
70
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
f = 1 MHz
25°C
30
Ω
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
ICC
Supply current
VO = 2.5 V, No load, VIC = 2.5 V
(1)
VIC = ±2.5 V, RL = 2 kΩ,
VO = 1 V to -1.5 V
nA
3.45
IOL = 15 mA
IOL = 1 mA
µV
3.65
IOL = 150 µA
IOL = 1.5 mA
–2
–2.3
3.8
IOH = –10 mA
100
200
Full range
UNIT
µV/°C
1.7
RS = 50 Ω
IOH = –1 mA
VOL
1900
2600
Full range
IOH = –150 µA
VOH
MAX
220
Full range
25°C
IOH = –1.5 mA
TYP
25°C
85
Full range
80
25°C
90
Full range
85
25°C
118
dB
106
6.6
Full range
V/mV
dB
8.8
9.2
mA
Full range is –40°C to 125°C.
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OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR+
Positive slew rate
AVD = –1, RL = 2 kΩ (1), CL = 500 pF
45
V/µs
SR–
Negative slew rate
AVD = –1, RL = 2 kΩ (1), CL = 500 pF
42
V/µs
ts
Settling time
AVD = –1, 2.5-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
Vn(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.92
f = 1 kHz
0.5
THD+N
Total harmonic distortion plus noise
VO = 1 V to 3 V, RL = 2 kΩ (1), AVD = 2,
f = 10 kHz
B1
Unity-gain bandwidth
RL = 2 kΩ (1), CL = 100 pF
5.9
MHz
Gain-bandwidth product
RL = 2 kΩ (1), CL = 100 pF, f = 100 kHz
5.8
MHz
Maximum output-swing bandwidth
VO(PP) = 2 V, RL = 2 kΩ (1), AVD = 1, CL = 100 pF
660
kHz
57
°
BOM
φm
(1)
6
Phase margin at unity gain
To 0.1%
0.16
To 0.01%
0.22
f = 10 Hz
15
f = 1 kHz
10.5
(1)
RL = 2 kΩ , CL = 100 pF
0.0052
µs
nV/√Hz
µV
pA/√Hz
%
RL terminated at 2.5 V.
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ELECTRICAL CHARACTERISTICS
VCC = ±15 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VIC = 0, RS = 50 Ω
αVIO
Temperature coefficient of
input offset voltage
VIC = 0, RS = 50 Ω
IIO
Input offset current
VIC = 0, RS = 50 Ω
IIB
Input bias current
VIC = 0, RS = 50 Ω
VICR
Common-mode input
voltage range
TA (1)
MIN
25°C
7
Full range
25°C
–0.7
–15 to –15.3 to
13
13.2
Full range
–15 to –15.3 to
12.7
12.9
13.8
25°C
14
IO = –15 mA
13.3
13.7
IO = –100 µA
13.7
13.3
IO = 150 µA
–14.7
–14.9
VOM–
25°C
–14.5
–14.8
IO = 15 mA
–13.4
–13.8
IO = 100 µA
–14.6
IO = 1 mA
Full range
IO = 10 mA
nA
µA
V
V
13.6
IO = –10 mA
IO = 1.5 mA
µV
14.1
13.7
Full range
–1.5
–1.8
25°C
RS = 50 Ω
100
250
Full range
UNIT
µV/°C
1.7
25°C
IO = –1 mA
Maximum negative peak
output voltage swing
1200
2000
Full range
IO = –1.5 mA
Maximum positive peak
output voltage swing
MAX
290
Full range
IO = –150 µA
VOM+
TYP
V
–14.5
–13.4
25°C
100
Full range
20
450
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
65
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
f = 1 MHz
25°C
30
Ω
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
IOS
Short-circuit output current
VO = 0
ICC
Supply current
VO = 0, No load, VIC = 2.5 V
(1)
VO = ±10 V, RL = 2 kΩ
VID = 1 V
VID = –1 V
25°C
85
Full range
80
25°C
90
Full range
85
25°C
25°C
108
dB
106
–25
–50
20
31
6.9
Full range
V/mV
dB
mA
9
9.4
mA
Full range is –40°C to 125°C.
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OPERATING CHARACTERISTICS
VCC = ±15 V, TA = 25°C (unless otherwise noted)
MIN
TYP
SR+
Positive slew rate
PARAMETER
AVD = –1, RL = 2 kΩ, CL = 100 pF
TEST CONDITIONS
27
45
V/µs
SR–
Negative slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
27
42
V/µs
ts
Settling time
AVD = –1, 10-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
Vn(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.89
f = 1 kHz
0.47
THD+N
Total harmonic distortion plus noise
VO(PP) = 20 V, RL = 2 kΩ, AVD = 10, f = 10 kHz
0.01
B1
Unity-gain bandwidth
RL = 2 kΩ, CL = 100 pF
To 0.1%
0.34
To 0.01%
0.4
f = 10 Hz
15
f = 1 kHz
10.5
MAX
UNIT
µs
nV/√Hz
µV
pA/√Hz
%
6
MHz
Gain-bandwidth product
RL = 2 kΩ, CL = 100 pF, f = 100 kHz
5.9
MHz
BOM
Maximum output-swing bandwidth
VO(PP) = 20 V, AVD = 1, RL = 2 kΩ, CL = 100 pF
668
kHz
φm
Phase margin at unity gain
RL = 2 kΩ, CL = 100 pF
58
°
8
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TYPICAL CHARACTERISTICS
Table of Graphs
VIO
Input offset voltage
Distribution
Figure 1
IIO
Input offset current
vs Free-air temperature
Figure 2
IIB
Input bias current
vs Common-mode input voltage
Figure 3
vs Free-air temperature
Figure 4
vs Supply voltage
Figure 5
vs Free-air temperature
Figure 6
vs Output current
Figure 7
vs Settling time
Figure 9
vs Supply voltage
Figure 5
vs Free-air temperature
Figure 6
vs Output current
Figure 8
vs Settling time
Figure 9
VOM+
VOM–
Maximum positive peak output voltage
Maximum negative peak output voltage
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
Figure 10
VOH
High-level output voltage
vs Output current
Figure 11
VOL
Low-level output voltage
vs Output current
Figure 12
Phase shift
vs Frequency
Figure 13
vs Frequency
Figure 13
vs Free-air temperature
Figure 14
AVD
Large-signal differential voltage amplification
zo
Closed-loop output impedance
vs Frequency
Figure 15
IOS
Short-circuit output current
vs Free-air temperature
Figure 16
vs Frequency
Figure 17
vs Free-air temperature
Figure 18
vs Frequency
Figure 19
vs Free-air temperature
Figure 20
vs Supply voltage
Figure 21
vs Free-air temperature
Figure 22
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
ICC
Supply current
Vn
Equivalent input noise voltage
vs Frequency
Figure 23
Vn
Input noise voltage
Over a 10-second period
Figure 24
In
Noise current
vs Frequency
Figure 25
THD+N
Total harmonic distortion plus noise
vs Frequency
Figure 26
vs Free-air temperature
Figure 27
vs Load capacitance
Figure 28
Noninverting large signal
vs Time
Figure 29
Inverting large signal
vs Time
Figure 30
Small signal
vs Time
Figure 31
Unity-gain bandwidth
vs Load capacitance
Figure 32
Gain margin
vs Load capacitance
Figure 33
Phase margin
vs Load capacitance
Figure 34
SR
Slew rate
Pulse response
B1
φm
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INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
TLE2142
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
20
24
18
IIIO
IO − Input Offset Current − nA
Percentage of Units − %
20
236 Units Tested From 1 Wafer Lot
VCC ± = ± 15 V
TA = 25°C
P Package
16
12
8
4
VO = 0
VIC = 0
16
14
12
10
VCC ± = ± 2.5 V
8
6
VCC ± = ± 15 V
4
2
0
−800 −600
200 400 600
−400 −200 0
VIO − Input Offset Voltage − µV
0
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
800
Figure 1.
Figure 2.
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
−1000
0
VCC ± = ± 2.5 V
VO = 0
VIC = 0
IIIB
IB − Input Bias Current − nA
uA
IIIB
IB − Input Bias Current − µA
−0.2
−0.4
−0.6
TA = 125°C
−0.8
TA = 25°C
−1
−1.2
−1.4
−3
TA = − 55°C
−2.5 −2
−1.5 −1 −0.5
0
0.5
VIC − Common-Mode Input Voltage − V
1
−900
VCC ± = ± 2.5 V
−800
−700
VCC ± = ± 15 V
−600
−500
−75 −50 −25
0
25
50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 3.
10
Figure 4.
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MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
15
RL = 2 kΩ
TA = 25°C
18
VCC ± = ± 15 V
V OM − Maximum Peak Output Voltage − V
V OM − Maximum Peak Output Voltage − V
24
12
VOM +
6
0
−6
VOM −
−12
−18
− 24
0
3
6
9
12
15
18
21
14.6
RL = ∞
14.2
VOM +
13.8
RL = 2 kΩ
−13.8
−14.2
RL = 2 kΩ
VOM −
−14.6
RL = ∞
−15
−75 −50 −25
0
25
50 75 100 125 150
TA − Free-Air Temperature − °C
24
VCC ± − Supply Voltage − V
Figure 5.
Figure 6.
MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
14.6
VCC ± = ± 15 V
14.4
14.2
TA = 125°C
14
TA = 25°C
TA = − 55°C
13.8
13.6
−0.1
−0.4
−1
−4
−10
− 40
−100
V OM − − Maximum Negative Peak Output Voltage − V
V OM + − Maximum Positive Peak Output Voltage − V
MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
−13.4
VCC ± = ± 15 V
−13.6
−13.8
TA = 125°C
−14
−14.2
TA = − 55°C
−14.4
TA = 25°C
−14.6
−14.8
− 15
0.1
IO − Output Current − mA
Figure 7.
0.4
1
4
10
40
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IO − Output Current − mA
Figure 8.
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MAXIMUM PEAK OUTPUT VOLTAGE
vs
SETTLING TIME
AVD = −1
VCC ± = ± 15 V
TA = 25°C
10
7.5
0.1%
0.01%
5
2.5
Rising
0
Falling
−2.5
0.01%
−5
0.1%
−7.5
−10
−12.5
0
100
200
300
400
500
V O(PP) − Maximum Peak-to-Peak Output Voltage − V
VVOM
OM − Maximum Peak Output Voltage − V
12.5
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
ts − Settling Time − ns
30
VCC ± = ± 15 V
RL = 2 kΩ
25
TA = 25°C
20
TA = 125°C
15
10
TA = − 55°C
5
0
100 k
400 k
Figure 9.
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
10 M
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4.6
1400
VCC = 5 V
VOL
V
OL − Low-Level Output Voltage − mV
VCC = 5 V
V OH − High-Level Output Voltage − V
4M
1M
f − Frequency − Hz
Figure 10.
4.4
TA = 125°C
4.2 TA = 25°C
4 TA = − 55°C
3.8
3.6
1200
TA = 125°C
1000
800
600
TA = 25°C
400
200
TA = − 55°C
3.4
−0.1
−1
−10
−100
0
0.1
IO − Output Current − mA
Figure 11.
12
1
10
100
IO − Output Current − mA
Figure 12.
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LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
0°
110
20°
100
40°
90
60°
80 Phase Shift
80°
70
100°
60
120°
AVD
50
140°
40
160°
180°
30
VCC ± = ± 15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
20
10
0
200°
220°
240°
− 10
1
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
140
VCC ± = ± 15 V
VO = ± 10 V
AAVD
VD − Large-Signal Differential
Voltage Amplification − dB
120
Phase Shift
AAVD
VD − Large-Signal Differential
Voltage Amplification − dB
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
260°
10 M
RL = 10 kΩ
120
RL = 2 kΩ
100
80
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 13.
Figure 14.
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
60
100
VCC ± = ± 15 V
VO = 0
IOS − Short-Circuit Output Current − mA
z o − Closed-Loop Output Impedance − Ω
30 Ω
10
1
AVD = 100
0.1
AVD = 10
AVD = 1
0.01
0.001
1k
10 k
100 k
f − Frequency − Hz
1M
10 M
50
VID = 1
40
30
VID = − 1
20
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 15.
Figure 16.
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COMMON-MODE REJECTION RATIO
vs
FREQUENCY
120
VCC ± = ± 15 V
TA = 25°C
CMRR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
140
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
120
100
80
60
40
20
0
100
1k
10 k
100 k
VIC = VICRmin
VCC = 5 V
116
112
108
VCC ± = ± 15 V
104
100
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 18.
1M
f − Frequency − Hz
Figure 17.
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
110
kkSVR
SVR − Supply-Voltage Rejection Ratio − dB
kkSVR
SVR − Supply-Voltage Rejection Ratio − dB
160
140
kSVR +
120
kSVR −
100
80
60
40
20 VCC ± = ± 2.5 V to ± 15 V
TA = 25°C
0
10
100
1k
10 k
100 k
f − Frequency − Hz
1M
10 M
108
106
104
102
100
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 19.
14
VCC ± = ± 2.5 V to ± 15 V
Figure 20.
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SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
4
3.8
VO = 0
No Load
TA = 125°C
IIDD
CC − Supply Current − mA
IIDD
CC − Supply Current − mA
3.6
3.5
TA = 25°C
3
TA = − 55°C
2.5
VCC ± = ± 15 V
3.4
VCC ± = ± 2.5 V
3.2
3
VO = 0
No Load
2.8
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
2
0
4
8
12
16
20
|VCC ±| − Supply Voltage − V
24
Figure 21.
Figure 22.
INPUT NOISE VOLTAGE
OVER A 10-SECOND PERIOD
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
750
VCC ± = ± 15 V
RS = 20 Ω
VCC ± = ± 15 V
f = 0.1 to 10 Hz
TA = 25°C
500
200
Input Noise Voltage − nV
Vn − Equivalent Input Noise Voltage − nV/ Hz
250
TA = − 55°C
150
TA = 125°C
100
TA = 25°C
50
250
0
−250
−500
−750
0
1
10
100
1k
10 k
0
f − Frequency − Hz
Figure 23.
2
4
6
8
10
t − Time − s
Figure 24.
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NOISE CURRENT
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
6
TA = − 55°C
4
TA = 25°C
2
TA = 125°C
0
10
1
100
1k
10 k
f − Frequency − Hz
THD + N − Total Harmonic Distortion + Noise − %
In − Noise Current − pA/ Hz
8
1%
VO(PP) = 20 V
VCC ± = ± 15 V
TA = 25°C
0.1%
AV = 10
RL = 600 Ω
AV = 10
RL = 2 kΩ
0.001%
10
100
Figure 25.
100 k
Figure 26.
50
50
40
SR − Slew Rate − V/ µ s
SR +
SR − Slew Rate − V/ µ s
1k
10 k
f − Frequency − Hz
SLEW RATE
vs
LOAD CAPACITANCE
60
40
SR −
30
20
VCC ± = ± 15 V
AVD = − 1
RL = 2 kΩ
CL = 500 pF
SR+
30
20
SR −
10 VCC ± = ± 15 V
AVD = − 1
TA = 25°C
0
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
0
0.01
Figure 27.
16
AV = 100
RL = 2 kΩ
0.01%
SLEW RATE
vs
FREE-AIR TEMPERATURE
10
AV = 100
RL = 600 Ω
0.1
1
CL − Load Capacitance − nF
10
Figure 28.
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INVERTING
LARGE-SIGNAL
PULSE RESPONSE
NONINVERTING
LARGE-SIGNAL
PULSE RESPONSE
15
15
TA = 125°C
TA = 25°C
10
TA = 25°C
5
V
VO
O − Output Voltage − V
V
VO
O − Output Voltage − V
10
TA = − 55°C
0
TA = − 55°C
−5
TA = 25°C
VCC ± = ± 15 V
AVD = 1
RL = 2 kΩ
CL = 300 pF
−10
TA = − 55°C
TA = 125°C
5
0
TA = 125°C
TA = 25°C
−5
VCC ± = ± 15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
−10
TA = 125°C
−15
−15
0
1
2
3
4
5
0
1
2
Figure 29.
4
5
Figure 30.
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
SMALL-SIGNAL
PULSE RESPONSE
100
7
VCC ± = ± 15 V
RL = 2 kΩ
B
B1
1 − Unity-Gain Bandwidth − MHz
TA = − 55°C
50
0
VCC ± = ± 15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
TA = 25°C
−50
3
t − Time − µs
t − Time − µs
V
VO
O − Output Voltage − mV
TA = − 55°C
6
TA = 25°C
5
TA = 125°C
4
3
2
−100
0
400
800
t − Time − ns
1200
1600
1
10
100
1000
10000
CL − Load Capacitance − pF
Figure 31.
Figure 32.
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PHASE MARGIN
vs
LOAD CAPACITANCE
GAIN MARGIN
vs
LOAD CAPACITANCE
14
12
TA = − 55°C
8
6
TA = 125°C
TA = 25°C
50°
TA = 125°C
40°
30°
20°
4
2
10°
TA = 25°C
0
10
TA = − 55°C
60°
φ m − Phase Margin
Gain Margin − dB
10
70°
VCC ± = ± 15 V
AVD = 1
RL = 2 kΩ to ∞
VO = − 10 V to 10 V
100
1000
CL − Load Capacitance − pF
10000
VCC ± = ± 15 V
RL = 2 kΩ
0°
10
Figure 33.
18
100
1000
CL − Load Capacitance − pF
10000
Figure 34.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
TLE2142QDRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
2142Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2014
OTHER QUALIFIED VERSIONS OF TLE2142-Q1 :
• Catalog: TLE2142
• Military: TLE2142M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLE2142QDRQ1
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLE2142QDRQ1
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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