Texas Instruments | 1.8-GHz Low Distortion Current Feedback Amplifier (Rev. B) | Datasheet | Texas Instruments 1.8-GHz Low Distortion Current Feedback Amplifier (Rev. B) Datasheet

Texas Instruments 1.8-GHz Low Distortion Current Feedback Amplifier (Rev. B) Datasheet
D-8
DBV-5
DGN-8
THS3201-EP
DGK-8
www.ti.com ..................................................................................................................................................... SGLS283B – APRIL 2005 – REVISED JANUARY 2009
1.8-GHz LOW-DISTORTION CURRENT-FEEDBACK AMPLIFIER
FEATURES
1
• Unity Gain Bandwidth: 1.8 GHz
• High Slew Rate: 6700 V/µs (G = 2 V/V,
RL = 100 Ω, 5-V Step)
• IMD3: –78 dBc at 20 MHz: (G = 10 V/V,
RL = 100 Ω, 2-VPP Envelope)
• Noise Figure: 11 dB (G = 10 V/V, RG = 28 Ω,
RF = 255 Ω)
• Input Referred Noise (f > 10 MHz)
– Voltage Noise: 1.65 nV/√Hz
– Noninverting Current Noise: 13.4 pA/√Hz
– Inverting Current Noise: 20 pA/√Hz
• Output Drive: 100 mA
• Power-Supply Voltage Range: ±3.3 V to ±7.5 V
2
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
APPLICATIONS
•
•
•
•
(1)
DESCRIPTION
The THS3201 is a wide-band, high-speed
current-feedback amplifier, designed to operate over
a wide supply range of ±3.3 V to ±7.5 V for today's
high-performance applications.
The wide supply range, combined with low distortion
and high slew rate, makes the THS3201 ideally
suited for arbitrary waveform driver applications. The
distortion
performance
also
enables
driving
high-resolution and high-sampling rate ADCs.
High-voltage operation capabilties make the
THS3201 especially suitable for many test,
measurement, and ATE
applications
where
lower-voltage devices do not offer enough voltage
swing capabilty. Output rise and fall times are nearly
independent of step size (to first-order appoximation),
making the THS3201 ideal for buffering small to large
step pulses with excellent linearity in high dynamic
systems.
The THS3201 is offered in 8-pin SOIC and 8-pin
MSOP with PowerPAD™ packages.
RELATED DEVICES AND DESCRIPTIONS
THS3202
±7.5-V 2-GHz Dual Low-Distortion CFB Amplifier
THS3001
±15-V 420-MHz Low-Distortion CFB Amplifier
THS3061/2 ±15-V 300-MHz Low-Distortion CFB Amplifier
THS3122
±15-V Dual CFB Amplifier With 350-mA Drive
THS4271
±7.5-V 1.4-GHz Low-Distortion VFB Amplifier
High-Resolution, High-Sampling-Rate
Analog-to-Digital Converter Drivers
High-Resolution, High-Sampling-Rate
Digital-to-Analog Converter Output Buffers
Test and Measurement
ATE
Additional temperature ranges are available - contact factory
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2009, Texas Instruments Incorporated
THS3201-EP
SGLS283B – APRIL 2005 – REVISED JANUARY 2009 ..................................................................................................................................................... www.ti.com
Low-Noise, Low-Distortion, Wideband Application Circuit
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
+7.5 V
50 Ω Source
8
7
50 Ω
49.9 Ω
VI
Noninverting Gain - dB
RF = 768 Ω
+
49.9 Ω
THS3201
_
50 Ω
-7.5 V
768 Ω
6
5
4
3
2
1
768 Ω
0
100 k
NOTE: Power supply decoupling capacitors not shown
Gain = 2.
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
1M
10 M
100 M
1G
10 G
f - Frequency - Hz
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VS
Supply voltage
VI
Input voltage
IO
Output current
VID
Differential input voltage
16.5 V
±VS
175 mA
±3 V
Continuous power dissipation
See Dissipation Ratings Table
TJ
Maximum junction temperature (2)
TJ
Maximum junction temperature, continuous operation, long-term reliability (3)
Tstg
Storage temperature range
ESD ratings
(1)
(2)
(3)
2
150°C
125°C
–65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s
300°C
Human body model
3000 V
Charged device model
1500 V
Machines model
100 V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum ratings under any condition are limited by the constraints of the silicon process. Stresses above these ratings
may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See Figure 1 for additional information on thermal derating.
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1G
Time-to-Fail − Hrs
100M
80°C, 74M Hrs
10M
100°C, 5.9M Hrs
1M
120°C, 490K Hrs
100K
140°C, 58K Hrs
10K
80
90
100
110
120
130
140
150
TJ − Junction Temperature − °C
Figure 1. EME-G600 Estimated Wirebond Life
DISSIPATION RATINGS
(1)
(2)
PACKAGE
0JC
(°C/W)
0JA (1)
(°C/W)
D (8)
38.3
97.5
DGN (8) (2)
4.7
58.4
This data was taken using the JEDEC standard High-K test PCB.
The THS3201 may incorporate a thermal pad on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature;
which could permanently damage the device. See Texas Instruments technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
RECOMMENDED OPERATING CONDITIONS
Supply voltage
TA
Operating free air temperature
MIN
MAX
Dual supply
±3.3
±7.5
Single supply
6.6
15
–55
125
UNIT
V
°C
PACKAGE/ORDERING INFORMATION
PART NUMBER
THS3201MDEP (1)
THS3201MDREP (1)
THS3201MDGNEP (1)
THS3201MDGNREP
(1)
PACKAGE TYPE
PACKAGE MARKING
SOIC-8
—
MSOP-8-PP
BLM
TRANSPORT MEDIA, QUANTITY
Rails, 75
Tape and reel, 2500
Rails, 80
Tape and reel, 2500
Product Preview
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SGLS283B – APRIL 2005 – REVISED JANUARY 2009 ..................................................................................................................................................... www.ti.com
PIN ASSIGNMENTS
D OR DGN PACKAGE
(TOP VIEW)
NC
VIN −
VIN +
VS−
1
8
2
7
3
6
4
5
NC
VS+
VOUT −
NC
NC − No internal connection
A.
4
If a PowerPAD package is used, the thermal pad is electrically isolated from the active circuitry.
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ELECTRICAL CHARACTERISTICS
VS = ±7.5 V: Rf = 1 kΩ, RL = 100 Ω, G = +2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER
TEMPERATURE
25°C
–55°C to
125°C
UNIT
MIN/
TYP/
MAX
AC Performance
Small-signal bandwidth, –3 dB
(VO = 200 mVPP)
G = +1, RF = 1.2 kΩ
1.8
G = +2, RF = 768 Ω
850
G = +5, RF = 619 Ω
565
GHz
MHz
Typ
G = +10, RF = 487 Ω
520
Bandwidth for 0.1-dB flatness
G = +2, VO = 200 mVpp, RF = 768 Ω
380
MHz
Typ
Large-signal bandwidth
G = +2, VO = 2 Vpp, RF = 715 Ω
880
MHz
Typ
V/µs
Typ
ns
Typ
ns
Typ
dBc
Typ
Slew rate (25% to 75% level)
Rise and fall time
Settling time to 0.1%
Settling time to 0.01%
G = +2, VO = 5-V step, RF = 768 Ω,
Rise/fall
5400/4000
G = +2, VO = 10-V step, RF = 768 Ω,
Rise/fall
9800/6700
G = +2, VO = 4-V step, RF = 768 Ω,
Rise/fall
0.7/0.9
20
G = –2, VO = 2-V step
60
Harmonic distortion
Second-order harmonic
G = +5, f = 10 MHz, VO = 2 Vpp, RL = 100 Ω
Third-order harmonic
–64
–73
Third-order intermodulation
distortion (IMD3)
G = +10, fc = 20 MHz, Δf = 1 MHz,
VO(envelope) = 2 Vpp
–78
dBc
Typ
Noise figure
G = +10, fc = 100 MHz, RF = 255 Ω,
RG = 28
11
dB
Typ
Input voltage noise
f > 10 MHz
1.65
nV/√Hz
Typ
13.4
pA/√Hz
Typ
20
pA/√Hz
Typ
%
Typ
°
Typ
Input current noise (noninverting)
Input current noise (inverting)
f > 10 MHz
Differential gain
G = +2, RL = 150 Ω,
RF = 768 Ω
NTSC
0.008
PAL
0.004
Differential phase
G = +2, RL = 150 Ω,
RF = 768 Ω
NTSC
0.007
PAL
0.011
DC Performance
Open-loop transimpedance gain
VO = ±4 V, RL = 1 kΩ
300
200
100
kΩ
Min
Input offset voltage
VCM = 0 V, RL = 1 kΩ
±0.7
±4
±6
mV
Max
Average offset voltage drift
VCM = 0 V, RL = 1 kΩ
±13
µV/°C
Typ
Input bias current (inverting)
VCM = 0 V, RL = 1 kΩ
Max
Average bias current drift (–)
VCM = 0 V, RL = 1 kΩ
Input bias current (noninverting)
VCM = 0 V, RL = 1 kΩ
Average bias current drift (+)
VCM = 0 V, RL = 1 kΩ
±13
±14
±65
±40
±90
µA
±400
nA/°C
Typ
±60
µA
Max
±400
nA/°C
Typ
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ELECTRICAL CHARACTERISTICS (continued)
VS = ±7.5 V: Rf = 1 kΩ, RL = 100 Ω, G = +2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER
TEMPERATURE
UNIT
MIN/
TYP/
MAX
Min
25°C
25°C
–55°C to
125°C
±5.1
±5
±5
V
58
53
Input
Common-mode input range
RL = 1 kΩ
Common-mode rejection ratio
VCM = ±3.75 V
71
dB
Min
Inverting input impedance, Zin
Open loop
16
Ω
Typ
Noninverting
780
kΩ
Inverting
11
Ω
Noninverting
1
pF
Typ
RL = 1 kΩ
±6
±5.9
±5.7
RL = 100 Ω
±5.8
±5.7
±5.35
V
Min
Current output, sourcing
RL = 20 Ω
115
105
100
mA
Min
Current output, sinking
RL = 20 Ω
100
85
80
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
Input resistance
Input capacitance
Typ
Output
Voltage output swing
Power Supply
Minimum operating voltage
Absolute minimum
±3.3
±3.3
V
Min
Maximum operating voltage
Absolute maximum
±7.5
±7.5
V
Max
Maximum quiescent current
Output open
14
18
22
mA
Max
Power-supply rejection (+PSRR)
VS+ = 7 V to 8 V, RL = 1 kΩ
69
60
56
dB
Min
Power-supply rejection (–PSRR)
VS– = –7 V to –8 V, RL = 1 kΩ
65
58
55
dB
Min
6
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ELECTRICAL CHARACTERISTICS
VS = ±5 V: Rf = 1 kΩ, RL = 100 Ω , G = +2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER
TEMPERATURE
25°C
–55°C to
125°C
UNIT
MIN/
TYP/
MAX
AC Performance
Small-signal bandwidth, –3 dB
(VO = 200 mVPP)
G = +1, RF= 1.2 kΩ
1.3
G = +2, RF = 715 Ω
725
G = +5, RF = 576 Ω
540
GHz
MHz
Typ
G = +10, RF = 464 Ω
480
Bandwidth for 0.1-dB flatness
G = +2, VO = 200 mVpp, RF = 715 Ω
170
MHz
Typ
Large-signal bandwidth
G = +2, VO = 2 Vpp, RF = 715 Ω
900
MHz
Typ
Slew rate (25% to 75% level)
G = +2, VO = 5-V step, RF = 715 Ω,
Rise/Fall
5200/4000
V/µs
Typ
Rise and fall time
G = +2, VO = 4-V step, RF = 715 Ω,
Rise/Fall
0.7/0.9
ns
Typ
ns
Typ
Settling time to 0.1%
Settling time to 0.01%
20
G = –2, VO = 2-V step
60
Harmonic distortion
Second-order harmonic
G = +5, f = 10 MHz,
VO = 2 Vpp
RL = 100 Ω
–69
dBc
Typ
Third-order harmonic
G = +5, f = 10 MHz,
VO = 2 Vpp
RL = 100 Ω
–75
dBc
Typ
Third-order intermodulation
distortion (IMD3)
G = +10, fc = 20 MHz, Δf = 1 MHz,
VO(envelope) = 2 Vpp
–81
dBc
Typ
Noise figure
G = +10, fc = 100 MHz, RF = 255 Ω,
RG = 28
11
dB
Typ
Input voltage noise
f > 10 MHz
1.65
nV/√Hz
Typ
13.4
pA/√Hz
Typ
20
pA/√Hz
Typ
%
Typ
°
Typ
Input current noise (noninverting)
Input current noise (inverting)
f > 10 MHz
Differential gain
G = +2, RL = 150 Ω,
RF = 768 Ω
NTSC
0.006
PAL
0.004
Differential phase
G = +2, RL = 150 Ω,
RF = 768 Ω
NTSC
0.03
PAL
0.04
DC Performance
Open-loop transimpedance gain
VO = ±2 V, RL = 1 kΩ
300
200
100
kΩ
Min
Input offset voltage
VCM = 0 V, RL = 1 kΩ
±0.7
±3
±5.5
mV
Max
Average offset voltage drift
VCM = 0 V, RL = 1 kΩ
±13
µV/°C
Typ
Input bias current (inverting)
VCM = 0 V, RL = 1 kΩ
Max
Average bias current drift (–)
VCM = 0 V, RL = 1 kΩ
Input bias current (noninverting)
VCM = 0 V, RL = 1 kΩ
Average bias current drift (+)
VCM = 0 V, RL = 1 kΩ
±13
±14
±65
±40
±90
µA
±400
nA/°C
Typ
±60
µA
Max
±400
nA/°C
Typ
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ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V: Rf = 1 kΩ, RL = 100 Ω , G = +2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER
TEMPERATURE
UNIT
MIN/
TYP/
MAX
Min
25°C
25°C
–55°C to
125°C
±2.6
±2.5
±2.5
V
71
56
50
Input
Common-mode input range
RL = 1 kΩ
Common-mode rejection ratio
VCM = ±2.5 V
dB
Min
Inverting input impedance, Zin
Open loop, RL = 1 kΩ
17.5
Ω
Typ
Noninverting
780
kΩ
Inverting
11
Ω
Noninverting
1
pF
Typ
V
Min
Input resistance
Input capacitance
Typ
Output
RL = 1 kΩ
±3.65
±3.5
±3.4
RL = 100 Ω
±3.45
±3.33
±3.2
Current output, sourcing
RL = 20 Ω
115
105
90
mA
Min
Current output, sinking
RL = 20 Ω
100
80
75
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
Voltage output swing
Power Supply
Minimum operating voltage
Absolute minimum
±3.3
±3.3
V
Min
Maximum operating voltage
Absolute maximum
±7.5
±7.5
V
Max
Maximum quiescent current
14
16.8
20.5
mA
Max
Power-supply rejection (+PSRR)
VS+ = 4.5 V to 5.5 V, RL = 1 kΩ
69
60
56
dB
Min
Power-supply rejection (–PSRR)
VS– = –4.5 V to –5.5 V, RL = 1 kΩ
65
58
55
dB
Min
8
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TYPICAL CHARACTERISTICS
Table of Graphs (VS = ±7.5 V)
FIGURE NO.
Noninverting small-signal frequency response
2, 3
Inverting small-signal frequency response
4
Inverting large-signal frequency response
5, 6
0.1-dB gain flatness frequency response
7
Capacitive load frequency response
8
Recommended switching resistance
vs Capacitive load
9
2nd harmonic distortion
vs Frequency
10
3rd harmonic distortion
vs Frequency
11
2nd-order harmonic distortion, G = 2
vs Output voltage
12
3rd-order harmonic distortion, G = 2
vs Output voltage
13
2nd-order harmonic distortion, G = 5
vs Output voltage
14
3rd-order harmonic distortion, G = 5
vs Output voltage
15
2nd-order harmonic distortion, G = 10
vs Output voltage
16
3rd-order harmonic distortion, G = 10
vs Output voltage
17
3rd-order intermodulation distortion (IMD3)
vs Frequency
18
S-Parameter
vs Frequency
19, 20
Input voltage and current noise
vs Frequency
21
Noise figure
vs Frequency
22
Transimpedance
vs Frequency
23
Input offset voltage
vs Case temperature
24
Input bias and offset current
vs Case temperature
25
Slew rate
vs Output voltage
Settling time
26
27, 28
Quiescent current
vs Supply voltage
29
Output voltage
vs Load resistance
30
Rejection ratio
vs Frequency
31
Noninverting small-signal transient response
32
Inverting large-signal transient response
33
Overdrive recovery time
34
Differential gain
vs Number of loads
35
Differential phase
vs Number of loads
36
Closed-loop output impedance
vs Frequency
37
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Table of Graphs (VS = ±5 V)
Figure No.
Noninverting small-signal frequency response
38
Inverting small-signal frequency response
39
0.1-dB gain flatness frequency response
40
2nd-order harmonic distortion
vs Frequency
41
3rd-order harmonic distortion
vs Frequency
42
2nd-order harmonic distortion, G = 2
vs Output voltage
43
3rd-order harmonic distortion, G = 2
vs Output voltage
44
2nd-order harmonic distortion, G = 5
vs Output voltage
45
3rd-order harmonic distortion, G = 5
vs Output voltage
46
2nd-order harmonic distortion, G = 10
vs Output voltage
47
3rd-order harmonic distortion, G = 10
vs Output voltage
48
3rd-order intermodulation distortion (IMD3)
vs Frequency
49
S-Parameter
vs Frequency
50, 51
Slew rate
vs Output voltage
52
Noninverting small-signal transient response
53
Inverting large-signal transient response
54
Overdrive recovery time
55
10
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VS = ±7.5 V Graphs
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Noninverting Gain - dB
RF = 768 Ω
7
6
5
RF = 1 kΩ
4
3
Gain = 2.
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
2
1
0
100 k
1M
10 M
100 M
1G
20
18
16
14
12
10
G = 5, RF = 619 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
8
6
4
2
0
-2
-4
10 G
G = 2, RF = 768 Ω
G =1, RF = 1.2 kΩ
100 k
1M
1G
10 G
6
RL = 100 Ω,
VO = 2 VPP.
VS = ±7.5 V
10
RL = 100 Ω,
VO = 2 VPP.
VS = ±7.5 V
8
6
4
2
G = -1, RF = 576 Ω
0
6.2
6.1
6
5.9
5.8
5.7
-2
0
5.6
-4
100 k
1M
10 M
100 M
f - Frequency - Hz
100 k
1G
10 M
100 M
f - Frequency - Hz
1M
10 M
100 M
f - Frequency - Hz
1G
10 G
Figure 7.
CAPACITIVE LOAD
FREQUENCY RESPONSE
RECOMMENDED SWITCHING
RESISTANCE
vs
CAPACITIVE LOAD
2nd HARMONIC DISTORTION
vs
FREQUENCY
60
R(ISO) = 20 Ω,
CL = 50 pF
-40
Gain = 5,
RF = 619 Ω
RL = 100 Ω,
VS = ±7.5 V
50
Recommended R
- Ω
ISO
12
Gain = 5
RF = 619 Ω
RL = 100 Ω
VS = ±7.5 V
R(ISO) = 15 Ω,
CL = 100 pF
40
30
20
_
+
10
R(ISO) = 20 Ω,
CL = 47 pF
RISO
CL
0
0
100 k
1G
Figure 6.
14
0
1M
Figure 5.
R(ISO) = 30 Ω, CL = 22 pF
2
10 G
Gain = 2,
RF = 768 Ω,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±7.5 V
6.3
G =-5, RF = 549 Ω
Noninverting Gain - dB
Inverting Gain - dB
G = 2, RF = 715 Ω
4
1G
6.4
14
8
6
100 M
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
10
8
10 M
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
12
10
1M
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
12
16
G = -1, RF = 619 Ω
f - Frequency - Hz
16
2
G = -2, RF = 576 Ω
2
0
-2
-4
100 k
Figure 4.
G =-5, RF = 576 Ω
4
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
Figure 3.
14
Inverting Gain - dB
100 M
G = -5, RF = 549 Ω
16
14
12
10
8
6
4
Figure 2.
16
Gain - dB
10 M
G = -10, RF = 499 Ω
20
18
f - Frequency - Hz
f - Frequency - Hz
-2
24
22
G = 10, RF = 487 Ω
2nd Order Harmonic Distortion - dBc
Noninverting Gain - dB
24
22
RF = 619 Ω
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Noninverting Gain - dB
8
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
100
200
300
400
500
f - Frequency - MHz
Figure 8.
10
100
CL - Capacitive Load - pF
Figure 9.
G = 10
RF = 499 W, RG = 54.9 W
-50
G=5
RF = 619 W,
-60
RG = 154 W
-70
Vs = ±7.5V
Vout = 2VPP
-80
RL = 100 W
G=2
RF = 768 W, RG = 768 W
-90
-100
1
10
Figure 10.
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100
f - Frequency - MHz
11
THS3201-EP
SGLS283B – APRIL 2005 – REVISED JANUARY 2009 ..................................................................................................................................................... www.ti.com
VS = ±7.5 V Graphs (continued)
2nd HARMONIC DISTORTION
G=2
vs
OUTPUT VOLTAGE
3rd HARMONIC DISTORTION
vs
FREQUENCY
2nd Order Harmonic Distortion - dBc
G=2
RF = 768 W, RG = 768 W
-70
-75
Vs = ±7.5V
Vout = 2VPP
-80
RL = 100 W
-85
G=5
RF = 619 W, RG = 154 W
-90
G = 10
RF = 499 W, RG = 54.9 W
-95
-100
-40
-50
RL = 100 W
-60
10
32MHz
-70
-80
1MHz
-90
-100
-110
1
100
16MHz
0
1
3
4
5
-90
1MHz
8MHz
-100
4MHz
2MHz
16MHz
0
1
2
3
4
5
3rd HARMONIC DISTORTION
G=5
vs
OUTPUT VOLTAGE
2nd ORDER HARMONIC DISTORTION
G = 10
vs
OUTPUT VOLTAGE
64MHz
-70
-80
1MHz
-90
4MHz
-100
16MHz
1
2
2MHz
8MHz
3
4
5
-40
-50
RL = 100 W
32MHz
64MHz
-60
-70
-80
-90
1MHz
-100
-110
6
-30
Vs = ±7.5V
G=5
RF = 649 W, RG = 154 W
2nd Order Harmonic Distortion - dBc
32MHz
-60
8MHz
4MHz
16MHz
0
1
2
3
2MHz
4
5
32MHz
64MHz
RL = 100 W
-50
-60
-70
-80
1MHz
-90
4MHz
2MHz
8MHz
16MHz
-100
-110
6
Vs = ±7.5V, G = 10
RF = 499 W, RG = 54.9 W
-40
0
1
2
3
4
5
Vout - Output Voltage - VPP
Vout - Output Voltage - VPP
Vout - Output Voltage - VPP
Figure 14.
Figure 15.
Figure 16.
3rd ORDER HARMONIC DISTORTION
G = 10
vs
OUTPUT VOLTAGE
3rd ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
S-PARAMETER
vs
FREQUENCY
-40
Vs = ±7.5V
G = 10
RF = 499 W, RG = 54.9 W
-50
RL = 100 W
3rd Order Intermodulation Distortion - dBc
-30
32MHz
64MHz
-60
-70
-80
-90
1MHz
-100
-110
8MHz
4MHz
16MHz
0
6
2nd HARMONIC DISTORTION
G=5
vs
OUTPUT VOLTAGE
RL = 100 W
0
-80
Figure 13.
-30
-50
-70
Figure 12.
Vs = ±7.5V
G=5
RF = 619 W, RG = 154 W
-40
-60
-110
6
64MHz
32MHz
Figure 11.
3rd Order Harmonic Distortion - dBc
2nd Order Harmonic Distortion - dBc
2
2MHz
4MHz
RL = 100 W
-50
Vout - Output Voltage - VPP
-30
3rd Order Harmonic Distortion - dBc
8MHz
Vs = ±7.5V
G=2
RF = 768 W, RG = 768 W
-40
Vout - Output Voltage - VPP
f - Frequency - MHz
1
2
3
2MHz
4
5
Vout - Output Voltage - VPP
Figure 17.
12
64MHz
6
0
-40
-50
Vs = ±7.5V
Vout = 2VPP
G10
RF = 499 W, RG = 54.9 W
RL = 100W
-20
S-Parameter - dB
3rd Order Harmonic Distortion - dBc
-65
-30
Vs = ±7.5V
G=2
RF = 768 W, RG = 768 W
3rd Order Harmonic Distortion - dBc
-30
-60
-110
3rd HARMONIC DISTORTION
G=2
vs
OUTPUT VOLTAGE
-60
-70
-80
G2
RF = 768 W, RG = 768 W
-90
-100
10
VS = ±7.5 V
Gain = +10
C = 0 pF
6
S11
S22
-40
S12
-60
RG
RF
C
+
-80
G5
RF = 619 W, RG = 154 W
50 Ω
Source
50 Ω
50 Ω
50 Ω
-100
20
30
40
50
60
70
80
90 100
f - Frequency - MHz
Figure 18.
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1M
10 M
100 M
1G
f - Frequency - Hz
10 G
Figure 19.
Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201-EP
THS3201-EP
www.ti.com ..................................................................................................................................................... SGLS283B – APRIL 2005 – REVISED JANUARY 2009
VS = ±7.5 V Graphs (continued)
INPUT VOLTAGE AND
CURRENT NOISE
vs
FREQUENCY
S-PARAMETER
vs
FREQUENCY
S12
-60
S11
RG
RF
C
+
-80
50 Ω
Source
-100
1M
50 Ω
50 Ω
50 Ω
10 M
100 M
1G
f - Frequency - Hz
10 G
3
Vn
35
2.5
30
1.5
Inverting
Noise Current
25
0.5
20
0
Noninverting
Current Noise
15
10
100 k
1M
10 M
f - Frequency - Hz
Figure 20.
Hz
nV/
3.5
40
V n - Voltage Noise Density -
S-Parameter - dB
S22
-40
4
VS = ±7.5 V and ±5 V
TA = 25°C
45
I n - Input Current Noise Density -
VS = ±7.5 V
Gain = +10
C = 3.3 pF
-20
50
pA Hz
0
100 M
Figure 21.
NOISE FIGURE
vs
FREQUENCY
TRANSIMPEDANCE
vs
FREQUENCY
14
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
3
120
VS = ±5 and ±7.5V
11
10
9
Gain = +10
RG = 28 Ω
RF = 255 Ω
VS = ±7.5 V & ±5 V
8
7
50
100 150 200 250 300 350 400
f - Frequency - MHz
60
40
_
+
10 Ω
V
20
Gain W +
+
_
1M
10 M
SLEW RATE
vs
OUTPUT VOLTAGE
7
4
14
IIB+
13
3
12
2
IOS
1
11
10
-40 -30 -20 -10
1.5
VS = ±5 V
1
0.5
Figure 24.
SETTLING TIME
1.5
Rising Edge
9000
1
8000
SR± - Slew Rate - V/ms
5
I OS - Input Offset Currents - µ A
IIB-
VS = ±7.5 V
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
1G
10000
VS = ±7.5 V
15
2
TC - Case Temperature - °C
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
6
2.5
f - Frequency - Hz
Figure 23.
16
O
I IB
100 M
Figure 22.
17
I IB - Input Bias Currents - µ A
80
0
100 k
6
0
100
0
0 10 20 30 40 50 60 70 80 90
TC - Case Temperature - °C
Figure 25.
SR+
VO - Output Voltage - V
Noise Figure - dB
12
VOS - Input Offset Voltage - mV
Transimpedance Gain -dB Ω
13
7000
6000
SR5000
4000
3000
2000
0.5
Gain = -2
RL = 100 Ω
RF = 576 Ω
f= 1 MHz
VS = ±7.5 V
0
-0.5
Falling Edge
-1
1000
0
-1.5
1
2
3
4
5
6
7
8
9
Vout - Output Voltage - Vstep
Figure 26.
10
0
2
4
6
Product Folder Link(s): THS3201-EP
10
Figure 27.
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8
t - Time - ns
13
THS3201-EP
SGLS283B – APRIL 2005 – REVISED JANUARY 2009 ..................................................................................................................................................... www.ti.com
VS = ±7.5 V Graphs (continued)
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
SETTLING TIME
3
20
2.5
Rising Edge
2
1.5
TA = 85°C
18
16
Gain = -2
RL = 100 Ω
RF = 576 Ω
f= 1 MHz
VS = ±7.5 V
0
-0.5
-1
-1.5
-2
12
8
6
4
Falling Edge
2
-3
0
2.5
7.5
5
TA = -40°C
10
-2.5
0
TA = 25°C
14
VO - Output Voltage - V
1
0.5
Quiescent Current - mA
VO - Output Voltage - V
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
12.5
10
2 2.5
VS = ±7.5 V
TA = -40 to 85°C
0
-1
-2
-3
-4
-5
10
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
VS - Supply Voltage - ±V
100
Figure 29.
Figure 30.
REJECTION RATIO
vs
FREQUENCY
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
0.3
6
VS = ±7.5 V
5
Output
70
40
PSRR+
30
20
0.1
Input
0
Gain = 2
RL = 100 Ω
RF = 715 Ω
VS = ±7.5 V
-0.1
VO - Output Voltage - V
VO - Output Voltage - V
CMRR
50
3
2
1
0
Input
-1
-2
-3
-4
-0.2
10
Gain = -5
RL = 100 Ω
RF = 549 Ω
VS = ±7.5 V
4
0.2
60
1000
RL - Load Resistance - Ω
Figure 28.
80
Rejection Ratios - dB
2
1
-6
-7
t - Time - ns
Output
-5
0
100 k
1M
10 M
-6
-0.3
100 M
Figure 31.
Figure 33.
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
OVERDRIVE RECOVERY TIME
5
G = 2,
RF = 768 Ω,
VS = ±7.5 V
3
4
2
2
1
0
0
-2
-1
-4
-2
-6
-3
-8
-4
-5
0.2
0.4
0.6
0.8
t - Time - µs
Gain = 2
RF = 768 Ω
VS = ±7.5 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0.025
1
Differential Gain - %
VO - Output Voltage - V
6
0.030
4
VI - Input Voltage - V
8
0
t - Time - µs
Figure 32.
10
-10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
t - Time - µs
f - Frequency - Hz
0.020
PAL
0.015
0.010
NTSC
0.005
0
0
1
2
3
4
5
6
7
8
Number of Loads - 150 Ω
Figure 34.
14
7
6
5
4
3
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Figure 35.
Copyright © 2005–2009, Texas Instruments Incorporated
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THS3201-EP
www.ti.com ..................................................................................................................................................... SGLS283B – APRIL 2005 – REVISED JANUARY 2009
VS = ±7.5 V Graphs (continued)
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
0.040
1000
0.030
Differential Phase -
°
0.025
0.020
Closed-Loop Output Impedance - Ω
Gain = 2
RF = 768 kΩ
VS = ±7.5 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0.035
PAL
0.015
NTSC
0.010
0.005
0
Gain = 2
RF = 715 Ω
RL = 100 Ω
VS = ±7.5 V
100
10
1
0.1
0.01
0.001
0
1
2
3
4
5
6
7
8
100 k
1M
Number of Loads - 150 Ω
10 M
1M
1G
f - Frequency - Hz
Figure 36.
Figure 37.
VS = ±5 V Graphs
G = 5, RF = 576 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±5 V
G = 2, RF = 715 Ω
G =1, RF = 1.2 kΩ
6.4
G = -10, RF = 499 Ω
18
16
14
12
G = -5, RF = 549 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±5 V
10
8
6
4
2
G = -2, RF = 576 Ω
0
100 k
1M
10 M
100 M
1G
10 G
Figure 39.
Figure 40.
2nd HARMONIC DISTORTION
vs
FREQUENCY
3rd ORDER HARMONIC DISTORTION
vs
FREQUENCY
2nd ORDER HARMONIC DISTORTION
G=2
vs
OUTPUT VOLTAGE
RL = 100 W
-90
G=2
RF = 715 W, RG = 715 W
10
3rd Order Harmonic Distortion - dBc
2nd Order Harmonic Distortion - dBc
Vs = ±5V
Vout = 2VPP
-80
10 M
100 M
1G
100 k
10 G
-65
G=2
RF = 715 W, RG = 715 W
-70
-75
Vs = ±5V
Vout = 2VPP
-80
RL = 100 W
-85
G=5
RF = 576 W, RG = 143 W
-90
G = 10
RF = 464 W, RG = 51.1 W
-95
-100
100
f - Frequency - MHz
Figure 41.
1M
1G
10 G
-30
-60
-70
1
5.7
Figure 38.
RG = 143 W
-100
5.8
10 M
100 M
f - Frequency - Hz
G=5
RF = 576 W,
-60
6
5.9
f - Frequency - Hz
G = 10
RF = 464 W, RG = 51.1 W
-50
6.1
5.6
100 k 1 M
f - Frequency - Hz
-40
6.2
G =-1, RF = 576 Ω
-2
-4
Gain = 2,
RF = 715 Ω,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
6.3
Noninverting Gain - dB
8
6
4
2
0
-2
-4
24
22
20
G = 10, RF = 464 Ω
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
2nd Order Harmonic Distortion - dBc
24
22
20
18
16
14
12
10
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Inverting Gain - dB
Noninverting Gain - dB
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
-50
Vs = ±5V
64MHz
G=2
RF = 715 W, RG = 715 W
RL = 100 W
-60
32MHz
-40
-70
1MHz
-80
2MHz
-90
4MHz
-100
-110
1
10
f - Frequency - MHz
Figure 42.
100
16MHz
0
1
2
8MHz
3
4
Product Folder Link(s): THS3201-EP
6
Figure 43.
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5
Vout - Output Voltage - VPP
15
THS3201-EP
SGLS283B – APRIL 2005 – REVISED JANUARY 2009 ..................................................................................................................................................... www.ti.com
VS = ±5 V Graphs (continued)
3rd ORDER HARMONIC
DISTORTION, G = 2
vs
OUTPUT VOLTAGE
2nd ORDER HARMONIC
DISTORTION, G = 5
vs
OUTPUT VOLTAGE
-40
-50
RL = 100 W
32MHz
-60
-70
1MHz
-80
2MHz
4MHz
-90
8MHz
-100
16MHz
0
1
2
3
4
5
1MHz
-80
2MHz
-90
16MHz
-100
0
1
2
8MHz
4MHz
3
4
5
1MHz
-80
2MHz
4MHz
-90
8MHz
-100
16MHz
-110
6
0
1
2
3
4
5
6
2nd ORDER HARMONIC
DISTORTION, G = 10
vs
OUTPUT VOLTAGE
3rd ORDER HARMONIC
DISTORTION, G = 10
vs
OUTPUT VOLTAGE
3rd ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
-80
2MHz
-90
16MHz
-100
0
1
2
8MHz
4MHz
3
4
5
-40
Vs = ±5V
G = 10
RF = 464 W, RG = 51.1 W
-50
RL = 100 W
-60
64MHz
32MHz
-70
1MHz
-80
2MHz
4MHz
-90
8MHz
-100
16MHz
-110
6
3rd Order Intermodulation Distortion - dBc
3rd Order Harmonic Distortion - dBc
64MHz
1MHz
0
1
2
3
4
5
6
-50
-55
Vs = ±5V
Vout = 2VPP
-60
RL = 100W
G2
RF = 715 W, RG = 715 W
-65
-70
-75
-80
G10
RF = 464 W,
-85
RG = 51.1 W
-90
G5
RF = 576 W,
-95
RG = 143 W
-100
10
20
30
40
50
60
70
80
Vout - Output Voltage - VPP
Vout - Output Voltage - VPP
Figure 47.
Figure 48.
Figure 49.
S-PARAMETER
vs
FREQUENCY
S-PARAMETER
vs
FREQUENCY
SLEW RATE
vs
OUTPUT VOLTAGE
0
VS = ±5 V
Gain = +10
C = 0 pF
-20
S22
S12
S11
RG
RF
C
+
50 Ω
Source
1M
32MHz
-70
Figure 46.
-70
-100
-60
Figure 45.
-60
-60
RL = 100 W
Figure 44.
RL = 100 W
-40
-50
64MHz
Vout - Output Voltage - VPP
S-Parameter - dB
2nd Order Harmonic Distortion - dBc
S-Parameter - dB
-70
Vs = ±5V
G=5
RF = 576 W, RG = 143 W
Vout - Output Voltage - VPP
-80
50 Ω
10 M
100 M
1G
f - Frequency - Hz
-40
6000
5000
S22
S12
-60
S11
RG
RF
C
+
50 Ω
Source
50 Ω
-100
10 G
1M
90 100
f - Frequency - MHz
VS = ±5 V
Gain = +10
C = 3.3 pF
-80
50 Ω
Figure 50.
16
-60
-30
-50
-20
32MHz
-40
Vout - Output Voltage - VPP
Vs = ±5V, G = 10
32MHz
RF = 464 W, RG = 51.1 W
-40
0
64MHz
RL = 100 W
-50
-110
6
-30
-110
-40
SR± - Slew Rate - V/ms
-110
-30
Vs = ±5V
G=5
RF = 576 W, RG = 143 W
3rd Order Harmonic Distortion - dBc
-30
64MHz
Vs = ±5V
G=2
RF = 715 W, RG = 715 W
2nd Order Harmonic Distortion - dBc
3rd Order Harmonic Distortion - dBc
-30
3rd ORDER HARMONIC
DISTORTION, G = 5
vs
OUTPUT VOLTAGE
50 Ω
10 M
100 M
1G
f - Frequency - Hz
50 Ω
SR+
4000
3000
SR2000
1000
50 Ω
10 G
Figure 51.
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0
1
2
3
4
5
Vout - Output Voltage - Vstep
Figure 52.
Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201-EP
THS3201-EP
www.ti.com ..................................................................................................................................................... SGLS283B – APRIL 2005 – REVISED JANUARY 2009
VS = ±5 V Graphs (continued)
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
0.3
-0.1
-0.2
Gain = 2
RL = 100 Ω
RF = 715 Ω
VS = ±5 V
VO - Output Voltage - V
VO - Output Voltage - V
0
1.5
1
Gain = -5
RL = 100 Ω
RF = 549 Ω
VS = ±5 V
3
0.5
0
Input
-0.5
-1
-1.5
-2
Output
G = 2,
RF = 715 Ω,
VS = ±5 V
4
VO - Output Voltage - V
2
0.2
Input
6
2.5
Output
0.1
OVERDRIVE RECOVERY TIME
3
2
2
1
0
0
-2
-1
-4
-2
VI - Input Voltage - V
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
-2.5
-0.3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-6
-3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
t - Time - µs
t - Time -µs
Figure 53.
Figure 54.
0
0.2
0.4
0.6
0.8
t - Time - µs
Figure 55.
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Product Folder Link(s): THS3201-EP
-3
1
17
THS3201-EP
SGLS283B – APRIL 2005 – REVISED JANUARY 2009 ..................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Wideband Noninverting Operation
The THS3201 is a unity gain stable 1.8-GHz
current-feedback operational amplifier, designed to
operate from a ±3.3-V to ±7.5-V power supply.
Figure 56 shows the THS3201 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves are
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment
presenting a 50-Ω load impedance. The 49.9-Ω shunt
resistor at the VI terminal in Figure 56 matches the
source impedance of the test generator.
7.5 V
+
0.1 µF
±7.5
—
1.2 k
±5
—
1.2 k
±7.5
768
768
1
2
5
±5
715
715
±7.5
154.9
619
±5
143
576
±7.5
54.9
487
±5
51.1
464
±7.5
619
619
±5
576
576
6.8 µF
–2
±7.5 and ±5
287
576
–5
±7.5 and ±5
110
549
–10
±7.5 and ±5
49.9
499
49.9 Ω
THS3201
50 Ω
Wideband Inverting Gain Operation
768 Ω
0.1 µF
100 pF
-7.5 V
RF
(Ω)
–1
_
RG
RG
(Ω)
+
RF
768 Ω
Supply Voltage
(V)
10
100 pF
49.9 Ω
THS3201 RF for AC When Rload = 100 Ω
Gain
(V/V)
+VS
50 Ω Source
VI
Table 1. Recommended Resistor Values for
Optimum Frequency Response
6.8 µF
+
Figure 57 shows the THS3201 is a typical inverting
gain configuration, where the input and output
impedances and signal gain from Figure 56 are
retained in an inverting circuit configuration.
-VS
7.5 V +V
S
Figure 56. Wideband Noninverting Gain
Configuration
+
100 pF
Unlike voltage-feedback amplifiers, current-feedback
amplifiers are highly dependent on the feedback
resistor RF for maximum performance and stability.
Table 1 shows the optimal gain setting resistors RF
and RG at different gains to give maximum bandwidth
with minimal peaking in the frequency response.
Higher bandwidths can be achieved, at the expense
of added peaking in the frequency response, by using
even lower values for RF. Conversely, increasing RF
decreases the bandwidth, but stability is improved.
+
0.1 µF
6.8 µF
49.9 Ω
THS3201
_
50 Ω
50 Ω Source
VI
RG
RF
287 Ω
RM
60.4 Ω
576 Ω
0.1 µF
100 pF
-7.5 V
6.8 µF
+
-VS
Figure 57. Wideband Inverting Gain Configuration
18
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Single Supply Operation
768 Ω
The THS3201 has the capability to operate from a
single-supply voltage ranging from 6.6 V to 15 V.
When operating from a single power supply, care
must be taken to ensure the input signal and amplifier
is biased appropriately to allow for the maximum
output voltage swing. The circuits shown in Figure 58
demonstrate methods to configure an amplifier in a
manner conducive for single-supply operation
768 Ω
±7.5 V
THS3201
VI
75-Ω Transmission Line
+
±7.5 V
75 Ω
n Lines
75 Ω
VO(n)
75 Ω
+VS
75 Ω
50 Ω Source
+
VI
49.9 Ω
RT
VO(1)
75 Ω
49.9 Ω
Figure 59. Video Distribution Amplifier
Application
THS3201
_
50 Ω
+VS
2
ADC Driver Application
RF
RG
768 Ω
+VS
2
768 Ω
The THS3201 can be used as a high-performance
ADC driver in applications such as radio receiver IF
stages and test and measurement devices. All
high-performance ADCs have differential inputs. The
THS3201 can be used in conjunction with a
transformer as a drive amplifier in these applications.
Figure 60 and Figure 61 show two different
approaches.
RF
576 Ω
50 Ω Source
VI
60.4 Ω
+VS
2
VS
RG
_
287 Ω
THS3201
RT
49.9 Ω
+
50 Ω
+VS
2
In Figure 60, a transformer is used after the amplifier
to convert the signal to differential. The advantage of
this approach is fewer components are required.
ROUT and RT are required for impedance matching
the transformer.
Figure 58. DC-Coupled Single-Supply Operation
VS+
0.1 µF
Video HDTV Drivers
RG
The exceptional bandwidth and slew rate of the
THS3201 matches the demands for professional
video and HDTV. Most commercial HDTV standards
require a video passband of 30 MHz. To ensure high
signal quality with minimal degradation of
performance, a 0.1-dB gain flatness should be at
least 7x the passband frequency to minimize group
delay variations requiring 210-MHz 0.1-dB frequency
flatness from the amplifier. High slew rates ensure
there is minimal distortion of the video signal.
Component video and RGB video signals require fast
transition times and fast settling times to keep high
signal quality. The THS8135, for example, is a
240-MSPS video DAC and has a transition time
approaching 4 ns. The THS3201 is a perfect
candidate for interfacing the output of such
high-performance video components.
RF
ROUT
THS3201
VIN
1:n
24.9 Ω
RT
47pF
24.9 Ω
ADC
VS-
CM
47pF
0.1 µF
0.1 µF
Figure 60. Differential ADC Driver Circuit 1
In Figure 61, a transformer is used before two
amplifiers to convert the signal to differential. The two
amplifiers then amplify the differential signal. The
advantage to this approach is each amplifier is
required to drive one half the voltage as before. RT is
used to impedance match the transformer.
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fP +
VS+
0.1 µF
RG
VIN
RF
THS3201
1:n
24.9 Ω
47pF
ADC
RT
RG
THS3201
24.9 Ω
CM
47pF
RF
VS-
0.1 µF
0.1 µF
Figure 61. Differential ADC Driver Circuit 2
It is almost universally recommended to use a
resistor and capacitor between the operational
amplifier output and the ADC input as shown in
Figure 60 and Figure 61.
This resistor-capacitor (RC) combination has multiple
functions:
• The capacitor is a local charge reservoir for ADC.
• The resistor isolates the amplifier from the ADC.
• In conjunction, they form a low-pass noise filter.
During the sampling phase, current is required to
charge the ADC input sampling capacitors. By placing
external capacitors directly at the input pins, most of
the current is drawn from them. They are seen as a
low-impedance source. They can be thought of as
serving much the same purpose as a power-supply
bypass capacitor - to supply transient current - with
the amplifier then providing the bulk charge.
Typically, a low-value capacitor in the range of 10 pF
to 100 pF provides the required transient charge
reservoir.
The capacitance and the switching action of the ADC
is one of the worst loading scenarios that a
high-speed amplifier encounters. The resistor
provides a simple means of isolating the associated
phase shift from the feedback network and
maintaining the phase margin of the amplifier.
1
2pRC
Placing this pole at about 10x the highest frequency
of interest ensures it has no impact on the signal.
Since the resistor is typically a small value, it is bad
practice to place the pole at (or near) frequencies of
interest. At the pole frequency, the amplifiers see a
load with a magnitude of:
Ǹ2 xR
If R is only 10 Ω, the amplifier is heavily loaded
above the pole frequency, and generates excessive
distortion.
DAC Driver Application
The THS3201 can be used as a high-performance
DAC output driver in applications such as radio
transmitter
stages,
and
arbitrary
waveform
generators. All high-performance DACs have
differential current outputs. Two THS3201s can be
used as a differential drive amplifier in these
applications as shown in Figure 62.
RPU on the DAC output is used to convert the output
current to voltage. The 24.9-Ω resistor and 47-pF
capacitor between each DAC output and the
operational amplifier input is used to reduce the
images generated at multiples of the sampling rate.
The values shown form a pole a 136 MHz. ROUT sets
the output impedance of each amplifier.
VS+
0.1 µF
AVDD
RG
RF
RPU
ROUT
24.9 Ω
THS3201
VOUT1
IOUT1
47pF
24.9 Ω
DAC
ROUT
IOUT2
47pF
RPU
RG
THS3201
VOUT2
RF
AVDD
VS-
0.1 µF
Figure 62. Differential DAC Driver Circuit
Typically, a low-value resistor in the range of 10 Ω to
100 Ω provides the required isolation. Together, the
R and C form a real pole in the s-plane located at the
frequency:
20
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Printed-Circuit Board Layout Techniques for
Optimal Performance
Achieving optimum performance with high-frequency
amplifier-like devices in the THS3201 requires careful
attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any power or
ground plane for the negative input and ouput pins
by voiding the area directly below these pins and
connecting traces and the feedback path.
Parasitic capacitance on the output and negative
input pins can cause instability. To reduce
unwanted capacitance, a window around the
signal I/O pins should be opened in all of the
ground and power planes around those pins and
the feedback path. Otherwise, ground and power
planes should be unbroken elsewhere on the
board.
• Minimize the distance (<0.25 in) from the
power-supply pins to high frequency 0.1-µF and
100-pF decoupling capacitors. At the device pins,
the ground and power-plane layout should not be
in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power-supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board. The primary goal is to
minimize
the
impedance
seen
in
the
differential-current return paths. For driving
differential loads with the THS3201, adding a
capacitor between the power-supply pins
improves
2nd
order
harmonic
distortion
performance. This also minimizes the current loop
formed by the differential drive.
• Careful selection and placement of external
components preserve the high frequency
performance of the THS3201. Resistors should be
a low-reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Again,
keep their leads and PC board trace length as
short as possible. Never use wirebound-type
resistors in a high-frequency application. Since the
output pin and inverting input pins are the most
sensitive to parasitic capacitance, always position
the feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed close
to the gain-setting resistors. Even with a
low-parasitic capacitance shunting the external
•
•
•
•
resistors, excessively high resistor values can
create significant time constants that can degrade
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately
0.2 pF in shunt with the resistor. For resistor
values >2 kΩ, this parasitic capacitance can add a
pole and/or a zero that can effect circuit operation.
Keep resistor values as low as possible,
consistent with load driving considerations.
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils) should
be used, preferably with ground and power planes
opened up around them. Estimate the total
capacitive load and determine if isolation resistors
on the outputs are necessary. Low parasitic
capacitive loads (<4 pF) may not need an RS
since the THS3201 is nominally compensated to
operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded
phase margin). If a long trace is required and the
6-dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for these techniques).
A 50-Ω environment is not necessary onboard
and, in fact, a higher-impedance environment
improves distortion as shown in the distortion
versus load plots. With a characteristic board
trace impedance based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS3201 is used,
as well as a terminating shunt resistor at the input
of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device; this
total effective impedance should be set to match
the trace impedance. If the 6-dB attenuation of a
doubly-terminated
transmission
line
is
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high-speed part such as the THS3201
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network, which can make it almost
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impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
THS3201 parts directly onto the board.
0.205
0.060
0.017
PowerPAD Design Considerations
Pin 1
The THS3201 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which
the die is mounted [see Figure 63(a) and
Figure 63(b)]. This arrangement results in the lead
frame being exposed as a thermal pad on the
underside of the package [see Figure 63(c)]. Because
this thermal pad has direct thermal contact with the
die, excellent thermal performance can be achieved
by providing a good thermal path away from the
thermal pad.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other
heat-dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 63. Views of Thermally Enhanced Package
Although there are many ways to properly heat sink
the PowerPAD package, the following steps define
the recommended approach.
22
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 64. DGN PowerPAD PCB Etch and Via
Pattern
PowerPAD PCB Layout Considerations
1. Prepare the PCB with a top-side etch pattern as
shown in Figure 64. There should be etch for the
leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal-pad
area. This helps dissipate the heat generated by
the THS3201 IC. These additional vias may be
larger than the 10-mil diameter vias directly under
the thermal-pad. They can be larger because
they are not in the thermal pad area to be
soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer.
Therefore, the holes under the THS3201
PowerPAD
package
should
make
their
connection to the internal ground plane with a
complete
connection
around
the
entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal-pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal-pad area. This prevents solder from
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Power Dissipation and Thermal
Considerations
To maintain maximum output capabilities, the
THS3201 does not incorporate automatic thermal
shutoff protection. The designer must take care to
ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure
may result if the absolute maximum junction
temperature of 150°C is exceeded. For the best
performance, design for a maximum junction
temperature of 125°C. Between 125°C and 150°C,
damage does not occur, but the performance of the
amplifier begins to degrade.
The thermal characteristics of the device are dictated
by the package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
Tmax * T A
P Dmax +
q JA
where:
PDmax is the maximum power dissipation in the
amplifier (W).
Tmax is the absolute maximum junction
temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
ambient air (°C/W).
For systems where heat dissipation is more critical,
the THS3201 is offered in an 8-pin MSOP with
PowerPAD and the THS3201 is available in the
SOIC-8 PowerPAD package offering even better
thermal performance. The thermal coefficient for the
PowerPAD packages are substantially improved over
the traditional SOIC. Maximum power dissipation
levels are listed in the Dissipation Ratings table.. The
data for the PowerPAD packages assume a board
layout that follows the PowerPAD layout guidelines
referenced above and detailed in the PowerPAD
application report SLMA002. Figure 65 also shows
the effect of not soldering the PowerPAD to a PCB.
The thermal impedance increases substantially,
which may cause serious heat and performance
issues. Be sure to always solder the PowerPAD to
the PCB for optimum performance.
4.0
PD - Maximum Power Dissipation - W
being pulled away from the thermal-pad area
during the reflow process.
7. Apply solder paste to the exposed thermal-pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
TJ = 125°C
3.5
3.0
θJA = 58.4°C/W
2.5
θJA = 98°C/W
2.0
1.5
1.0
0.5
θJA = 158°C/W
0.0
-40
-20
0
20
40
60
80
100
TA - Free-Air Temperature - °C
Results are With No Air Flow and PCB Size = 3”x3”
θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
θJA = 98°C/W for 8-Pin SOIC High Test PCB (D)
θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
Figure 65. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power-dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
Design Tools
Evaluation Fixture, Spice Models, and
Applications Support
TI is committed to providing its customers with the
highest quality of applications support. To support this
goal, an evaluation board has been developed for the
THS3201 operational amplifier. The board is easy to
use, allowing for straightforward evaluation of the
device. The evaluation board can be ordered through
the TI web site, www.ti.com, or through your local TI
sales representative. The schematic diagram, board
layers, and bill of materials of the evaluation boards
are in Figure 66 through Figure 70.
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PD
J9*
C8*
R5
Vs+ 768 Ω
7 8
2 _
R3
J1
Vin 0Ω
768 Ω
R2
U1
R6
6
3 +
49.9 Ω
4 1
Vs -
J4
Vout
R7
Not Populated
J8*
PD Ref
J2
Vin+
49.9 Ω
C7*
R4
*Does Not Apply to the THS3201
J6
GND
J7
VS-
VS-
FB1
C1
+
C6
22 µF 0.1 µF
C5
100 pF
TP1
VS+
C4
100 pF
J5
VS+
FB2
C3
0.1 µF
+
C2
22 µF
Figure 66. THS3201 EVM Circuit Configuration
24
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Figure 67. THS3201 EVM Board Layout
(Top Layer)
Figure 68. THS3201 EVM Board Layout
(Second Layer, Ground)
Figure 69. THS3201 EVM Board Layout
(Third Layer, Power)
Figure 70. THS3201 EVM Board Layout
(Bottom Layer)
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Table 2. Bill of Materials (1)
THS3201DGN EVM
ITEM
(1)
DESCRIPTION
SMD SIZE
REF DES
PCB
QUANTITY
1
Bead, ferrite, 3 A, 80 Ω
1206
FB1, FB2
2
(Steward) HI1206N800R-00
2
Cap, 22 F, tanatalum, 25 V, 10%
D
C1, C2
2
(AVX) TAJD226K025R
3
Cap, 100 pF, ceramic, 5%, 150 V
AQ12
C4, C5
2
(AVX) AQ12EM101JAJME
4
Cap, 0.1 F, ceramic, X7R, 50 V
0805
C3, C6
2
(AVX) 08055C104KAT2A
6
Open
0805
R7
1
7
Resistor, 49.9 Ω, 1/8 W, 1%
0805
R6
1
(Phycomp) 9C08052A49R9FKHFT
9
Resistor, 768 Ω, 1/8 W, 1%
0805
R3, R5
2
(Phycomp) 9C08052A7680FKHFT
10
Open
1206
C7, C8
2
11
Resistor, 0 Ω, 1/4 W, 1%
1206
R2
1
(KOA) RK73Z2BLTD
12
Resistor, 49.9 Ω, 1/4 W, 1%
1206
13
Test point, black
14
Open
15
R4
1
(Phycomp) 9C12063A49R9FKRFT
TP1
1
(Keystone) 5001
J8, J9
2
Jack, Banana Receptance, 0.25” dia.
hole
J5, J6, J7
3
(HH Smith) 101
16
Connector, edge, SMA PCB jack
J1, J2, J4
3
(Johnson) 142-0701-801
17
Standoff, 4-40 hex, 0.625” length
4
(Keystone) 1804
18
Screw, Phillips, 4-40, .250”
4
SHR-0440-016-SN
19
IC, THS3201
1
(Texas Instruments) THS3201DGN
20
Board, printed circuit
1
(Texas Instruments) Edge # 6447972 Rev.A
U1
The components shown in the BOM were used in test by TI.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF-amplifier circuits,
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the THS4500 family of devices is available
through the TI web site (www.ti.com). The Product
Information Center (PIC) is available for design
assistance and detailed product information. These
models do a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. They are not intended to model
the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package
types in their small-signal ac performance. Detailed
information about what is and is not modeled is
contained in the model file itself.
26
MANUFACTURER PART NUMBER
Additional Reference Material
•
•
•
•
•
•
PowerPAD™ Made Easy, application brief
(SLMA004)
PowerPAD™
Thermally-Enhanced
Package,
technical brief (SLMA002)
Voltage Feedback vs Current Feedback Amplifiers
(SLVA051)
Current Feedback Analysis and Compensation
(SLOA021)
Current Feedback Amplifiers: Review, Stability,
and Application (SBOA081)
Effect of Parasitic Capacitance in Op Amp Circuits
(SLOA013)
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS3201MDGNREP
NRND
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
BLM
V62/05609-01YE
NRND
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
BLM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
OTHER QUALIFIED VERSIONS OF THS3201-EP :
• Catalog: THS3201
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS3201MDGNREP
Package Package Pins
Type Drawing
SPQ
HVSSOP
2500
DGN
8
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS3201MDGNREP
HVSSOP
DGN
8
2500
358.0
335.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.846
1.646
TYPICAL
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.846)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(2.15)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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