Texas Instruments | Comparator With Output Voltage-Level Translation (Rev. A) | Datasheet | Texas Instruments Comparator With Output Voltage-Level Translation (Rev. A) Datasheet

Texas Instruments Comparator With Output Voltage-Level Translation (Rev. A) Datasheet
TXS03121
www.ti.com ...................................................................................................................................................... SCES680A – JULY 2007 – REVISED JANUARY 2009
COMPARATOR WITH OUTPUT VOLTAGE-LEVEL TRANSLATION
FEATURES
1
•
•
•
•
•
•
Low Supply Current: 8 µA (Max)
Supply Voltage: 2.5 V to 5.5 V
Output FET Provides Down Translation
Small Package: SOT-563
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance
– 2500-V Human-Body Model (JESD-A114E)
– 250-V Machine Model
(EIA/JESD A115-A)
– 1500-V Charged-Device Model
(JESD22-C101-A Level III)
DRL PACKAGE
(TOP VIEW)
V+
1
6
S
+IN
2
5
D
–IN
3
4
GND
DESCRIPTION/ORDERING INFORMATION
The TXS03121 is a comparator designed for battery monitoring applications. It can be operated with a voltage of
2.5 V to 5.5 V. The reference voltage is applied to the –IN terminal, whereas the voltage to be monitored is
connected to +IN. When the voltage at +IN is greater than the voltage at –IN, the output FET is turned On. When
the voltage at +IN is less than the voltage at –IN, the output FET is turned Off. The source (S) of the output FET
can be connected to 1.1 V to 3.6 V, which allows the output signal to be level translated to another voltage value.
The voltage at V+ must be greater than or equal to the voltage at S. The voltage at S must be greater than or
equal to the voltage at D (V+ ≥ VS ≥ VD).
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
PACKAGE (1) (2)
SOT-563 – DRL
Tape and reel
ORDERABLE PART NUMBER
TXS03121DRLR
TOP-SIDE MARKING
2FR
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
TXS03121
SCES680A – JULY 2007 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
APPLICATION BLOCK DIAGRAM
V+ = 5.5 V
Input to
Monitor
S
+
T1
–
Ref
D
GND
PIN ASSIGNMENTS
2
NO.
NAME
1
V+
Comparator supply voltage
DESCRIPTION
2
+IN
Comparator positive input
3
–IN
Comparator negative input
4
GND
5
D
Drain of output FET
6
S
Source of output FET
Ground
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS03121
TXS03121
www.ti.com ...................................................................................................................................................... SCES680A – JULY 2007 – REVISED JANUARY 2009
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
V+
Supply voltage range (2)
–0.5
6.5
V
+IN,
–IN
Input voltage range
–0.5
6.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current (On-state switch current)
–50
mA
Continuous current through V+ or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
DRL package
UNIT
±100
mA
171.6
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
V+
Comparator supply voltage
2.5
5.5
V
VS, VD (1)
Output FET source or drain voltage
1.1
3.6
V
TA
Operating free-air temperature
–40
85
°C
(1)
UNIT
V+ must be greater than or equal to VS, and VS must be greater than or equal to VD (V+ ≥ VS ≥ VD).
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS03121
3
TXS03121
SCES680A – JULY 2007 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
COMPARATOR ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOS
Input offset voltage
V+ = 2.5 V to 5.5 V
VCM
Common-mode voltage range
V+ = 2.5 V to 5.5 V
I+IN
Input leakage current
V+ = 2.5 V to 5.5 V
I+
Supply current
V+ = 2.5 V to 5.5 V
CIN
Capacitance of +IN, –IN pins
I–IN
4
VCM = 0.8 V, IO = 0
VCM = V+, IO = 0
MIN
TYP
MAX
–10
0.5
10
mV
V+
V
0.5
µA
8
µA
2.5
pF
0.8
V+IN = 0 V to V+
V–IN = 0 V to V+
2
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UNIT
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS03121
TXS03121
www.ti.com ...................................................................................................................................................... SCES680A – JULY 2007 – REVISED JANUARY 2009
OUTPUT FET ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
IDS(ON)
On leakage current
VS = 1.1 V to 3.6 V, Switch ON
0.5
µA
IDS(OFF)
Off leakage current
VS = 1.1 V to 3.6 V, VD = Open, Switch OFF
0.5
µA
C(ON)
On capacitance
C(OFF)
Off capacitance, S and D
terminals
rON
On resistance of output
FET
V+ ≥ VS, ID = -100 µA
V–IN = 0.8 V, VS = 1.65 V
20-mV overdrive
V–IN = V+, VS = 1.65 V
V-IN = 0.8 V, VS = 1.65 V
50-mV overdrive
tEN
Enable time
V–IN = 0.8 V, VS = 1.65 V
100-mV overdrive
V–IN = V+, VS = 1.65 V
V–IN = 0.8 V, VS = 1.65 V
20-mV overdrive
V–IN = V+, VS = 1.65 V
V–IN = 0.8 V, VS = 1.65 V
50-mV overdrive
tDIS
Disable time
V–IN = V+, VS = 1.65 V
V–IN = 0.8 V, VS = 1.65 V
100-mV overdrive
V–IN = V+, VS = 1.65 V
5.1
6
pF
1.5
3.4
5
pF
VS = 1.1 V
150
VS = 1.4 V
65
VS = 1.65 V
61
VS = 2.3 V
50
VS = 3 V
44
V+ = 4.5 V
1.7
V+ = 3 V
3.9
V+ = 4.5 V
3.9
V+ = 4.5 V
1.2
V+ = 3 V
2.7
V+ = 2.5 V
6.2
1
V+ = 3 V
2.4
V+ = 2.5 V
5.3
V+ = 4.5 V
0.8
V+ = 3 V
1.4
V+ = 2.5 V
5
V+ = 4.5 V
0.7
V+ = 3 V
1.3
V+ = 2.5 V
4.7
V+ = 4.5 V
4.4
V+ = 3 V
12
V+ = 4.5 V
3.5
V+ = 3 V
6.1
V+ = 4.5 V
4.1
V+ = 3 V
9.6
V+ = 2.5 V
5.3
V+ = 4.5 V
2.5
V+ = 3 V
3.2
V+ = 2.5 V
5.2
V+ = 4.5 V
4.6
V+ = 3 V
6.7
V+ = 2.5 V
5.2
V+ = 4.5 V
1.9
V+ = 3 V
2.8
V+ = 2.3 V
4.9
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS03121
Ω
1
V+ = 3 V
V+ = 4.5 V
V–IN = V+, VS = 1.65 V
4
µs
µs
5
TXS03121
SCES680A – JULY 2007 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
S
+IN
+
–IN
–
D
50 pF
10 kW
Overdrive voltage
Voltage applied to –IN
Overdrive voltage
Voltage applied to +IN
VS – 0.3 V
VS
VS/2
Voltage observed at D
0V
tEN
6
tDIS
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TXS03121
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TXS03121DRLR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOT-5X3
DRL
6
4000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
2FR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TXS03121DRLR
Package Package Pins
Type Drawing
SPQ
SOT-5X3
4000
DRL
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
1.98
B0
(mm)
K0
(mm)
P1
(mm)
1.78
0.69
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXS03121DRLR
SOT-5X3
DRL
6
4000
202.0
201.0
28.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
SCALE 8.000
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
1
A
6
4X 0.5
1.7
1.5
NOTE 3
2X 1
4
3
B
1.3
1.1
6X
0.3
0.1
0.6 MAX
0.05
TYP
0.00
C
SEATING PLANE
6X
0.18
0.08
0.05 C
SYMM
SYMM
6X
6X
0.4
0.2
0.27
0.15
0.1
0.05
C A B
4223266/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4223266/A 09/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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