Texas Instruments | Wideband, Low Noise, Voltage-Feedback Operational Amplifier (Rev. E) | Datasheet | Texas Instruments Wideband, Low Noise, Voltage-Feedback Operational Amplifier (Rev. E) Datasheet

Texas Instruments Wideband, Low Noise, Voltage-Feedback Operational Amplifier (Rev. E) Datasheet
OPA
OPA84
OPA846
846
6
www.ti.com
SBOS250E – JULY 2002 – REVISED DECEMBER 2008
Wideband, Low-Noise, Voltage-Feedback
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
●
●
●
●
●
●
●
●
● HIGH DYNAMIC RANGE ADC PREAMPS
● LOW-NOISE, WIDEBAND, TRANSIMPEDANCE
AMPLIFIERS
● WIDEBAND, HIGH GAIN AMPLIFIERS
● LOW-NOISE DIFFERENTIAL RECEIVERS
● VDSL LINE RECEIVERS
● ULTRASOUND CHANNEL AMPLIFIERS
● SECURITY SENSOR FRONT ENDS
● UPGRADE FOR THE OPA686, CLC425, AND
LMH6624
HIGH BANDWIDTH: 400MHz (G = +10)
LOW INPUT VOLTAGE NOISE: 1.2nV/√Hz
VERY LOW DISTORTION: –100dBc (5MHz)
HIGH SLEW RATE: 625V/µs
HIGH DC ACCURACY: VIO ±150µV
LOW SUPPLY CURRENT: 12.6mA
HIGH GAIN BANDWIDTH PRODUCT: 1750MHz
STABLE FOR GAINS ≥ 7
DESCRIPTION
The OPA846 combines very high gain bandwidth and large
signal performance with very low input voltage noise, while
dissipating a low 12.6mA supply current. The classical differential input stage, along with two stages of forward gain and
a high power output stage, combine to make the OPA846 an
exceptionally low distortion amplifier with excellent DC accuracy and output drive. The voltage-feedback architecture
allows all standard op amp applications to be implemented
with very high performance.
The combination of low input voltage and current noise,
along with a 1.75GHz gain bandwidth product, make the
OPA846 an ideal amplifier for wideband transimpedance
stages. As a voltage gain stage, the OPA846 is optimized for
a flat response at a gain of +10 and is stable down to a gain
of +7.
+5V
A new external compensation technique can be used to give
a very flat frequency response below the minimum stable
gain for the OPA846, further improving its already exceptional distortion performance. Using this compensation makes
the OPA846 one of the premier 12- to 16-bit Analog-to-Digital
(A/D) converter input drivers. The supply current for the
OPA846 is precisely trimmed to 12.6mA at +25°C. This,
along with carefully defined supply current tempco in the
input and output stages, combine to provide exceptional
performance over the full specified temperature range.
OPA846 RELATED PRODUCTS
SINGLES
OPA842
OPA843
OPA847
Power-supply
decoupling not shown.
INPUT NOISE
VOLTAGE (nV/ √Hz )
GAIN BANDWIDTH
PRODUCT (MHz)
2.4
2.0
0.85
200
800
3900
WIDEBAND TRANSIMPEDANCE
100
20 log(50kΩ) = 94dBΩ
0.1µF
λ
50kΩ
IS
OPA846
–5V
10pF
Photodiode
VO
95
20 • log(ZT) [5dB/div]
100pF
50kΩ
0.2pF
–VB
90
85
80
75
70
65
60
High Gain, 20MHz Transimpedance Amplifier
0.1
1
10
100
Frequency (MHz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002-2008, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation ........................ See Thermal Analysis Section
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: D, DBV ........................... –65°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +150°C
ESD Rating (Human Body Model) .................................................. 2000V
(Charge Device Model) ............................................... 1500V
(Machine Model) ........................................................... 200V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
SO-8
D
–40°C to +85°C
OPA846
"
"
"
"
SOT23-5
DBV
–40°C to +85°C
OASI
"
"
"
"
OPA846ID
OPA846IDR
OPA846IDBVT
OPA846IDBVR
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
OPA846
"
OPA846
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
PIN CONFIGURATIONS
1
8
NC
Inverting Input
2
7
+VS
Noninverting Input
3
6
Output
–VS
4
5
NC
SOT23
Output
1
–VS
2
Noninverting Input
3
5
NC
Top View
5
+VS
4
Inverting Input
4
SO
1
2
OASI
NC = No Connection
3
Top View
Pin Orientation/Package Marking
2
OPA846
www.ti.com
SBOS250E
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RF = 453Ω, RL = 100Ω, and G = +10, unless otherwise noted. See Figure 1 for AC performance.
OPA846ID, IDBV
TYP
PARAMETER
AC PERFORMANCE (see Figure 1)
Closed-Loop Bandwidth
Gain Bandwidth Product (GBP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +7
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
2-Tone, 3rd-Order Intercept
Input Voltage Noise
Input Current Noise
Rise-and-Fall Time
Slew Rate
Settling Time to 0.01%
0.1%
1%
Differential Gain
Differential Phase
DC PERFORMANCE(4)
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
Common-Mode Input Range (CMIR)(5)
Common-Mode Rejection (CMR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Output Voltage Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (–PSRR)
THERMAL CHARACTERISTICS
Specified Operating Range: D, DBV Package
Thermal Resistance, θJA
D
DBV
MIN/MAX OVER TEMPERATURE
CONDITIONS
+25°C
+25°C(1)
0°C to
70°C (2)
–40°C to
+85°C (2)
G = +7, RG = 50Ω, VO = 200mVPP
G = +10, RG = 50Ω, VO = 200mVPP
G = +20, RG = 50Ω, VO = 200mVPP
G ≥ +40
G = +10, RL = 100Ω, VO = 200mVPP
500
400
110
1750
140
270
82
1275
40
250
80
1245
36
225
75
1200
35
G = +10, f = 5MHz, VO = 2VPP
RL = 100Ω
RL = 500Ω
RL = 100Ω
RL = 500Ω
G = +10, f = 10MHz
f > 1MHz
f > 1MHz
0.2V Step
2V Step
2V Step
2V Step
2V Step
–76
–100
–109
–112
44
1.2
2.8
1.2
625
15
10
6
–70
–89
–95
–105
41
1.3
3.5
1.5
500
–68
–87
–92
–101
40
1.4
3.6
1.6
425
–66
–85
–90
–96
38
1.5
3.6
1.8
350
12
8
14
10
16
12
G = +10, NTSC, RL = 150Ω
G = +10, NTSC, RL = 150Ω
0.02
0.02
VO = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
90
±0.15
±0.4
–10
±1
±0.1
±0.7
VCM = ±1V, Input Referred
±3.2
110
VCM = 0V
VCM = 0V
6.6 || 2.0
4.7 || 1.8
≥ 400Ω Load
100Ω Load
VO = 0V
VO = 0V
G = +10, f = 100kHz
±3.4
±3.3
80
–80
0.002
VS = ±5V
VS = ±5V
–VS = –4.5 to –5.5 (Input Referred)
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
min
typ
C
B
B
B
B
C
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
ns
V/µs
ns
ns
ns
max
max
max
max
min
max
max
max
min
typ
max
max
B
B
B
B
B
B
B
B
B
C
B
B
%
deg
typ
typ
C
C
81
±0.68
±1.5
–19.8
±20
±0.45
±2
80
±0.70
±1.5
–21
±35
±0.60
±3.5
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±2.9
93
±2.8
90
V
dB
min
min
A
A
kΩ || pF
MΩ || pF
typ
typ
C
C
V
V
mA
mA
Ω
min
min
min
min
typ
A
A
A
A
C
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
±5
12.6
12.6
95
82
UNITS
±0.60
±1.5
–19
±20
±0.35
±2
±3.0
95
±3.3
±3.2
65
–65
±6
12.9
12.3
90
±3.2
±3.0
61
–61
±3.1
±2.9
60
–60
±6
13.0
12.1
88
±6
13.2
11.8
85
Junction-to-Ambient
SO-8
SOT23-5
NOTES: (1) Junction temperature = ambient for +25°C min/max specifications.
(2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature min/max
specifications.
(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical
value only for information.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
OPA846
SBOS250E
www.ti.com
3
TYPICAL CHARACTERISTICS: VS = ±5V
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
6
VO = 0.2VPP
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
3
G = +7 G = +10
G = –12
0
Normalized Gain (dB)
0
–3
–6
–9
G = +20
–12
–3
–12
–15
See Figure 1
See Figure 2
–18
–18
1
23
20
10
100
1000
1
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
RL = 100Ω
G = +10V/V
29
VO = 0.2VPP
26
VO = 1VPP
23
VO = 2VPP
14
11
VO = 0.2VPP
RL = 100Ω
RG = RS = 50Ω
G = –20V/V
20
VO = 1VPP
VO = 2VPP
17
14
VO = 5VPP
11
VO = 5VPP
5
8
See Figure 1
See Figure 2
2
5
10
100
1000
10
100
NONINVERTING PULSE RESPONSE
Large Signal ± 1V
1.2
0.8
Left Scale
0.4
Small Signal ± 100mV
0
Right Scale
–0.4
2.0
0.4
1.6
0.3
0.2
0.1
0
–0.1
Output Voltage (400mV/div)
G = +10V/V
INVERTING PULSE RESPONSE
0.5
Output Voltage (100mV/div)
2.0
0.4
Large Signal ± 1V
0.3
0.8
Right Scale
0.2
0.4
Small Signal ± 100mV
0
Left Scale
–0.4
–0.2
–1.2
–0.3
–1.6
–0.4
–1.6
–0.5
–2.0
See Figure 1
0.5
G = –20V/V
1.2
–0.8
–2.0
1000
Frequency (MHz)
Frequency (MHz)
Output Voltage (400mV/div)
1000
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
8
0.1
0
–0.1
–0.8
–0.2
–1.2
–0.3
Time (5ns/div)
4
100
Frequency (MHz)
Gain (dB)
Gain (dB)
10
Frequency (MHz)
17
1.6
G = –20
G = –50
–9
G = +50
–15
VO = 0.2VPP
RG = RS = 50Ω
–6
Output Voltage (100mV/div)
Normalized Gain (dB)
3
–0.4
See Figure 2
–0.5
Time (5ns/div)
OPA846
www.ti.com
SBOS250E
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE
–75
Harmonic Distortion (dBc)
–80
Harmonic Distortion (dBc)
1MHz HARMONIC DISTORTION vs LOAD RESISTANCE
–75
G = +10V/V
VO = 2VPP
–85
–90
–95
–100
–105
–110
G = +10V/V
VO = 5VPP
–80
–85
–90
–95
–100
See Figure 1
See Figure 1
–105
–115
100
150
200
250
300
350
400
450
500
100
150
200
Load Resistance (Ω)
–85
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–80
G = +10V/V
VO = 2VPP
RL = 200Ω
–75
2nd-Harmonic
–85
3rd-Harmonic
–95
–105
350
400
450
500
G = +10V/V
F = 5MHz
RL = 200Ω
2nd-Harmonic
–90
–95
–100
–105
3rd-Harmonic
–110
See Figure 1
See Figure 1
–115
–115
0.1
1
10
100
0.1
1
Frequency (MHz)
10
Output Voltage Swing (VPP)
HARMONIC DISTORTION vs NONINVERTING GAIN
HARMONIC DISTORTION vs INVERTING GAIN
–75
VO = 2VPP
RL = 200Ω
F = 5MHz
2nd-Harmonic
2nd-Harmonic
Harmonic Distortion (dBc)
–75
Harmonic Distortion (dBc)
300
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs FREQUENCY
–65
250
Load Resistance (Ω)
–85
–95
–105
3rd-Harmonic
–85
VO = 2VPP
RL = 200Ω
F = 5MHz
–95
–105
3rd-Harmonic
See Figure 2
See Figure 1
–115
–115
5
10
15
20
25
30
35
40
45
50
10
OPA846
SBOS250E
15
20
25
30
35
40
45
50
Gain –V/V 
Gain (–V/V)
www.ti.com
5
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
50
10
G = +10V/V
50Ω Source
PIN
Intercept Point (+dBm)
Voltage Noise (nV/√Hz)
Current Voise (pA/√Hz)
45
2.8pA/√Hz
Current Noise
1.2nV/√Hz
Voltage Noise
–5V
RF
453Ω
40
RG
50Ω
35
30
100
1k
10k
100k
1M
10M
100M
5
10
15
20
Frequency (Hz)
0.2
NG = 8.0
2
NG = 8.5
NG = 9.0
0.1
0
–0.1
NG = 9.5
–0.2
NG = 10.0
–0.3
External Compensation
See Figure 9
–0.4
35
40
45
50
LOW GAIN INVERTING BANDWIDTH
Normalized Gain (1dB)
0.3
30
3
VO = 200mVPP
AV = +8
RF = 453Ω
RG = 64.9Ω
0.4
25
Frequency (MHz)
NONINVERTING GAIN FLATNESS TUNE
0.5
Deviation from 18.06dB Gain (0.1dB)
PO
RL
50Ω
20
10
VO = 200mVPP
RF = 400Ω
1
G = –6
0
G = –4
–1
G = –2
–2
G = –1
–3
–4
External Compensation
See Figure 5
–5
–6
–0.5
1
10
100
1000
1
10
Normalized Gain to Capacitive Load (dB)
G = +10V/V
10
1
10
100
1000
FREQUENCY RESPONSE vs CAPACITIVE LOAD
RECOMMENDED RS vs CAPACITIVE LOAD
100
1
100
Frequency (MHz)
Frequency (MHz)
RS (Ω)
RS
50Ω
25
1
1000
Capacitive Load (pF)
6
+5V
50Ω OPA846
23
RS adjusted for capacitive load.
C = 10pF
20
C = 22pF
17
Power-supply
+5V decoupling not shown.
RS
VO
50Ω OPA846
RL
CL
1kΩ
–5V
50Ω Source
VIN
14
R
453Ω
11
C = 47pF
C = 100pF
(1kΩ is optional.)
RG
50Ω
8
1
10
100
1000
Frequency (MHz)
OPA846
www.ti.com
SBOS250E
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
OPEN-LOOP GAIN AND PHASE
120
0
100
–30
CMRR
110
+PSRR
90
80
70
–PSRR
60
50
40
–60
80
∠AOL
60
–90
–120
40
20log (AOL)
20
–150
0
–180
Open-Loop Phase (°)
100
Open-Loop Gain (dB)
CMRR and PSRR (dB)
120
30
–210
–20
20
102
103
104
105
106
107
102
108
103
104
106
107
108
109
Frequency (Hz)
Frequency (Hz)
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
4
10
3
ZO
Output Impedance (Ω)
RL = 100Ω
2
RL = 50Ω
1
VO (V)
105
RL = 25Ω
0
–1
–2
OPA846
1
453Ω
0.1
50Ω
0.01
–3
0.001
–100
–50
0
50
100
102
150
103
104
NONINVERTING OVERDRIVE RECOVERY
Output Voltage (2V/div)
G = +10V/V
RL = 100Ω
6
4
10
0.8
8
0.6
6
0.4
Output
2
0.2
0
0
Output Voltage (2V/div)
Input
–8
–0.8
–8
–1.0
–10
400 450 500
–0.1
Output
–4
–0.2
–6
–0.3
–0.4
See Figure 2
–0.5
50
100 150 200
250 300 350
400 450 500
Time (50ns/div)
OPA846
SBOS250E
–2
0
Time (50ns/div)
0.3
0
–0.6
250 300 350
0.4
0
–6
See Figure 1
G = –20V/V
RL = 100Ω
0.1
–0.4
–10
0.5
Input
0.2
–4
100 150 200
108
2
–0.2
50
107
4
–2
0
106
INVERTING OVERDRIVE RECOVERY
1.0
Input Voltage (200mV/div)
10
8
105
Frequency (Hz)
IO (mA)
www.ti.com
7
Input Voltage (100mV/div)
–4
–150
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
SETTLING TIME
0.25
0.15
Transimpedance Gain (dBΩ)
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
RF = 10kΩ
CF Adjusted
80
CD = 100pF
77
CD = 50pF
74
71
CD = 20pF
68
65
See Figure 1
See Figure 4
–0.25
62
0
5
10
15
20
1
25
10
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
TYPICAL DC DRIFT OVER TEMPERATURE
0.25
15
0.10
10
VIO
0.05
5
0
0
–0.05
–5
Ib
–0.10
–10
–0.15
–15
–0.20
–20
–0.25
–25
0
25
50
75
100
18
Sourcing Output Current
130
16
120
14
Supply Current
110
12
100
10
90
8
80
6
Sinking Output Current
70
–25
–50
20
140
Output Current (10mA/div)
20
100 x IOS
0.15
Input Bias and Offset Current (µA)
Input Offset Voltage (mV)
150
25
0.20
100
Frequency (MHz)
Time (ns)
4
–50
125
–25
0
25
50
75
100
Ambient Temperature (°C)
Ambient Temperature (°C)
COMMON-MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
COMMON-MODE AND DIFFERENTIAL
INPUT IMPEDANCE
6
125
107
+VIN
Common-Mode
4.7MΩ
4
106
+VOUT
2
0
–2
–VOUT
Input Impedance (Ω)
Voltage Range (V)
CD = 10pF
105
6.6kΩ
104
Differential
103
–4
–VIN
–6
102
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
102
Supply Voltage (±V)
8
103
104
105
106
107
108
Frequency (Hz)
OPA846
www.ti.com
SBOS250E
Supply Current (2mA/div)
Percent of Final Value (%)
83
G = +10V/V
RL = 100Ω
VO = 2V Step
0.20
TYPICAL CHARACTERISTICS: VS = ±5V
TA = 25°C, GD = 20, RG = 50Ω, and RL = 400Ω, unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL
FREQUENCY RESPONSE
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
3
+5V
GD = 10V/V
OPA846
Gain =
VI
RG
50Ω
RF
1kΩ
RG
50Ω
RF
1kΩ
Normalized Gain (dB)
0
RF V O
=
= GD
RG
VI
RL
400Ω
VO
GD = 20V/V
–3
–6
–9
GD = 30V/V
–12
GD = 40V/V
–15
–18
OPA846
1
10
100
1k
Frequency (Hz)
–5V
DIFFERENTIAL LARGE-SIGNAL
FREQUENCY RESPONSE
GD = 20V/V
GD = 20V/V
VO = 4VPP
F = 5MHz
Harmonic Distortion (dBc)
–65
26
Gain (dB)
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
–60
29
VO = 400mVPP
23
VO = 5VPP
20
VO = 8VPP
17
–70
–75
–80
2nd-Harmonic
–85
–90
–95
–100
–105
3rd-Harmonic
–110
–115
14
1
10
100
50
1k
100
150
–85
2nd-Harmonic
300
350
400
450
500
GD = 20V/V
RL = 400Ω
F = 5MHz
–85
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–80
GD = 20V/V
RL = 400Ω
VO = 4VPP
–75
250
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
–65
200
Resistance (Ω)
Frequency (Hz)
3rd-Harmonic
–95
–105
–90
2nd-Harmonic
–95
–100
–105
3rd-Harmonic
–110
–115
–115
1
10
100
1
Frequency (MHz)
OPA846
SBOS250E
10
Output Voltage Swing (VPP)
www.ti.com
9
APPLICATIONS INFORMATION
WIDEBAND, NONINVERTING OPERATION
The OPA846 provides a unique combination of features. Low
input voltage noise, along with a very low distortion output
stage, gives one of the highest dynamic range op amps
available. The very high Gain Bandwidth Product (GBP) can
be used either to deliver high signal bandwidths at high gain,
or to deliver very low distortion signals at moderate frequencies and lower gains. To achieve the full performance of the
OPA846, careful attention to PC board layout and component selection is required, as discussed in the following
sections of this data sheet.
Figure 1 shows the noninverting gain of a 10V/V circuit used
as the basis of the Electrical Characteristics and most of the
Typical Characteristic curves. Most of the curves are characterized using signal sources with a 50Ω driving impedance,
and with a 50Ω load impedance presented by the measurement equipment. In Figure 1, the 50Ω resistor at the VIN
terminal matches the source impedance of the test generator, while the 50Ω series resistor at the VO terminal provides
a matching resistor for the measurement equipment load.
Generally, the data sheet voltage swing specifications are at
the output pin (VO in Figure 1), while the output power (dBm)
specifications are at the matched 50Ω load. The total 100Ω
load at the output, combined with the 503Ω total feedback
network load, presents the OPA846 with an effective output
load of 83Ω for the circuit of Figure 1.
guideline ensures that the noise added at the output due to
the Johnson noise of the resistors does not significantly
increase the total noise over that due to the 1.2nV/√Hz input
voltage noise for the op amp. Higher resistor values can
certainly be used where the application requires it, but can
start to add significantly to the output noise power as described in the Setting Resistor Values to Minimize Noise
section.
WIDEBAND INVERTING GAIN OPERATION
Operating the OPA846 as an inverting amplifier has several
benefits and is particularly appropriate when a matched input
impedance is required. Figure 2 shows the inverting gain
circuit used as the basis of the inverting mode of the Typical
Characteristic curves.
+5V
VCC
0.1µF
0.1µF
50Ω Source
RG
50Ω
91Ω
OPA846
RF
1kΩ
VI
0.1µF
0.1µF
50Ω
6.8µF
OPA846
RF
453Ω
RG
50Ω
0.1µF
+
6.8µF
VEE
–5V
FIGURE 1. DC-Coupled, G = +10V/V, Bipolar Supply, Specification and Test Circuit.
Voltage-feedback op amps (unlike current-feedback designs)
can use a wide range of resistor values to set the gain,
although these resistors usually have low values to maintain
a low total output noise. The circuit of Figure 1, and the
specifications at other gains, use the constraint that RG be
set to 50Ω and RF adjusted to get the desired gain. Using this
10
6.8µF
FIGURE 2. DC-Coupled, G = –20V/V, Bipolar Supply, Specification and Test Circuit.
RS 50Ω Load
50Ω
VO
+
VEE
–5V
50Ω Source
VI
6.8µF
RS 50Ω Load
50Ω
VO
+5V
+VCC
+
+
Driving this circuit from a 50Ω source, and constraining the
gain resistor (RG) to equal 50Ω, gives both a signal bandwidth and noise advantage. RG acts as both the input
termination resistor and the gain setting resistor for the
circuit. Although the signal gain (VO/VI) for the circuit of
Figure 2 is double that for Figure 1, the noise gains are in fact
equal when the 50Ω source resistor is included. This has the
interesting effect of doubling the equivalent GBP of the
amplifier. This can be seen by observing the 200MHz bandwidth for the inverting gain of –20. This implies a GBP of
4GHz, when in fact this extended bandwidth is given by the
reduced noise gain when the matched source resistor is
included. If the signal source is actually the low impedance
output of another amplifier, RG is increased to the minimum
load resistance value allowed for that amplifier and RF is then
adjusted to achieve the desired gain. For stable operation of
the OPA846, it is critical that this driving amplifier show very
low output impedance at frequencies beyond the expected
closed-loop bandwidth for the OPA846.
OPA846
www.ti.com
SBOS250E
WIDEBAND, HIGH-SENSITIVITY
TRANSIMPEDANCE DESIGN
The high GBP and low input voltage and current noise for the
OPA846 make it an ideal wideband transimpedance amplifier. Very high transimpedance gains (> 100kΩ) benefit from
the low input noise current of a JFET-input op amp, such as
the OPA657. Unity-gain stability in the op amp is not required
for application as a transimpedance amplifier. One transimpedance design example is shown on the front page of this
data sheet. Designs that require high bandwidths from a
large area (high capacitance) detector with relatively low
transimpedance gain will benefit from the low input voltage
noise offered by the OPA846. This input voltage noise is
peaked up over frequency at the output by the diode source
capacitance, and can, in many cases, become the limiting
factor to input sensitivity. The key elements of the design are
the expected diode capacitance (CD) with the reverse bias
voltage (–VB) applied, the desired transimpedance gain (RF),
and the GBP of the OPA846 (1750MHz). Figure 3 shows a
design using a 50pF detector diode capacitance and a 10kΩ
transimpedance gain. With these three variables set (including the parasitic input capacitance for the OPA846 added to
CD) the feedback capacitor (CF) value can be set to control
the frequency response. To achieve a maximally flat 2ndorder Butterworth frequency response, set the feedback pole
as shown in Equation 1.
1
=
2πRF CF
GBP
4 πRF CD
(1)
Power-supply
decoupling not shown.
10kΩ
OPA846
VO = ID RF
–5V
λ
ID
CD
50pF
(3)
Where:
IEQ = equivalent input noise current if the output noise is
bandlimited to F < 1/(2πRFCF)
IN = input current noise for the op amp inverting input
EN = input voltage noise for the op amp
CD = diode capacitance
F = bandlimiting frequency in Hz (usually a post filter prior
to further signal processing)
4kT = 1.6E – 20J at T = 290K
Evaluating this expression up to the feedback pole frequency
at 16.1MHz for the circuit of Figure 3 gives an equivalent
input noise current of 4.9pA/√Hz. This is much higher than
the 2.8pA/√Hz for just the op amp. This result is dominated
by the last term in the equivalent input noise current calculation from Equation 3. It is essential in this case to use a lowvoltage noise op amp. For example, if a slightly higher input
noise voltage, but otherwise identical op amp, was used
instead of the OPA846 amplifier in this application noise
amplifier (say 2.0nV/√Hz), the total input-referred current
noise would increase to 7.0pA/√Hz.
VOS = ±0.6mV (input offset voltage) ± 0.35µA (input offset
current) • 10kΩ = ±4.1mV
CF
0.8pF
Worst-case output offset DC drift is over the 0°C to 70°C span
is dVOS/dT = ±1.5µV/°C (input offset drift) ± 2nA/C (input
offset current drift) • 10kΩ = ±21.5µV/°C
FIGURE 3. Wideband, Low Noise, Transimpedance Amplifier.
Adding the common-mode and differential-mode input capacitance (1.8 + 2.0)pF to the 50pF diode source capacitance of
Figure 3, with a 10kΩ transimpedance gain using the 1750MHz
GBP for the OPA846, requires a feedback pole set to 16.1MHz.
This requires a 1pF total feedback capacitance. Typical surface-mount resistors have 0.2pF parasitic capacitance leaving
a required extrinsic 0.8pF value, as shown in Figure 3.
Equation 2 gives the approximate –3dB bandwidth, if CF is set
using Equation 1.
GBP
(Hz)
2πRF CD
Improved output DC precision and drift is possible, particularly at higher transimpedance gains, using the JFET input of
the OPA657. The JFET input removes the input bias current
from the error equation (eliminating the need for the resistor
to ground on the noninverting input), leaving only the input
offset voltage and drift as an output error term.
Included in the characteristic curves are transimpedance
frequency response curves for a fixed 10kΩ gain over various detector diode capacitance settings. These curves, along
with the test circuit, are repeated in Figure 4. As the photo-
(2)
OPA846
SBOS250E
2
4kT  EN  2 (EN 2πFCD )
+
+

RF
3
 RF 
RF
10kΩ
–VB
f −3dB =
IEQ = IN2 +
The output DC error for the circuit of Figure 3 is minimized by
including the 10kΩ to ground on the noninverting input. This
reduces the impact at the output of input bias current errors
to the offset current times the feedback resistor. To minimize
the output noise contribution of this resistor, a 0.01µF capacitor is included in parallel. Worst-case output DC error for the
circuit of Figure 3 at 25°C is:
+5V
0.01µF
The example of Figure 3 gives approximately 23MHz flat
bandwidth using the 0.8pF feedback compensation. If the
total output noise is bandlimited to a frequency less than the
feedback pole frequency, a simple expression for the equivalent input noise current is given as Equation 3.
www.ti.com
11
diode capacitance changes, the feedback capacitor must
change to maintain a stable and flat frequency response.
Using Equation 1, CF is adjusted to give the Butterworth
frequency responses presented in Figure 4.
+5V
Power-supply
decoupling not shown.
0.01µF
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
Tranimpedance Gain (dB Ω)
83
20 log(10kΩ)
RF = 10kΩ
CF Adjusted
80
OPA846
VO = –
RF
RG
VI
–5V
CD = 10pF
RG
250Ω
77
RF
500Ω
VI
74
71
0.01µF
68
10kΩ
OPA846
V O = ID R F
0Ω
Source
CD = 100pF
CS
27pF
CF
2.9pF
RF
10kΩ
λ
ID
CD
65
CD = 50pF
CF
CD = 20pF
–VB
FIGURE 5. Broadband, Low-Gain, Inverting Amplifier.
62
1
10
100
Frequency (MHz)
Physically, this ZO (11.6MHz for these values) is set by:
FIGURE 4. Transimpedance Bandwidth versus CD.
1
2πRF (CF + CS )
LOW-GAIN COMPENSATION FOR IMPROVED SFDR
Where a low gain is desired, and inverting operation is
acceptable, a new external compensation technique may be
used to retain the full slew rate and noise benefits of the
OPA846, while giving increased loop gain and the associated improvement in distortion offered by the decompensated architecture. This technique shapes the loop gain for
good stability, while giving an easily controlled 2nd-order
low-pass frequency response. Considering only the noise
gain (noninverting signal gain) for the circuit of Figure 5, the
low-frequency noise gain (NG1) is set by the resistor ratios,
while the high-frequency noise gain (NG2) is set by the
capacitor ratios. The capacitor values set both the transition
frequencies and the high-frequency noise gain. If this noise
gain (determined by NG2 = 1 + CS/CF) is set to a value
greater than the recommended minimum stable gain for the
op amp and the noise gain pole (set by 1/RFCF) is placed
correctly, a very well controlled, 2nd-order, low-pass frequency response results.
To choose the values for both CS and CF, two parameters and
only three equations need to be solved. The first parameter is
the target high-frequency noise gain (NG2), which should be
greater than the minimum stable gain for the OPA846. Here,
a target NG2 of 10.5 is used. The second parameter is the
desired low-frequency signal gain –(RF/RG), which also sets
the low-frequency noise gain NG1 (= 1 + RF/RG). To simplify
this discussion, target a maximally flat 2nd-order, low-pass
Butterworth frequency response (Q = 0.707). The signal gain
of –2 shown in Figure 5 sets the low-frequency noise gain to
NG1 = 1 + RF/RG (= 3 in this example). Then, using only these
two gains and the GBP for the OPA846 (1750MHz), the key
frequency in the compensation can be determined as:
ZO =
12
167Ω
GBP
NG21

NG1 
NG1 
1 −
 − 1 − 2 NG 
NG



2
2 
(4)
and is the frequency at which the rising portion of the noise
gain would intersect the unity gain if projected back to a 0dB
gain. The actual zero in the noise gain occurs at NG1 • ZO,
and the pole in the noise gain occurs at NG2 • ZO. Since GBP
is expressed in Hz, multiply ZO by 2π, and use this to get CF
by solving:
CF =
1
(= 2.86pF)
2πRF ZO NG2
(5)
Finally, since CS and CF set the high-frequency noise gain,
determine CS by using NG2 = 10.5:
CS = (NG2 − 1)CF , which gives CS = 24.9pF
(6)
The resulting closed-loop bandwidth is approximately equal to:
f −3dB ≅ ZO • GBP
(7)
For the values of Figure 5, f–3dB is approximately 142MHz.
This is less than that predicted by dividing the GBP product by
NG1. The compensation network controls the bandwidth to a
lower value, while providing the full slew rate at the output and
an exceptional distortion performance due to increased loop
gain at frequencies below NG1 • ZO. The capacitor values
shown in Figure 5 are calculated for NG1 = 3 and NG2 = 10.5
with no adjustment for parasitic components.
See Figure 6 for the measured frequency response for the
circuit of Figure 5. This shows the expected gain of –2 (6dB)
with exceptional flatness through 70MHz and a –3dB bandwidth of 170MHz. Repeating the swept frequency distortion
measurement for a 2VPP output into a 200Ω load and
comparing to the gain of +10 data shown in the Typical
Characteristic curves illustrates the improved distortion for
this low-gain compensation circuit.
Figure 7 compares the distortion at a gain of +10 for the
circuit of Figure 1 to the distortion at a gain of –2 for the circuit
of Figure 5.
OPA846
www.ti.com
SBOS250E
former primary as a 50Ω input matching impedance. The
noninverting signal gain (noise gain, NG) to the amplifier
output is then 1 + 1000/400 = 3.5V/V. Taking the input
voltage noise (1.2nV/√Hz ) for the OPA846 times this noise
gain to the output, then reflecting this noise term to the input
side of the RG resistor, divides it by 5. This gives a net gain
of 0.7 for the noninverting input voltage noise when reflected to the input point for the op amp circuit. This term is
further reduced when referred back to the transformer input.
10
5
0
Gain (dB)
–5
–10
–15
–20
–25
–30
–35
105
106
107
108
109
Frequency (Hz)
FIGURE 6. Gain of –2 Frequency Response Using External
Compensation.
–65
VO = 2VPP
RL = 200Ω
–70
G = +10
Gain (dB)
–75
G = –2
–85
2nd-Harmonic
The 14dB gain to the matched load, for the circuit of Figure 8,
is precisely controlled (±0.2dB) and gives a 6dB noise figure
at the input of the transformer. The DC noise gain for this
circuit (3.5) is below the specified minimum stable gain. The
amplifier portion of the circuit uses the low-gain inverting
compensation described in the previous section. Measured
results show 140MHz small-signal bandwidth for the circuit of
Figure 8 with ±0.1dB flatness through 50MHz. The OPA846
easily delivers a 2VPP A/D converter full-scale input at the
matched 50Ω load. 2-tone testing at 20MHz for the circuit of
Figure 8 (1VPP for each test tone) shows that the 2-tone
intermodulation intercept has improved to 40dBm versus the
34dBm shown in the Typical Characteristic curves, giving a
72dBc SFDR for the two 4dBm test tones at the load. This high
SFDR comes with relatively low total power dissipation versus
fixed-gain IF amplifier alternatives. Significantly higher SFDR
is delivered at lower frequencies and/or for the lighter loads
driving A/D converter inputs directly.
G = +10
–85
G = –2
–90
+5V
3rd-Harmonic
–95
1
10
20
Power-supply
decoupling
not shown.
Frequency (MHz)
OPA846
VO
50Ω Load
50Ω
FIGURE 7. Distortion Comparison at G = +10 versus G = –2.
LOW-NOISE FIGURE,
HIGH DYNAMIC RANGE IF AMPLIFIER
50Ω Source
1:2
The low input noise voltage of the OPA846, and its high
2-tone, 3rd-order intercept, can be used to good advantage as
a fixed-gain IF amplifier. While input noise figures in the 10dB
range (for a matched 50Ω input) are easily achieved with just
the OPA846 alone, Figure 8 shows a technique that reduces
the noise figure even further, while providing a broadband,
moderate-gain IF amplifier stage using the OPA846.
Bringing the signal in through a step-up transformer to the
inverting input gain resistor has several advantages for the
OPA846. First, grounding the noninverting input eliminates
the contribution of the noninverting input current noise to
the output noise. Second, the noninverting input voltage
noise of the op amp is actually attenuated if reflected to the
input side of RG. Using the 1:2 (turns ratio) step-up transformer reflects the 50Ω source impedance at the primary
through to the secondary as a 200Ω source impedance.
The 200Ω RG resistor is reflected through to the trans-
NF = 6dB
–5V
CS
20pF
RF
1kΩ
2pF
FIGURE 8. Low-Noise Figure IF Amplifier.
NONINVERTING LOW-GAIN COMPENSATION
Decreasing the operating gain for the OPA846 from the
nominal design point of +10 decreases the phase margin.
This increases Q for the closed-loop poles, peaks up the
frequency response, and extends the bandwidth. A peaked
frequency response shows overshoot and ringing in the
pulse response, as well as a higher integrated output noise.
When operating the amplifier at a noise gain less than +7,
increased peaking and possible sustained oscillations may
OPA846
SBOS250E
RG
200Ω
www.ti.com
13
result. However, operation at low gains may be desirable to
take advantage of the higher slew rate and exceptional DC
precision of the OPA846. Numerous external compensation
techniques are suggested for operating a high-gain op amp
at low gains. Most of these give zero/pole pairs in the closedloop response that cause long term settling tails in the pulse
response and/or phase nonlinearity in the frequency response. Figure 9 shows an external compensation method
for a noninverting configuration that does not suffer from
these drawbacks.
+5V
50Ω Source
RT
50Ω
R1
65Ω OPA846
VO
Operating two OPA846 amplifiers in a differential inverting
configuration can further suppress even-order harmonic terms.
The Typical Characteristic curves show measured performance for this condition. For the distortion data, the output
swing is increased to 4VPP into 400Ω to allow direct comparison to the 2VPP into 200Ω data for single-channel operation.
Figure 11 shows the swept frequency 2nd- and 3rd-harmonic
distortion for an inverting differential configuration, where
each channel is set up for a gain of 20.
Comparing this to the single-channel distortion (at 10MHz for
instance), about the same 3rd-harmonic and about a 5dB
improvement in the 2nd-harmonic is shown.
Power-supply
decoupling not shown.
VI
DIFFERENTIAL OPERATION
RS
50Ω
–65
50Ω Load
–5V
RF
402Ω
GD = 20
VO = 4VPP
RL = 400Ω
–75
Gain (dB)
RG
402Ω
–85
2nd-Harmonic
3rd-Harmonic
–95
FIGURE 9. Noninverting Low-Gain Compensation.
–105
The R1 resistor across the two inputs increases the noise
gain (i.e., decreases the loop gain) without changing the
signal gain. This approach retains the full slew rate to the
output but gives up some of the low-noise benefit of the
OPA846. Assuming a low source impedance is used, set R1
so that 1 + RF /(RG || R1) is > 7. This approach may also be
used to tune the flatness by adjusting R1. The Typical
Characteristic curves show a signal gain of +8 with the
noise gain adjusted for flatness using different values for
R1. Figure 10 shows the measured frequency response for
the circuit of Figure 9 showing the flat frequency response
possible with this compensation.
10
5
Gain (dB)
0
–5
–10
–15
–20
–25
105
106
107
108
109
Frequency (Hz)
–115
1
10
100
Frequency (MHz)
FIGURE 11. Differential Distortion vs Frequency.
SINGLE-SUPPLY OPERATION
The OPA846 may be operated from a single power supply if
system constraints require it. Operation from a single +5V to
+12V supply is possible with minimal change in AC performance. The Typical Characteristics show the input and
output voltage ranges for a bipolar supply range from ±2.5V
to ±6V. The Common-Mode Input Range and Output Swing
vs Supply Voltage plot shows that the required headroom on
both the input and output nodes remains at approximately
1.5V over this entire range. On a single +5V supply for
instance, this means the noninverting input should remain
centered at 2.5V ±1V, as should the output pin. See Figure
12 for an example application biasing the noninverting input
at mid-supply and running an AC-coupled input to the inverting gain path. Since the gain resistor is blocked off for DC,
the bias point on the noninverting input appears at the
output, centering up that node, as well on the power supply.
The OPA846 can support this mode of operation down to a
single +5V supply and up to a single +12V supply.
FIGURE 10. Noninverting Gain of +2 Response Using External
Compensation.
14
OPA846
www.ti.com
SBOS250E
possible noise contributors is required. Figure 13 shows the
op amp noise analysis model with all the noise terms included. In this model, all the terms are taken to be noise
voltage or current density terms in either nV/√Hz or pA/√Hz.
+VCC
+5V
2RF
0.01µF
2RF
+12V
Range
Power-supply decoupling
not shown.
V
R
VO = CC – VI F
OPA846
2
RG
ENI
RG
EO
OPA846
RS
IBN
RF
VI
ERS
RF
√4kTRS
FIGURE 12. Single-Supply Inverting Amplifier.
4kT
RG
DESIGN-IN TOOLS
IBI
RG
√4kTRF
4kT = 1.6E – 20J
at 290°K
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to assist in
the initial evaluation of circuit performance using the OPA846
in its two package options. Both of these are offered free
of charge as unpopulated PCBs, delivered with a user’s
guide. The summary information for these fixtures is shown
in Table I.
PRODUCT
OPA846ID
OPA846IDBV
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
SO-8
SOT23-5
DEM-OPA-SO-1B
DEM-OPA-SOT-1B
SBOU026
SBOU027
FIGURE 13. Op Amp Noise Analysis Model.
The total output spot noise voltage is computed as the
square root of the squared contributing terms to the output
noise voltage. This computation adds all the contributing
noise powers at the output by superposition and then takes
the square root of the terms to get back to a spot noise
voltage. Equation 8 shows the general form for this output
noise voltage using the terms of Figure 13.
EO =
(E
2
NI
)
+ (IBN RS )2 + 4kTRS NG2 + (IBI RF )2 + 4kTRF NG
(8)
Dividing this expression by the noise gain (NG = 1 + RF/RG)
gives the equivalent input-referred spot noise voltage at the
noninverting input, as shown in Equation 9.
TABLE I. Demonstration Fixtures by Package.
The demonstration fixtures can be requested at the Texas
Instruments web site (www.ti.com) through the OPA846
product folder.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often a quick way to analyze the performance of the OPA846
and its circuit designs. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and inductance can play a major role on circuit performance. A SPICE
model for the OPA846 is available through the TI web page
(www.ti.com). These models predict typical small-signal AC,
transient steps, and DC performance under a wide variety of
operating conditions. The models include the noise terms
found in the electrical specification of this data sheet. These
models do not attempt to distinguish between the package
types in small-signal AC performance.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO MINIMIZE NOISE
 I R  2 4kTRF
2
EN = ENI
+ (IBN RS )2 + 4kTRS +  BI F  +
 NG 
NG
(9)
Setting high resistor values into Equation 9 can quickly
dominate the total equivalent input referred noise. A 90Ω
source impedance on the noninverting input adds a Johnson
voltage noise term equal to that of the amplifier. As a
simplifying constraint, set RG = RS in Equation 9 and assume
an RS/2 source impedance is at the noninverting input (where
RS is the signal source impedance with another matching RS
to ground on the noninverting input). This results in Equation
10, where NG > 10 is assumed to further simplify the
expression.
2
EN = ENI
+
5
 3R 
IB RS )2 + 4kT S 
(
 2 
4
(10)
Evaluating this expression for RS = 50Ω gives a total equivalent input noise of 1.7nV/√Hz. Note that the NG has dropped
out of this expression.
This is valid only for NG > 10 as will typically be required by
stability considerations.
The OPA846 provides a very low input noise voltage while
requiring a low 12.6mA quiescent current. To take full advantage of this low input noise, careful attention to the other
OPA846
SBOS250E
www.ti.com
15
FREQUENCY RESPONSE CONTROL
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the GBP shown in the Electrical
Characteristics. Ideally, dividing GBP by the noninverting
signal gain (also called the noise gain, or NG) predicts the
closed-loop bandwidth. In practice, this only holds true when
the phase margin approaches 90°, as it does in high-gain
configurations. At low gains (increased feedback factor),
most high-speed amplifiers exhibit a more complex response
with lower phase margin. The OPA846 is compensated to
give a maximally flat 2nd-order Butterworth closed-loop response at a noninverting gain of +10 (see Figure 1). This
results in a typical gain of +10 bandwidth of 400MHz, far
exceeding that predicted by dividing the 1750MHz GBP by
10. Increasing the gain causes the phase margin to approach
90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +50, the OPA846
shows the 35MHz bandwidth predicted using the simple
formula F–3dB = GBP/NG.
Inverting operation offers some interesting opportunities to
increase the available GBP. When the source impedance is
matched by the gain resistor (see Figure 2), the signal gain
is (– RF/RG), while the noise gain for bandwidth purposes is
(1 + RF/2RG). This cuts the noise gain almost in half,
increasing the minimum stable gain for inverting operation
under these conditions to –12V/V and increases the equivalent GBP to > 3.5GHz.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often the
capacitive load is the input of an A/D converter, including
additional external capacitance that may be recommended to
improve A/D linearity. A high-speed, high open-loop gain
amplifier like the OPA846 is susceptible to decreasing stability with capacitive loads and results in closed-loop response
peaking when a capacitive load is placed directly on the
amplifier output pin. If the primary considerations are frequency response flatness, pulse fidelity, and/or distortion,
the simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Characteristic curves help the designer pick a
recommended RS versus Capacitive Load. The resulting frequency response curves show the flat response for a given
capacitive load. Parasitic capacitive loads greater than 2pF
can begin to degrade the performance of the OPA846. Long
PC board traces, unmatched cables, and connections to
multiple devices can easily add additional capacitance to the
existing circuit. Always consider these effects carefully and
add the recommended series resistor as close to the output
pin of the OPA846 as possible (see the Board Layout section).
16
The criterion for setting the RS resistor for maximum bandwidth, flat frequency response at the load is a simple procedure. For the OPA846 operating in a gain of +10V/V, the
frequency response at the output pin is very flat to begin with,
allowing relatively small values of RS to be used for low
capacitive loads. As the signal gain increases, the unloaded
phase margin also increases. Driving capacitive loads at
higher gain settings require lower RS values than those
shown for a gain of +10V/V.
DISTORTION PERFORMANCE
The OPA846 is capable of delivering an exceptionally low
distortion signal at high frequencies over a wide range of
gains. The distortion plots found in the Typical Characteristic
curves show the typical distortion under a wide variety of
conditions. Most of these plots are limited to 110dB dynamic
range. The OPA846 distortion, while driving a 500Ω load,
does not rise above –90dBc until either the signal level
exceeds 2.0VPP and/or the fundamental frequency exceeds
5MHz. Distortion in the audio band is < –120dBc.
Generally, until the fundamental signal reaches very high
frequencies or power, the 2nd-harmonic dominates the distortion with negligible 3rd-harmonic component. Focusing
then on the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network: in the noninverting configuration, this is the sum of RF + RG, while in the inverting
configuration it is just RF (see Figures 1 and 2). Increasing
output voltage swing increases harmonic distortion directly.
A 6dB increase in output swing generally increases the 2ndharmonic to 12dB and the 3rd-harmonic to 18dB. Increasing
the signal gain also increases the 2nd-harmonic distortion.
Again, a 6dB increase in gain increases the 2nd- and 3rdharmonic by approximately 6dB, even with constant output
power and frequency. Finally, the distortion increases as the
fundamental frequency increases, due to the roll-off in the
loop gain with frequency. Conversely, the distortion improves
going to lower frequencies down to the dominant open-loop
pole at approximately 100kHz. Starting from the –86dBc 2ndharmonic for a 5MHz, 2VPP fundamental into a 200Ω load at
a gain = +10V/V (from the Typical Characteristic curves), the
2nd-harmonic distortion for frequencies lower than 100KHz
is approximately –86dBc – 20 log(5MHz/100kHz) = –120dBc.
The OPA846 has extremely low 3rd-order distortion. This
also gives a high 2-tone, 3rd-order intermodulation intercept,
as shown in the Typical Characteristic curves. This intercept
curve is defined at the 50Ω load when driven through a 50Ωmatching resistor to allow direct comparisons to RF devices.
This matching network attenuates the voltage swing from the
output pin to the load by 6dB. If the OPA846 drives directly
into the input of a high-impedance device, such as an A/D
converter, the 6dB attenuation is not present. Under these
conditions, the intercept increases by a minimum of 6dBm.
The intercept is used to predict the intermodulation spurious
for two closely-spaced frequencies. If the two test frequencies f1 and f2 are specified in terms of average and delta
frequency, fO = (f1 + f2)/2 and ∆f = f2 – f1/2, the two 3rdorder, close-in spurious tones appear at fO ±3 • ∆f. The
OPA846
www.ti.com
SBOS250E
DC ACCURACY AND OFFSET CONTROL
The OPA846 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection, high
power-supply rejection, and low input offset voltage and bias
current offset errors. To take full advantage of its low ±0.6mV
maximum (25°C) input offset voltage, careful attention to
input bias current cancellation is also required. The low-noise
input stage for the OPA846 has a relatively high input bias
current (10µA typical into the pins), but with a very close
match between the two input currents—typically ±100nA
input offset current. Figures 14 and 15 show typical distributions of input offset voltage and current for the OPA846. The
total output offset voltage can be considerably reduced by
matching the source impedances looking out of the two pins.
600
500
Mean = –0.01
Standard Deviation = 0.17
Total Count = 2952
Count
400
300
200
100
< –0.70
< –0.63
< –0.56
< –0.49
< –0.42
< –0.35
< –0.28
< –0.21
< –0.14
< –0.07
0
< 0.07
< 0.14
< 0.21
< 0.28
< 0.35
< 0.42
< 0.49
< 0.56
< 0.63
< 0.70
> 0.70
0
mV
FIGURE 14. Input Offset Voltage Distribution.
800
600
500
400
300
200
100
< –0.45
< –0.41
< –0.36
< –0.32
< –0.27
< –0.23
< –0.18
< –0.14
< –0.09
< –0.05
0
< 0.04
< 0.09
< 0.14
< 0.18
< 0.23
< 0.27
< 0.32
< 0.36
< 0.41
< 0.45
> 0.45
0
µA
FIGURE 15. Input Offset Current Distribution.
For example, one way to add bias current cancellation to the
circuit of Figure 1 would be to insert a 20Ω series resistor into
the noninverting input from the 50Ω terminating resistor. When
the 50Ω source resistor is DC-coupled, this increases the
source resistances for the noninverting input bias current to
45Ω. Since this is now equal to the resistance looking out of
the inverting input (RF || RG), the circuit cancels the gains for
the bias currents to the output, leaving only the offset current
times the feedback resistor as a residual DC error term at the
output. Using the 453Ω feedback resistor, this output error is
now less than ±600nA • 453Ω = ±272µV over the full temperature range.
A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available
for introducing a DC offset control into an op amp circuit.
Most of these techniques eventually reduce to setting up a
DC current through the feedback resistor. One key consideration to selecting a technique is to ensure that it has minimal
impact on the desired signal path frequency response. If the
signal path is intended to be noninverting, the offset control
is best applied as an inverting summing signal to avoid
interaction with the signal source. If the signal path uses the
inverting mode, applying an offset control to the noninverting
input can be considered. For a DC-coupled inverting input
signal, this DC offset signal sets up a DC current back into
the source that must be considered. An offset adjustment
placed on the inverting op amp input can also change the
noise gain and frequency response flatness. See Figure 16
for one example of an offset adjustment for a DC-coupled
signal path that has minimum impact on the signal frequency
response. In this case, the input is brought into an inverting
gain resistor with the DC adjustment as an additional current
summed into the inverting node. The resistor values for
setting this offset adjustment are chosen to be much larger
than the signal path resistors. This ensures that the adjustment has minimal impact on the loop gain and hence, the
frequency response.
OPA846
SBOS250E
Mean = –0.01
Standard Deviation = 0.08
Total Count = 2952
700
Count
difference between the two equal test-tone power levels
and these intermodulation spurious power levels is given by
∆dBc = 2 • (IM3 – PO) where IM3 is the intercept taken from
the typical characteristic curve and PO is the power level in
dBm at the 50Ω load for one of the two closely-spaced test
frequencies. At 5MHz for instance, the OPA846 at a gain of
+10V/V has an intercept of 48dBm at a matched 50Ω load.
If the full envelope of the two frequencies needs to be 2VPP,
this requires each tone to be 4dBm. The 3rd-order
intermodulation spurious tones are 2 • (48 – 4) = 88dBc
below the test-tone power level (–84dBm). If this same 2VPP,
2-tone envelope were delivered directly into the input of an
A/D converter—without the matching loss or the loading of
the 50Ω network—the intercept would increase to at least
54dBm. With the same signal and gain conditions, but now
driving directly into a light load, the spurious tones will then
be at least 2 • (54 – 4) = 100dBc below the 4dBm test-tone
power levels centered on 5MHz.
www.ti.com
17
BOARD LAYOUT
+5V
VCC
Power-supply decoupling
not shown.
48Ω
0.1µF
OPA846
VO
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted capacitance, create a window around the signal I/O pins leave
opened in all of the ground and power planes around those
pins.
VEE
–5V
+5V
RG
50Ω
RF
1kΩ
VI
5kΩ
20kΩ
±200mV Output Adjustment
100Ω
0.1µF
5kΩ
VO
VI
=–
RF
RG
= –20V/V
–5V
FIGURE 16. DC-Coupled, Inverting Gain of –20V/V with
Output Offset Adjustment.
THERMAL ANALYSIS
The OPA846 does not require heat sinking or airflow in most
applications. Maximum desired junction temperature sets the
maximum allowed internal power dissipation as described
following. In no case should the maximum junction temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
the specified no-load supply current times the total supply
voltage across the part. PDL depends on the required output
signal and load but would, for a grounded resistive load, be
at a maximum when the output is fixed at a voltage equal to
1/2 either supply voltage (for equal bipolar supplies). Under
this worst-case condition, PDL = VS2/(4 • RL), where RL
includes the feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA846IDBV (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 100Ω load at +2.5VDC.
PD = 10V(13.9mA) + 52/(4 • (100Ω || 500Ω)) = 214mW
Maximum TJ = +85°C + (0.21W • 150°C/W) = 117°C
All actual applications will operate at a lower junction temperature than the 117°C computed above. Compute the
actual stage power to get an accurate estimate of maximum
junction temperature, or use the results shown here as an
absolute maximum.
18
Achieving optimum performance with a high-frequency amplifier such as the OPA846 requires careful attention to board
layout parasitics and external component types. Recommendations that optimize performance include:
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power plane layout should
not be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors are
effective at lower frequencies, and are recommended on the
main supply pins. These may be placed somewhat further
from the device and shared among several devices in the
same area of the PC board.
c) Careful selection and placement of external components preserves the high-frequency performance of the
OPA846. Use resistors that have low reactance at high
frequencies. Surface-mount resistors work best and allow a
tighter overall layout. Metal-film and carbon composition,
axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board
trace length as short as possible. Never use wire wound type
resistors in a high-frequency application. Since the output pin
and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series output
resistor, if any, as close as possible to the output pin. Other
network components, such as noninverting input termination
resistors, should also be placed close to the package. Where
double-feedback side component mounting is allowed, place
the feedback resistor directly under the package on the other
side of the board between the output and inverting input pins.
Even with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create significant time constants that can degrade performance. Good
axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values
> 1.5kΩ, this parasitic capacitance can add a pole and/or a
zero below 500MHz that can effect circuit operation. Keep
resistor values as low as possible consistent with load driving
considerations. It has been suggested here that a good
starting point for design would be set the RG be set to 50Ω.
Doing this automatically keeps the resistor noise terms low,
and minimizes the effect of parasitic capacitance. Transimpedance applications can use much higher resistor values.
The compensation techniques described in this data sheet
allow excellent frequency response control, even with very
high feedback resistor values.
OPA846
www.ti.com
SBOS250E
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the
trace and the input to the next device as a lumped capacitive
load. Relatively wide traces (50mils to 100mils) should be
used, preferably with ground and power planes opened up
around them. Estimate the total capacitive load and set RS
from the plot of Recommended RS vs Capacitive Load. Low
parasitic capacitive loads (< 5pF) may not need an RS, since
the OPA846 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an RS
are allowed, as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmission
line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50Ω environment is normally not necessary
onboard and, in fact, a higher impedance environment improves distortion, as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
based on board material and trace dimensions, a matching
series resistor into the trace from the output of the OPA846
is used, as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance is the parallel combination of the shunt resistor
and input impedance of the destination device; this total
effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive
load in this case and set the series resistor value as shown
in the plot of Recommended RS vs Capacitive Load. This
does not preserve signal integrity as well as a doublyterminated line. If the input impedance of the destination
device is low, there will be some signal attenuation due to the
voltage divider formed by the series output into the terminating impedance.
e) Socketing a high-speed part like the OPA846 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA846
onto the board.
INPUT AND ESD PROTECTION
The OPA846 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages are
relatively low for these very small geometry devices. These
breakdowns are reflected in the Absolute Maximum Ratings
table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 17.
+VCC
External
Pin
–VCC
FIGURE 17. Internal ESD Protection.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply parts
driving into the OPA846), current-limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible, since high values degrade both
noise performance and frequency response.
OPA846
SBOS250E
Internal
Circuitry
www.ti.com
19
Revision History
DATE
REVISION
PAGE
12/08
E
2
3/06
D
15
SECTION
DESCRIPTION
Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C.
Design-In Tools
Board part number changed.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
20
OPA846
www.ti.com
SBOS250E
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA846ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
846
OPA846IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OASI
OPA846IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OASI
OPA846IDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OASI
OPA846IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
846
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA846IDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA846IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising