Texas Instruments | Precision, Gain of 0.2 Level Translation Difference Amplifier | Datasheet | Texas Instruments Precision, Gain of 0.2 Level Translation Difference Amplifier Datasheet

Texas Instruments Precision, Gain of 0.2 Level Translation Difference Amplifier Datasheet
INA159-EP
www.ti.com .......................................................................................................................................................................................... SBOS443 – NOVEMBER 2008
PRECISION, GAIN OF 0.2 LEVEL
TRANSLATION DIFFERENCE AMPLIFIER
FEATURES
1
• Gain of 0.2 to Interface ±10-V Signals to
Single-Supply ADCs
• Gain Accuracy: ±0.024% (max)
• Wide Bandwidth: 1.5 MHz
• High Slew Rate: 15 V/µs
• Low Offset Voltage: ±100 µV
• Low Offset Drift: ±1.5 µV/°C
• Single-Supply Operation Down to 1.8 V
2
APPLICATIONS
•
•
•
•
Industrial Process Controls
Instrumentation
Differential to Single-Ended Conversion
Audio Line Receivers
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
The INA159 is a high slew rate, G = 1/5 difference
amplifier consisting of a precision op amp with a
precision resistor network. The gain of 1/5 makes the
INA159 useful to couple ±10-V signals to
single-supply analog-to-digital converters (ADCs),
particularly those operating on a single +5-V supply.
The on-chip resistors are laser-trimmed for accurate
gain and high common-mode rejection. Excellent
temperature coefficient of resistance (TCR) tracking
of the resistors maintains gain accuracy and
common-mode rejection over temperature. The input
common-mode voltage range extends beyond the
positive and negative supply rails. It operates on a
total of 1.8-V to 5.5-V single or split supplies. The
INA159 reference input uses two resistors for easy
mid-supply or reference biasing.
The difference amplifier is the foundation of many
commonly-used circuits. The INA159 provides this
circuit function without using an expensive external
precision resistor network. The INA159 is available in
an MSOP-8 surface-mount package and is specified
for operation over the extended industrial temperature
range, –55°C to 125°C.
Additional temperature ranges are available - contact factory
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
INA159-EP
SBOS443 – NOVEMBER 2008 .......................................................................................................................................................................................... www.ti.com
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
DOUT
+IN
C1
1000pF
VIN
+IN
100kΩ
40kΩ
V+
ADS8325
ADC
−IN
CS
REF 2
40kΩ
DCLOCK
GND
REF 1
INA159
Figure 1. Typical Application
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
TEMPERATURE
ORDERABLE PART
NUMBER (2)
PACKAGE LEAD
PACKAGE
DESIGNATOR
TOP-SIDE MARKING
-55°C to 125°C
INA159AMDGKTEP
MSOP-8 Tape and reel
DGK
OAA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
TOP VIEW
MSOP
INA159
2
REF 1
1
8
REF 2
−IN
2
7
V+
+IN
3
6
OUT
V−
4
5
SENSE
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Product Folder Link(s): INA159-EP
INA159-EP
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
Signal input terminals (−IN and +IN), voltage
Reference (REF 1 and REF2) and sense pins
Current
Voltage
(V–) – 0.5
Output short circuit
UNIT
+5.5
V
±30
V
±10
mA
(V+) + 0.5
V
Continuous
Operating temperature
–55
+125
°C
Storage temperature
–65
+150
°C
+150
°C
Human-Body Model
4000
V
Charged-Device Model
1000
V
Junction temperature
ESD rating
(1)
MAX
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
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INA159-EP
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ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –55°C to +125°C.
At TA = +25°C, RL = 10 kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5 V,
unless otherwise noted.
PARAMETER
CONDITIONS
OFFSET VOLTAGE (1)
INA159
MIN
TYP
MAX
±100
±500
RTO
Initial (1)
VOS
VS = ±2.5 V, Reference and Input
Pins Grounded
Over Temperature
vs Power Supply
PSRR VS = ±0.9 V to ±2.75 V
Over Temperature
(2)
over Temperature
µV
±1450
µV
±100
µV/V
±200
µV/V
±20
PSRR VS = ±0.9 V to ±2.75 V
Reference Divider Accuracy
INPUT IMPEDANCE
UNIT
±0.002
±0.024
%
±0.002
±0.050
%
(3)
Differential
Common-Mode
INPUT VOLTAGE RANGE
240
kΩ
60
kΩ
RTI
Common-Mode Voltage Range
VCM
Positive
17.5
Negative
–12.5
V
80
96
dB
74
94
dB
10
µVPP
30
nV/√Hz
Common-Mode Rejection Ratio
CMRR VCM = –10 V to +10 V, RS = 0 Ω
over Temperature
OUTPUT VOLTAGE NOISE
(4)
V
RTO
f = 0.1 Hz to 10 Hz
f = 10 kHz
VREF2 = 4.096 V,
RL Connected to GND,
(VIN+) – (VIN–) = –10 V to +10 V,
VCM = 0 V
GAIN
Initial
G
0.2
Error
±0.005
vs Temperature
V/V
±0.024
±0.035
Nonlinearity
±0.0002
%
%
% of FS
OUTPUT
VREF2 = 4.096 V,
RL Connected to GND
Voltage, Positive
over Temperature
(V+) –
0.02
(V+) – 0.2
VREF2 = 4.096 V,
RL Connected to GND
Voltage, Negative
over Temperature
(V–) + 0.048
See Typical Characteristic
RO f = 1 MHz, IO = 0
V
V
±60
Capacitive Load
V
V
(V–) +
0.01
(V–) + 0.070
Current Limit, Continuous to Common
Open-Loop Output Impedance
(V+) – 0.1
mA
pF
110
Ω
1.5
MHz
15
V/µs
1
µs
FREQUENCY RESPONSE
Small-Signal Bandwidth
Slew Rate
Settling Time, 0.01%
(1)
(2)
(3)
(4)
4
–3 dB
SR
tS 4 V Output Step, CL = 100 pF
Includes effects of amplifier input bias and offset currents.
Reference divider accuracy specifies the match between the reference divider resistors using the configuration in Figure 2.
Internal resistors are ratio matched but have 20% absolute value.
Includes effects of amplifier input current noise and thermal noise contribution of resistor network.
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INA159-EP
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ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –55°C to +125°C.
At TA = +25°C, RL = 10 kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5 V,
unless otherwise noted.
PARAMETER
INA159
CONDITIONS
Overload Recovery Time
MIN
50% Overdrive
TYP
MAX
250
UNIT
ns
POWER SUPPLY
Specified Voltage Range
VS
Operating Voltage Range
+1.8
Quiescent Current
IQ
IO = 0 mA, VS = ±2.5 V, Reference
and Input Pins Grounded
1.1
over Temperature
+5
V
+5.5
V
1.5
mA
2.0
mA
TEMPERATURE RANGE
Specified Range
–55
+125
°C
Operating Range
–55
+125
°C
Storage Range
–65
+150
°C
θJA
Thermal Resistance
MSOP-8
Surface Mount
150
°C/W
+5V
V+
2
7
100kΩ
20kΩ
5
6
3
40kΩ
100kΩ
40kΩ
INA159
V−
1
8
OUT
The test is performed by
measuring the output
with the reference
applied to alternate
reference resistors, and
calculating a result such
that the amplifier offset is
cancelled in the final
measurement.
4
Figure 2. Test Circuit for Reference Divider Accuracy
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INA159-EP
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TYPICAL CHARACTERISTICS
At TA = +25°C, RL = 10 kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5 V,
unless otherwise noted.
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
−500
−450
−400
−350
−300
−250
−200
−150
−100
−50
0
50
100
150
200
250
300
350
400
450
500
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
Population
Population
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
Offset Voltage Drift (µV/_C)
Offset Voltage (µV)
GAIN vs FREQUENCY
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
0
PSRR (dB)
Gain (dB)
−10
−20
−30
−40
−50
10
100
1k
10k
100k
1M
130
120
110
100
90
80
70
60
50
40
30
20
10
0
−10
10
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
COMMON−MODE REJECTION RATIO vs FREQUENCY
QUIESCENT CURRENT vs TEMPERATURE
120
1.20
110
VS = 5.5V
1.15
100
1.10
80
IQ (mA)
CMRR (dB)
90
70
60
VS = 5V
1.05
1.00
0.95
VS = 1.8V
50
0.90
40
0.85
30
0.80
20
10
100
1k
10k
100k
1M
10M
−50
Frequency (Hz)
6
−25
0
25
50
75
100
125
Temperature (_C)
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Product Folder Link(s): INA159-EP
INA159-EP
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5 V,
unless otherwise noted.
SHORT−CIRCUIT CURRENT vs TEMPERATURE
120
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
3.0
VS = ±2.75V
100
2.5
2.0
80
ISC (mA)
Output Swing (V)
VS = ±2.5V
60
40
20
VS = ±0.9V
0
−20
VS = ±2.5V
−40
1.5
TA = −40_C
1.0
0.5
TA = −40_C
TA = +25_C
TA =
+125_ C
0
−0.5
TA = +125_C
−1.0
−1.5
−60
−2.0
−80
−100
−50
−25
0
25
50
VS = ±0.9V
−2.5
VS = ±2.75V
VS = ±2.5V
−3.0
75
100
0
125
10
20
30
40
50
60
70
80
Temperature (_C)
Output Current (mA)
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
OUTPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
90
1000
Output Voltage Noise (nV/√Hz)
THD+Noise (%)
0.01
0.25VPP
2kΩ
4VPP
100
600Ω
10
0.001
10
100
1k
10k
1
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
0.1Hz TO 10Hz NOISE
SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
60
5µV/div
Overshoot (%)
50
40
30
VS = 5V
20
10
0
Time (1s/div)
100
1000
3000
Load Capacitance (pF)
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INA159-EP
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5 V,
unless otherwise noted.
SMALL−SIGNAL STEP RESPONSE
1V/div
200mV/div
LARGE−SIGNAL STEP RESPONSE
Time (500ns/div)
Time (500ns/div)
SETTLING TIME
2mV/div
VOUT = 4V Step
CL = 100pF
Time (250ns/div)
8
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INA159-EP
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APPLICATION INFORMATION
The internal op amp of the INA159 has a rail-to-rail
common-mode voltage capability at its inputs. A
rail-to-rail op amp allows the use of ±10-V inputs into
a circuit biased to 1/2 of a 5-V reference (2.5-V
quiescent output). The inputs to the op amp will swing
from approximately 400 mV to 3.75 V in this
application.
The unique input topology of the INA159 eliminates
the input offset transition region typical of most
rail-to-rail
complementary
stage
operational
amplifiers. This allows the INA159 to provide superior
glitch- and transition-free performance over the entire
common-mode range.
Good layout practice includes the use of a 0.1-µF
bypass capacitor placed closely across the supply
pins.
COMMON-MODE RANGE
The common-mode range of the INA159 is a function
of supply voltage and reference. Where both pins,
REF1 and REF2, are connected together:
V CM) + (V)) ) 5[(V)) * VREF]
(1)
V CM* + (V*) * 5[V REF * (V*)]
V CM) + (V)) ) 5[(V)) * (0.5VREF)]
(3)
V CM* + (V*) * 5[(0.5V REF) * (V*)]
(4)
Some typical values are shown in Table 1.
Table 1. Common-Mode Range For Various
Supply and Reference Voltages
REF 1 and REF 2 Connected Together
V+
V−
VREF
VCM+
VCM−
5
0
3
15
–15
5
0
2.5
17.5
–12.5
5
0
1.25
23.75
–6.25
1/2 Reference Connection
V+
V−
VREF
VCM+
VCM−
5
0
5
17.5
–12.5
5
0
4.096
19.76
–10.24
5
0
2.5
23.75
–6.25
3.3
0
3.3
11.55
–8.25
3.3
0
2.5
13.55
–6.25
3.3
0
1.25
16.675
–3.125
(2)
Where one REF pin is connected to the reference,
and the other pin grounded (1/2 reference
connection):
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INA159-EP
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Input and Output Relationships for Various Reference and Connection Combinations
VREF
(V)
REF CONNECTION
VOUT for VIN = 0
(V)
LINEAR VIN RANGE
(V)
USEFUL VOUT SWING
(V)
2.5
+10
0
–10
4.5
(±2V swing)
0.5
2.048
10
0
–10
4.048
(±2V swing)
0.048
1.65
+10
0
–7.885
3.65
(–1.577V, +2V swing)
0.048
1.25
+10 (also +5)
0
–6 (also –5)
3.25
(–1.2V, +2V swing)
0.048
0.9
+10
0
–4.26
2.9
(–0.852V, +2V swing)
0.048
2.5
+10
0
–10
4.5
(=2V swing)
0.5
1.8
+10
0
–8.76
3.8
(–1.752V, +2V swing)
0.048
1.2
+10
0
–5.76
3.2
(–1.15V, +2V swing)
0.048
5V
5
V+
−IN
100kΩ
20kΩ
SENSE
4.096
OUT
3.3
2.5
VIN
+IN
100kΩ
40kΩ
40kΩ
REF 2
VREF
REF 1
INA159
1.8
5V
2.5
V+
− IN
100kΩ
20kΩ
SENSE
1.8
OUT
1.2
VIN
+IN
100kΩ
40kΩ
40kΩ
REF 2
V REF
REF 1
INA159
10
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VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
DOUT
+IN
C1
1000pF
VIN
+IN
100kΩ
40kΩ
40kΩ
V+
−IN
ADS8325
ADC
DCLOCK
CS
REF 2
GND
REF 1
INA159
Figure 3. Typical Application Circuit Interfacing to Medium-Speed, Single-Supply ADCs
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
DOUT
+IN
100kΩ
40kΩ
40kΩ
ADS8361 or
ADS7861
ADC
−IN
+IN
C1
1000pF
VIN
V+
REF 2
DCLOCK
CS
GND
REF 1
INA159
Figure 4. Typical Application Circuit Interfacing to Medium-Speed, Single-Supply ADCs with
Pseudo-Differential Inputs (such as the ADS7861 and ADS8361)
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VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
VIN
+IN
V+
REF
R1
100Ω
100kΩ
40kΩ
40kΩ
+IN
C1
1000pF
ADC
−IN
REF 2
GND
REF 1
INA159
a) Unipolar, Noninverting, G = 0.2
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
VIN
+IN
100kΩ
40kΩ
40kΩ
+IN
C1
1000pF
V+
ADC
−IN
REF 2
GND
REF 1
INA159
b) Bipolar, Noninverting, G = 0.2
VREF
5V
V+
−IN
100kΩ
20kΩ
SENSE
REF
R1
100Ω
+IN
100kΩ
40kΩ
40kΩ
+IN
C1
1000pF
REF 2
V+
ADC
−IN
GND
REF 1
INA159
VIN
c) Unipolar, Unity Gain
Figure 5. Basic INA159 Configurations
12
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5V
V+
VIN−
−IN A
100kΩ
20kΩ
SENSE A
OUT A
100Ω
1000pF
VIN+
+IN A
100kΩ
40kΩ
40kΩ
REF 2A
REF 1A
INA159
VREF
V+
−IN B
100kΩ
20kΩ
REF
SENSE B
OUT B
V+
+IN
100Ω
−IN
5V
ADC
1000pF
GND
+IN B
100kΩ
40kΩ
40kΩ
REF 2B
REF 1B
INA159
Figure 6. Differential ADC Drive
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
INA159AMDGKTEP
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-55 to 125
OAA
V62/09613-01XE
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-55 to 125
OAA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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OTHER QUALIFIED VERSIONS OF INA159-EP :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Catalog: INA159
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
INA159AMDGKTEP
Package Package Pins
Type Drawing
VSSOP
DGK
8
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA159AMDGKTEP
VSSOP
DGK
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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