Texas Instruments | Dual, Ultra-Wideband, Current-Feedback Operational Amplifier with Disable (Rev. A) | Datasheet | Texas Instruments Dual, Ultra-Wideband, Current-Feedback Operational Amplifier with Disable (Rev. A) Datasheet

Texas Instruments Dual, Ultra-Wideband, Current-Feedback Operational Amplifier with Disable (Rev. A) Datasheet
OP
A2
69
OPA2695
5
OPA
2695
www.ti.com ...................................................................................................................................................... SBOS354A – APRIL 2008 – REVISED AUGUST 2008
Dual, Ultra-Wideband, Current-Feedback
OPERATIONAL AMPLIFIER with Disable
FEATURES
1
•
•
•
•
•
23
•
•
GAIN = +2V/V BANDWIDTH (850MHz)
GAIN = +8V/V BANDWIDTH (450MHz)
OUTPUT VOLTAGE SWING: ±4.1V
ULTRA-HIGH SLEW RATE: 2900V/µs
DIFFERENTIAL 3RD-ORDER INTERCEPT:
> 40dBm (f < 140MHz, 800Ω)
LOW POWER: 129mW/channel
LOW DISABLED POWER: 0.5mW/channel
APPLICATIONS
•
•
•
•
•
•
VERY WIDEBAND ADC DRIVERS
LOW-COST PRECISION IF AMPLIFIERS
BROADBAND VIDEO LINE DRIVERS
PORTABLE INSTRUMENTS
ACTIVE FILTERS
ARB WAVEFORM OUTPUT DRIVERS
+5V
1/2
OPA2695
ZI = RT || 2RG
1:1
VI
RG
RF
500W
RG
RF
500W
RT
VO
VI
=
500W
RG
RL
800W
The OPA2695 is a dual, very high bandwidth,
current-feedback op amp that combines exceptional
2900V/µs slew rate and low input voltage noise to
deliver a precision, low-cost, high dynamic range
intermediate frequency (IF) amplifier. The device has
been optimized for high gain operation, and the pin
outs of the two available packages (QFN-16, SO-8)
have been optimized to provide symmetrical input
and output paths. This architecture makes the
OPA2695 an ideal choice as a differential driver, such
as for a high-speed analog-to-digital converter (ADC).
The OPA2695 low 12.9mA/channel supply current is
precisely trimmed at +25°C. This trim, along with a
low temperature drift, gives low system power over
temperature. System power may be further reduced
with the optional disable control pin. Leaving this pin
open, or holding it high, gives normal operation. If
pulled low, the OPA2695 supply current drops to less
than 200µA/channel. This power-saving feature,
along with exceptional single +5V operation, makes
the OPA2695 ideal for portable applications. The
OPA2695 is available in an SO-8 (without disable)
package or QFN-16 package (with disable).
OPA2695 RELATED PRODUCTS
VO
1/2
OPA2695
= GD
DESCRIPTION
SINGLES
DUALS
TRIPLES
COMMENTS
OPA695
—
OPA3695
Ultra-wideband
current-feedback operational
amplifier with disable
OPA691
OPA2691
OPA3691
Wideband, high output
current, current-feedback
operational amplifier with
disable
OPA693
—
OPA3693
Ultra-wideband, fixed-gain
operational amplifier
OPA694
OPA2694
—
-5V
Differential Driver Test Circuit
Harmonic Distortion (dBc)
-65
GD = 10V/V
VO = 2VPP
RL = 800W
-70
-75
Ultra-wideband, low-power,
current-feedback operational
amplifier
-80
3rd Harmonic
-85
-90
-95
2nd Harmonic
-100
10
100
Frequency (MHz)
Differential Harmonic Distortion
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
OPA2695
SBOS354A – APRIL 2008 – REVISED AUGUST 2008 ...................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
OPA2695
SO-8
D
–40°C to +85°C
OP2695
OPA2695
QFN-16
RGT
–40°C to +85°C
2695
(1)
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
OPA2695ID
Rails, 75
OPA2695IDR
Tape and Reel, 2500
OPA2695IRGTT
Tape and Reel, 250
OPA2695IRGTR
Tape and Reel, 3000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
OPA2695
Power supply
UNITS
±6.5
Internal power dissipation
VDC
See Thermal Analysis
Differential input voltage
±1.2
V
Input common-mode voltage range
±VS
V
Storage temperature range: D, RGT
–65 to +125
°C
Lead temperature (soldering, 10s)
+300
°C
Junction temperature (TJ)
+150
°C
Junction temperature (TJ), continuous operation
+140
°C
Human body model (HBM) (2)
1500
V
Charged device model (CDM)
1000
V
50
V
ESD rating:
Machine model (MM)
(1)
(2)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these and any other conditions beyond
those specified is not supported.
Pins 1 and 4 on the SO-8 package and pins 6 and 15 on the QFN package are greater than 500V HBM.
PIN CONFIGURATIONS
SO-8 PACKAGE
(TOP VIEW)
2
Out B
OUT A
5
DIS A
1
12
-VS
+IN A
2
11
+VS
+IN B
3
10
+VS
DIS B
4
9
-VS
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OUT B
4
NC
-In B
13
+VS
8
6
14
3
7
+In B
NC
-VS
-IN A
7
15
2
6
+In A
-IN B
Out A
NC
8
5
1
NC
-In A
16
QFN-16 PACKAGE
(TOP VIEW)
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2695
OPA2695
www.ti.com ...................................................................................................................................................... SBOS354A – APRIL 2008 – REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
At RF = 402Ω, RL = 100Ω, and G = +8V/V, unless otherwise noted.
OPA2695ID, IRGT
TYP
PARAMETER
MIN/MAX OVER TEMPERATURE
UNITS
MIN/
MAX
TEST
LEVEL (1)
1100
MHz
typ
C
850
MHz
typ
C
MHz
min
B
MHz
typ
C
MHz
min
B
dB
max
B
MHz
typ
C
B
CONDITIONS
+25°C
G = +1V/V, RF = 523Ω
G = +2V/V, RF = 511Ω
G = +8V/V, RF = 402Ω
450
G = +16V/V, RF = 249Ω
350
+25°C (2)
0°C to
70°C (3)
–40°C to
+85°C (3)
AC PERFORMANCE (see Figure 68)
Small-signal bandwidth (VO = 0.2VPP)
Bandwidth for 0.2dB gain flatness
G = +2V/V, VO = 0.2VPP, RF = 511Ω
300
Peaking at a gain of +1
RF = 523Ω, VO = 0.2VPP
4.6
Large-signal bandwidth
G = +8V/V, RF = 402Ω, VO = 4VPP
400
Slew rate
Rise-and-fall time
400
5.4
380
5.8
350
6.0
G = -8V/V, VO = 4V step
2500
2000
1900
1800
V/µs
min
G = +8V/V, VO = 4V step
2900
2600
2500
2400
V/µs
min
B
G = +8V/V, VO = 1V step
0.8
ns
typ
C
G = +8V/V, VO = 4V step
1.0
ns
typ
C
Settling time to 0.02%
G = +8V/V, VO = 2V step
16
ns
typ
C
Settling time to 0.1%
G = +8V/V, VO = 2V step
10
ns
typ
C
Harmonic distortion
G = +8V/V, f = 10MHz, VO = 2VPP
2nd harmonic
RL = 100Ω
–73
–62
–60
–59
dBc
max
B
RL ≥ 500Ω
–78
–76
–74
–73
dBc
max
B
RL = 100Ω
–82
–80
–75
–72
dBc
max
B
RL ≥ 500Ω
–81
–80
–79
–78
dBc
max
B
Input voltage noise
f > 1MHz
1.8
2
2.7
2.9
nV/√Hz
max
B
Noninverting input current noise
f > 1MHz
18
19
21
22
pA/√Hz
max
B
Inverting input current noise
f > 1MHz
22
24
26
27
pA/√Hz
max
B
Differential gain
G = +2V/V, NTSC, VO = 1.4VPP,
RL = 150Ω
–0.01
%
typ
C
Differential phase
G = +2V/V, NTSC, VO = 1.4VPP,
RL = 150Ω
-0.05
°
typ
C
f ≤ 10MHz
–50
dB
typ
C
3rd harmonic
Crosstalk
DC PERFORMANCE (4)
Open-loop transimpedance gain (ZOL)
VO = 0V, RL = 100Ω
85
45
43
41
kΩ
min
A
Input offset voltage
VCM = 0V
±0.3
±3.5
±4.0
±4.5
mV
max
A
Average offset voltage drift
VCM = 0V
±10
±15
µV/°C
max
B
Noninverting input bias current
VCM = 0V
±37
±41
µA
max
A
Average noninverting input bias current drift
VCM = 0V
+150
+180
nA/°C
max
B
Inverting input bias current
VCM = 0V
±66
±70
µA
max
A
Average inverting input bias current drift
VCM = 0V
±120
±160
nA/°C
max
B
A
+13
±20
±30
±60
INPUT
Common-mode input voltage range (CMIR) (5)
Common-mode rejection ratio (CMRR)
±3.3
±3.1
±3.0
±3.0
V
min
56
51
50
50
dB
min
A
280 || 1.2
kΩ || pF
typ
C
Open-loop
29
Ω
typ
C
VCM = 0V
Noninverting input Impedance
Inverting input resistance (RI)
OUTPUT
Voltage output swing
No load
±4.1
±3.9
±3.9
±3.9
V
min
A
100Ω load
±3.9
±3.7
±3.7
±3.6
V
min
A
Current output, sourcing
VO = 0
+120
+90
+80
+70
mA
min
A
Current output, sinking
VO = 0
–120
–90
–80
–70
mA
min
A
G = +8V/V, f = 100kHz
0.04
Ω
typ
C
Closed-loop output impedance
(1)
(2)
(3)
(4)
(5)
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +26°C at high temperature limit for over
temperature specifications.
Current is considered positive out of pin.
Tested < 3dB below minimum specified CMRR at ±CMIR limits.
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OPA2695
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ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C.
At RF = 402Ω, RL = 100Ω, and G = +8V/V, unless otherwise noted.
OPA2695ID, IRGT
TYP
MIN/MAX OVER TEMPERATURE
+25°C
+25°C (2)
0°C to
70°C (3)
–40°C to
+85°C (3)
UNITS
MIN/
MAX
Both channels, VDIS = 0
–200
–340
–375
–385
µA
typ
A
VIN = ±0.25VDC
1
µs
typ
C
Enable time
VIN = ±0.25VDC
25
ns
typ
C
Off isolation
G = +8V/V, 10MHz
80
dB
typ
C
4
pF
typ
C
PARAMETER
DISABLE (Disabled LOW)
CONDITIONS
TEST
LEVEL (1)
QFN-16 (RGT) package only
Power-down supply current (+VS)
Disable time
Output capacitance in disable
Turn-on glitch
G = +2V/V, RL = 150Ω, VIN = 0
±100
mV
typ
C
Turn-off glitch
G = +2V/V, RL = 150Ω, VIN = 0
±20
mV
typ
C
Enable voltage
3.3
3.5
3.6
3.7
V
min
A
Disable voltage
1.8
1.7
1.6
1.5
V
max
A
75
130
143
145
µA
max
A
V
typ
C
Minimum operating voltage
±1.75
±1.8
±1.9
V
min
B
Maximum operating voltage
±6
±6
±6
V
max
A
Control pin input bias current (DIS)
VDIS = 0
POWER SUPPLY
Specified operating voltage
±5
Maximum quiescent current
Both channels, VS = ±5V
25.8
26.8
27.6
28.6
mA
max
A
Minimum quiescent current
Both channels, VS = ±5V
25.8
25.2
23.6
22
mA
min
A
Input-referred
55
51
48
48
dB
typ
A
–40 to +85
°C
typ
C
Power-supply rejection ratio (+PSRR)
TEMPERATURE RANGE
Specification: ID, IRGT
Thermal resistance, θJA
4
Junction-to-ambient
D
SO-8
100
°C/W
typ
C
RGT
QFN-16
55
°C/W
typ
C
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2695
OPA2695
www.ti.com ...................................................................................................................................................... SBOS354A – APRIL 2008 – REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At RF = 422Ω, RL = 100Ω to VS/2, and G = +8, unless otherwise noted.
OPA2695ID, IRGT
TYP
PARAMETER
MIN/MAX OVER TEMPERATURE
UNITS
MIN/
MAX
TEST
LEVEL (1)
940
MHz
typ
C
700
MHz
typ
C
MHz
typ
B
MHz
typ
C
MHz
min
B
dB
max
B
MHz
typ
C
CONDITIONS
+25°C
G = +1V/V, RF = 511Ω
G = +2V/V, RF = 487Ω
G = +8V/V, RF = 348Ω
395
G = +16V/V, RF = 162Ω
275
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
AC PERFORMANCE
Small-signal bandwidth (VO = 0.2VPP)
Bandwidth for 0.2dB gain flatness
380
330
300
G = +2V/V, VO < 0.2VPP, RF = 487Ω
Peaking at a gain of +1
RF = 511Ω, VO < 0.2VPP
1.0
Large-signal bandwidth
G = +8V/V, VO = 2VPP
363
Slew rate
2.0
1200
3.0
G = +8V/V, 2V step
1800
V/µs
min
B
Rise-and-fall time
G = +8V/V, VO = 2V step
1
ns
typ
C
Settling time to 0.02%
G = +8V/V, VO = 2V step
16
ns
typ
C
Settling time to 0.1%
G = +8V/V, VO = 2V step
10
ns
typ
C
Harmonic distortion
1300
2.5
1100
G = +8V/V, f = 10MHz, VO = 2VPP
2nd harmonic
RL = 100Ω to VS/2
–67
–55
–55
–54
dBc
max
B
RL ≥ 500Ω to VS/2
–101
–64
–64
–63
dBc
max
B
RL = 100Ω to VS/2
–64
–62
–62
–63
dBc
max
B
RL ≥ 500Ω to VS/2
–92
–61
–61
–60
dBc
max
B
Input voltage noise
f > 1MHz
1.8
2
2.7
2.9
nV/√Hz
max
B
Noninverting input current noise
f > 1MHz
18
19
21
22
pA/√Hz
max
B
Inverting input current noise
f > 1MHz
22
24
26
27
pA/√Hz
max
B
3rd harmonic
DC PERFORMANCE (4)
Open-loop transimpedance Gain (ZOL)
VO = VS/2, RL = 100Ω to VS/2
70
40
38
36
kΩ
min
A
Input offset voltage
VCM = VS/2
±0.3
±3.5
±4.0
±4.5
mV
max
A
Average offset voltage drift
VCM = VS/2
±10
±15
µV/°C
max
B
Noninverting input bias current
VCM = VS/2
±45
±50
µA
max
A
Average noninverting input bias current drift
VCM = VS/2
±110
±170
nA/°C
max
B
Inverting input bias current
VCM = VS/2
±66
±70
µA
max
A
Average inverting input bias current drift
VCM = VS/2
±120
±160
nA/°C
max
B
±5
±10
±40
±60
INPUT
Least positive input voltage (5)
1.7
1.8
1.9
1.9
V
max
A
Most positive input voltage (5)
3.3
3.2
3.1
3.1
V
min
A
54
51
50
50
dB
min
A
280 || 1.2
kΩ || pF
typ
C
Open-loop
32
Ω
typ
C
Common-mode rejection ratio (CMRR)
VCM = VS/2
Noninverting input impedance
Inverting input resistance (RI)
OUTPUT
Most positive output voltage
No load
4.2
4.0
3.9
3.8
V
min
A
RL = 100Ω load to VS/2
4.0
3.9
3.8
3.7
V
min
A
No load
0.8
1.0
1.1
1.2
V
max
A
RL = 100Ω load to VS/2
1.0
1.1
1.2
1.3
V
max
A
Current output, sourcing
VO = VS/2
+90
+70
+67
+66
mA
min
A
Current output, sinking
VO = VS/2
–90
–70
–67
–66
mA
min
A
G = +2V/V, f = 100kHz
0.05
Ω
typ
C
Least positive output voltage
Closed-loop output impedance
(1)
(2)
(3)
(4)
(5)
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +12°C at high temperature limit for over
temperature specifications.
Current is considered positive out of pin.
Tested < 3dB below minimum specified CMRR at ±CMIR limits.
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OPA2695
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ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At RF = 422Ω, RL = 100Ω to VS/2, and G = +8, unless otherwise noted.
OPA2695ID, IRGT
TYP
PARAMETER
DISABLE (Disabled LOW)
CONDITIONS
MIN/MAX OVER TEMPERATURE
+25°C
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
UNITS
MIN/
MAX
TEST
LEVEL (1)
–190
–320
–350
–360
µA
max
A
µs
typ
C
25
ns
typ
C
80
dB
typ
C
4
pF
typ
C
QFN-16 (RGT) package only
Power-down supply current (+VS)
Both channels, VDIS = 0
Disable time
1
Enable time
Off isolation
G = +8V/V, 10MHz
Output capacitance in disable
Turn-on glitch
G = +2V/V, RL = 150Ω, VIN = VS/2
±100
mV
typ
C
Turn-off glitch
G = +2V/V, RL = 150Ω, VIN = VS/2
±20
mV
typ
C
Enable voltage
3.3
3.5
3.6
3.7
V
min
A
Disable voltage
1.8
1.7
1.6
1.5
V
max
A
75
130
143
149
µA
max
A
V
typ
C
3.6
3.6
3.8
V
min
B
12
12
12
V
max
A
A
Control pin input bias current (DIS)
VDIS = 0
POWER SUPPLY
Specified single-supply operating voltage
5
Minimum single-supply operating voltage
3.5
Maximum single-supply operating voltage
Maximum quiescent current
Both channels, VS = +5V
22.8
24.2
25.2
26.0
mA
max
Minimum quiescent current
Both channels, VS = +5V
22.8
21.8
18.8
18.2
mA
min
A
Input-referred
56
dB
typ
C
–40 to +85
°C
typ
C
Power-supply rejection ratio (+PSRR)
TEMPERATURE RANGE
Specification: ID, IRGT
Thermal resistance, θJA
Junction-to-ambient
D
SO-8
100
°C/W
typ
C
RGT
QFN-16
55
°C/W
typ
C
6
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OPA2695
www.ti.com ...................................................................................................................................................... SBOS354A – APRIL 2008 – REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V
At G = +8V/V, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
6
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
3
G = +1V/V
G = -2, RF = 499W
0
Normalized Gain (dB)
Normalized Gain (dB)
3
0
-3
G = +2V/V
-6
G = +4V/V
-9
G = +8V/V
-3
-6
G = -4, RF = 470W
-9
G = -8, RF = 442W
-12
G = -16, RF = 806W
-15
-12
G = +16V/V
-15
10M
100M
1G
-18
10M
10G
100M
Figure 1.
Figure 2.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
3
3
0
0
-3
Normalized Gain (dB)
Normalized Gain (dB)
Frequency (Hz)
VO = 1VPP and 2VPP
-6
-9
-12
-15
VO = 4VPP
-18
0
200M
G = -8
RF = 442W
-3
-6
-9
VO = 1VPP, 2VPP, 4VPP, and 7VPP
-12
-15
VO = 7VPP
RF = 402W
-21
-18
400M
600M
1G
800M
0
200M
Frequency (Hz)
Figure 3.
Figure 4.
2.0
1.00
2.0
1.5
0.75
1.5
0.5
0.25
0
0
-0.5
Small-Signal ±500mV
-1.0
-1.5
-2.0
-2.5
G = +8V/V
RF = 402W
Time (1ns/div)
-0.25
-0.50
75MHz Square Wave Input
Large-Signal ±2V
1.0
0.5
Small-Signal ±500mV
-1.0
-1.00
-2.0
-1.25
-2.5
0.75
0.50
0
-0.5
-1.5
1.00
0.25
0
-0.75
1.25
-0.50
-0.75
G = -8V/V
RF = 442W
Figure 5.
-0.25
Output Voltage (V)
0.50
Output Voltage (V)
Large-Signal ±2V
Output Voltage (V)
2.5
75MHz Square Wave Input
1G
800M
INVERTING PULSE RESPONSE
1.25
1.0
600M
400M
Frequency (Hz)
NONINVERTING PULSE RESPONSE
2.5
Output Voltage (V)
1G
Frequency (Hz)
-1.00
Time (1ns/div)
-1.25
Figure 6.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +8V/V, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 2VPP
G = +8V/V
f = 10MHz
-70
-75
2nd Harmonic
-80
-85
HARMONIC DISTORTION vs SUPPLY VOLTAGE
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-65
2nd Harmonic
-70
-75
-80
-85
3rd Harmonic
3rd Harmonic
-90
-90
50
100
5
1k
6
7
Figure 7.
f = 10MHz
G = +8V/V
RL = 100W
2nd Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
-70
3rd Harmonic
-80
-90
11
12
-70
2nd Harmonic
-75
-80
-85
3rd Harmonic
-90
-100
1
10
0.5
100
Figure 9.
HARMONIC DISTORTION vs NONINVERTING GAIN
HARMONIC DISTORTION vs INVERTING GAIN
-68
2nd Harmonic
Harmonic Distortion (dBc)
-75
-80
VO = 2VPP
f = 10MHz
RL = 100W
-70
-70
3rd Harmonic
VO = 2VPP
f = 10MHz
RL = 100W
-90
6
Figure 10.
-65
-85
1
Output Voltage (VPP)
Frequency (MHz)
Harmonic Distortion (dBc)
10
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-65
VO = 2VPP
G = +8V/V
RL = 100W
9
Figure 8.
HARMONIC DISTORTION vs FREQUENCY
-50
8
Supply Voltage (VS+ - VS-) (V)
Resistance (W)
-72
2nd Harmonic
-74
-76
-78
-80
3rd Harmonic
-82
-84
10
2
8
VO = 2VPP
f = 10MHz
G = +8V/V
RL = 100W
-65
20
10
2
Gain (V/V)
Gain (|V/V|)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +8V/V, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE DENSITY
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
100
45
Inverting Input Current Noise
Output Intercept (+dBm)
Current Noise (pA/ÖHz)
Voltage Noise (nV/ÖHz)
50W
22pA/ÖHz
19pA/ÖHz
Noninverting Input Current Noise
10
1.7nV/ÖHz
Input Voltage Noise
1
10
3
10
4
10
5
10
6
10
7
10
50W
50W
402W
PI
35
G = +8V/V, Noninverting
30
25
G = -8V/V, Inverting
PI
50W
PO
OPA2695
20
50W
56.2W
402W
15
8
40
20
60
80
100 120 140 160 180 200 220 240
Frequency (Hz)
Frequency (MHz)
Figure 13.
Figure 14.
INPUT RETURN LOSS vs FREQUENCY (S11)
OUTPUT RETURN LOSS vs FREQUENCY (S22)
0
0
G = ±8V/V
G = -8V/V
-10
-10
-20
Return Loss (dB)
Return Loss (dB)
PO
OPA2695
40
-30
G = +8V/V
-40
-50
Without 2.7pF Trim Capacitor
-20
-30
-40
50W
1/2
OPA2695
-50
-60
S22
With 2.7pF Trim Capacitor
-70
10M
1k
100M
-60
10M
1G
Trim Cap
2.7pF
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 15.
Figure 16.
RECOMMENDED RS vs CAPACITIVE LOAD
SMALL-SIGNAL FREQUENCY RESPONSE
vs CAPACITIVE LOAD
21
0.1dB Peaking Allowed
VO = 0.5VPP
CL = 22pF
CL = 47pF
CL = 10pF
18
RS (W)
Gain (dB)
100
CL = 100pF
15
RS
10
50W OPA2695
12
402W
CL
1kW
(1)
56.2W
NOTE: (1) 1kW is optional.
1
1
10
100
1000
9
10M
100M
Capacitive Load (pF)
Frequency (Hz)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +8V/V, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE
+PSRR
Rejection Ratio (dB)
55
50
-PSRR
CMRR
45
40
35
30
25
20
10
3
10
4
5
6
10
10
Frequency (Hz)
10
7
10
8
100
0
20 log|ZOL|
90
-40
70
-60
60
-80
50
-100
Ð ZOL
40
-140
20
-160
10
-180
0
10
5
10
6
7
10
Frequency (Hz)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
8
10
9
-200
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
183
30
Sourcing Output Current
Left Scale
100W
Load Line
182
2
50W
Load Line
1
0
-1
25W
Load Line
-2
-3
1W
Internal
Power
Output Current (mA)
1W
Internal
Power
28
Sinking Output Current
Left Scale
181
26
Supply Current
Right Scale
180
24
179
22
Supply Current (mA)
Output Voltage (V)
10
Figure 20.
5
3
-120
30
Figure 19.
4
-20
80
Open-Loop Phase (°)
Open-Loop Transimpedance Gain (dBW)
CMRR AND PSRR vs FREQUENCY
60
-4
-5
-250 -200 -150 -100 -50
178
0
50
100 150 200 250
20
-50
-25
Output Current (mA)
0
25
50
75
Figure 22.
NONINVERTING OVERDRIVE RECOVERY
INVERTING OVERDRIVE RECOVERY
6
6
4
4
Input
Output
Linear Input
Range
0
-2
-4
Input/Output Voltage (V)
Input/Output Voltage (V)
Output
Input
2
10
Linear Input
Range
0
-2
-4
G = +8V/V
-6
125
Ambient Temperature (°C)
Figure 21.
2
100
-6
G = -8V/V
RF = 442W
Time (100ns/div)
Time (100ns/div)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +8V/V, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
SETTLING TIME
DISABLE FEEDTHROUGH vs FREQUENCY
20
VO = 2V Step
G = +8V/V
15
Input/Output Voltage (mV)
-60
G = +8V/V
-65
-70
10
Input
-75
Gain (dB)
5
0
-5
-80
-85
-90
Output
-10
Forward
-95
-15
-100
-20
-105
Time (1ns/div)
Reverse
1
10
100
Frequency (MHz)
Figure 25.
Figure 26.
COMPOSITE VIDEO (dG/dØ)
TYPICAL DC DRIFT OVER TEMPERATURE
0.02
1.0
-dG
Input Offset Voltage (mV)
-0.02
-dÆ
-0.04
VI
75W
1/2
OPA2695
1kW
-0.08
511W
511W
+dG, 1kW Pull-Down
VO
Video
Loads
0.9
12
0.8
4
Inverting Input Bias Current
0.7
-4
Input Offset Voltage
0.6
-5V
+dÆ, 1kW Pull-Down
1kW, Optional Pull-Down
-0.10
0.5
1
2
4
3
-50
-25
Video Loads
0
25
50
75
100
125
Figure 28.
COMMON-MODE INPUT AND OUTPUT SWING
vs SUPPLY VOLTAGE
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
6
5
5
2.5
4
2.0
VDIS
Output Voltage Swing
VDIS (V)
3
Input Voltage Swing
VOUT
3
1.5
2
1.0
1
0.5
0
0
1
Output Voltage (V)
4
2
-20
Ambient Temperature (°C)
Figure 27.
Input/Output Swing (±V)
-12
Input Bias Current (mA)
dG/dÆ (%/°)
0
-0.06
20
Noninverting Input Bias Current
VIN = 0.25VDC
0
-1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
-0.5
Time (1ms/div)
Power Supplies (±V)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +8V/V, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
SMALL-SIGNAL BANDWIDTH vs
SINGLE-SUPPLY VOLTAGE
CROSSTALK
0
600
Small-Signal Bandwidth (MHz)
-10
Crosstalk (dB)
-20
Input: Channel A
Output: Channel B
-30
-40
-50
Input: Channel B
Output: Channel A
-60
-70
400
300
G = +8V/V
RF = 348W
VO = 500mVPP
200
-80
1M
12
500
10M
100M
1G
4
5
6
7
8
9
Frequency (Hz)
Single-Supply Voltage (V)
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS: VS = ±5V, Differential Operation
At GD = 10V/V, RF = 500Ω, and RL = 800Ω, unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
+5V
1
0
ZI = RT || 2RG
1:1
VI
RG
RT
RG
VO
VI
=
500W
RG
= GD
Normalized Gain (dB)
1/2
OPA2695
RF
500W
RL
800W
RF
500W
VO
GD = 5V/V
-1
-2
-3
-4
GD = 10V/V
-5
-6
GD = 20V/V
-7
1/2
OPA2695
-8
10M
100M
-5V
Figure 33.
Figure 34.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL HARMONIC DISTORTION vs FREQUENCY
21
-65
20
19
VO = 2VPP
VO = 8VPP
18
VO = 4VPP
17
Harmonic Distortion (dBc)
GD = 10V/V
Gain (dB)
1G
Frequency (Hz)
VO = 12VPP
GD = 10V/V
VO = 2VPP
RL = 800W
-70
-75
-80
3rd Harmonic
-85
-90
-95
2nd Harmonic
VO = 16VPP
16
-100
10
100
500
10
100
Frequency (MHz)
Frequency (MHz)
Figure 35.
Figure 36.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
9
1k
CL = 100pF
CL = 47pF
CL = 22pF
CL = 10pF
6
3
RS (W)
Gain (dB)
100
10
+5V
0
-3
OPA2695
50W
500W
RS
50W
500W
RS
PI
-6
CL
(1)
1kW
OPA2695
NOTE: (1) Optional 1kW load.
1
-5V
-9
1
10
100
1000
10
100
Capacitive Load (pF)
Frequency (MHz)
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS: VS = ±5V, Differential Operation (continued)
At GD = 10V/V, RF = 500Ω, and RL = 800Ω, unless otherwise noted.
DIFFERENTIAL HARMONIC DISTORTION vs LOAD
RESISTANCE
GD = 10V/V
f = 20MHz
VO = 2VPP
-70
2nd Harmonic
-80
-90
3rd Harmonic
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT
VOLTAGE
GD = 10V/V
f = 20MHz
RL = 800W
-70
3rd Harmonic
-80
2nd Harmonic
-90
-100
-100
200
1
1k
2
3
4
DIFFERENTIAL HARMONIC DISTORTION vs INVERTING
GAIN
-80
-85
3rd Harmonic
-90
-95
f = 20MHz
VO = 2VPP
RL = 800W
-85
3rd Harmonic
-90
-95
2nd Harmonic
-100
-100
10
2
20
10
2
Figure 41.
Figure 42.
DIFFERENTIAL HARMONIC DISTORTION vs SUPPLY
VOLTAGE
GD = 10V/V
f = 20MHz
VO = 2VPP
RL = 800W
-70
3rd Harmonic
-80
2nd Harmonic
-90
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
50
Output Intercept (+dBm)
-60
45
+5V
40
35
OPA2695
50W
500W
50W
500W
PI
30
6
7
8
9
10
PO
800W
OPA2695
-5V
25
-100
5
20
Inverting Gain (|V/V|)
Noninverting Gain (V/V)
Harmonic Distortion (dBc)
8
DIFFERENTIAL HARMONIC DISTORTION vs
NONINVERTING GAIN
2nd Harmonic
20
40
60
80
100 120 140 160 180 200 220 240
Frequency (MHz)
Supply Voltage (V)
Figure 43.
14
7
Figure 40.
f = 20MHz
VO = 2VPP
RL = 800W
-80
6
Figure 39.
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-75
5
Output Voltage (VPP)
Load Resistance (W)
Figure 44.
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TYPICAL CHARACTERISTICS: VS = 5V
At G = +8V/V, RF = 348Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
3
3
G = +1V/V
G = -2, RF = 453W
0
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
G = +2V/V
-6
-9
G = +4V/V
-12
-3
-6
-9
G = -4, RF = 442W
-12
G = -8, RF = 422W
G = +8V/V
-15
-15
G = -16, RF = 806W
G = +16V/V
-18
100M
1G
2G
10
100
Frequency (Hz)
Frequency (MHz)
Figure 45.
Figure 46.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
3
3
0
0
Normalized Gain (dB)
Normalized Gain (dB)
-18
10M
-3
VO = 1VPP,
VO = 2VPP
-6
-9
-12
-3
-6
VO = 1VPP,
VO = 2VPP
-9
-12
G = -8V/V
RF = 422W
RG = 52.7W
-15
-15
-18
-18
0
200M
400M
600M
800M
0
1G
200M
Figure 47.
Figure 48.
NONINVERTING PULSE RESPONSE
1G
INVERTING PULSE RESPONSE
75MHz Square-Wave Input
1.0
Output Voltage (mV)
1.0
Output Voltage (V)
800M
1.5
75MHz Square-Wave Input
0.5
0
-0.5
-1.5
600M
Frequency (Hz)
1.5
-1.0
400M
Frequency (Hz)
0.5
0
-0.5
-1.0
G = +8V/V
RF = 348W
-1.5
G = -8V/V
RF = 422W
Time (1ns/div)
Time (1ns/div)
Figure 49.
Figure 50.
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TYPICAL CHARACTERISTICS: VS = 5V (continued)
At G = +8V/V, RF = 348Ω, and RL = 100Ω, unless otherwise noted.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
9
200
100
VO = 0.5VPP
RL = 1kW
6
Gain (dB)
RS (W)
3
10
CL = 10pF
0
+5V
1000pF
+5V
2kW
CL = 22pF
RS
VI
-3
50W
VO
2kW OPA2695
CL
(1)
1kW
CL = 47pF
348W
-6
50W
NOTE: (1) 1kW is optional.
CL = 100pF
1000pF
1
-9
1
10
100
1000
1
Frequency (MHz)
Figure 51.
Figure 52.
HARMONIC DISTORTION vs FREQUENCY
-50
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
3rd Harmonic
-60
2nd Harmonic
-70
-80
-90
-60
2nd Harmonic
-70
-80
-90
3rd Harmonic
-100
G = +8V/V
f = 10MHz
RL = 100W
-110
-100
100k
-120
1M
10M
0
100M
0.5
1.0
Figure 53.
2.0
2.5
Figure 54.
HARMONIC DISTORTION vs LOAD RESISTANCE
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
35
-50
-60
3rd Harmonic
-70
-80
-90
-100
G = +8V/V
f = 10MHz
VO = 2VPP
-110
2nd Harmonic
Output Intercept (+dBm)
Harmonic Distortion (dBc)
1.5
Output Voltage (VPP)
Frequency (Hz)
30
25
20
G = +8V/V
VO = 2VPP At Matched Load
15
-120
50
100
600
20
Resistance (W)
40
60
80
100 120 140 160 180 200 220 240
Center Frequency (MHz)
Figure 55.
16
500
-40
G = +8V/V
VO = 2VPP
RL = 100W
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-40
100
10
Capacitive Load (pF)
Figure 56.
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TYPICAL CHARCTERISTICS: VS = 5V, Differential Operation
At GD = 10V/V, RF = 500Ω, and RL = 800Ω, unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
+2.5V
1
0
Normalized Gain (dB)
1/2
OPA2695
-2.5V
ZI = RT || 2RG
1:1
VI
RT
RG
RF
500W
RG
RF
500W
RL
800W
VO
VI
=
500W
RG
= GD
-2
-3
GD = 5V/V
-4
GD = 10V/V
-5
-6
GD = 20V/V
-7
+2.5V
VO
-1
-8
10M
1/2
OPA2695
100M
1G
Frequency (Hz)
-2.5V
Figure 57.
Figure 58.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
21.0
50
20.0
Gain (dB)
19.5
19.0
2VPP
18.5
18.0
17.5
4VPP
17.0
Output Intercept (+dBm)
20.5
45
40
OPA2695
35
1:1
PI
50W
500W
50W
500W
PO
30
OPA2695
16.5
8VPP
16.0
10
100
25
20
400
40
60
80
100 120 140 160 180 200 220 240
Center Frequency (MHz)
Frequency (MHz)
Figure 59.
Figure 60.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
300
9
100
6
VO = 1.25VPP
RL = 1kW
CL = 10pF
+5V
Gain (dB)
RS (W)
3
10
OPA2695
50W
500W
RS
50W
500W
RS
CL = 22pF
PI
0
CL
1kW
(1)
PO
OPA2695
NOTE: (1) Optional 1kW load.
-3
-5V
CL = 47pF
-6
VO = 1.25VPP
RL = 1kW
1
1
CL = 100pF
-9
10
100
1000
10
100
Capacitive Load (pF)
Frequency (MHz)
Figure 61.
Figure 62.
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TYPICAL CHARCTERISTICS: VS = 5V, Differential Operation (continued)
At GD = 10V/V, RF = 500Ω, and RL = 800Ω, unless otherwise noted.
DIFFERENTIAL HARMONIC DISTORTION vs LOAD
RESISTANCE
-50
GD = 10V/V
f = 20MHz
VO = 2VPP
3rd Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT
VOLTAGE
-70
-80
-90
GD = 10V/V
f = 20MHz
RL = 800W
-60
3rd Harmonic
-70
2nd Harmonic
-80
2nd Harmonic
-90
-100
200
1.0
1k
1.5
3.0
3.5
4.0
Figure 64.
DIFFERENTIAL HARMONIC DISTORTION vs
NONINVERTING GAIN
DIFFERENTIAL HARMONIC DISTORTION vs INVERTING
GAIN
-60
f = 20MHz
VO = 2VPP
RL = 800W
-65
2.5
Figure 63.
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
2.0
Output Voltage (VPP)
Load Resistance (W)
3rd Harmonic
-70
-75
-80
2nd Harmonic
-85
f = 20MHz
VO = 2VPP
RL = 800W
-65
3rd Harmonic
-70
-75
-80
2nd Harmonic
-90
-85
10
2
20
10
2
Noninverting Gain (V/V)
20
Inverting Gain (V/V)
Figure 65.
Figure 66.
DIFFERENTIAL HARMONIC DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
-50
GD = 10V/V
VO = 2VPP
RL = 800W
-55
-60
3rd Harmonic
-65
-70
-75
-80
2nd Harmonic
-85
10
100
Frequency (MHz)
Figure 67.
18
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APPLICATIONS INFORMATION
WIDEBAND CURRENT-FEEDBACK
OPERATION
+5V
The OPA2695 gives a new level of performance in
wideband current-feedback op amps. Nearly constant
ac performance over a wide gain range, along with
2900V/µs slew rate, gives a lower power and cost
solution for high-intercept IF amplifier requirements.
While optimized at a gain of +8V/V (12dB to a
matched 50Ω load) to give 450MHz bandwidth,
applications from gains of 1 to 40 can be supported.
At gains above 20, the signal bandwidth starts to
decrease, but continues to exceed 180MHz up to a
gain of 40V/V (26dB to a matched 50Ω load). Single
+5V supply operation is also supported with similar
bandwidths but reduced output power capability. For
lower speed (< 250MHz) requirements with higher
output power, consider the OPA2691.
Figure 68 shows the dc-coupled, gain of +8V/V, dual
power-supply circuit used as the basis of the ±5V
Electrical Characteristics and Typical Characteristics.
For test purposes, the input impedance is set to 50Ω
with a resistor to ground and the output impedance is
set to 50Ω with a series output resistor. Voltage
swings reported in the specifications are taken
directly at the input and output pins while load powers
(dBm) are defined at a matched 50Ω load. For the
circuit of Figure 68, the total effective load is 100Ω ||
458Ω = 82Ω. The disable control line (DIS) is typically
left open to get normal amplifier operation. The
disable line must be asserted low to shut off the
OPA2695. Figure 68 includes one optional
component. In addition to the usual power-supply
decoupling capacitors to ground, a 0.01µF capacitor
is included between the two power-supply pins. In
practical printed circuit board (PCB) layouts, this
optional added capacitor typically improves the
2nd-harmonic distortion performance by 3dB to 6dB
for bipolar supply operation.
+
0.1mF
6.8mF
50W Source
DIS
VI
50W
Optional
0.01mF
50W
VO
1/2
OPA2695
50W Load
RF
402W
RG
56.2W
0.1mF
+
6.8mF
-5V
Figure 68. DC-Coupled, G = +8V/V, Bipolar Supply
Specifications and Test Circuit
Figure 69 shows the dc-coupled, gain of –8V/V, dual
power-supply circuit used as the basis of the Inverting
Typical Characteristic curves. Inverting operation
offers several performance benefits. Because there is
no common-mode signal across the input stage, the
slew rate for inverting operation is higher and the
distortion performance is slightly improved. An
additional input resistor, RT, is included in Figure 69
to set the input impedance equal to 50Ω. The parallel
combination of RT and RG set the input impedance.
Both the noninverting and inverting applications of
Figure 68 and Figure 69 benefit from optimizing the
feedback resistor (RF) value for bandwidth (see the
discussion in Setting Resistor Values to Optimize
Bandwidth). The typical design sequence is to select
the RF value for best bandwidth, set RG for the gain,
then set RT for the desired input impedance. As the
gain increases for the inverting configuration, a point
is reached where RG equals 50Ω, where RT is
removed and the input match is set by RG only. With
RG fixed to achieve an input match to 50Ω, RF is
simply increased to increase gain. This increase,
however, quickly reduces the achievable bandwidth,
as shown by the inverting gain of –16V/V frequency
response in the Typical Characteristic curves. For
gains greater than 10V/V (14dB at the matched load),
noninverting operation is recommended to maintain
broader bandwidth.
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ranges at both the input and the output. The circuit of
Figure 70 establishes an input midpoint bias using a
simple resistive divider from the +5V supply (two
806Ω resistors) to the noninverting input. The input
signal is then ac-coupled into this midpoint voltage
bias. The input voltage can swing to within 1.6V of
either supply pin, giving a 1.8VPP input signal range
centered between the supply pins. The input
impedance matching resistor (57.6Ω) used in
Figure 70 is adjusted to give a 50Ω input match when
the parallel combination of the biasing divider network
is included. The gain resistor (RG) is ac-coupled,
giving the circuit a dc gain of +1. This configuration
puts the input dc bias voltage (2.5V) on the output as
well. The feedback resistor value has been adjusted
from the bipolar supply condition to re-optimize for a
flat frequency response in +5V only, gain of +8
operation (see Setting Resistor Values to Optimize
Bandwidth). On a single +5V supply, the output
voltage can swing to within 1.0V of either supply pin
while delivering more than 90mA output current,
giving 3V output swing into 100Ω (7dBm maximum at
the matched load). The circuit of Figure 70 shows a
blocking capacitor driving into a 50Ω output resistor,
then into a 50Ω load. Alternatively, the blocking
capacitor could be removed with the load tied to a
supply midpoint or to ground if the dc current required
by this grounded load is acceptable.
+5V
+VS
+
0.1mF
20W
6.8mF
DIS
VO
1/2
OPA2695
50W Load
50W
Optional
0.01mF
50W Source
RF
442W
RG
54.9W
VI
RT
562W
0.1mF
+
6.8mF
-VS
-5V
Figure 69. DC-Coupled, G = –8V/V, Bipolar Supply
Specifications and Test Circuit
Figure 70 shows the ac-coupled, single +5V supply,
gain of +8V/V circuit configuration used as a basis for
the +5V only Electrical Characteristics and Typical
Characteristics. The key requirement for broadband
single-supply operation is to maintain input and
output signal swings within the useable voltage
+5V
+VS
+
0.1mF
6.8mF
806W
50W Source
0.1mF
DIS
VI
57.6W
1000pF
1/2
OPA2695
806W
RF
348W
VO
50W Load
0.1mF
50W
1000pF
RG
50W
1000pF
0.1mF
Figure 70. AC-Coupled, G = +8V/V, Single-Supply Specifications and Test Circuit
20
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Figure 71 shows the ac-coupled, single +5V supply,
gain of –8V/V circuit configuration used as a basis for
the +5V only Typical Characteristics. In this case, the
midpoint dc bias on the noninverting input is also
decoupled with an additional 0.1µF decoupling
capacitor. This decoupling configuration reduces the
source impedance at higher frequencies for the
noninverting input bias current noise. This 2.5V bias
on the noninverting input pin appears on the inverting
input pin and, because RG is dc blocked by the input
capacitor, also appears at the output pin. One
advantage to inverting operation is that because
there is no signal swing across the input stage, higher
slew rates and operation to even lower supply
voltages are possible. To retain a 1VPP output
capability, operation down to a 3V supply is allowed.
At a +3V supply, the input common-mode range is
0V. However, for the inverting configuration of a
current-feedback amplifier, wideband operation is
retained even with the input stage saturated.
The single-supply test circuits of Figure 70 and
Figure 71 show +5V operation. These same circuits
can be used over a single-supply range of +5V to
+12V. Operating on a single +12V supply, with the
absolute maximum supply voltage specification of
+13V, gives adequate design margin for the typical
±5% supply tolerance.
+5V
+VS
+
0.1mF
6.8mF
806W
20W
1000pF
0.1mF
806W
DIS
1/2
OPA2695
VO
50W Load
0.1mF
50W
1000pF
0.1mF
RG
52.8W
RF
422W
VI
1000pF
Figure 71. AC-Coupled, G = –8V/V, Single-Supply Specifications and Test Circuit
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WIDEBAND VIDEO MULTIPLEXING
(QFN-16 Package Only)
One common application for video speed amplifiers
that include a disable pin is to wire multiple amplifier
outputs together, then select one of several possible
video inputs to source onto a single line. This simple
wired-OR video multiplexer can be easily
implemented using the OPA2695IRGT, as Figure 72
shows.
Typically, channel switching is performed either on
sync or retrace time in the video signal. The two
inputs are approximately equal at this time. The
make-before-break disable characteristic of the
OPA2695 ensures that there is always one amplifier
controlling the line when using a wired-OR circuit
such as the one presented in Figure 72. Because
both inputs may be on for a short period during the
transition between channels, the outputs are
combined through the output impedance matching
resistors (82.5Ω in this case). When one channel is
disabled, its feedback network forms part of the
output impedance and slightly attenuates the signal in
getting out onto the cable. The gain and output
matching resistors have been slightly increased to
achieve a signal gain of +1V/V at the matched load
and provide a 75Ω output impedance to the cable.
The video multiplexer connection (as shown in
Figure 72) also ensures that the maximum differential
voltage across the inputs of the unselected channel
does not exceed the rated ±1.2V maximum for
standard video signal levels.
+5V
2kW
VDIS
+5V
Power-supply
decoupling not shown.
Video 1
1/2
OPA2695
DIS
75W
432W
-5V
82.5W
511W
75W Cable
432W
RG-59
511W
+5V
82.5W
1/2
OPA2695
Video 2
DIS
75W
-5V
2kW
Figure 72. Two-Channel Video Multiplexer
22
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HIGH-SPEED ACTIVE FILTERS
Wideband current-feedback op amps make ideal
elements for implementing high-speed active filters
where the amplifier is used as a fixed gain block
inside a passive RC circuit network. The relatively
constant bandwidth versus gain provides low
interaction between the actual filter poles and the
required gain for the amplifier. Figure 73 shows a
typical single-supply buffered filter application. In this
case, one of the OPA2695 channels is used to set up
the dc operating point and provide impedance
isolation from the signal source into the 2nd-stage
filter. That stage is set up to implement a 20MHz,
maximally flat Butterworth frequency response and
provide an ac gain of +4V/V.
The 51Ω input matching resistor is optional in this
case. The input signal is ac-coupled to the 2.5V dc
reference voltage developed through the resistor
divider from the +5V power supply. This first stage
acts as a gain of +1V/V voltage buffer for the signal
where the 511Ω feedback resistor is required for
stability. This first stage easily drives the low input
resistors required at the input of this high-frequency
filter. The second stage is set for a dc gain of +1V/V,
carrying the 2.5V operating point through to the
output pin and an ac gain of +4V/V. The feedback
resistor has been adjusted to optimize bandwidth for
the amplifier itself. As the single-supply frequency
response plots show, the OPA2695 in this
configuration gives greater than 400MHz small-signal
bandwidth. The capacitor values were chosen to be
as low as possible, but still large enough to overcome
the effects of the parasitic input capacitance of the
amplifier. The resistor values were slightly adjusted to
give the desired filter frequency response while
accounting for the approximate 1ns propagation delay
through each channel of the OPA2695.
+5V
20MHz, 2ND-ORDER BUTTERWORTH
LOW-PASS FREQUENCY RESPONSE
Power-supply
decoupling not shown.
0.1mF
12
5kW
100pF
8
VI
5kW
1/2
OPA2695
32.3W
105W
150pF
4
1/2
OPA2695
4VI
Gain (dB)
51W
0
-4
470W
511W
-8
20MHz, 2nd-Order Butterworth Low-Pass
158W
-12
0.1
1
10
100
Frequency (MHz)
0.1mF
Figure 73. Buffered Single-Supply Active Filter
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DIFFERENTIAL I/O APPLICATIONS
The OPA2695 offers very low third-order distortion
terms with a dominant second-order distortion for the
single amplifier operation. For the lowest distortion,
particularly where differential outputs are needed,
operating two OPA2695s in a differential I/O design
suppresses these even-order terms, delivering
extremely low harmonic distortion through high
frequencies and powers. Differential outputs are often
preferred for high performance ADCs, twisted-pair
driving, and mixer interfaces. Two basic approaches
to differential I/Os are the noninverting or inverting
configurations. Since the output is differential, the
signal polarity is somewhat meaningless—the
noninverting and inverting terminology applies here to
where the input is brought into the two OPA2695s.
Each
approach
has
its
advantages
and
disadvantages. Figure 74 shows a basic starting point
for noninverting differential I/O applications.
+VCC
OPA2695
VI
RG
-VCC
RF
500W
+VCC
RF
500W
VO
OPA2695
frequency response. It is common for ac-coupled
applications to include a blocking capacitor in series
with RG. This reduces the gain to 1 at low frequency,
rising to the AD expression shown above at higher
frequencies. The noninverting input approach of
Figure 74 can be used for higher gains than the
inverting input approach. It does, however, have a
reduced full-power bandwidth because of the lower
slew rate of the OPA2695 running noninverting
versus inverting input mode of operation.
Various combinations of single-supply or ac-coupled
gain can also be delivered using the basic circuit of
Figure 74. Common-mode bias voltages on the two
noninverting inputs pass on to the output with a gain
of 1, since an equal dc voltage at each inverting node
creates no current through RG. This circuit does show
a common-mode gain of 1 from input to output. The
source connection should either remove this
common-mode signal if undesired (using an input
transformer can provide this function), or the
common-mode voltage at the inputs can be used to
set the output commonmode bias. If the low
common-mode rejection of this circuit is a problem,
the output interface may also be used to reject that
common-mode. For
instance,
most
modern
differential input ADCs reject common-mode signals
very well, while a line driver application through a
transformer will also remove the common-mode
signal at the secondary of the transformer.
Figure 75 shows a differential I/O stage configured as
an inverting amplifier. In this case, the gain resistors
(RG) become part of the input resistance for the
source. This provides a better noise performance
than the non-inverting configuration, but does limit the
flexibility in setting the input impedance separately
from the gain.
+VCC
-VCC
VCM
Figure 74. Noninverting Input Differential I/O
Amplifier
This approach allows for a source termination
impedance that is independent of the signal gain. For
instance, simple differential filters may be included in
the signal path right up to the noninverting inputs
without interacting with the gain setting. The
differential signal gain for the circuit of Figure 74 is:
OPA2695
RG
VI
-VCC
RF
500W
RF
500W
RG
VO
AD = 1 + 2 × RF/RG
Since the OPA2695 is a current-feedback amplifier,
its bandwidth is principally controlled with the
feedback resistor value—Figure 74 shows a typical
value of 500Ω. However, the differential gain may be
adjusted with considerable freedom using just the RG
resistor. In fact, RG may be a reactive network
providing a very isolated shaping to the differential
24
OPA2695
VCM
-VCC
Figure 75. Inverting Input Differential I/O Amplifier
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The two noninverting inputs provide an easy
common-mode control input. This is particularly easy
if the source is ac-coupled through either blocking
caps or a transformer. In either case, the
common-mode input voltages on the two noninverting
inputs again have a gain of 1 to the output pins,
giving particularly easy common-mode control for
single-supply operation. The OPA2695 used in this
configuration does constrain the feedback to the
500Ω region for best frequency response. With RF
fixed, the input resistors may be adjusted to the
desired gain, but also change the input impedance as
well. The high-frequency common-mode gain for this
circuit from input to output is the same as for the
signal gain. Again, if the source might include an
undesired common-mode signal, that could be
rejected at the input using blocking caps (for
low-frequency and dc common-mode) or a
transformer coupling. The differential performance
plots shown in the Typical Characteristics used the
configuration of Figure 75 and an input 1:1
transformer. The differential signal gain in the circuit
of Figure 75 is:
with over 400MHz –3dB bandwidth. Using
Equation 3, this implies a differential output slew of
18000V/µs, or 9000V/µs at each output. This output
slew rate is far higher than specified, and probably
due to the lighter load used in the differential tests.
Slew Rate
FMAX =
2pVP (0.707)
(3)
AD = RF/RG
ΔdBc = 2 × (48 – 3) = 90dBc
Using this configuration suppresses the second
harmonics, leaving only third harmonic terms as the
limit to output SFDR. The much higher slew rate of
the inverting configuration also extends the full-power
bandwidth and the range of very low intermodulation
distortion over the performance bandwidth available
from the circuit of Figure 74. The Typical
Characteristics show that the circuit of Figure 75
operating at an AD = 10 can deliver a 16VPP signal
The single-tone distortion data shows approximately
72dB SFDR at 70MHz for a 2VPP output into this light
800Ω load. A modest post filter after the amplifier can
reduce these harmonics (second at 140MHz, third at
210MHz) to the point where the full SFDR to a
converter can be in the 85dB range for a 70MHz IF
operation.
This inverting input differential configuration is
particularly suited to very high SFDR converter
interfaces—specifically narrowband IF channels. The
Typical Characteristics show the two-tone, third-order
intermodulation intercept exceeding 45dBm through
90MHz. Although this data was taken with an 800Ω
load, the intercept model appears to work for this
circuit, simply treating the power level as if it were
into 50Ω. For example, at 70MHz, the differential
Typical Characteristic plots show a 48dBm intercept.
To predict the two-tone intermodulation SFDR,
assuming a –1dB below full-scale envelope to a 2VPP
maximum differential input converter, the test power
level would be 9dBm – 6dBm = 3dBm for each tone.
Putting this into the intercept equation, gives:
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DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA2695 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user’s guide. The summary
information for these fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA2695ID
SO-8
DEM-OPA-SO-2E
SBOU064
OPA2695IRGT
QFN-16
DEM-OPA-QFN-2C
SBOU061
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA2695 product folder.
resistor values on the inverting side of the circuit for a
current-feedback op amp can be treated as frequency
response compensation elements while the ratios set
the signal gain. Figure 76 shows the analysis circuit
for the OPA2695 small-signal frequency response.
The key elements of this current-feedback op amp
model are:
α → Buffer gain from the noninverting input to the
inverting input
RI → Buffer output impedance
iERR → Feedback error current signal
Z(S)
→
Frequency-dependent,
open-loop
transimpedance gain from iERR to VO
VI
a
VO
RI
MACROMODELS AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
practice is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the OPA2695 is available through
the TI web site (www.ti.com). This model does a good
job of predicting small-signal ac and transient
performance under a wide variety of operating
conditions. They do not do as well in predicting the
harmonic distortion or dG/dP characteristics. These
models do not attempt to distinguish between the
package types in the respective small-signal ac
performance, nor do they attempt to simulate
channel-to-channel coupling.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE
BANDWIDTH
A current-feedback op amp such as the OPA2695
can hold an almost constant bandwidth over signal
gain settings with the proper adjustment of the
external resistor values. This performance is shown in
the Typical Characteristics. The small-signal
bandwidth decreases only slightly with increasing
gain. These curves also show that the feedback
resistor has been changed for each gain setting. The
26
IERR
Z(S) IERR
RF
RG
Figure 76. Current-Feedback Transfer Function
Analysis Circuit
The buffer gain is typically very close to 1.00 and is
normally neglected from signal gain considerations. It
also, however, sets the CMRR for a single op amp
differential amplifier configuration. For the buffer gain
α < 1.0, the CMRR = –20 × log (1 – α).
RI, the buffer output impedance, is a critical portion of
the bandwidth control equation. For the OPA2695, it
is typically about 29Ω for ±5V operation and 32Ω for
single +5V operation.
A current-feedback op amp senses an error current in
the inverting node (as opposed to a differential input
error voltage for a voltage-feedback op amp) and
passes this current on to the output through an
internal frequency-dependent transimpedance gain.
The Typical Characteristics show this open-loop
transimpedance response. This response is
analogous to the open-loop voltage gain curve for a
voltage-feedback op amp.
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Where: NC = 1 + RF/RG = Noise Gain
This formula is written in a loop gain analysis format,
where the errors arising from a non-infinite open-loop
gain are shown in the denominator. If Z(S) were
infinite over all frequencies, the denominator of
Equation 5 would reduce to 1, and the ideal desired
signal gain shown in the numerator would be
achieved. The fraction in the denominator of
Equation 5 determines the frequency response and
also gives an expression for the loop gain:
Z(S)
= Loop Gain
RF + RI ´ NG
(6)
If 20 × log (RF + NG × RI) were superimposed on the
open-loop transimpedance plot, the difference
between the two would be the loop gain at a given
frequency. Eventually, Z(S) rolls off to equal the
denominator of Equation 6, at which point the loop
gain has reduced to 1 (and the curves have
intersected). This point of equality is where the
amplifier closed-loop frequency response given by
Equation 5 starts to roll off, and is exactly analogous
to the frequency at which the noise gain equals the
open-loop voltage gain for a voltage-feedback op
amp. The difference here is that the total impedance
in the denominator of Equation 6 may be controlled
separately from the desired signal gain (or NG).
The OPA2695 is internally compensated to give a
maximally flat frequency response for RF = 402Ω at
NG = 8 on ±5V supplies. Evaluating the denominator
of Equation 5 (the feedback transimpedance) gives
an optimal target of 663Ω. As the signal gain
changes, the contribution of the NG × RI term in the
feedback transimpedance changes, but the total can
be held constant by adjusting RF. Equation 7 gives an
approximate equation for optimum RF over signal
gain:
RF = 663W - NG ´ RI
(7)
As the desired signal gain increases, this equation
eventually predicts a negative RF. A somewhat
subjective limit to this adjustment can also be set by
holding RG to a minimum value of 10Ω. Lower values
load both the buffer stage at the input and the output
stage if RF goes too low, actually decreasing the
bandwidth. Figure 77 shows the recommended RF
versus NG for both ±5V and a single +5V operation.
The optimum target feedback impedance for +5V
operation used in Equation 5 is 604Ω, while the
typical buffer output impedance is 32Ω. The values
for RF versus gain shown here are approximately
equal to the values used to generate the Typical
Characteristic curves. In some cases, the values
used differ slightly from that shown here, in that the
values used in the Typical Characteristics are also
correcting for board parasitics not considered in the
simplified analysis leading to Equation 7. The values
shown in Figure 77 give a good starting point for
designs where bandwidth optimization is desired and
a flat frequency response is needed.
600
500
Feedback Resistor (W)
Developing the transfer function for the circuit of
Figure 79 gives Equation 5:
RF
a 1+
VO
RG
aNG
=
=
RF
VI
RF + RI ´ NG
RF + RI 1+
1+
RG
Z(S)
1+
Z(S)
(5)
VS = ±5V
400
VS = +5V
300
200
100
0
0
2
4
6
8
10
12
Noise Gain (V/V)
14
16
18
20
Figure 77. Recommended Feedback Resistor
versus Noise Gain
The total impedance presented to the inverting input
may be used to adjust the closed-loop signal
bandwidth. Inserting a series resistor between the
inverting input and the summing junction increases
the feedback impedance (denominator of Equation 6)
and decreases the bandwidth. The internal buffer
output impedance for the OPA2695 is slightly
influenced by the source impedance looking out of
the noninverting input terminal. High source resistors
have the effect of increasing RI and decreasing the
bandwidth. For those single-supply applications that
develop a midpoint bias at the noninverting input
through high-valued resistors, the decoupling
capacitor is essential for power-supply ripple
rejection, noninverting input noise current shunting,
and minimizing the high-frequency value for RI in
Figure 76.
OUTPUT CURRENT AND VOLTAGE
The OPA2695 provides output voltage and current
capabilities that are consistent with driving
doubly-terminated 50Ω lines. For a 100Ω load at a
gain of +8V/V (see Figure 68), the total load is the
parallel combination of the 100Ω load and the 458Ω
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total feedback network impedance. This 82Ω load
requires no more than 45mA output current to
support the ±3.7V minimum output voltage swing
specified for 100Ω loads. This minimal requirement is
well below the minimum ±90mA specifications.
The specifications described above, though familiar in
the industry, consider voltage and current limits
separately. In many applications, it is the voltage ×
current, or V-I, product that is more relevant to circuit
operation. Refer to the Output Voltage and Current
Limitations plot (Figure 21) in the Typical
Characteristics. The X- and Y-axes of this graph
show the zero-voltage output current limit and the
zero-current output voltage limit, respectively. The
four quadrants provide a more detailed view of the
OPA2695 output drive capabilities. Superimposing
resistor load lines onto the plot shows the available
output voltage and current for specific loads.
The minimum specified output voltage and current
overtemperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup do
the output current and voltage decrease to the
numbers shown in the specification tables. As the
output transistors deliver power, the junction
temperatures increase, decreasing the VBEs
(increasing the available output voltage swing) and
increasing the current gains (increasing the available
output current). In steady-state operation, the
available output voltage and current always are
greater than that shown in the over-temperature
specifications, because the output stage junction
temperatures are greater than the minimum specified
operating ambient.
To maintain maximum output stage linearity, no
output shortcircuit protection is provided. This lack of
protection is normally a problem, because most
applications include a series-matching resistor at the
output that limits the internal power dissipation if the
output side of this resistor is shorted to ground.
However, shorting the output pin directly to the
adjacent positive power-supply pin does, in most
cases, destroy the amplifier. If additional short-circuit
protection is required, consider a small series resistor
in the power-supply leads. Under heavy output loads,
this additional resistor reduces the available output
voltage swing. A 5Ω series resistor in each
power-supply lead limits the internal power
dissipation to less than 1W for an output short circuit
while decreasing the available output voltage swing
only 0.25V for up to 50mA desired load currents.
Always place the 0.1µF power-supply decoupling
capacitors directly on the supply pins after these
supply current-limiting resistors.
28
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance that
may be recommended to improve analog-to-digital
linearity. A high-speed, high open-loop gain amplifier
such as the OPA2695 can be very susceptible to
decreased stability and closed-loop response peaking
when a capacitive load is placed directly on the
output pin. When the amplifier open-loop output
resistance is considered, this capacitive load
introduces an additional pole in the signal path that
can decrease the phase margin. Several external
solutions to this problem have been suggested. When
the primary considerations are frequency response
flatness, pulse response fidelity, and/or distortion, the
simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a
series isolation resistor between the amplifier output
and the capacitive load. This isolation resistor does
not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency.
The additional zero acts to cancel the phase lag from
the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Characteristics show the recommended
RS versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads
greater than 2pF can begin to degrade the
performance of the OPA2695. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully and add the
recommended series resistor as close as possible to
the OPA2695 output pin (see the Board Layout
Guidelines section).
DISTORTION PERFORMANCE
The OPA2695 provides good distortion performance
into a 100Ω load on ±5V supplies. Relative to
alternative solutions, the OPA2695 holds much lower
distortion at higher frequencies (> 20MHz). Generally,
until the fundamental signal reaches very high
frequency or power levels, the 2nd harmonic will
dominate the distortion with a negligible 3rd-harmonic
component. Focusing then on the 2nd harmonic,
increasing the load impedance improves distortion
directly. Remember that the total load includes the
feedback network. In the noninverting configuration
(Figure 68), this value is the sum of RF + RG, while in
the inverting configuration, it is only RF. Also,
providing an additional supply decoupling capacitor
(0.01µF) between the supply pins (for bipolar
operation) improves the 2nd-order distortion slightly
(3dB to 6dB).
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In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the 2nd harmonic increasing at
a little less than the expected 2x rate, while the 3rd
harmonic increases at a little less than the expected
3x rate. Where the test power doubles, the difference
between it and the 2nd harmonic decreases less than
the expected 6dB, while the difference between it and
the 3rd decreases by less than the expected 12dB.
The OPA2695 has extremely low third-order
harmonic distortion. This also gives a high two-tone,
third-order intermodulation intercept, as shown in the
Typical Characteristics. This intercept curve is
defined at the 50Ω load when driven through a 50Ω
matching resistor to allow direct comparisons to RF
MMIC devices and is shown for both gains of ±8V/V.
There is a slight improvement in third-order intercept
by operating the OPA2695 in the inverting mode. The
output matching resistor attenuates the voltage swing
from the output pin to the load by 6dB. If the
OPA2695 drives directly into the input of a high
impedance device, such as an ADC, this 6dB
attenuation is not taken. Under these conditions, the
intercept increases by a minimum of 6dBm.
The third-order intercept is used to predict the
intermodulation products for two closely-spaced
frequencies. If the two test frequencies, F1 and F2,
are specified in terms of average and delta
frequency, FO = (F1 + F2)/2 and ΔF = |F2 – F1|/2, the
two third-order, close-in spurious tones appear at
FO ±3 × ΔF. The difference between two equal
test-tone power levels and these intermodulation
spurious power levels is given by ΔdBc = 2 × (OP3 –
PO), where OP3 is the intercept taken from the
Typical Characteristic curves (see Figure 14,
Figure 44, Figure 56, and Figure 60) and PO is the
power level in dBm at the 50Ω load for one of the two
closely-spaced test frequencies. For example, at
50MHz, gain of –8V/V, the OPA2695 has an intercept
of 32dBm at a matched 50Ω load. If the full envelope
of the two frequencies must be 2VPP, each tone must
be 4dBm. The third-order intermodulation spurious
tones are then 2 × (32 – 4) = 56dBc below the
test-tone power level (–52dBm). If this same 2VPP
two-tone envelope were delivered directly into the
input of an ADC without the matching loss or the
loading of the 50Ω network, the intercept would
increase to at least 38dBm. With the same signal and
gain conditions, but now driving directly into a light
load, the third-order spurious tones are then at least 2
× (38 – 4) = 68dBc below the 4dBm test-tone power
levels centered on 50MHz. Tests have shown that, in
reality, the third-order spurious levels are much lower
as a result of the lighter loading presented by most
ADCs.
NOISE PERFORMANCE
The OPA2695 offers an excellent balance between
voltage and current noise terms to achieve low output
noise. The inverting current noise (22pA/√Hz) is lower
than most other current-feedback op amps while the
input voltage noise (1.8nV/√Hz) is lower than any
unity-gain stable, wideband, voltage-feedback op
amp. This low-input voltage noise was achieved at
the price of a higher noninverting input current noise
(18pA/√Hz). As long as the ac source impedance
looking out of the noninverting node is less than 50Ω,
this current noise does not contribute significantly to
the total output noise. The op amp input voltage noise
and the two input current noise terms combine to give
low output noise under a wide variety of operating
conditions. Figure 78 shows the op amp noise
analysis model with all the noise terms included. In
this model, all noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
ENI
1/2
OPA2695
RS
EO
IBN
ERS
RF
Ö 4kTRS
4kT
RG
RG
Ö 4kTRF
IBI
4kT = 1.6E - 20J
at 290°K
Figure 78. Op Amp Noise Analysis Model
The total output spot-noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 8 shows the
general form for the output noise voltage using the
terms shown in Figure 78.
EO =
Ö(
ENI2 + (IBNRS)2 + 4kTRS ) GN2 + (IBIRF)2 + 4kTRFGN
(8)
Dividing this expression by the noise gain (NG = (1 +
RF/RG)) gives the equivalent input-referred spot-noise
voltage at the noninverting input as shown in
Equation 9:
EO =
Ö
ENI2 + (IBNRS)2 + 4kTRS +
( INGR ) + 4kTR
NG
BI
F
2
F
(9)
Evaluating these two equations for the OPA2695
circuit and component values shown in Figure 68
gives a total output spot-noise voltage of 18.7nV/√Hz
and a total equivalent input spot-noise voltage of
2.3nV/√Hz. This total input-referred spot-noise
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voltage is higher than the 1.8nV/√Hz specification for
the op amp voltage noise alone. This increased value
reflects the noise added to the output by the inverting
current noise times the feedback resistor. If the
feedback resistor is reduced in high-gain
configurations (as suggested previously), the total
input-referred voltage noise given by Equation 9
approaches the 1.8nV/√Hz of the op amp itself. For
example, going to a gain of +20 (using RF = 200Ω)
gives a total input-referred noise of 2.0nV/√Hz.
signal isolation is not ensured. Using this feature to
multiplex two or more outputs together is not
recommended. Large signals applied to the shutdown
output stages can turn on parasitic devices,
degrading signal linearity for the desired channel.
For a more complete discussion of op amp noise
calculation, see TI Application Note, SBOA066, Noise
Analysis for High Speed Op Amps, available through
the TI web site at www.ti.com.
To shut down, the control pin must be asserted low.
This logic control is referenced to the positive supply,
as shown in the simplified circuit of Figure 79.
Turn-on time is very quick from the shutdown
condition, typically less than 60ns. Turn-off time
strongly depends on the external circuit configuration,
but is typically 200ns for the circuit of Figure 68.
+VS
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp such as the OPA2695
provides exceptional bandwidth in high gains, giving
fast pulse settling but only moderate dc accuracy.
The typical specifications show an input offset voltage
comparable
to
high-speed
voltage-feedback
amplifiers; however, the two input bias currents are
somewhat higher and are unmatched. Although bias
current cancellation techniques are very effective with
most voltage-feedback op amps, they do not
generally reduce the output dc offset for wideband
current-feedback op amps. Because the two input
bias currents are unrelated in both magnitude and
polarity, matching the source impedance looking out
of each input to reduce the respective error
contribution to the output is ineffective. Evaluating the
configuration of Figure 80, using a worst-case +25°C
input offset voltage and the two input bias currents,
gives a worst-case output offset range equal to:
±(NG × VOS) + (IBN ×RS/2 × NG) ± (IBI × RF)
where NG = noninverting signal gain.
= ±(8 × 3.5mV) ± (30µA × 25Ω × 8) ± (402Ω ×
60µA)
= ±28mV ± 8mV ± 24mV
= ±60mV
A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most simple adjustment techniques do
not correct for temperature drift.
POWER SHUTDOWN OPERATION
(QFN-16 Package Only)
The OPA2695IRGT provides an optional power
shutdown feature that can be used to reduce system
power. If the VDIS control pin is left unconnected, the
OPA2695IRGT operates normally. This shutdown is
intended only as a power-saving feature. Forward
path isolation is very good for small signals. Large
30
8kW
Q1
120kW
17kW
VDIS
IS
Control
-VS
Figure 79. Simplified Shutdown Circuit
In normal operation, base current to Q1 is provided
through the 120kΩ resistor, while the emitter current
through the 8kΩ resistor sets up a voltage drop that is
inadequate to turn on the two diodes in the Q1
emitter. As VDIS is pulled low, additional current is
pulled through the 8kΩ resistor, eventually turning on
these two diodes (≈ 180µA). At this point, any further
current pulled out of VDIS goes through those diodes
holding the emitter-base voltage of Q1 at
approximately 0V. This limitation shuts off the
collector current out of Q1, turning the amplifier off.
The supply current in the shutdown mode is only that
required to operate the circuit of Figure 79.
When disabled, the output and input nodes go to a
high-impedance state. If the OPA2695IRGT is
operating in a gain of +1V/V, this configuration shows
a very high impedance (3pF || 1MΩ) at the output and
exceptional signal isolation. If operating at a gain
greater than +1V/V, the total feedback network
resistance (RF + RG) appears as the impedance
looking back into the output, but the circuit continues
to show very high forward and reverse isolation. If
configured as an inverting amplifier, the input and
output are connected through the feedback network
resistance (RF + RG), giving relatively poor input to
output isolation.
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THERMAL ANALYSIS
The OPA2695 does not require external heatsinking
for most applications. Maximum desired junction
temperature sets the maximum allowed internal
power dissipation as described below. In no case
should the maximum junction temperature be allowed
to exceed +150°C.
Operating junction temperature (TJ) is given by TA +
PD × θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load. However, for a grounded resistive
load, PDL would be at a maximum when the output is
fixed at a voltage equal to one-half of either supply
voltage (for equal bipolar supplies). Under this
condition, PDL = VS2/(4 × RL), where RL includes
feedback network loading.
Note that it is the power in the output stage and not
into the load that determines internal power
dissipation.
As an absolute worst-case example, compute the
maximum TJ using an OPA2695ID (SO package) in
the circuit of Figure 68 operating at the maximum
specified ambient temperature of +85°C and driving a
grounded 100Ω load.
PD = 10V ´ 28.6mA + 52/(4 ´ (100W || 458W)) = 362mW
(10)
Maximum TJ = +85°C + (0.36W ´ 100°C/W) = 121°C
(11)
A similar calculation for the device in a QFN package
(OPA2695RGT) with a PowerPAD™ thermal
connection results in an estimated junction
temperature TJ = +105°C. These maximum operating
junction temperatures are well below most system
level targets. Most applications are lower because an
absolute worst-case output stage power was
assumed in this calculation.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier such as the OPA2695
requires careful attention to board layout parasitics
and external component types. Recommendations
that will optimize performance include:
a) Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability; on the noninverting input, it can
react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b) Minimize the distance (< 0.25", or 0.635cm)
from the power-supply pins to high-frequency
0.1µF decoupling capacitors. At the device pins,
the ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. An optional
supply-decoupling capacitor across the two power
supplies
(for
bipolar
operation)
improves
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at a lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components
preserves
the
high-frequency
performance of the OPA2695. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep the leads and PCB trace length as short
as possible. Never use wirewound-type resistors in a
high frequency application. Because the output pin
and inverting input pin are the most sensitive to
parasitic capacitance, always position the feedback
and series output resistor, if any, as close as possible
to the output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Where double-sided
component mounting is allowed, place the feedback
resistor directly under the package on the other side
of the board between the output and inverting input
pins. The frequency response is primarily determined
by the feedback resistor value, as described
previously. Increasing its value reduces the
bandwidth, while decreasing it gives a more peaked
frequency response. The 402Ω feedback resistor
(used in the Typical Characteristics at a gain of +8 on
±5V supplies) is a good starting point for design. Note
that a 523Ω feedback resistor, rather than a direct
short, is required for the unity gain follower
application. A current-feedback op amp requires a
feedback resistor—even in the unity gain follower
configuration—to control stability.
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
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wide traces (50mils to 100mils or 1.27mm to 2.54mm,
respectively) should be used, preferably with ground
and power planes opened up around them. Estimate
the total capacitive load and set RS from the plot of
Recommended RS vs Capacitive Load (Figure 17,
Figure 37, Figure 61, and Figure 51). Low parasitic
capacitive loads (< 5pF) may not need an RS since
the OPA2695 is nominally compensated to operate
with a 2pF parasitic load. If a long trace is required,
and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is usually not
necessary on board. In fact, a higher impedance
environment does improve distortion, as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined (based on board
material and trace dimensions), a matching series
resistor into the trace from the output of the OPA2695
is used. A terminating shunt resistor at the input of
the destination device is used as well. Remember
also that the terminating impedance is the parallel
combination of the shunt resistor and the input
impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. The high output voltage and current
capability of the OPA2695 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If
the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the
series resistor value as shown in the plot of RS
versus capacitive load. If the input impedance of the
destination device is low, there will be some signal
attenuation because of the voltage divider formed by
the series output into the terminating impedance.
32
e) Socketing a high-speed part such as the
OPA2695 is not recommended. The additional lead
length and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome parasitic
network that can make it almost impossible to
achieve a smooth, stable frequency response. Best
results are obtained by soldering the OPA2695
directly onto the board.
INPUT AND ESD PROTECTION
The OPA2695 is built using a very high-speed,
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table
where an absolute maximum ±6.5V supply is
reported. All device pins have limited ESD protection
using internal diodes to the power supplies, as shown
in Figure 80.
These diodes also provide moderate protection to
input overdrive voltages above the supplies. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA2695), current-limiting
series resistors should be added into the two inputs.
Keep these resistor values as low as possible
because high values degrade both noise performance
and frequency response.
+VCC
Internal
Circuitry
External
Pin
-VCC
Figure 80. Internal ESD Protection
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Revision History
Changes from Original (April 2008) to Revision A .......................................................................................................... Page
•
•
Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C ................................................................................................................................................................................... 2
Changed ordering number for OPA2695IRGT in Table 1 ................................................................................................... 26
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2695ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP2695
OPA2695IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP2695
OPA2695IRGTR
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2695
OPA2695IRGTRG4
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2695
OPA2695IRGTT
ACTIVE
VQFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2695
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2695IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2695IRGTR
VQFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2695IRGTT
VQFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2695IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2695IRGTR
VQFN
RGT
16
3000
367.0
367.0
35.0
OPA2695IRGTT
VQFN
RGT
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016A
VQFN - 1 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1.45 0.1
(0.2) TYP
5
12X 0.5
8
EXPOSED
THERMAL PAD
4
9
4X
1.5
SYMM
17
1
12
16X
PIN 1 ID
(OPTIONAL)
13
16
0.1
0.05
SYMM
16X
0.30
0.18
C A B
0.5
0.3
4219032/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.45)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
17
(0.475)
TYP
(2.8)
12X (0.5)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.475) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219032/A 02/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.34)
13
16
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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