Texas Instruments | Dual, Low-Power, High-Speed, Fixed-Gain Operational Amplifier (Rev. C) | Datasheet | Texas Instruments Dual, Low-Power, High-Speed, Fixed-Gain Operational Amplifier (Rev. C) Datasheet

Texas Instruments Dual, Low-Power, High-Speed, Fixed-Gain Operational Amplifier (Rev. C) Datasheet
OPA2832
www.ti.com ............................................................................................................................................. SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008
Dual, Low-Power, High-Speed, Fixed-Gain Operational Amplifier
FEATURES
Using complementary common-emitter outputs
provides an output swing to within 30mV of ground
and 60mV of the positive supply. The high output
drive current and low differential gain and phase
errors also make it ideal for single-supply consumer
video products.
1
• HIGH BANDWIDTH: 75MHz (G = +2)
• LOW SUPPLY CURRENT: 7.8mA (VS = +5V)
• FLEXIBLE SUPPLY RANGE:
±1.5V to ±5.5V Dual Supply
+3V to +11V Single Supply
• INPUT RANGE INCLUDES GROUND ON
SINGLE SUPPLY
• 4.9VPP OUTPUT SWING ON +5V SUPPLY
• HIGH SLEW RATE: 350V/µs
• LOW INPUT VOLTAGE NOISE: 9.3nV/√Hz
2
Low distortion operation is ensured by high bandwidth
product (75MHz) and slew rate (350V/µs), making the
OPA2832 an ideal input buffer stage to 3V and 5V
CMOS converters. Unlike earlier low-power,
single-supply amplifiers, distortion performance
improves as the signal swing is decreased. A low
9.3nV/√Hz input voltage noise supports wide dynamic
range operation.
APPLICATIONS
•
•
•
•
The OPA2832 is available in an industry-standard
SO-8 package or a small MSOP-8 package. For
gains other than +1, –1, or +2, consider the
OPA2830.
SINGLE-SUPPLY VIDEO LINE DRIVERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
PORTABLE CONSUMER ELECTRONICS
RELATED PRODUCTS
DESCRIPTION
DESCRIPTION
The OPA2832 is a dual, low-power, high-speed,
fixed-gain amplifier designed to operate on a single
+3V to +11V supply. Operation on ±1.5V to ±5.5V
supplies is also supported. The input range extends
below ground and to within 1.7V of the positive
supply.
SINGLES
DUALS
TRIPLES
QUADS
Rail-to-Rail Output
OPA830
OPA2830
—
OPA4830
Rail-to-Rail Fixed-Gain
OPA832
—
OPA3832
—
General-Purpose
(1800V/µs slew rate)
OPA690
OPA2690
OPA3690
—
Low-Noise,
High DC Precision
OPA820
OPA2822
—
OPA4820
150pF
+5V
0.1µF
238Ω
506Ω
1/2
OPA2832
+5V
238Ω
5kΩ
VI
100pF
400Ω
400Ω
400Ω
400Ω
VI
2.5V
VO
BUF602
0.1µF
0.1µF
5kΩ
238Ω
238Ω
100pF
1/2
OPA2832
506Ω
150pF
Single-Supply, 3rd-Order, Differential Chebyshev Low-Pass Filter
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
OPA2832
SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008 ............................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA2832
SO-8 Surface-Mount
D
–40°C to +85°C
OPA2832
OPA2832
MSOP-8
DGK
–40°C to +85°C
A61
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA2832ID
Rails, 100
OPA2832IDR
Tape and Reel, 2500
OPA2832IDGK
Tape and Reel, 250
OPA2832IDGKR
Tape and Reel, 2500
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Power Supply
11VDC
Internal Power Dissipation
See Thermal Characteristics
Differential Input Voltage (2)
±1.2V
Input Voltage Range
–0.5V to ±VS + 0.3V
Storage Voltage Range: D, DGK
–65°C to +125°C
Lead Temperature (soldering, 10s)
+300°C
Junction Temperature (TJ)
+150°C
ESD Rating:
Human Body Model (HBM)
2000V
Charge Device Model (CDM)
1000V
Machine Model (MM)
(1)
(2)
200V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Noninverting input to internal inverting mode.
Top View
SO, MSOP
Output
1
−Input 1
1
400Ω
2
400Ω
8
+VS
7
Output 2
6
−Input
2
5
+Input
2
400Ω
+Input
2
1
3
−VS
4
400Ω
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Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2832
OPA2832
www.ti.com ............................................................................................................................................. SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted (see Figure 63).
OPA2832ID, IDGK
PARAMETER
UNITS
MIN/
MAX
TEST
LEVEL (3)
MHz
typ
V
54
MHz
min
B
55
MHz
min
B
dB
typ
C
V/µs
min
B
ns
max
B
6.0
ns
max
B
65
66
ns
max
B
–60
–58
–58
dBc
max
B
–63
–61
–61
dBc
max
B
–57
–50
–49
–48
dBc
max
B
RL = 500Ω
–73
–64
–60
–57
dBc
max
B
f > 1MHz
9.2
nV/√Hz
typ
C
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
CONDITIONS
+25°C
G = +1, VO ≤ 0.5VPP
250
G = +2, VO ≤ 0.5VPP
70
55
54
G = –1, VO ≤ 0.5VPP
85
57
56
VO ≤ 0.5VPP
6
Slew Rate
G = +2, 2V Step
300
220
210
200
Rise Time
0.5V Step
5.6
5.8
6.0
6.0
Fall Time
0.5V Step
5.6
5.8
6.0
Settling Time to 0.1%
G = +2, 1V Step
45
63
Harmonic Distortion
VO = 2VPP, 5MHz
RL = 150Ω
–64
RL = 500Ω
–66
RL = 150Ω
AC PERFORMANCE (see Figure 63)
Small-Signal Bandwidth
Peaking at a Gain of +1
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Input Current Noise
f > 1MHz
2.2
pA/√Hz
typ
C
NTSC Differential Gain
RL = 150Ω
0.10
%
typ
C
NTSC Differential Phase
RL = 150Ω
0.16
°
typ
C
G = +2
±0.3
±1.5
±1.6
±1.7
%
min
A
G = –1
±0.2
±1.5
±1.6
±1.7
%
max
B
Maximum
400
455
460
462
Ω
max
A
Minimum
400
345
340
338
Ω
max
A
±0.1
±0.1
%/°C
max
B
±8.7
±9.3
mV
max
A
±27
±27
µV/°C
max
B
+12
+13
µA
max
A
±45
±45
nA/°C
max
B
±2
±2.5
µA
max
A
±10
±10
nA/°C
max
B
DC PERFORMANCE (4)
Gain Error
Internal RF and RG
Average Drift
Input Offset Voltage
±1.4
Average Offset Voltage Drift
±7.5
—
Input Bias Current
+5.5
Input Bias Current Drift
+10
—
Input Offset Current
±0.1
Input Offset Current Drift
±1.5
—
INPUT
Negative Input Voltage Range
–5.4
–5.2
–5.0
–4.9
V
max
B
Positive Input Voltage Range
3.2
3.1
3.0
2.9
V
min
B
Input Impedance
Differential Mode
10 || 2.1
kΩ || pF
typ
C
Common-Mode
400 || 1.2
kΩ || pF
typ
C
OUTPUT
Output Voltage Swing
RL = 1kΩ to GND
±4.9
±4.8
±4.75
±4.75
V
max
A
RL = 150Ω to GND
±4.6
±4.5
±4.45
±4.4
V
max
A
±82
±63
±58
±53
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
Output Shorted to Either Supply
120
mA
typ
C
G = +2, f ≤ 100kHz
0.2
Ω
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of node.
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Product Folder Link(s): OPA2832
3
OPA2832
SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008 ............................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted (see Figure 63).
OPA2832ID, IDGK
PARAMETER
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
V
min
B
POWER SUPPLY
Minimum Operating Voltage
±1.4
Maximum Operating Voltage
—
±5.5
±5.5
±5.5
V
max
A
Maximum Quiescent Current
VS = ±5V
8.5
9.5
10.7
11.9
mA
max
A
Minimum Quiescent Current
VS = ±5V
8.5
8.0
7.2
6.6
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDGK
Thermal Resistance
D
SO-8
125
°C/W
typ
C
DGK
MSOP-8
150
°C/W
typ
C
4
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Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2832
OPA2832
www.ti.com ............................................................................................................................................. SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 61).
OPA2832ID, IDGK
PARAMETER
UNITS
MIN/
MAX
TEST
LEVEL (3)
MHz
typ
C
55
MHz
min
B
58
MHz
min
B
dB
typ
C
V/µs
min
B
ns
max
B
5.9
ns
max
B
66
67
ns
max
B
–56
–54
–53
dBc
max
B
–59
–57
–57
dBc
max
B
–56
–50
–49
–47
dBc
max
B
RL = 500Ω
–72
–65
–62
–58
dBc
max
B
f > 1MHz
9.3
nV/√Hz
typ
C
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
CONDITIONS
+25°C
G = +1, VO ≤ 0.5VPP
210
G = +2, VO ≤ 0.5VPP
75
56
55
G = –1, VO ≤ 0.5VPP
95
60
58
VO ≤ 0.5VPP
7
Slew Rate
G = +2, 2V Step
320
230
220
220
Rise Time
0.5V Step
4.8
5.8
5.8
5.9
Fall Time
0.5V Step
4.8
5.8
5.8
Settling Time to 0.1%
G = +2, 1V Step
46
64
Harmonic Distortion
VO = 2VPP, 5MHz
RL = 150Ω
–59
RL = 500Ω
–62
RL = 150Ω
AC PERFORMANCE (see Figure 61)
Small-Signal Bandwidth
Peaking at a Gain of +1
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Input Current Noise
f > 1MHz
2.3
pA/√Hz
typ
C
NTSC Differential Gain
RL = 150Ω
0.11
%
typ
C
NTSC Differential Phase
RL = 150Ω
0.14
°
typ
C
G = +2
±0.3
±1.5
±1.6
±1.7
%
min
A
G = –1
±0.2
±1.5
±1.6
±1.7
%
max
B
400
455
460
462
Ω
max
A
400
345
DC PERFORMANCE (4)
Gain Error
Internal RF and RG, Maximum
Minimum
Average Drift
Input Offset Voltage
±1.5
Average Offset Voltage Drift
Input Bias Current
—
VCM = 2.0V
Input Bias Current Drift
Input Offset Current
±6
+5.5
+10
—
VCM = 2.0V
Input Offset Current Drift
±0.1
±1.5
—
340
338
Ω
max
A
±0.1
±0.1
%/°C
max
B
±7
±7.5
mV
max
A
±20
±20
µV/°C
max
B
+12
+13
µA
max
A
±45
±45
nA/°C
max
B
±2
±2.5
µA
max
A
±10
±10
nA/°C
max
B
B
INPUT
Least Positive Input Voltage
–0.5
–0.2
0
+0.1
V
max
Most Positive Input Voltage
3.3
3.2
3.1
3.0
V
min
B
Input Impedance, Differential Mode
10 || 2.1
kΩ || pF
typ
C
Common-Mode
400 || 1.2
kΩ || pF
typ
C
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
RL = 1kΩ to 2.0V
0.03
0.16
0.18
0.20
V
max
A
RL = 150Ω to 2.0V
0.18
0.3
0.35
0.40
V
max
A
RL = 1kΩ to 2.0V
4.94
4.8
4.6
4.4
V
min
A
RL = 150Ω to 2.0V
4.86
4.6
4.5
4.4
V
min
A
±75
±58
±53
±50
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Output Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
Output Shorted to Either Supply
100
mA
typ
C
G = +2, f ≤ 100kHz
0.2
Ω
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of node.
Submit Documentation Feedback
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2832
5
OPA2832
SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008 ............................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 61).
OPA2832ID, IDGK
PARAMETER
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
V
typ
C
POWER SUPPLY
Minimum Operating Voltage
+2.8
Maximum Operating Voltage
—
+11
+11
+11
V
max
A
Maximum Quiescent Current
VS = +5V
7.8
8.4
9.8
11.2
mA
max
A
Minimum Quiescent Current
VS = +5V
7.8
7.4
7.0
6.4
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDGK
Thermal Resistance
D
SO-8
125
°C/W
typ
C
DGK
MSOP-8
150
°C/W
typ
C
6
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Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2832
OPA2832
www.ti.com ............................................................................................................................................. SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = +3.3V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 62).
OPA2832ID, IDGK
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.5VPP
180
+25°C (1)
0°C to
+70°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
MHz
typ
C
B
AC PERFORMANCE (see Figure 62)
Small-Signal Bandwidth
G = +2, VO ≤ 0.5VPP
85
59
57
MHz
min
G = –1, VO ≤ 0.5VPP
100
63
61
MHz
min
B
VO ≤ 0.5VPP
8
dB
typ
C
Slew Rate
1V Step
130
110
100
V/µs
min
B
Rise Time
0.5V Step
4.6
5.6
5.7
ns
max
B
Fall Time
0.5V Step
4.6
5.6
5.7
ns
max
B
1V Step
48
70
80
ns
max
B
RL = 150Ω
–71
–64
–61
dBc
max
B
RL = 500Ω
–74
–70
–64
dBc
max
B
RL = 150Ω
–66
–60
–55
dBc
max
B
RL = 500Ω
–69
–66
–62
dBc
max
B
Input Voltage Noise
f > 1MHz
9.4
nV/√Hz
typ
C
Input Current Noise
f > 1MHz
2.4
pA/√Hz
typ
C
G = +2
±0.3
±1.5
±1.6
%
min
A
G = –1
±0.2
±1.5
±1.6
%
max
B
Maximum
400
455
460
Ω
max
A
Minimum
400
345
340
Ω
max
A
±0.1
%/°C
max
B
±1.4
±7.5
±8.7
mV
max
A
±27
µV/°C
max
B
+12
µA
max
A
±45
nA/°C
max
B
±2
µA
max
A
±10
nA/°C
max
B
Peaking at a Gain of +1
Settling Time to 0.1%
Harmonic Distortion
5MHz
2nd-Harmonic
3rd-Harmonic
DC PERFORMANCE (4)
Gain Error
Internal RF and RG
Average Drift
Input Offset Voltage
Average Offset Voltage Drift
—
Input Bias Current
VCM = 0.75V
Input Bias Current Drift
+5.5
+10
—
Input Offset Current
VCM = 0.75V
Input Offset Current Drift
±0.1
±1.5
—
INPUT
Least Positive Input Voltage
–0.5
–0.3
–0.2
V
max
B
Most Positive Input Voltage
1.5
1.4
1.3
V
min
B
Input Impedance
Differential Mode
10 || 2.1
kΩ || pF
typ
C
Common-Mode
400 || 1.2
kΩ || pF
typ
C
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
RL = 1kΩ to 0.75V
0.03
0.16
0.18
V
max
B
RL = 150Ω to 0.75V
0.1
0.3
0.35
V
max
B
RL = 1kΩ to 0.75V
3
2.8
2.6
V
min
B
RL = 150Ω to 0.75V
3
2.8
2.6
V
min
B
±35
±25
±20
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Output Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
Output Shorted to Either Supply
80
mA
typ
C
See Figure 2, f < 100kHz
0.2
Ω
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of node.
Submit Documentation Feedback
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2832
7
OPA2832
SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008 ............................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +3.3V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 62).
OPA2832ID, IDGK
PARAMETER
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
V
typ
C
POWER SUPPLY
Minimum Operating Voltage
+2.8
Maximum Operating Voltage
–
+11
+11
V
max
A
Maximum Quiescent Current
VS = +3.3V
7.6
8.1
9.5
mA
max
A
Minimum Quiescent Current
VS = +3.3V
7.6
6.8
6.2
mA
min
A
Input-Referred
60
dB
typ
C
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDGK
Thermal Resistance
D
SO-8
125
°C/W
typ
C
DGK
MSOP-8
150
°C/W
typ
C
8
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TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted (see Figure 63).
SMALL-SIGNAL FREQUENCY RESPONSE
3
VO = 0.2VPP
RL = 150Ω
0
Normalized Gain (dB)
0
Normalized Gain (dB)
LARGE-SIGNAL FREQUENCY RESPONSE
3
G = −1
−3
−6
−9
G = +2
−6
VO = 1VPP
−9
−12
−12
−15
−15
1
10
100
VO = 0.5VPP
−3
500
1
10
Figure 1.
Figure 2.
LARGE-SIGNAL PULSE RESPONSE
Output Voltage (500mV/div)
G = +2V/V
RL = 150Ω
VO = 0.2VPP
See Figure 63
0
−50
−100
G = +2V/V
RL = 150Ω
VO = 2VPP
See Figure 63
1.0
0.5
0
−0.5
−1.0
−1.5
−150
Time (10ns/div)
Time (10ns/div)
Figure 3.
Figure 4.
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
REQUIRED RS vs CAPACITIVE LOAD
1dB Peaking Targeted
35
30
RS (Ω)
25
20
15
10
5
0
10
400
1.5
50
40
100
Frequency (MHz)
SMALL-SIGNAL PULSE RESPONSE
Output Voltage (50mV/div)
VO = 4VPP
Frequency (MHz)
150
100
VO = 2VPP
G = +2V/V
RL = 150Ω
See Figure 63
100
1k
3
CL = 10pF
0
−3
CL = 1000pF
−6
C L = 100pF
−9
VI
1 /2
RS
O P A28 3 2
1kΩ(1)
CL
−12
NOTE: (1) 1kΩis optional.
−15
1
10
100
Capacitive Load (pF)
Frequency (MHz)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted (see Figure 63).
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−50
−50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−40
−60
2nd−Harmonic
−70
G = +2V/V
VO = 2VPP
f = 5MHz
See Figure 63
−80
−90
3rd−Harmonic
3rd−Harmonic
−80
2nd−Harmonic
−90
0
1
7
8
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
9
10
−40
G = +2V/V
RL = 500Ω
VO = 2VPP
See Figure 63
2nd−Harmonic
3rd−Harmonic
−110
−45
PI
1/ 2
O P A 283 2
50Ω
−50
PO
500Ω
400Ω
−55
400Ω
−60
−65
−70
20MHz
−75
10MHz
−80
5MHz
−85
−90
0.1
1
10
−26
20
4
Current Lim it
One Channel
Only
RL = 500Ω
RL = 50Ω
RL = 100Ω
0
−1
−2
−3
Output
1W Internal
Current Limit
P ower Limit
−120
−80
−6
−2
−40
0
40
80
120
160
2
6
OUTPUT SWING vs LOAD RESISTANCE
5
Maximum Output Voltage (V)
Power Lim it
−6
−160
−10
Figure 10.
4
−4
−14
Figure 9.
Output
2
1
−18
Single−Tone Load Power (2dBm/div)
1W Internal
3
−22
Frequency (MHz)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
VO (V)
6
HARMONIC DISTORTION vs FREQUENCY
−100
10
5
Figure 8.
−90
−5
4
Figure 7.
−80
5
3
Output Swing (VPP)
−70
6
2
Load Resistance (Ω)
3rd−Order Spurious Level (dBc)
Harmonic Distortion (dBc)
−70
1k
−40
−60
−60
−100
100
−50
G = +2V/V
RL = 500Ω
f = 5MHz
See Figure 63
G = +2V/V
VS = ±5V
3
2
1
0
−1
−2
−3
−4
−5
10
100
IO (mA)
RL (Ω )
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: VS = ±5V (Differential)
At TA = +25°C, Differential Gain = +2V/V, and RL = 500Ω, unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
SMALL-SIGNAL FREQUENCY RESPONSE
9
+5V
GD = +2V/V
RL = 500Ω
VO = 0.2VPP
6
1 /2
O PA 28 32
3
Gain (dB)
400Ω
400Ω
RL
VI
400Ω
VO
0
−3
400Ω
−6
1 /2
O PA 28 32
−9
1
10
−5V
Figure 13.
LARGE-SIGNAL FREQUENCY RESPONSE
HARMONIC DISTORTION vs FREQUENCY
6
−70
Harmonic Distortion (dBc)
−60
Gain (dB)
3
0
−3
GD = +2V/V
RL = 500Ω
VO = 4VPP
−9
10
100
2nd−Harmonic
−90
3rd−Harmonic
−100
−110
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Figure 15.
Figure 16.
HARMONIC DISTORTION vs OUTPUT SWING
−75
GD = +2V/V
RL = 500Ω
f = 1MHz
−90
2nd−Harmonic
−95
−100
3rd−Harmonic
100
HARMONIC DISTORTION vs LOAD RESISTANCE
−80
Harmonic Distortion (dBc)
Harmonic Distortion (dB)
−80
300
−80
−105
G D = +2V/V
R L = 500Ω
VO = 2VPP
−120
1
−85
400
Figure 14.
9
−6
100
Frequency (MHz)
2nd−Harmonic
GD = +2V/V
VO = 2VPP
f = 1MHz
−85
−90
3rd−Harmonic
−95
−100
−105
−110
1
10
−110
100
1k
Output Voltage (VPP)
Load Resistance (Ω )
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 61).
SMALL-SIGNAL FREQUENCY RESPONSE
3
0
Normalized Gain (dB)
0
Normalized Gain (dB)
LARGE-SIGNAL FREQUENCY RESPONSE
3
VO = 0.2VPP
RL = 150Ω
G = −1
−3
−6
−9
G = +2
−12
VO = 0.5VPP
−3
−6
VO = 1VPP
−9
G = +2V/V
RL = 150Ω
See Figure 61
−12
−15
−15
1
10
100
400
1
10
Frequency (MHz)
Figure 19.
Figure 20.
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
Output Voltage (500mV/div)
Output Voltage (50mV/div)
0
−0.05
−0.10
G = +2V/V
RL = 150Ω
VO = 2VPP
See Figure 61
1.0
0.5
0
−0.5
−1.0
−1.5
−0.15
Time (10ns/div)
Time (10ns/div)
Figure 21.
Figure 22.
FREQUENCY RESPONSE vs CAPACITIVE LOAD
1dB Peaking Targeted
35
RS (Ω )
30
25
20
15
10
5
0
100
1k
Normalized Gain to Capacitive Load (dB)
REQUIRED RS vs CAPACITIVE LOAD
40
12
300
1.5
G = +2V/V
RL = 150Ω
VO = 0.2VPP
See Figure 61
0.05
10
100
Frequency (MHz)
0.15
0.10
VO = 2VPP
3
CL = 10pF
0
−3
CL = 1000pF
−6
CL = 100pF
−9
−12
VI
1/ 2
RS
O P A 2 832
1 kΩ(1)
CL
−15
NOTE: (1) 1kΩ is optio nal.
−18
1
10
Capacitive Load (pF)
Frequency (MHz)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 61).
HARMONIC DISTORTION vs LOAD RESISTANCE
G = +2, HARMONIC DISTORTION vs FREQUENCY
−40
−50
−60
2nd−Harmonic
−70
G = +2V/V
VO = 2VPP
f = 5MHz
See Figure 61
−80
3rd−Harmonic
−60
−70
−80
−90
3rd−Harmonic
−110
100
1k
0.1
−60
Figure 25.
Figure 26.
−80
3rd−Harmonic
−90
G = −1V/V
RL = 500Ω
f = 5MHz
See Figure 61
−40
2nd−Harmonic
−50
−60
−70
3rd−Harmonic
−80
−90
2nd−Harmonic
−100
−100
−110
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.1
4.5
Figure 27.
Figure 28.
INPUT VOLTAGE AND CURRENT NOISE
50Ω
1 /2
OP A2 832
PO
Input Voltage Noise (nV/√Hz)
Input Current Noise (pA/√Hz)
3rd−Order Spurious Level (dBc)
PI
500Ω
−60
−65
20MHz
−75
−85
20
100
−55
−80
10
Frequency (MHz)
−40
−70
1
Output Voltage Swing (VPP)
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
−50
20
G = –1, HARMONIC DISTORTION vs FREQUENCY
−30
G = +2V/V
RL = 500Ω
f = 5MHz
See Figure 61
−70
10
Frequency (MHz)
Harmonic Distortion (dBc)
−50
1
Load Resistance (Ω )
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−40
−45
2nd−Harmonic
−100
−90
Harmonic Distortion (dBc)
G = +2V/V
RL = 500Ω
VO = 2VPP
See Figure 61
−50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−40
10MHz
Voltage Noise (9.3nV/√Hz)
10
Current Noise (2.3pA/√Hz)
5MHz
−90
1
−24 −22 −20 −18 −16 −14 −12 −10 −8
−6
−4
−2
100
Single−Tone Load Power (dBm)
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 61).
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
COMPOSITE VIDEO dG/dP
80
1.2
+5V
70
1.0
1 /2
60
Video
Loads
OPA 2832
0.8
50
+PSRR
dP
dG/dP
PSRR and CMRR (dB)
CMRR
VI
40
0.6
30
0.4
dG
20
0.2
10
0
0
100
1k
10k
100k
1M
10M
100M
1
2
Frequency (Hz)
3
Figure 31.
Figure 32.
OUTPUT SWING vs LOAD RESISTANCE
5.0
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
100
G = +2V/V
VS = +5V
400Ω
4.0
+5V
Output Impedance (Ω )
Maximum Output Voltage (V)
4.5
4
Number of 150ΩLoads
3.5
3.0
2.5
2.0
1.5
400Ω
10
1/2
O P A 28 32
ZO
200Ω
1
1.0
0.5
0
0.1
100
1k
1k
10k
100k
Figure 33.
VOLTAGE RANGES vs TEMPERATURE
100M
TYPICAL DC DRIFT OVER TEMPERATURE
2.5
10
Input Offset Voltage (VOS)
4.5
Most Positive Output Voltage
3.5
3.0
Most Positive Input Voltage
2.5
RL = 150Ω
2.0
1.5
1.0
Least Positive Output Voltage
0.5
0
−0.5
−1.0
0
8
1.5
6
Bias Current (I B)
1.0
4
0.5
2
0
0
10 × Input Offset (IOS)
−0.5
Least Positive Input Voltage
−50
Input Offset Voltage (mV)
2.0
4.0
Voltage Ranges (V)
10M
Figure 34.
5.0
50
90
−1.0
−40
−20
−2
−4
0
20
40
60
80
100
120
140
Ambient Temperature (20_C/div)
Ambient Temperature (10_ C/div)
Figure 35.
14
1M
Frequency (Hz)
RL (Ω )
Input Bias and Offset Current (µA)
10
Figure 36.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted (see Figure 61).
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
100
11
Output Current, Sinking
10
Output Current, Sourcing
60
9
40
8
Supply Current
20
0
−40
Supply Current (mA)
Output Current (mA)
80
7
−20
6
0
20
40
60
80
100
120
140
Ambient Temperature (20_C/div)
Figure 37.
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TYPICAL CHARACTERISTICS: VS = +5V (Differential)
At TA = +25°C, Differential Gain = +2V/V, and RL = 500Ω, unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
SMALL-SIGNAL FREQUENCY RESPONSE
9
+5V
Normalized Gain (dB)
6
1/2
OPA2832
400Ω
400Ω
RL
VI
400Ω
VO
400Ω
3
0
−3
G = +2V/V
VO = 0.2VPP
RL = 500Ω
−6
1/2
OPA2832
−9
1
10
100
300
Frequency (MHz)
Figure 38.
Figure 39.
HARMONIC DISTORTION vs FREQUENCY
−50
6
−60
Harmonic Distortion (dBc)
Normalized Gain (dB)
LARGE-SIGNAL FREQUENCY RESPONSE
9
3
0
−3
G = +2V/V
VO = 4VPP
RL = 500Ω
−6
−9
1
100
3rd−Harmonic
−80
−90
2nd−Harmonic
−100
0.1
300
1
10
Frequency (MHz)
Frequency (MHz)
Figure 40.
Figure 41.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−70
G = +2V/V
RL = 500Ω
f = 1MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dB)
−70
−110
10
−40
−50
G = +2V/V
RL = 500Ω
VO = 2VPP
−60
−70
−80
−90
2nd−Harmonic
100
HARMONIC DISTORTION vs LOAD RESISTANCE
G = +2V/V
VO = 2VPP
f = 1MHz
−80
2nd−Harmonic
−90
3rd−Harmonic
−100
−100
3rd−Harmonic
−110
1
16
10
−110
100
1k
Output Voltage (VPP)
Load Resistance (Ω )
Figure 42.
Figure 43.
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TYPICAL CHARACTERISTICS: VS = +3.3V
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 62).
SMALL-SIGNAL FREQUENCY RESPONSE
3
LARGE-SIGNAL FREQUENCY RESPONSE
3
VO = 0.2VPP
RL = 150Ω
0
0
VO = 1VPP,
VO = 0.5VPP
Normalized Gain (dB)
G = −1
−3
Gain (dB)
−3
G = +2
−6
−6
−9
−9
−12
−12
−15
−15
1
10
100
300
G = +2V/V
RL = 150Ω
See Figure 62
1
10
Frequency (MHz)
Figure 44.
Figure 45.
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
Output Voltage (V)
Output Voltage (V)
G = +2V/V
RL = 150Ω
VO = 1VPP
See Figure 62
0.4
0.05
0
−0.05
−0.10
0.2
0
−0.2
−0.4
−0.15
−0.6
Time (10ns/div)
Time (10ns/div)
Figure 46.
Figure 47.
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
REQUIRED RS vs CAPACITIVE LOAD
1dB Peaking Targeted
50
RS (Ω)
40
30
20
10
0
1
300
0.6
G = +2V/V
RL = 150Ω
VO = 200mVPP
See Figure 62
60
100
Frequency (MHz)
0.15
0.10
VO = 1.5VPP
10
100
1k
3
CL = 10pF
0
−3
C L = 1000pF
−6
CL = 100pF
−9
VI
1/2
RS
O P A 2 832
−12
1kΩ(1)
CL
NOTE: (1) 1kΩis optional.
−15
1
10
Capacitive Load (pF)
Frequency (MHz)
Figure 48.
Figure 49.
100
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TYPICAL CHARACTERISTICS: VS = +3.3V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted (see Figure 62).
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−40
G = +2V/V
VO = 1VPP
f = 5MHz
See Figure 62
−55
−60
3rd−Harmonic
−65
−70
2nd−Harmonic
−75
−80
−60
3rd−Harmonic
−70
2nd−Harmonic
−80
−90
−100
100
1k
0.50
−60
1.00
1.25
1.50
Output Voltage Swing (V)
Figure 50.
Figure 51.
HARMONIC DISTORTION vs FREQUENCY
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
−40
G = +2V/V
RL = 500Ω
VO = 1VPP
See Figure 62
3rd−Order Spurious Level (dBc)
−50
0.75
Load Resistance (Ω )
−40
Harmonic Distortion (dBc)
G = +2V/V
RL = 500Ω
f = 5MHz
See Figure 62
−50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−50
−70
−80
2nd−Harmonic
−90
−100
3rd−Harmonic
−110
−45
PI
−50
1/2
OPA2832
50Ω
PO
500Ω
−55
−60
−65
−70
−75
20MHz
−80
5MHz
10MHz
−85
−90
0.1
1
10
−26
20
−24
−22
−20
−18
−16
−14
−12
Frequency (MHz)
Single−Tone Load Power (dBm)
Figure 52.
Figure 53.
−10
−8
OUTPUT SWING vs LOAD RESISTANCE
3.3
G = +2V/V
VS = +3.3V
Maximum Output Voltage (V)
3.0
2.7
Most Positive Output Voltage
2.4
2.1
1.8
1.5
1.2
0.9
0.6
Least Positive Output Voltage
0.3
0
10
100
1k
RL (Ω )
Figure 54.
18
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TYPICAL CHARACTERISTICS: VS = +3.3V (Differential)
At TA = +25°C, Differential Gain = +2V/V, and RL = 500Ω, unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
SMALL-SIGNAL FREQUENCY RESPONSE
9
+3.3V
6
1/2
OPA2832
3
Gain (dB)
400Ω
400Ω
RL
VI
400Ω
VO
0
−3
400Ω
G = +2V/V
VO = 0.2VPP
RL = 500Ω
−6
1/2
OPA2832
−9
1
10
100
300
Frequency (MHz)
Figure 55.
Figure 56.
LARGE-SIGNAL FREQUENCY RESPONSE
HARMONIC DISTORTION vs FREQUENCY
−50
6
−60
Harmonic Distortion (dBc)
9
Gain (dB)
3
0
−3
G = +2V/V
RL = 500Ω
VO = 2VPP
−6
−9
1
10
100
−100
3rd−Harmonic
1
10
Frequency (MHz)
Figure 57.
Figure 58.
−60
3rd−Harmonic
−60
−70
−80
Input Limited
−90
−90
0.1
300
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−50
−80
Frequency (MHz)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
G = +2V/V
RL = 500Ω
f = 1MHz
2nd−Harmonic
−70
−110
−30
−40
G = +2V/V
RL = 500Ω
VO = 1VPP
2nd−Harmonic
−100
−110
1
10
100
HARMONIC DISTORTION vs LOAD RESISTANCE
G = +2V/V
VO = 1VPP
f = 1MHz
−70
−80
−90
2nd−Harmonic
−100
3rd−Harmonic
−110
−120
100
1k
Output Voltage (VPP)
Load Resistance (Ω )
Figure 59.
Figure 60.
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APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The OPA2832 is a unity-gain stable, very high-speed
voltage-feedback op amp designed for single-supply
operation (+3V to +11V). The input stage supports
input voltages below ground and to within 1.7V of the
positive supply. The complementary common-emitter
output stage provides an output swing to within 25mV
of ground and the positive supply. The OPA2832 is
compensated to provide stable operation with a wide
range of resistive loads.
Figure 61 shows the AC-coupled, gain of +2
configuration used for the +5V Specifications and
Typical Characteristic Curves. For test purposes, the
input impedance is set to 50Ω with the 66.7Ω resistor
to ground in parallel with the 200Ω bias network.
Voltage
swings
reported
in
the
Electrical
Characteristics are taken directly at the input and
output pins. For the circuit of Figure 61, the total
effective load on the output at high frequencies is
150Ω || 800Ω. The 332Ω and 505Ω resistors at the
noninverting input provide the common-mode bias
voltage. Their parallel combination equals the DC
resistance at the inverting input RF), reducing the DC
output offset due to input bias current.
VS = +5V
6.8µF
+
505Ω
0.1µF
VIN
66.7Ω
0.1µF
2V
332Ω
400Ω
1/2
OPA2832
VOUT
RL
150Ω
400Ω
+VS/2
+VS
2
Figure 61. AC-Coupled, G = +2, +5V Single-Supply
Specification and Test Circuit
Figure 62 shows the AC-coupled, gain of +2
configuration used for the +3.3V Specifications and
Typical Characteristic Curves. For test purposes, the
input impedance is set to 66.5Ω with a resistor to
20
ground. Voltage swings reported in the Electrical
Characteristics are taken directly at the input and
output pins. For the circuit of Figure 62, the total
effective load on the output at high frequencies is
150Ω || 800Ω. The 255Ω and 1.13kΩ resistors at the
noninverting input provide the common-mode bias
voltage. Their parallel combination equals the DC
resistance at the inverting input RF), reducing the DC
output offset due to input bias current.
VS = +3.3V
6.8µF
+
1.13kΩ
0.1µF
0.1µF
+0.75V
VIN
66.5Ω
255Ω
400Ω
1/2
OPA2832
400Ω
VOUT
RL
150Ω
+0.75
0.75V
Figure 62. AC-Coupled, G = +2, +3V Single-Supply
Specification and Test Circuit
Figure 63 shows the DC-coupled, gain of +2, dual
power-supply circuit configuration used as the basis
of the ±5V Electrical Characteristics and Typical
Characteristics. For test purposes, the input
impedance is set to 50Ω with a resistor to ground and
the output impedance is set to 150Ω with a series
output resistor. Voltage swings reported in the
specifications are taken directly at the input and
output pins. For the circuit of Figure 63, the total
effective load will be 150Ω || 800Ω. Two optional
components are included in Figure 63. An additional
resistor (175Ω) is included in series with the
noninverting input. Combined with the 25Ω DC
source resistance looking back towards the signal
generator, this gives an input bias current cancelling
resistance that matches the 200Ω source resistance
seen at the inverting input (see the DC Accuracy and
Offset Control section). In addition to the usual
power-supply decoupling capacitors to ground, a
0.01µF capacitor is included between the two
power-supply pins. In practical PC board layouts, this
optional capacitor will typically improve the
2nd-harmonic distortion performance by 3dB to 6dB.
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SINGLE-SUPPLY ACTIVE FILTER
0.1µF
6.8µF
+
50Ω Source
175Ω
VIN
VO
1/2
OPA2832
50Ω
150Ω
0.01µF
400Ω
400Ω
+
6.8µF
0.1µF
−5V
Figure 63. DC-Coupled, G = +2, Bipolar Supply
Specification and Test Circuit
SINGLE-SUPPLY ADC INTERFACE
The ADC interface in Figure 64 shows a DC-coupled,
single-supply ADC driver circuit. Many systems are
now requiring +3.3V supply capability of both the
ADC and its driver. The OPA2832 provides excellent
performance in this demanding application. Its large
input and output voltage ranges and low distortion
support converters such as the ADS5203. The input
level-shifting circuitry was designed so that VIN can
be between 0V and 0.5V, while delivering an output
voltage of 1V to 2V for the ADS5203.
2.26kΩ
+3.3V
374Ω
1/2
OPA2832
100Ω
22pF
400Ω
Both the input signal and the gain setting resistor are
AC-coupled using 0.1µF blocking capacitors (actually
giving bandpass response with the low-frequency
pole set to 3.2kHz for the component values shown).
As discussed for Figure 61, this allows the midpoint
bias formed by one 2kΩ and one 3kΩ resistor to
appear at both the input and output pins. The
midband signal gain is set to +2 (6dB) in this case.
The capacitor to ground on the noninverting input is
intentionally set larger to dominate input parasitic
terms. At a gain of +2, the OPA2832 on a single
supply will show 75MHz small- and large-signal
bandwidth. The resistor values have been slightly
adjusted to account for this limited bandwidth in the
amplifier stage. Tests of this circuit, shown in
Figure 65, illustrate a precise 1MHz, –3dB point with
a maximally-flat passband (above the 3.2kHz
AC-coupling corner), and a maximum stop band
attenuation of 36dB.
9
6
3
0
−3
−6
−9
+3.3V
VIN
The OPA2832, while operating on a single +3.3V or
+5V supply, lends itself well to high-frequency active
filter designs. Again, the key additional requirement is
to establish the DC operating point of the signal near
the supply midpoint for highest dynamic range.
Figure 66 shows an example design of a 1MHz
low-pass Butterworth filter using the Sallen-Key
topology.
Gain (dB)
+5V
1/2
ADS5203
10−Bit
30MSPS
−12
−15
−18
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 65. 1MHz, 2nd-Order, Butterworth
Low-Pass Filter
400Ω
Figure 64. DC-Coupled, +3V ADC Driver
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+5V
470pF
3kΩ
0.1µF
205Ω
866Ω
VI
1/2
OPA2832
300pF
2kΩ
2V I
400Ω
1MHz, 2nd−Order
Butterworth Filter
400Ω
0.1µF
Figure 66. Single-Supply, High-Frequency Active Filter
DIFFERENTIAL LOW-PASS FILTERS
The dual OPA2832 offers an easy means to
implement low-power differential active filters. On a
single supply, one way to implement a 2nd-order,
low-pass filter is shown in Figure 67. This circuit
provides a net differential gain of 1 with a precise
5MHz Butterworth response. The signal is
AC-coupled (giving a high-pass pole at low
frequencies) with the DC operating point for the
circuit set by the unity-gain buffer—the BUF602. This
buffer gives a very low output impedance to high
frequencies to maintain accurate filter characteristics.
If the source is a DC-coupled signal already biased
into the operating range of the OPA2832 input CMR,
these capacitors and the midpoint bias may be
removed. To get the desired 5MHz cutoff, the input
resistors to the filter is actually 119Ω. This is
implemented in Figure 67 as the parallel combination
of the two 238Ω resistors on each half of the
differential input as part of the DC biasing network. If
the BUF602 is removed, these resistors should be
collapsed back to a single 119Ω input resistor.
22
150pF
+5V
0.1µF
238Ω
506Ω
1 /2
+5V
O PA 283 2
238Ω
5kΩ
VI
2.5V
0.1µF
0.1µF
100pF
400Ω
400Ω
400Ω
400Ω
VI
VO
BUF602
5kΩ
238Ω
238Ω
100pF
1 /2
O PA 28 32
506Ω
150pF
Figure 67. Single-Supply, 5MHz, 2nd-Order,
Low-Pass Sallen-Key Filter
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Implementing the DC bias in this way also attenuates
the differential signal by half. This is recovered by
setting the amplifier gain at 2V/V to get a net
unity-gain filter characteristic from input to output. The
filter design shown here has also adjusted the
resistor values slightly from an ideal analysis to
account for the 100MHz bandwidth in the amplifier
stages. The filter capacitors at the noninverting inputs
are shown as two separate capacitors to ground.
While it is certainly correct to collapse these two
capacitors into a single capacitor across the two
inputs (which would be 50pF for this circuit) to get the
same differential filtering characteristic, tests have
shown two separate capacitors to a low impedance
point act to attenuate the common-mode feedback
present in this circuit giving more stable operation in
actual implementation. Figure 68 shows the
frequency response for the filter of Figure 67.
+VS
+5V
374Ω
2.2nF
2.2nF
1/2
OPA2832
750Ω
400Ω
2kΩ
1µF
VO
VS/2
VI
400Ω
2kΩ
750Ω
2.2nF
0
−1
1/2
OPA2832
2.2nF
374Ω
Differential Gain (dB)
−2
−3
Figure 69. 138kHz, 2nd-Order, High-Pass Filter
−4
−5
−6
Results showing the frequency response for the
circuit of Figure 69 is shown in Figure 70.
−7
−8
−9
3
−10
−11
−12
0
10k
100k
1M
10M
Frequency (Hz)
Figure 68. 5MHz, 2nd-Order, Butterworth
Low-Pass Filter
Gain (dB)
1k
−3
−6
−9
HIGH-PASS FILTERS
Another approach to mid-supply biasing is shown in
Figure 69. This method uses a bypassed divider
network in place of the buffer used in Figure 67. The
impedance is set by the parallel combination of the
resistors forming the divider network, but as
frequency increases it looks more and more like a
short due to the capacitor. Generally, the capacitor
value needs to be two to three orders of magnitude
greater than the filter capacitors shown for the circuit
to work properly.
−12
0.01
0.1
1
10
Frequency (MHz)
Figure 70. Frequency Response for the Filter of
Figure 69
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DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA2832 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user's guide. The summary
information for these fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA2832ID
SO-8
DEM-OPA-SO-2A
SBOU003
OPA2832IDGK
MSOP-8
DEM-OPA-MSOP-2A
SBOU004
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA2832 product folder.
the available output voltage and current will always
be greater than that shown in the over-temperature
specifications, since the output stage junction
temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no
output short-circuit protection is provided. This will not
normally be a problem, since most applications
include a series matching resistor at the output that
will limit the internal power dissipation if the output
side of this resistor is shorted to ground. However,
shorting the output pin directly to the adjacent
positive power-supply pin (8-pin packages) will, in
most cases, destroy the amplifier. If additional
short-circuit protection is required, consider a small
series resistor in the power-supply leads. This will
reduce the available output voltage swing under
heavy output loads.
DRIVING CAPACITIVE LOADS
MACROMODEL AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using
SPICE is often a quick way to analyze the
performance of the OPA2832 and its circuit designs.
This is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can play a major role on circuit performance. A
SPICE model for the OPA2832 is available through
the TI web page (www.ti.com). The applications
department is also available for design assistance.
These models predict typical small signal AC,
transient steps, DC performance, and noise under a
wide variety of operating conditions. The models
include the noise terms found in the electrical
specifications of the data sheet. These models do not
attempt to distinguish between the package types in
their small-signal AC performance.
OPERATING SUGGESTIONS
OUTPUT CURRENT AND VOLTAGES
The OPA2832 provides outstanding output voltage
capability. For the +5V supply, under no-load
conditions at +25°C, the output voltage typically
swings closer than 90mV to either supply rail.
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at
cold startup will the output current and voltage
decrease to the numbers shown in the ensured
tables. As the output transistors deliver power, their
junction temperatures will increase, decreasing their
VBEs (increasing the available output voltage swing)
and increasing their current gains (increasing the
available output current). In steady-state operation,
24
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance which
may be recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier like the
OPA2832 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series isolation resistor between the
amplifier output and the capacitive load.
The Typical Characteristic curves show the
recommended RS versus capacitive load and the
resulting frequency response at the load. Parasitic
capacitive loads greater than 2pF can begin to
degrade the performance of the OPA2832. Long PC
board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the output pin (see the Board Layout Guidelines
section).
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a
gain of +2, the frequency response at the output pin
is already slightly peaked without the capacitive load,
requiring relatively high values of RS to flatten the
response at the load. Increasing the noise gain will
also reduce the peaking (see Figure 24).
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DISTORTION PERFORMANCE
The OPA2832 provides good distortion performance
into a 150Ω load. Relative to alternative solutions, it
provides exceptional performance into lighter loads
and/or operating on a single +3.3V supply. Generally,
until the fundamental signal reaches very high
frequency or power levels, the 2nd-harmonic will
dominate the distortion with a negligible 3rd-harmonic
component. Focusing then on the 2nd-harmonic,
increasing the load impedance improves distortion
directly. Remember that the total load includes the
feedback network; in the noninverting configuration
(see Figure 62) this is sum of RF + RG, while in the
inverting configuration, only RF needs to be included
in parallel with the actual load. Running differential
suppresses the 2nd-harmonic, as shown in the
differential typical characteristic curves.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve their slew rate at the expense
of a higher input noise voltage. The 9.2nV/√Hz input
voltage noise for the OPA2832, however, is much
lower than comparable amplifiers. The input-referred
voltage noise and the two input-referred current noise
terms (2.8pA/√Hz) combine to give low output noise
under a wide variety of operating conditions.
Figure 71 shows the op amp noise analysis model
with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current
density terms in either nV/√Hz or pA/√Hz.
ENI
1/2
OPA2832
RS
EO
IBN
ERS
RF
√ 4kTRS
4kT
RG
RG
IBI
√ 4kTRF
4kT = 1.6E − 20J
at 290_K
Figure 71. Noise Analysis Model
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 1 shows the
general form for the output noise voltage using the
terms shown in Figure 71:
EO +
Ǹǒ
2
Ǔ
2
2
E NI ) ǒI BNRSǓ ) 4kTRS NG 2 ) ǒI BIR FǓ ) 4kTRFNG
(1)
Dividing this expression by the noise gain
(NG = (1 + RF/RG)) will give the equivalent
input-referred spot noise voltage at the noninverting
input, as shown in Figure 71:
EN +
Ǹ
2
2
ENI ) ǒIBNR SǓ ) 4kTRS )
ǒ Ǔ
IBIRF
NG
2
)
4kTRF
NG
(2)
Evaluating these two equations for the circuit and
component values shown in Figure 61 will give a total
output spot noise voltage of 19.3nV/√Hz and a total
equivalent input spot noise voltage of 9.65nV/√Hz.
This is including the noise added by the resistors.
This total input-referred spot noise voltage is not
much higher than the 9.2nV/√Hz specification for the
op amp voltage noise alone.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband
voltage-feedback op amp allows good output DC
accuracy in a wide variety of applications. The
power-supply current trim for the OPA2832 gives
even tighter control than comparable products.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output DC error
caused by this current. This is done by matching the
DC source resistances appearing at the two inputs.
Evaluating the configuration of Figure 63 (which has
matched DC input resistances), using worst-case
+25°C input offset voltage and current specifications,
gives a worst-case output offset voltage equal to:
• (NG = noninverting signal gain at DC)
• ±(NG × VOS(MAX)) + RF × IOS(MAX))
• = ±(2 × 7.5mV) + (400Ω × 1.5µA)
• = –14.4mV to +15.6mV
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A fine-scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques
are available for introducing DC offset control into an
op amp circuit. Most of these techniques are based
on adding a DC current through the feedback
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
be noninverting, the offset control is best applied as
an inverting summing signal to avoid interaction with
the signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. Bring the DC
offsetting current into the inverting input node through
resistor values that are much larger than the signal
path resistors. This will insure that the adjustment
circuit has minimal effect on the loop gain and hence
the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature will set the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by
TA + PD × θJA. The total internal power dissipation
(PD) is the sum of quiescent power (PDQ) and
additional power dissipated in the output stage (PDL)
to deliver load power. Quiescent power is simply the
specified no-load supply current times the total supply
voltage across the part. PDL will depend on the
required output signal and load; though, for resistive
loads connected to mid-supply (VS/2), PDL is at a
maximum when the output is fixed at a voltage equal
to VS/4 or 3VS/4. Under this condition, PDL = VS2/(16
× RL), where RL includes feedback network loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
As a worst-case example, compute the maximum TJ
using an OPA2832 (MSOP-8 package) in the circuit
of Figure 63 operating at the maximum specified
ambient temperature of +85°C and driving both
channels at a 150Ω load at mid-supply.
2 52
P D + 10V 11.9mA )
+ 144mV
ǒ16 ǒ150W ø 800WǓǓ
Maximum T J + ) 85 oC ) ǒ0.144W
150 oCńWǓ + 107 oC
Although this is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
26
dissipation will occur if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
puts a high current through a large internal voltage
drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the OPA2832 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
b) Minimize the distance ( < 0.25") from the
power-supply
pins
to
high-frequency
0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each
power-supply
connection
should
always
be
decoupled with one of these capacitors. An optional
supply decoupling capacitor (0.1µF) across the two
power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PC board.
c) Careful selection and placement of external
components will preserve the high-frequency
performance. Resistors should be a very low
reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal film or carbon
composition axially-leaded resistors can also provide
good high-frequency performance. Again, keep their
leads and PCB traces as short as possible. Never
use wire-wound type resistors in a high-frequency
application. Since the output pin and inverting input
pin are the most sensitive to parasitic capacitance,
always position the series output resistor, if any, as
close as possible to the output pin. Other network
components, such as noninverting input termination
resistors, should also be placed close to the package.
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d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the typical characteristic curve
Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since
the OPA2832 is nominally compensated to operate
with a 2pF parasitic load. Higher parasitic capacitive
loads without an RS are allowed as the signal gain
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and
in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
(based on board material and trace dimensions), a
matching series resistor into the trace from the output
of the OPA2832 is used as well as a terminating
shunt resistor at the input of the destination device.
Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and
the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in this
case and set the series resistor value as shown in the
typical characteristic curve Recommended RS vs
Capacitive Load. This will not preserve signal integrity
as well as a doubly-terminated line. If the input
impedance of the destination device is low, there will
be some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
e) Socketing a high-speed part is not
recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA2832 onto the board.
INPUT AND ESD PROTECTION
The OPA2832 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 72.
+VCC
External
Pin
Internal
Circuitry
−VCC
Figure 72. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (that is, in systems with ±15V supply parts
driving into the OPA2832), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible, since high
values degrade both noise performance and
frequency response.
Submit Documentation Feedback
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2832
27
OPA2832
SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008 ............................................................................................................................................. www.ti.com
Revision History
Changes from Revision B (May 2006) to Revision C ...................................................................................................... Page
•
Changed rating for storage voltage range in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C ................................................................................................................................................................................... 2
Changes from Revision A (April 2005) to Revision B .................................................................................................... Page
•
•
•
28
Changed Demonstration Boards title to Demonstration Fixtures. ....................................................................................... 24
Changed OPA830 changed to OPA2832 of first paragraph of Demonstration Fixtures section......................................... 24
Changed Table 1 title and columns 3 and 4. ....................................................................................................................... 24
Submit Documentation Feedback
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2832
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2832ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2832
OPA2832IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A61
OPA2832IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2832
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2832IDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2832IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2832IDGKT
VSSOP
DGK
OPA2832IDR
SOIC
D
8
250
210.0
185.0
35.0
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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