Texas Instruments | Dual, Wideband, Low-Noise, Voltage-Feedback Operational Amplifier (Rev. C) | Datasheet | Texas Instruments Dual, Wideband, Low-Noise, Voltage-Feedback Operational Amplifier (Rev. C) Datasheet

Texas Instruments Dual, Wideband, Low-Noise, Voltage-Feedback Operational Amplifier (Rev. C) Datasheet
OPA2846
SBOS274C −JUNE 2003 − REVISED AUGUST 2008
Dual, Wideband, Low-Noise, Voltage-Feedback
Operational Amplifier
FEATURES
D
D
D
D
D
D
D
D
DESCRIPTION
HIGH BANDWIDTH: 300MHz (G = +10)
The OPA2846 provides two very low-noise, high gain
bandwidth, voltage-feedback op amps in a single
package. Operating from a low 12.6mA/channel quiescent
current, each channel provides a 1.2nV/√Hz input voltage
noise with a 1.65GHz gain bandwidth product. Minimum
stable gain is specified at +7V/V while exceptional flatness
is ensured at a gain of +10V/V.
LOW INPUT VOLTAGE NOISE: 1.2nV/√Hz
VERY LOW DISTORTION: –100dBc (5MHz)
HIGH SLEW RATE: 600V/µs
HIGH DC ACCURACY: VIO = 150µV
LOW SUPPLY CURRENT: 12.6mA/ch
The combination of low noise, high slew rate (600V/µs)
and broad bandwidth allow very high SFDR differential
receivers to be implemented. Additionally, decompensated, low-noise, voltage-feedback op amps are ideal for
broadband transimpedance requirements. The dual channel OPA2846 provides matched channels for high-speed
transimpedance requirements. With over 200MHz bandwidth at a gain of 20dB, excellent gain and phase matching
are provided at IF frequencies for matched I and Q channel
amplifiers.
HIGH GAIN BANDWIDTH PRODUCT: 1650MHz
STABLE FOR GAINS ≥ +7V/V
APPLICATIONS
D HIGH DYNAMIC RANGE ADC PREAMPS
D LOW-NOISE, WIDEBAND, TRANSIMPEDANCE
AMPLIFIERS
OPA2846 RELATED PRODUCTS
WIDEBAND, HIGH GAIN AMPLIFIERS
LOW-NOISE DIFFERENTIAL RECEIVERS
VDSL LINE RECEIVERS
ULTRASOUND CHANNEL AMPLIFIERS
SECURITY SENSOR FRONT ENDS
Power−supply decoup ling
not sho wn.
1000pF
GAIN BANDWIDTH
PRODUCT (MHz)
OPA842
OPA843
OPA846
OPA847
2.6
2.0
1.2
0.85
200
800
1750
3900
−80
C1
100Ω
1/2
O P A 28 46
R1
L
V+
2.1pF
14−Bit
10MSPS
ADS850
R2
100Ω
500Ω
100Ω
500Ω
VI
C
50 Ω
2.1pF
R2
C1
18pF
1 /2
O P A2 84 6
100Ω
V CM
0.1µF
Single−to−Differential
Gain of 10
1000pF
INPUT NOISE
VOLTAGE (nV/√Hz)
+5V
18p F
1:2
SINGLES
R1
Harmonic Distortion (dBc)
D
D
D
D
D
VO = 2VPP Differential
−85
2nd−Harmonic
−90
−95
−100
−105
3rd−Harmonic
L
V−
−110
1
−5V
10
Frequency (MHz)
Differential, 14-Bit, ADC Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2003-2008, Texas Instruments Incorporated
! ! www.ti.com
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC
Internal Power Dissipation . . . . . . . . . . . . . . See Thermal Analysis
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Storage Temperature Range: D . . . . . . . . . . . . . . . . −65°C to +125°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 2000V
(Charge Device Model) . . . . . . . . . . . . . . . . . . . 1500V
(Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA2846
SO-8
D
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
−40°C to +85°C
OPA2846
OPA2846ID
OPA2846IDR
Rails, 100
Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
TOP VIEW
SO
OPA2846
2
Out A
1
8
V+
−In A
2
7
Out B
+In A
3
6
−In B
V−
4
5
+In B
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are 100% tested at +25°C.
RF = 453Ω, RL = 100Ω, and G = +10, unless otherwise noted. See Figure 1 for AC performance.
OPA2846ID
TYP
PARAMETER
AC Performance (see Figure 1)
Closed-Loop Bandwidth
Gain Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +7
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
2-Tone, 3rd-Order Intercept
Input Voltage Noise
Input Current Noise
Rise-and-Fall Time
Slew Rate
Settling Time to 0.01%
0.1%
1%
Differential Gain
Differential Phase
Channel-to-Channel Crosstalk
DC Performance(4)
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
Input
Common-Mode Input Range (CMIR)(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
Output
Output Voltage Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
MIN/MAX OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C(1)
0°C to
+70°C(2)
−40°C to
+85°C(2)
G = +7, RG = 50Ω, VO = 200mVPP
G = +10, RG = 50Ω, VO = 200mVPP
G = +20, RG = 50Ω, VO = 200mVPP
G ≥ +40
G = +10, RL = 100Ω, VO = 200mVPP
425
300
100
1650
100
3
250
80
1250
40
225
76
1225
35
200
70
1200
30
UNITS
MIN/
MAX
TEST
LEVEL
(3)
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
min
typ
C
B
B
B
B
C
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
ns
V/µs
ns
ns
ns
%
deg
dBc
max
max
max
max
min
max
max
max
min
typ
max
max
typ
typ
typ
B
B
B
B
B
B
B
B
B
C
B
B
C
C
C
G = +10, f = 5MHz, VO = 2VPP
RL = 100Ω
RL = 500Ω
RL = 100Ω
RL = 500Ω
G = +10, f = 10MHz
f > 1MHz
f > 1MHz
0.2V Step
2V Step
2V Step
2V Step
2V Step
G = +10, NTSC, RL = 150Ω
G = +10, NTSC, RL = 150Ω
Input Referrred, f = 5MHz
−76
−100
−109
−112
44
1.2
2.8
1.3
600
18
12
8
0.02
0.02
−60
−70
−89
−95
−105
41
1.3
3.5
1.6
500
−68
−87
−92
−101
40
1.4
3.6
1.7
400
−66
−85
−90
−96
38
1.5
3.6
1.9
350
14
10
16
12
18
14
VO = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
90
±0.15
±0.5
−10
±1
±0.1
±0.7
82
±0.65
±1.6
−20
±20
±0.4
±3.0
81
±0.73
±1.6
−20.8
±20
±0.5
±3.0
80
±0.76
±1.6
−21.2
±35
±0.6
±3.5
dB
mV
µV/°C
µΑ
nA/°C
µΑ
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
VCM = ±1V, Input Referred
±3.2
110
±3.0
95
±2.9
93
±2.8
90
V
dB
min
min
A
A
VCM = 0V
VCM = 0V
6.6  2.0
4.7  1.8
kΩ  pF
MΩ  pF
typ
typ
C
C
≥ 400Ω Load
100Ω Load
VO = 0V
VO = 0V
G = +10, f = 100kHz
±3.4
±3.3
80
−80
0.008
V
V
mA
mA
Ω
min
min
min
min
typ
A
A
A
A
C
±3.3
±3.2
65
−65
±3.2
±3.0
61
−61
±3.1
±2.9
60
−60
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum CMRR specification at ± CMIR limits.
3
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are 100% tested at +25°C.
RF = 453Ω, RL = 100Ω, and G = +10, unless otherwise noted. See Figure 1 for AC performance.
OPA2846ID
TYP
PARAMETER
Power Supply
Specified Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (−PSRR)
TEST CONDITIONS
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
+70°C(2)
−40°C to
+85°C(2)
UNITS
MIN/
MAX
TEST
LEVEL
(3)
±6
25.9
24.5
90
±6
26.3
23.9
88
±6
26.7
23.3
85
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
−40 to
+85
°C
typ
C
125
°C/W
typ
C
+25°C
±5
VS = ±5V, Both Channels
VS = ±5V, Both Channels
−VS = −4.5 to 5.5 (Input Referred)
25.2
25.2
95
Thermal Characteristics
Specified Operating Range: D Package
Thermal Resistance, qJA
D
SO-8
Junction-to-Ambient
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum CMRR specification at ± CMIR limits.
4
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
6
3
VO = 0.2VPP
RG = 50Ω
G = −12
G=7
0
0
Normalized Gain (dB)
−3
G = 10
−6
G = 50
−9
G = 20
−12
VO = 0.2VPP
RG = RS = 50Ω
−3
−6
−12
−15
−15
See Figure 1
−18
1M
See Figure 2
−18
10M
100M
1G
1M
10M
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
29
VO = 0.2VPP
26
20
RL = 100Ω
G = +10V/V
23
Gain (dB)
Gain (dB)
VO = 0.2VPP
VO = 1VPP
14
11
20
17
14
11
VO = 2VPP
VO = 5VPP
5
See Figure 1
2
10M
8
VO = 5VPP
100M
See Figure 2
5
10M
1G
Frequency (Hz)
Large Signal ±1V
Left Scale
2.0
0.4
1.6
0.3
0.8
0.2
0.4
0.1
Small Signal ±100mV
Right Scale
0
0
−0.4
−0.1
−0.8
−0.2
−1.2
−0.3
−1.6
See Figure 1
Time (5ns/div)
Output Voltage (400mV/div)
1.2
1G
INVERTING PULSE RESPONSE
0.5
Output Voltage (100mV/div)
G = +10V/V
100M
Frequency (Hz)
NONINVERTING PULSE RESPONSE
2.0
−2.0
VO = 1VPP
RL = 100Ω
RG = RS = 50Ω
G = −20V/V
VO = 2VPP
8
1.6
1G
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
23
17
100M
Frequency (Hz)
Frequency (Hz)
Output Voltage (400mV/div)
G = −20
G = −50
−9
1.2
G = −20V/V
0.5
Large Signal ±1V
Left Scale
0.8
0.4
0
0.4
0.3
0.2
Small Signal ±100mV
Right Scale
0.1
0
−0.4
−0.1
−0.8
−0.2
−1.2
−0.3
−0.4
−1.6
−0.4
−0.5
−2.0
Output Voltage (100mV/div)
Normalized Gain (dB)
3
−0.5
Time (5ns/div)
5
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE
−60
−70
2nd−Harmonic
−75
−80
−85
−90
−95
−100
−105
3rd−Harmonic
−110
−115
100
200
250
300
350
400
450
−75
2nd−Harmonic
−80
−85
−90
3rd−Harmonic
−95
−100
−105
See Figure 1
150
G = +10V/V
VO = 5VPP
−70
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−65
1MHz HARMONIC DISTORTION vs LOAD RESISTANCE
−65
G = +10V/V
VO = 2VPP
−110
100
500
150
200
Resistance (Ω )
G = +10V/V
VO = 2VPP
RL = 200Ω
2nd−Harmonic
3rd−Harmonic
−85
−95
−105
−75
10
−95
−100
3rd−Harmonic
−105
See Figure 1
0.1
100
1
HARMONIC DISTORTION vs NONINVERTING GAIN
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2VPP
f = 5MHz
RL = 200Ω
−90
−95
−100
−105
−75
VO = 2VPP
f = 5MHz
RL = 200Ω
−85
−95
−105
3rd−Harmonic
−110
3rd−Harmonic
See Figure 1
−115
5
10
15
20
25
30
Gain (V/V)
6
2nd−Harmonic
−75
−85
HARMONIC DISTORTION vs INVERTING GAIN
−65
2nd−Harmonic
−80
35
10
Output Voltage (VPP)
−60
−70
500
−90
Frequency (MHz)
−65
450
−85
−115
1
400
2nd−Harmonic
−80
−110
See Figure 1
0.1
G = +10V/V
f = 5MHz
RL = 200Ω
−70
−75
−115
350
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−65
Harmonic Distortion (dBc)
Normalized Gain (dB)
−65
300
Resistance (Ω )
HARMONIC DISTORTION vs FREQUENCY
−55
250
40
45
−115
50
10
15
20
25
30
Gain (−V/V)
35
40
45
50
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE
2−TONE, 3RD−ORDER INTERMODULATION INTERCEPT
50
10
50 Ω S o u rce
G = +10V/V
+5V
RS
5 0Ω
P IN
Intercept Point (+dBm)
Voltage Noise (nV/√Hz)
Current Voise (pA/√Hz)
45
Current Noise
2.8pA/√Hz
Voltage Noise
1.2nV/√Hz
RL
RF
45 3 Ω
35
RG
50Ω
30
100
1k
10k
100k
1M
10M
100M
5
10
15
20
Frequency (Hz)
Normalized Gain (1dB)
Deviation from 18.06dB Gain (0.1dB)
2
NG = 9.0
0
NG = 9.5
−0.2
−0.5
NG = 10.0
External Compensation
See Figure 9
1M
10M
1
50
G = −4
−1
G = −2
−2
G = −1
−3
−4
External Compensation
See Figure 5
−5
−6
100M
1G
1M
10M
RECOMMENDED RS vs CAPACITIVE LOAD
1
Capacitive Load (pF)
1000
Normalized Gain to Capacitive Load (dB)
10
100
1G
FREQUENCY RESPONSE vs CAPACITIVE LOAD
G = +10V/V
10
100M
Frequency (Hz)
100
RS (Ω)
45
G = −6
0
Frequency (Hz)
1
40
VO = 200mVPP
RF = 400Ω
NG = 8.0
NG = 8.5
−0.1
−0.4
35
LOW GAIN INVERTING BANDWIDTH
0.1
−0.3
30
3
VO = 200mVPP
AV = +8
RF = 453Ω
RG = 64.9Ω
0.2
25
Frequency (MHz)
NONINVERTING GAIN FLATNESS TUNE
0.3
5 0Ω
− 5V
40
20
10
0.4
O P A 2 8 46
25
1
0.5
PO
1 /2
50 Ω
23
RS adjusted for capacitive load.
C = 10pF
20
C = 22pF
17
50 Ω So urce
V IN
1/ 2
50Ω
P ow er− su pp ly
+5 V de c ou plin g no t sh ow n.
RS
VO
O P A 2 846
14
CL
−5V
R
45 3Ω
11
C = 47pF
C = 100pF
RL
1kΩ
(1 kΩ is op tion al.)
RG
50 Ω
8
1M
10M
100M
1G
Frequency (Hz)
7
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
COMMON−MODE REJECTION RATIO AND
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
OPEN−LOOP GAIN AND PHASE
120
120
0
100
−30
+PSRR
Open−Loop Gain (dB)
CMRR and PSRR (dB)
100
90
80
70
−PSRR
60
50
−60
80
∠AOL
60
−90
−120
40
20log (AOL)
40
30
20
−150
0
−180
−20
−210
102
20
102
103
104
105
106
107
Open−Loop Phase (_)
CMRR
110
103
104
108
105
106
Frequency (Hz)
107
108
109
Frequency (Hz)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY
4
10
3
RL = 100Ω
Output Impedance (Ω )
2
RL = 50Ω
VO (V)
1
RL = 25Ω
0
ZO
1/2
−1
−2
O PA2846
1
453Ω
0.1
50Ω
0.01
−3
0.001
−100
−50
0
50
100
102
150
103
104
I O (mA)
10
0.8
8
0.6
6
0.4
Output
2
0
0.2
0
Output Voltage (2V/div)
4
0.3
0.1
0
−6
−0.6
−8
−0.8
−8
−1.0
−10
100 150 200 250 300 350 400 450 500
Time (50ns/div)
0.4
0
−0.4
50
G = −20V/V
RL = 100Ω
0.2
−4
See Figure 1
0.5
Input
2
−0.2
0
108
4
−2
−10
8
G = +10V/V
RL = 100Ω
1.0
Input Voltage (200mV/div)
Output Voltage (2V/div)
6
107
INVERTING OVERDRIVE RECOVERY
NONINVERTING OVERDRIVE RECOVERY
Input
106
Frequency (Hz)
10
8
105
−2
Output
−4
−6
−0.1
−0.2
−0.3
See Figure 2
0
50
100 150 200 250 300 350 400 450 500
Time (50ns/div)
−0.4
−0.5
Input Voltage (100mV/div)
−4
−150
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
SETTLING TIME
0.25
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
−0.20
See Figure 1
−0.25
5
10
15
20
80
CD = 100pF
77
CD = 50pF
74
71
CD = 20pF
68
65
See Figure 4
62
25
1
10
Time (ns)
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
TYPICAL DC DRIFT OVER TEMPERATURE
15
0.10
10
VIO
0.05
5
0
0
−0.05
−5
Ib
−0.10
−10
−0.15
−15
−0.20
−20
−0.25
−50
−25
0
25
50
75
Ambient Temperature (_C)
18
Sourcing Output Current
130
16
120
110
12
100
10
90
8
6
Sinking Output Current
70
−50
−25
0
25
50
75
100
4
125
Ambient Temperature (_ C)
COMMON−MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
COMMON−MODE AND DIFFERENTIAL
INPUT IMPEDANCE
107
6
+VIN
Common−Mode
4.7MΩ
4
106
+VOUT
2
0
−2
−VOUT
Input Impedance (Ω )
Voltage Range (V)
14
Supply Current
80
−25
125
100
20
140
Output Current (10mA/div)
20
100 x IOS
Input Bias and Offset Current (µA)
Input Offset Voltage (mV)
150
25
0.15
100
Frequency (MHz)
0.25
0.20
CD = 10pF
Supply Current (2mA/div)
0
RF = 10kΩ
CF Adjusted
20 log(10kΩ)
Transimpedance Gain (dBΩ )
Percent of Final Value (%)
83
G = +10V/V
RL = 100Ω
VO = 2V Step
0.20
105
6.6kΩ
104
Differential
103
−4
−VIN
−6
102
2.5
3.0
3.5
4.0
4.5
Supply Voltage (±V)
5.0
5.5
6.0
102
103
104
105
106
107
108
Frequency (Hz)
9
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
TA = 25°C, G = +10, RF = 453Ω, RG = 50Ω, and RL = 100Ω, unless otherwise noted.
CHANNEL−TO−CHANNEL CROSSTALK
−30
Input−Referred
−35
Crosstalk (5dB/div)
−40
−45
−50
−55
−60
−65
−70
−75
−80
1
10
Frequency (MHz)
10
100
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TYPICAL CHARACTERISTICS: VS = ±5V, DIFFERENTIAL CONFIGURATION
TA = 25°C, G = +10, RF = 1kΩ, RG = 50Ω, and RL = 400Ω, unless otherwise noted.
DIFFERENTIAL SMALL−SIGNAL
FREQUENCY RESPONSE
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
3
+5V
OPA2846
Gain =
VI
RG
50Ω
RF
1kΩ
RG
50Ω
RF
1kΩ
Normalized Gain (dB)
0
RF VO
=
= GD
RG VI
RL
400Ω
VO
OPA2846
GD = +20V/V
RL = 400Ω
VO = 400mVPP
−3
GD = +10V/V
−6
−9
GD = +30V/V
−12
GD = +40V/V
−15
−5V
−18
1
10
100
500
Frequency (MHz)
DIFFERENTIAL LARGE−SIGNAL
FREQUENCY RESPONSE
−60
GD = +20V/V
RL = 400Ω
Gain (dB)
26
23
VO = 0.4VPP
20
VO = 8VPP
17
Harmonic Distortion (dBc)
29
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
−55
VO = 5VPP
−70
−75
−80
−85
3rd−Harmonic
−90
−95
−100
−105
−110
−115
14
1
10
100
50
300
100
150
2nd−Harmonic
−85
3rd−Harmonic
−95
−105
−75
G = +20V/V
f = 5MHz
RL = 400Ω
−80
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
GD = +20V/V
RL = 400Ω
VO = 4VPP
−75
250
300
350
400
450
500
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
−65
200
Resistance (Ω )
Frequency (MHz)
−115
VO = 4VPP
G = 20V/V
2nd−Harmonic
−65
−85
2nd−Harmonic
−90
−95
−100
−105
3rd−Harmonic
−110
−115
1
10
Frequency (MHz)
100
1
10
Output Voltage Swing (VPP)
11
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The OPA2846 provides a unique combination of
features—low input voltage noise along with a very low
distortion output stage—to give one of the highest dynamic
range dual op amps available. Its very high Gain
Bandwidth Product (GBP) can be used either to deliver
high signal bandwidths at high gains, or to deliver very low
distortion signals at moderate frequencies and lower
gains. To achieve the full performance of the OPA2846,
careful attention to printed circuit board (PCB) layout and
component selection is required, as discussed in the
remaining sections of this data sheet.
Figure 1 shows the noninverting gain of +10 circuit used as
the basis of the Electrical Characteristics and most of the
Typical Characteristics. Most of the curves were characterized using signal sources with 50Ω driving impedance,
and with measurement equipment presenting a 50Ω load
impedance. In Figure 1, the 50Ω shunt resistor at the VI
terminal matches the source impedance of the test
generator, while the 50Ω series resistor at the VO terminal
provides a matching resistor for the measurement equipment load. Generally, data sheet voltage swing specifications are at the output pin (VO in Figure 1), while output
power (dBm) specifications are at the matched 50Ω load.
The total 100Ω load at the output, combined with the 503Ω
total feedback network load, presents the OPA2846 with
an effective output load of 83Ω for the circuit of Figure 1.
Operating the OPA2846 as an inverting amplifier has
several benefits and is particularly appropriate when a
matched input impedance is required. Figure 2 shows the
inverting gain circuit used as the basis of the inverting
mode Typical Characteristics.
+5V
+VS
0.1µF
0.1µF
50Ω Source
91Ω
VO
1 /2
O PA 2846
RG
50Ω
6.8µF
50Ω
50Ω Load
RF
1kΩ
VI
0.1µF
6.8µF
−VS
−5V
+5V
+VS
0.1µF
WIDEBAND, INVERTING GAIN OPERATION
+
WIDEBAND, NONINVERTING OPERATION
set to 50Ω and RF adjusted to get the desired gain.
Observing this guideline will ensure that the thermal noise
contribution of the feedback network is insignificant
compared to the 1.2nV/√Hz input voltage noise for the op
amp itself.
+
APPLICATIONS INFORMATION
6.8µF
+
Figure 2. Inverting, G = −20 Characterization
Circuit
50Ω Source
50Ω Load
VI
VO
1/2
O PA 2 846
50Ω
50Ω
RF
453Ω
RG
50Ω
6.8µF
0.1µF
+
−VS
−5V
Figure 1. Noninverting, G = +10 Specification and
Test Circuit
Voltage-feedback op amps, unlike current-feedback
designs, can use a wide range of resistor values to set their
gains. The circuit of Figure 1, and the specifications at
other gains, uses the constraint that RG should always be
12
Driving this circuit from a 50Ω source, and constraining the
gain resistor (RG) to equal 50Ω, will give both a signal
bandwidth and noise advantage. RG acts as both the input
termination resistor and the gain setting resistor for the
circuit. Although the signal gain (VO/VI) for the circuit of
Figure 2 is double that for Figure 1, the noise gains are in
fact equal when the 50Ω source resistor is included. This
has the interesting effect of doubling the equivalent GBP
of the amplifier. This can be seen in comparing the G = +10
and G = −20 small-signal frequency response curves. Both
show approximately 250MHz bandwidth, but the inverting
configuration of Figure 2 gives 6dB higher signal gain. If
the signal source is actually the low impedance output of
another amplifier, RG should be increased to the minimum
load resistance value allowed for that amplifier and RF
should be adjusted to achieve the desired gain. For stable
operation of the OPA2846, it is critical that this driving
amplifier show a very low output impedance at frequencies
beyond the expected closed-loop bandwidth for the
OPA2846.
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
LOW-NOISE VDSL RECEIVER
SINGLE-STAGE TRANSIMPEDANCE DESIGN
Most xDSL transceiver channels are differential for both
the driver and the receiver. The low-noise, high-gain
bandwidth, and low distortion for the dual OPA2846 make
it an ideal receiver channel element for the demanding
requirements emerging in VDSL. One possible implementation is shown in Figure 3. This circuit presumes full
duplex communication using frequency division multiplexing, with send-and-receive isolation improved through the
use of a diplexer line interface. The differential receive
signal is brought into the inverting channel gain resistors
to get both noise and distortion improvement for a given
desired gain setting. To get impedance matching, set 2RG
equal to the required load looking out of the diplexer. The
signal gain is then set by adjusting feedback resistors, RF.
Using the OPA2846 in the inverting mode will give you a
reduced noise gain as described in the Wideband,
Inverting Gain Operation section of this data sheet. This
will improve both the SNR and distortion performance. If
the noise gain for a particular application drops below the
minimum recommended stable gain (+7), consider using
the Low-Gain Compensation technique described later in
this data sheet.
When setting up either one or both stages as a broadband
photodiode amplifier, the key elements in the design are
the expected diode capacitance (CD) with the reverse bias
voltage (−VB) applied, the desired transimpedance gain
RF, and the GBP of the OPA2846 (1650MHz). Figure 4
shows a design using a 10pF source capacitance diode
and a 10kΩ transimpedance gain. With these three
variables set (and including the parasitic input capacitance
for the OPA2846 added to CD), the feedback capacitor
value (CF) may be set to control the frequency response.
+5V
Power−supply decoupling
not shown.
1/2
O P A28 46
VO = ID RF
RF
10kΩ
λ
ID
CD
10pF
−5V
CF
0.3pF
−VB
Figure 4. Wideband, Low-Noise, Transimpedance
Amplifier
1/ 2
OPA28 46
RG
RF
RG
RF
Passive
Filter
Analog
Front
End
Diplexer
1/ 2
OPA28 46
Driver
Low−Noise VDSL Receiver
Figure 3. Low-Noise VDSL Receiver
To achieve a maximally-flat, 2nd-order Butterworth
frequency response, the feedback pole should be set to:
1ń(2pR FCF) + ǸǒGBPń(4pR FC D)Ǔ
(1)
Adding the common-mode and differential mode input
capacitance (1.8 + 2.0)pF to the 10pF diode source
capacitance of Figure 4, and targeting a 10kΩ
transimpedance gain using the 1650MHz GBP for the
OPA2846, will require a feedback pole set to 31MHz. This
will require a total feedback capacitance of 0.5pF. Typical
surface-mount resistors have a parasitic capacitance of
0.2pF, leaving the required 0.3pF value shown in Figure 4
to get the required feedback pole.
13
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
This will give a −3dB bandwidth approximately equal to:
f *3dB + ǸǒGBPń2pRFC DǓHz
(2)
The example of Figure 4 will give approximately 44MHz
flat bandwidth using the 0.3pF feedback compensation.
If the total output noise is bandlimited to a frequency less
than the feedback pole frequency, a very simple
expression for the equivalent input noise current can be
derived as:
I EQ +
Ǹ
ǒ Ǔ
EN
I N ) 4kT )
RF
RF
2
2
(E 2pCDF)
) N
3
(3)
IEQ = Equivalent input noise current if the output noise is
bandlimited to F < 1/(2πRFCF)
IN = Input current noise for the op amp inverting input
EN = Input voltage noise for the op amp
CD = Diode capacitance
F = Bandlimiting frequency in Hz (usually a post filter
prior to further signal processing)
Evaluating this expression up to the feedback pole
frequency at 31MHz for the circuit of Figure 4 gives an
equivalent input noise current of 3.1pA/Hz. This is only
slightly higher than the current noise of the op amp itself.
TWO-STAGE TRANSIMPEDANCE DESIGN
The dual OPA2846 may be used as either a dual
transimpedance channel from two photodetectors, or as a
very high gain stage by using one amplifier as the
transimpedance stage with the second used as a post gain
amplifier. See Figure 5 for an example of using one
channel as a transimpedance front end from a large area
detector, with the second amplifier used as a voltage gain
stage to get a 100kΩ total gain (ZT) from a large 50pF
detector (CD in Figure 5).
1000pF
2.67kΩ
20Ω
1 /2
O P A 28 46
2.67kΩ
732Ω
λ
CD
50pF
20Ω
1.9pF
−VB
Figure 5. High-Gain, Wideband Transimpedance
Amplifier
14
ȡ Z ȣ
+ȧ
ȧ
Ȣ2pC GBPȤ
2
RF
T
D
(4)
Where:
2
Where:
1/2
O P A 2 84 6
One key question in this design is how best to split up the
first and second stage gains. If bandwidth optimization
from a given photodetector capacitance (CD in Figure 5) is
the primary goal, Equation 4 gives a solution for RF in the
input stage that will provide an equal bandwidth in the first
and second stages, giving the maximum overall channel
bandwidth.
ZT = Desired total transimpedance gain
CD = Diode capacitance at reverse bias
GBP = Amplifier Gain Bandwidth Product (MHz)
This equation is used to calculate the required input stage
feedback resistor in Figure 5. The remaining total signal
gain is provided by the second stage; in the example of
Figure 5, setting G = 37.5 gives the same bandwidth
(approximately 44MHz) as the bandwidth achieved by the
input stage. To set this first stage bandwidth to its
maximally flat values, use Equation 5 to set the feedback
capacitor value:
CF +
Ǹǒ
f *3dB + 1
Ǹ2
CD
p RF GBP
(GBP)
(2pC D)
1ń3
Ǔ
(5)
2ń3
(Z T)
1ń3
(6)
The approximate achievable bandwidth in the two stages
is given by Equation 6, which gives approximately 30MHz
for Figure 5.
LOW-GAIN COMPENSATION FOR
IMPROVED SFDR
Where a low gain is desired, and inverting operation is
acceptable, a new external compensation technique may
be used to retain the full slew rate and noise benefits of the
OPA2846 while giving increased loop gain and the
associated improvement in distortion offered by the
decompensated architecture. This technique shapes the
loop gain for good stability while giving an easily-controlled, 2nd-order, low-pass frequency response. Considering only the noise gain (noninverting signal gain, which
is also called the Noise Gain or NG) for the circuit of
Figure 6, the low-frequency noise gain, (NG1) will be set
by the resistor ratios while the high-frequency noise gain
(NG2) will be set by the capacitor ratios. The capacitor
values set both the transition frequencies and the
high-frequency noise gain. If this noise gain (determined
by NG2 = 1 + CS/CF) is set to a value greater than the
recommended minimum stable gain for the op amp, and
the noise gain pole (set by 1/RFCF) is placed correctly, a
very well-controlled, 2nd-order, low-pass frequency
response will result.
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
due to increased loop gain at frequencies below NG1 × Z0.
The capacitor values of Figure 6 are calculated for NG1 =
3 and NG2 = 10 with no adjustment for parasitics.
+5V
1/2
O P A 2846
RG
201Ω
Figure 7 shows the measured frequency response for the
circuit of Figure 6. This shows the expected gain of −2
(6dB) with exceptional flatness through 70MHz and a
−3dB bandwidth of 170MHz. Measured distortion into a
100Ω load shows > 5dB improvement through 20MHz
over the performance shown in the Typical Characteristics. Into a 500Ω load, the 5MHz, 2VPP, 2nd-harmonic
improves from −85dBc to −92dBc.
VO
RF
402Ω
VI
CS
29pF
CF
3.2pF
−5V
Figure 6. Broadband Low-Gain Inverting External
Compensation
9
6
Z 0 + GBP2
NG 1
ƪǒ
1*
Ǔ Ǹ1 * 2 NG
ƫ
NG
NG 1
*
NG 2
1
2
(7)
Physically, this Z0 (12.4MHz for the values shown above)
is set by 1/[2π × RF(CF + CS)] and is the frequency at which
the rising portion of the noise gain would intersect unity
gain if projected back to 0dB gain. The actual zero in the
noise gain occurs at NG1 × Z0, and the pole in the noise
gain occurs at NG2 × Z0. Since GBP is expressed in Hz,
multiply Z0 by 2π and use this to get CF by solving:
CF +
2p
1
R FZ 0NG 2
(+ 3.2pF)
(8)
Finally, since CS and CF set the high-frequency noise gain,
determine CS by:
C S + (NG 2 * 1)CF
(+ 28.8pF)
(9)
The resulting closed-loop bandwidth will be approximately
equal to:
f *3dB ^ ǸZ 0 GBP
(+ 143MHz)
(10)
For the values of Figure 6, the f−3dB will be approximately
130MHz. This is less than that predicted by simply dividing
the GBP by NG1. The compensation network controls the
bandwidth to a lower value while providing the full slew rate
at the output and an exceptional distortion performance
3
Gain (3dB/div)
To choose the values for both CS and CF, two parameters
and only three equations need to be solved. The first
parameter is the target high-frequency noise gain NG2,
which should be greater than the minimum stable gain for
the OPA2846. Here, a target NG2 of 10 will be used. The
second parameter is the desired low-frequency signal
gain, which also sets the low-frequency noise gain NG1. To
simplify this discussion, we will target a maximally-flat,
2nd-order, low-pass Butterworth frequency response
(Q = 0.707). The signal gain of −2 shown in Figure 6 will
set the low-frequency noise gain to NG1 = 1 + RF/RG
(NG1 = 3 in this example). Then, using only these two
gains and the GBP for the OPA2846 (1650MHz), the key
frequency in the compensation can be determined as:
0
−3
−6
−9
−12
−15
1M
10M
100M
1G
Frequency (Hz)
Figure 7. Low Gain Inverting Frequency
Response
DC-COUPLED, SINGLE-TO-DIFFERENTIAL
ADC DRIVER
Many very high performance CMOS ADCs are intended to
operate with a differential input signal. Translating a
single-ended source to this differential input while
controlling the common-mode operating voltage can
present a considerable challenge where high SFDR is
required. See Figure 8 for one way to do this, where very
low harmonic distortion is required, and good commonmode control and DC precision is desired.
This particular example is set for a signal gain of 16 from
the single-ended input to the differential output voltage.
Since the common-mode control signal (from the output of
the OPA820) is fed into the midpoint of the two gain
resistors (93.8Ω), this DC control path requires a very low
source impedance through high frequencies to maintain
the desired signal path gain. A wideband, unity-gain
stable, voltage-feedback op amp like the OPA820 makes
an ideal choice to provide this low output impedance DC
control signal. This op amp also compares the output
common-mode voltage to the desired VCM, and servos the
OPA2846 common-mode output voltage to that value,
using an integrator loop. This holds the output commonmode voltage precisely at VCM while giving the low output
impedance required of the circuit.
15
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
+5V
Power−supply decoupling
not shown.
12Ω
VI
750Ω
95Ω
1/2
OPA2846
50ΩInput
Impedance
200Ω
+5V
1.3µH
V+
750Ω
3.8kΩ
30pF
+5V
93.8Ω
14−Bit
10MSPS
ADS850
100Ω
0.1µF
OPA820
2.01kΩ
2.5V
VCM
+5V
−5V
93.8Ω
1µF
0.1µF
750Ω
93.8Ω
3.8kΩ
750Ω
1/2
OPA2846
49.9Ω
−5V
200Ω
1.3µH
V−
Voltage at V+ to V− = 2VPP
2nd−order Butterworth post filter f−3dB = 18MHz.
Figure 8. DC-Coupled, Single-to-Differential High SFDR ADC Driver
One side of the OPA2846 is operating at a gain of +9 with
some attenuation of the input signal to have an equivalent
+8 gain. The other side of the OPA2846 is operating at a
gain of −8.
To deliver a 2VPP differential input signal on a 2.5V
common-mode voltage, each output must swing between
2.0V and 3.0V. Tested harmonic distortion performance for
this condition from 1MHz to 10MHz is shown in Figure 9.
In this case, the 2nd-harmonic distortion is still dominant
due to slight signal path imbalances. The distortion levels,
however, are very low. Thus, narrowband applications
which are impacted by only 3rd-order terms will see very
low single- and two-tone distortion levels.
16
−70
Harmonic Distortion (dBc)
Operating at +2.5V output common-mode requires a DC
level shifting current through the feedback resistors. Since
this current is to the supply midpoint, pull-up resistors
equal to the feedback resistors are connected to the
positive supply to keep the output stage signal currents
equal and bipolar. This significantly improves 2nd-harmonic distortion.
−75
−80
2nd−Harmonic
−85
3rd−Harmonic
−90
−95
1
10
Frequency (MHz)
Figure 9. Harmonic Distortion vs Frequency for
the Circuit of Figure 8
For more information on the 2nd-order post filter, refer to
RLC Filter Design for ADC Interface Applications
(SBAA108), available for download at www.ti.com.
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
AC-COUPLED, SINGLE-TO-DIFFERENTIAL
ADC DRIVER
Where the signal path may be AC-coupled, a very
balanced, high SFDR dual op amp interface circuit can
easily be provided by the OPA2846. Figure 10 shows a
specific example of this application, where the input
single-to-differential conversion is provided by an input
transformer. Once the signal source is purely differential,
the circuit of Figure 10 provides low harmonic distortion
with a common-mode control path that does not interact
with the signal path gain. If the source is already
differential, such as at the output of a balanced mixer, the
input transformer could be replaced by blocking
capacitors.
In the example of Figure 10, the secondary of the
transformer is connected into the two inverting path gain
resistors (100Ω). These resistors provide both an input
impedance match (assuming a 50Ω source on the primary
of this 1:2 step-up transformer) and set the signal gain for
each amplifier along with the 500Ω feedback resistors.
Although relatively high signal gain is provided by this
Power−supply decoupling
not shown.
VCM
1000pF
circuit (10 in this case), each amplifier is operating at a
relatively low noise gain (3.5V/V). This low-noise gain at
low frequencies gives high loop gain for distortion
suppression in the baseband. External compensation
capacitors (18pF and 2.1pF) are included to hold the
frequency response flat, as described in the Low-Gain
Compensation For Improved SFDR section of this data
sheet. The common-mode operating voltage is fed into
each amplifier’s noninverting input. Since these are equal,
and will appear at each inverting input as well, no DC
current is produced through the transformer secondary
due to this common-mode operating voltage. Since no
current flows due to VCM, the output will operate at VCM as
well. This is one of the few common-mode operating point
control techniques that requires no current to flow. This
makes the common-mode control aspect of this circuit
essentially non-interactive with the signal path. To provide
a 2VPP differential signal operating at a 2.5V output
common-mode requires a 2.0V to 3.0V output swing on
each output. Tested performance over frequency for the
circuit of Figure 10 is shown in Figure 11.
+5V
R1
1/2
OPA2846
L
V+
C
18pF
2.1pF
100Ω
500Ω
R2
14−Bit
10MSPS
ADS850
500Ω
1:2
VI
2.5V
50Ω
VCM
VCM +10VI
100Ω
500Ω
1µF
2.1pF
500Ω
Single−to−Differential
Gain of 10
18pF
VCM
1000pF
L
1/2
OPA2846
V−
R1
C
R2
−5V
Figure 10. AC-Coupled, Single-to-Differential High SFDR ADC Driver
17
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
Harmonic Distortion (dBc)
−80
VO = 2VPP Differential
−85
ORDERING
NUMBER
LITERATURE
NUMBER
OPA2846ID
SO-8 Surface-Mount
DEM-OPA-SO-2A
SBOU003
The demonstration fixture can be requested at the Texas
Instruments web site (www.ti.com) through the OPA2846
product folder.
3rd−Harmonic, +2.5VDC
−95
2nd−Harmonic, +2.5VDC
−100
PACKAGE
Table 1. Evaluation Module Ordering Information
2nd−Harmonic, 0VDC
−90
PRODUCT
MACROMODELS AND APPLICATIONS
SUPPORT
−105
3rd−Harmonic, 0VDC
−110
1
10
Frequency (MHz)
Figure 11. Harmonic Distortion for Figure 10
Figure 11 shows 2nd- and 3rd-harmonic distortion for a
2VPP differential output swing at both 0V output
common-mode voltage and +2.5V common-mode voltage. Since there is no DC current required from the output
to level shift to +2.5V in this circuit, no pull-up resistors to
the power supply were used as in the circuit of Figure 8.
The 2nd harmonic remains the dominant distortion
mechanism, but shows little sensitivity to the commonmode operating voltage (improved 2nd-harmonic distortion results were achieved with this circuit using two
individual OPA846s with an extremely symmetrical
layout). The 3rd harmonic is essentially unmeasureable
for the ground-centered output swing, but increases as the
output is shifted to a +2.5V DC output. Narrowband
systems, where a bandpass filter less than an octave wide
can be inserted between the amplifier and the converter,
will only be concerned about 2-tone, 3rd-order intermodulation distortion. Since this bandpass filter is also
AC-coupled, the outputs of Figure 10 may be operated
ground-centered, giving the extremely low 3rd-order
distortions of Figure 11.
DESIGN-IN TOOLS
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the OPA2846 is available through the
Texas Instruments web page (http://www.ti.com).
These models do a good job of predicting small-signal AC
and transient performance under a wide variety of
operating conditions. They do not do as well in predicting
the harmonic distortion characteristics.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO MINIMIZE
NOISE
The OPA2846 provides a very low input noise voltage
while requiring a low 12.6mA/channel quiescent current.
To take full advantage of this low input noise, careful
attention to the other possible noise contributors is
required. Figure 12 shows the op amp noise analysis
model with all the noise terms included. In this model, all
the noise terms are taken to be noise voltage or current
density terms in either nV/√Hz or pA/√Hz.
ENI
1/2
OPA2846
RS
ERS
RF
√4kTRS
DEMONSTRATION BOARDS
A printed circuit board (PCB) is available to assist in the
initial evaluation of circuit performance using the
OPA2846. The fixture is offered free of charge as an
unpopulated PCB, delivered with a user’s guide. The
summary information for this board is shown in Table 1.
18
EO
IBN
4kT
RG
RG
IBI
√ 4kTRF
4kT = 1.6E − 20J
at 290_K
Figure 12. Op Amp Noise Analysis Model
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
The total output spot noise voltage can be computed as the
square root of the squared contributing terms to the output
noise voltage. This computation adds all the contributing
noise powers at the output by superposition, then takes the
square root to get back to a spot noise voltage.
Equation 11 shows the general form for this output noise
voltage using the terms shown in Figure 12.
EO +
Ǹǒ
(11)
Ǔ
E2NI ) ǒIBNRSǓ ) 4kTR S NG 2 ) ǒIBIRFǓ ) 4kTRFNG
2
2
Dividing this expression by the noise gain
(NG = 1 + RF/RG) will give the equivalent input-referred
spot noise voltage at the noninverting input as shown in
Equation 12.
EN +
Ǹ
E2NI )
ǒIBNRSǓ
2
ǒ Ǔ
I R
) 4kTR S ) BI F
NG
2
4kTR F
)
NG
(12)
Inserting high resistor values into Equation 12 can quickly
dominate the total equivalent input-referred noise. A 105Ω
source impedance on the noninverting input will add a
thermal voltage noise term equal to that of the amplifier
itself. As a simplifying constraint, set RG = RS in
Equation 12 and assume an RS/2 source impedance at
the noninverting input (where RS is the signal source
impedance with another matching RS to ground on the
noninverting input). This results in Equation 13, where
NG > 10 has been assumed to further simplify the
expression.
EN +
Ǹ
(ENI) ) 5 ǒI BR SǓ ) 4kT
4
2
2
ǒ3R2 Ǔ
S
(13)
Evaluating this expression for RS = 50Ω will give a total
equivalent input noise of 1.64nV/√Hz. Note that the NG
has dropped out of this expression. This is valid only for
NG > 10.
FREQUENCY RESPONSE CONTROL
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the GBP shown in the
specifications. Ideally, dividing GBP by the noninverting
signal gain will predict the closed-loop bandwidth. In
practice, this only holds true when the phase margin
approaches 90°, as it does in high gain configurations. At
low gains (with an increased feedback factor), most
high-speed amplifiers will exhibit a more complex
response with lower phase margin. The OPA2846 is
compensated to give a maximally-flat, 2nd-order,
Butterworth, closed-loop response at a noninverting gain
of +10 (see Figure 1). This results in a typical gain of +10
bandwidth of 300MHz, far exceeding that predicted by
dividing the 1650MHz GBP by 10. Increasing the gain will
cause the phase margin to approach 90° and the
bandwidth to more closely approach the predicted value of
(GBP/NG). At a gain of +40, the OPA2846 will show the
41MHz bandwidth predicted using the simple formula and
the typical GBP of 1650MHz.
Inverting operation offers some interesting opportunities to
increase the available GBP. When the source impedance
is matched by the gain resistor (see Figure 2), the signal
gain is (1 + RF/RG) while the noise gain for bandwidth
purposes is (1 + RF/2RG). This cuts the noise gain almost
in half, increasing the minimum stable gain for inverting
operation under these condition to −12 and the equivalent
GBP to 3.2GHz.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter, including
additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high
open-loop gain amplifier like the OPA2846 can be very
susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly
on the output pin. When the amplifier’s open-loop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. Several external solutions to this problem
have been suggested. When the primary considerations
are frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended RS vs
Capacitive Load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA2846. Long
PCB traces, unmatched cables, and connections to
multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and add
the recommended series resistor as close as possible to
the OPA2846 output pin (see the Board Layout section).
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA2846 operating in a gain of +10, the frequency
response at the output pin is very flat to begin with,
allowing relatively small values of RS to be used for low
capacitive loads. As the signal gain is increased, the
unloaded phase margin will also increase. Driving
capacitive loads at higher gains will require lower RS
values than those shown for a gain of +10.
19
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
DISTORTION PERFORMANCE
The OPA2846 is capable of delivering an exceptionally low
distortion signal at high frequencies over a wide range of
gains. The distortion plots in the Typical Characteristics
show the typical distortion under a wide variety of
conditions. Most of these plots are limited to 110dB
dynamic range.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd-harmonic will dominate the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that
the total load includes the feedback network; in the
noninverting configuration, this is sum of (RF + RG), while
in the inverting configuration, it is just RF (see Figure 1 and
Figure 2). Increasing output voltage swing increases
harmonic distortion directly. A 6dB increase in output
swing will generally increase the 2nd-harmonic to 12dB
and the 3rd-harmonic to 18dB. Increasing the signal gain
will also increase the 2nd-harmonic distortion. Again, a
6dB increase in gain will increase the 2nd and 3rd
harmonic by approximately 6dB each, even with constant
output power and frequency. Finally, the distortion
increases as the fundamental frequency increases, due to
the rolloff in the loop gain with frequency. Conversely, the
distortion will improve going to lower frequencies down to
the dominant open-loop pole at approximately 100kHz.
Starting from the −82dBc 2nd-harmonic for a 5MHz, 2VPP
fundamental into a 200Ω load at G = +10 (from the Typical
Characteristics), the 2nd-harmonic distortion for frequencies lower than 100kHz will approximately be:
−82dBc − 20 log(5MHz/100kHz) = −116dBc
The OPA2846 has extremely low 3rd-order harmonic
distortion. This also gives a high 2-tone, 3rd-order
intermodulation intercept as shown in the Typical
Characteristics. This intercept curve is defined at the 50Ω
load when driven through a 50Ω matching resistor to allow
direct comparisons to RF MMIC devices. This matching
network attenuates the voltage swing from the output pin
to the load by 6dB. If the OPA2846 drives directly into the
input of a high impedance device, such as an A/D
converter, the 6dB attenuation is not taken. Under these
conditions, the intercept will increase by a minimum 6dBm.
The intercept is used to predict the intermodulation
spurious for two, closely-spaced frequencies. If the two
test frequencies, f1 and f2, are specified in terms of
average and delta frequency, fO = (f1 + f2)/2 and f = |f2 −
f1|/2, the two 3rd-order, close-in spurious tones will appear
at fO ± 3 × ∆f. The difference between two equal test-tone
power levels and these intermodulation spurious power
levels is given by dBc = 2 × (IM3 − PO) where IM3 is the
intercept taken from the Typical Characteristic and PO is
the power level, in dBm, at the 50Ω load for one of the two
closely-spaced test frequencies. For instance, at 10MHz,
the OPA2846 at a gain of +10 has an intercept of 44dBm
20
at a matched 50Ω load. If the full envelope of the two
frequencies needs to be 2VPP, this requires each tone to
be 4dBm. The 3rd-order intermodulation spurious tones
will then be 2 × (48 − 4) = 88dBc below the test-tone
power level (−84dBm). If this same 2VPP, 2-tone envelope
were delivered directly into the input of an ADC—without
the matching loss or the loading of the 50Ω network—the
intercept would increase to at least 50dBm. With the same
signal and gain conditions, but now driving directly into a
light load, the spurious tones will then be at least
2 × (54 − 4) = 100dBc below the 4dBm test-tone power
levels centered on 10MHz.
DC ACCURACY AND OFFSET CONTROL
The OPA2846 can provide excellent DC signal accuracy
due to its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset
voltage and bias current offset errors. To take full
advantage of its low ±0.65mV input offset voltage, careful
attention to input bias current cancellation is also required.
The low noise input stage of the OPA2846 has a relatively
high input bias current (10µA typical into the pins), but with
a very close match between the two input currents—typically ±100nA input offset current. The total output offset
voltage may be reduced considerably by matching the
source impedances looking out of the two inputs. For
example, one way to add bias current cancellation to the
circuit of Figure 1 (page 12) would be to insert a 20Ω
series resistor into the noninverting input from the 50Ω
terminating resistor. When the 50Ω source resistor is
DC-coupled, this will increase the source resistances for
the noninverting input bias current to 45Ω. Since this is
now equal to the resistance looking out of the inverting
input (RF || RG), the circuit will cancel the gains for the bias
currents to the output, leaving only the offset current times
the feedback resistor as a residual DC error term at the
output. Using the 453Ω feedback resistor, this output error
will now be less than ±0.6µA × 453Ω = ±0.27mV over the
full temperature range.
A fine-scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing a DC offset control into an op amp
circuit. Most of these techniques eventually reduce to
setting up a DC current through the feedback resistor. One
key consideration to selecting a technique is to insure that
it has a minimal impact on the desired signal path
frequency response. If the signal path is intended to be
noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the
signal source. If the signal path is intended to be inverting,
applying the offset control to the noninverting input can be
considered. For a DC-coupled inverting input signal, this
DC offset signal will set up a DC current back into the
source that must be considered. An offset adjustment
placed on the inverting op amp input can also change the
noise gain and frequency response flatness.
"#$%
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
Figure 13 shows one example of an offset adjustment for
a DC-coupled signal path that will have minimum impact
on the signal frequency response. In this case, the input is
brought into an inverting gain resistor with the DC
adjustment an additional current summed into the
inverting node. The resistor values setting this offset
adjustment are much larger than the signal path resistors.
This will insure that this adjustment has minimal impact on
the loop gain and hence, the frequency response as well.
Power−supply decoupling
not shown.
+5V
48Ω
RG
50Ω
5kΩ
1/2
OPA2846
−5V
VO
RF
1kΩ
VI
20kΩ
±200mV Output Adjustment
10kΩ
0.1µF
5kΩ
PD = 10V × (26.6mA) + 2 × [52/(4 × (100Ω || 500Ω))] = 416mW
Maximum TJ = +85°C + (0.416Ω × 125°C/Ω) = 137°C
This absolute worst-case example will never be
encountered in practice. Therefore, 137°C sets an upper
limit to maximum operating junction temperature.
BOARD LAYOUT
+5V
0.1µF
As a worst-case example, compute the maximum TJ using
both channels of the OPA2846ID in the circuit of Figure 1
(page 12) operating at the maximum specified ambient
temperature of +85°C and driving a grounded 100Ω load
at +2.5VDC:
VO
R
= − F = −20
VI
RG
−5V
Figure 13. DC-Coupled, Inverting Gain of −20,
with Output Offset Adjustment
THERMAL ANALYSIS
The OPA2846 will not require heatsinking or airflow in
most applications. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by
TA + PD × qJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional power
dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. PDL
will depend on the required output signal and load but
would, for a grounded resistive load, be at a maximum
when the output is fixed at a voltage equal to 1/2 either
supply voltage (for equal bipolar supplies). Under this
worst-case condition, PDL = VS2/(4 × RL) where RL
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
Achieving optimum performance with a high-frequency
amplifier like the OPA2846 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on the
noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25”) from the
power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and
power-plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to
minimize inductance between the pins and the decoupling
capacitors. The power-supply connections should always
be decoupled with these capacitors. Larger (2.2µF to
6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These
may be placed somewhat farther from the device and may
be shared among several devices in the same area of the
PC board.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA2846. Resistors should be a very
low reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal-film and carbon
composition, axially-leaded resistors can also provide
good high-frequency performance. Again, keep their leads
and PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application.
Since the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Where double-side
component mounting is allowed, place the feedback
21
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SBOS274C −JUNE 2003 − REVISED AUGUST 2008
resistor directly under the package on the other side of the
board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create
significant time constants that can degrade performance.
Good axial metal-film or surface-mount resistors have
approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can add a pole
and/or a zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible,
consistent with load driving considerations. It has been
suggested here that a good starting point for design would
be to set RG to 50Ω. Doing this will automatically keep the
resistor noise terms low, and minimize the effect of their
parasitic capacitance.
d) Connections to other wideband devices on the
board may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the total
capacitive load and set RS from the plot of recommended
RS vs Capacitive Load. Low parasitic capacitive loads
(< 5pF) may not need an RS since the OPA2846 is
nominally compensated to operate with a 2pF parasitic
load. Higher parasitic capacitive loads without an RS are
allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance
transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and
stripline layout techniques). A 50Ω environment is
normally not necessary on board, and in fact, a higher
impedance environment will improve distortion, as shown
in the distortion versus load plots. With a characteristic
board trace impedance defined based on board material
and trace dimensions, a matching series resistor into the
trace from the output of the OPA2846 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance
will be the parallel combination of the shunt resistor and
the input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-terminated
22
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as
a capacitive load in this case and set the series resistor
value as shown in the plot, RS vs Capacitive Load. This will
not preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low,
there will be some signal attenuation due to the voltage
divider formed by the series output into the terminating
impedance.
e) Socketing a high-speed part like the OPA2846 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an
extremely troublesome parasitic network, which can make
it almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA2846 onto the board.
INPUT AND ESD PROTECTION
The OPA2846 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small
geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are
protected with internal ESD protection diodes to the power
supplies, as shown in Figure 13.
+VCC
External
Pin
Internal
Circuitry
−VCC
Figure 14. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA continuous
current. Where higher currents are possible (for example,
in systems with ±15V supply parts driving into the
OPA2846), current-limiting series resistors should be
added into the two inputs. Keep these resistor values as
low as possible since high values degrade both noise
performance and frequency response.
www.ti.com
SBOS274C −JUNE 2003 − REVISED AUGUST 2008
Revision History
DATE
REV
PAGE
SECTION
8/08
C
2
Absolute Maximum Ratings
5/06
B
18
Design-In Tools
DESCRIPTION
Changed Storage Temperature minimum value from −40°C to −65°C.
Demonstration fixture number changed.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
23
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2846ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2846
OPA2846IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2846
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA2846IDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2846IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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