Texas Instruments | Low-Power, Dual Current Feedback Operational Amplifier (Rev. D) | Datasheet | Texas Instruments Low-Power, Dual Current Feedback Operational Amplifier (Rev. D) Datasheet

Texas Instruments Low-Power, Dual Current Feedback Operational Amplifier (Rev. D) Datasheet
OPA2684
OPA
268
4
SBOS239D – APRIL 2002 – REVISED JULY 2008
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Low-Power, Dual Current-Feedback
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
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MINIMAL BANDWIDTH CHANGE VERSUS GAIN
170MHz BANDWIDTH AT G = +2
> 120MHz BANDWIDTH TO GAIN > +10
LOW DISTORTION: < –82dBc at 5MHz
HIGH OUTPUT CURRENT: 120mA
SINGLE +5V TO +12V SUPPLY OPERATION
DUAL ±2.5 TO ±6.0V SUPPLY OPERATION
LOW SUPPLY CURRENT: 3.4mA Total
DESCRIPTION
The OPA2684 provides a new level of performance in lowpower, wideband, current-feedback (CFB) amplifiers. This
CFBPLUS amplifier is among the first to use an internally
closed-loop input buffer stage that enhances performance
significantly over earlier low-power CFB amplifiers. While
retaining the benefits of very low power operation, this new
architecture provides many of the benefits of a more ideal
CFB amplifier. The closed-loop input stage buffer gives a
very low and linearized impedance path at the inverting input
to sense the feedback error current. This improved inverting
input impedance retains exceptional bandwidth to much
higher gains and improves harmonic distortion over earlier
solutions limited by inverting input linearity. Beyond simple
high-gain applications, the OPA2684 CFBPLUS amplifier permits the gain setting element to be set with considerable
SHORT-LOOP ADSL CO DRIVER
LOW-POWER BROADCAST VIDEO DRIVERS
DIFFERENTIAL EQUALIZING FILTERS
DIFFERENTIAL SAW FILTER POST AMPLIFIER
MULTICHANNEL SUMMING AMPLIFIERS
PROFESSIONAL CAMERAS
ADC INPUT DRIVERS
freedom from amplifier bandwidth interaction. This allows
frequency response peaking elements to be added, multiple
input inverting summing circuits to have greater bandwidth,
and low-power line drivers to meet the demanding requirements of studio cameras and broadcast video.
The output capability of the OPA2684 also sets a new mark
in performance for low-power, current-feedback amplifiers.
Delivering a full ±4Vp-p swing on ±5V supplies, the OPA2684
also has the output current to support > ±3Vp-p into 50Ω
loads. This minimal output headroom requirement is complemented by a similar 1.2V input stage headroom giving
exceptional capability for single +5V operation.
The OPA2684’s low 3.4mA supply current is precisely trimmed
at +25°C. This trim, along with low shift over temperature and
supply voltage, gives a very robust design over a wide range
of operating conditions.
BW (MHz) vs GAIN
1 of 2 Channels
+
6
Normalized Gain (3dB/div)
V+
VO
Z(S) IERR
V–
IERR
RF
0
–3
G=5
–6
–9
–12
G = 10
G = 20
–15
–18
–21
G = 50
G = 100
RF = 800Ω
–24
10
RG
Low-Power
G=1
G=2
3
Amplifier
100
200
MHz
US Patent #6,724,260
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation ................................. See Thermal Information
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: ID, IDBV ......................... –65°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
ESD Rating: Human Body Model (HBM) ........................................ 2000V
Charged Device Model (CDM) .................................. 1500V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
OPA2684 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
QUADS
OPA684
OPA691
OPA685
OPA2683
OPA2691
—
OPA3684
OPA3691
—
OPA2684
—
—
FEATURES
Low-Power CFBPLUS
High Slew Rate CFB
> 500MHz CFB
PACKAGE/ORDERING INFORMATION(1)
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA2684
SO-8
D
–40°C to +85°C
OPA2684
"
"
"
"
"
OPA2684ID
OPA2684IDR
Rails, 100
Tape and Reel, 2500
OPA2684
SOT23-8
DCN
–40°C to +85°C
A84
OPA2684IDCNT
Tape and Reel, 250
"
"
"
"
"
OPA2684IDCNR
Tape and Reel, 3000
PRODUCT
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at
www.ti.com.
PIN CONFIGURATION
Top View
SO
Top View
OPA2684
Out A
1
8
+VS
–In A
2
7
Out B
+In A
3
6
–In B
–VS
4
5
+In B
SOT
Out A
1
8
+VS
–In A
2
7
Out B
+In A
3
6
–In B
–VS
4
5
+In B
A84
Pin 1
2
OPA2684
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SBOS239D
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RF = 800Ω, RL = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted.
OPA2684ID, IDCN
TYP
PARAMETER
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (VO = 0.5Vp-p)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
Channel-to-Channel Isolation
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Common-Mode Input Range(5) (CMIR)
Common-Mode Rejection Ratio (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Voltage Output Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Minimum Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (–PSRR)
TEMPERATURE RANGE
Specification: ID, IDCN
Thermal Resistance, θJA
D
SO-8
DCN SOT23-8
+25°C
CONDITIONS
G = +1, RF = 800Ω
G = +2, RF = 800Ω
G = +5, RF = 800Ω
G = +10, RF = 800Ω
G = +20, RF = 800Ω
G = +2, VO = 0.5Vp-p, RF = 800Ω
RF = 800Ω, VO = 0.5Vp-p
G = +2, VO = 4Vp-p
G = –1, VO = 4V Step
G = +2, VO = 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 4V Step
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω
RL ≥ 1kΩ
RL = 100Ω
RL ≥ 1kΩ
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
f = 5MHz
VO = 0V, RL = 1kΩ
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
250
170
138
120
95
19
1.4
90
780
750
3
3.8
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
120
118
117
16
4.8
14
5.9
14
6.3
675
680
650
660
575
656
–59
–66
–66
–82
4.1
11
18
–59
–65
–65
–81
4.2
12
18.5
160
typ
min
typ
typ
typ
min
max
typ
min
min
typ
typ
C
B
C
C
C
B
B
C
B
B
C
C
–58
–65
–65
–81
4.4
12.5
19
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
deg
dB
max
max
max
max
max
max
max
typ
typ
typ
B
B
B
B
B
B
B
C
C
C
155
±4.4
±12
±12.5
±25
±18.5
±35
153
±4.6
±12
±13
±30
±19.5
±40
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±3.65
52
±3.6
52
V
dB
kΩ || pF
Ω
min
min
typ
typ
A
A
C
C
130
–100
±3.9
125
–95
±3.8
120
–90
V
mA
mA
Ω
min
min
min
typ
A
A
A
C
±6
±6
±6
1.8
1.6
54
1.85
1.55
53
1.85
1.45
53
V
V
V
mA
mA
dB
typ
max
min
max
min
typ
C
A
C
A
A
A
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
–67
–82
–70
–84
3.7
9.4
17
0.04
0.02
70
±3.8
±5.0
±11
±5.0
±17
±3.65
Open-Loop, DC
±3.75
60
50 || 2
4.0
1kΩ Load
VO = 0
VO = 0
G = +2, f = 100kHz
±4.1
160
–120
0.006
±3.9
±5
VS = ±5V/per channel
VS = ±5V/per channel
Input Referred
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
V/µs
ns
ns
355
±1.5
VCM = 0V
UNITS
±1.4
1.7
1.7
60
Junction-to-Ambient
53
NOTES: (1) Junction temperature = ambient for +25°C tested specifications.
(2) Junction temperature = ambient at low temperature limit, junction temperature = ambient +2°C at high temperature limit for over temperature tested
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
OPA2684
SBOS239D
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3
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
RF = 1kΩ, RL = 100Ω, and G = +2, (see Figure 3 for AC performance only), unless otherwise noted.
OPA2684ID, IDCN
TYP
PARAMETER
AC PERFORMANCE (see Figure 3)
Small-Signal Bandwidth (VO = 0.5Vp-p)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
Channel-to-Channel Isolation
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Refection Ratio (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Specified Single-Supply Operating Voltage
Max Single-Supply Operating Voltage Range
Min Single-Supply Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
+25°C
CONDITIONS
G = +1, RF = 1.0kΩ
G = +2, RF = 1.0kΩ
G = +5, RF = 1.0kΩ
G = +10, RF = 1.0kΩ
G = +20, RF = 1.0kΩ
G = +2, VO < 0.5Vp-p, RF = 1.0kΩ
RF = 1.0kΩ, VO < 0.5Vp-p
G = 2, VO = 2Vp-p
G = 2, VO = 2V Step
G = 2, VO = 0.5V Step
G = 2, VO = 2VStep
G = 2, f = 5MHz, VO = 2Vp-p
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
f = 5MHz
VO = VS/2, RL = 1kΩ to VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
140
110
100
90
75
21
0.5
86
380
4.3
4.8
–65
–84
–65
–74
3.7
9.4
17
0.04
0.07
70
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
86
85
82
12
2.6
11
3.4
10
3.7
300
290
280
–60
–62
–64
–70
4.1
11
18
–59
–61
–63
–70
4.2
12
18.5
160
UNITS
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
typ
min
min
typ
typ
min
max
typ
min
typ
typ
C
B
C
C
C
B
B
C
B
C
C
–59
–61
–63
–69
4.4
12.5
19
dBc
dBc
dBc
dBc
nV/ √Hz
pA/ √Hz
pA/ √Hz
%
deg
dB
max
max
max
max
max
max
max
typ
typ
typ
B
B
B
B
B
B
B
C
C
C
155
±3.9
±12
±12.5
±25
±14.5
±25
153
±4.1
±12
±13
±30
±16
±30
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
355
±1.0
±3.3
±5
±11
±5
±13
1.32
3.68
52
1.35
3.65
51
1.38
3.62
51
Open-Loop
1.25
3.75
58
50 || 1
4.4
V
V
dB
kΩ || pF
Ω
max
min
min
typ
typ
A
A
A
C
C
RL = 1kΩ to VS/2
RL = 1kΩ to VS/2
VO = VS/2
VO = VS/2
G = +2, f = 100kHz
4.10
0.9
80
70
0.006
3.9
1.1
65
55
3.9
1.1
60
50
3.8
1.2
55
45
V
V
mA
mA
Ω
min
max
min
min
typ
A
A
A
A
C
12
12
12
1.55
1.30
1.55
1.20
1.55
1.15
V
V
V
mA
mA
dB
typ
max
min
max
min
typ
C
A
C
A
A
C
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
VCM = VS/2
5
VS = +5V/per Channel
VS = +5V/per Channel
Input Referred
TEMPERATURE RANGE
Specification: ID, IDBV
Thermal Resistance, θJA Junction-to-Ambient
D
SO-8
DCN SOT23-8
2.8
1.45
1.45
58
NOTES: (1) Junction temperature = ambient for +25°C tested specifications.
(2) Junction temperature = ambient at low temperature limit, junction temperature = ambient +1°C at high temperature limit for over temperature tested
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
4
OPA2684
www.ti.com
SBOS239D
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
VO = 0.5Vp-p
RF = 800Ω
3
G=1
G=2
0
–3
–6
G=5
G = 10
–9
G = 20
–12
G = 50
–15
See Figure 1
VO = 0.5Vp-p
RF = 800Ω
0
–3
–6
G = 100
–18
See Figure 2
–12
1
10
100
200
1
10
Frequency (MHz)
G = +2
RL = 100Ω
VO = 0.5Vp-p
G = –1
RL = 100Ω
VO = 0.5Vp-p
0
Gain (dB)
Gain (dB)
200
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
3
6
VO = 1Vp-p
3
1Vp-p
–3
2Vp-p
5Vp-p
–6
VO = 2Vp-p
0
VO = 5Vp-p
–9
See Figure 1
–3
See Figure 2
–12
1
10
100
200
1
10
Frequency (MHz)
0.8
1.6
0.6
1.2
Large-Signal Right Scale
0.2
0.8
0.4
Small-Signal Left Scale
0
0
–0.2
–0.4
–0.4
–0.8
–0.6
Output Voltage (200mV/div)
G = –1
Output Voltage (400mV/div)
G = +2
–1.2
0.6
1.2
0.4
0.8
0.2
0.4
0
0
Small-Signal Left Scale
–0.2
–0.4
Large-Signal Right Scale
–0.4
–0.6
See Figure 1
–0.8
–1.2
See Figure 2
–0.8
–1.6
Time (10ns/div)
–0.8
–1.6
Time (10ns/div)
OPA2684
SBOS239D
200
INVERTING PULSE RESPONSE
1.6
0.4
100
Frequency (MHz)
NONINVERTING PULSE RESPONSE
0.8
Output Voltage (200mV/div)
100
Frequency (MHz)
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
9
G = –1
G = –2
G = –5
G = –10
G = –16
–9
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5
Output Voltage (400mV/div)
Normalized Gain (3dB/div)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
3
Normalized Gain (3dB/div)
6
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
–50
–50
VO = 2Vp-p
f = 5MHz
G = +2
–60
VO = 2Vp-p
RL = 100Ω
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
–65
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–85
See Figure 1
–90
See Figure 1
–90
100
0.1
1k
1
–50
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
f = 5MHz
RL = 100Ω
–60
–70
3rd-Harmonic
–80
0.5
1
VO = 2Vp-p
RL = 100Ω
5
2nd-Harmonic
–60
–70
3rd-Harmonic
–80
–90
±2.5
–90
±3
±3.5
Output Voltage (Vp-p)
±4
±4.5
±5
Supply Voltage (±V)
±5.5
±6
HARMONIC DISTORTION vs INVERTING GAIN
HARMONIC DISTORTION vs NONINVERTING GAIN
–50
–50
–55
–55
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
20
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
–50
–60
–65
–70
–75
3rd-Harmonic
–80
2nd-Harmonic
–60
–65
–70
3rd-Harmonic
–75
–80
–85
–85
See Figure 1
See Figure 2
–90
–90
1
10
1
20
10
20
Inverting Gain (V/V)
Noninverting Gain (V/V)
6
10
Frequency (MHz)
Load Resistance (Ω)
OPA2684
www.ti.com
SBOS239D
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
INPUT VOLTAGE AND CURRENT NOISE DENSITY
–50
100
20MHz
3rd-Order Spurious Level (dBc)
Noninverting Current Noise
9.4pA/√Hz
10
Voltage Noise
3.7nV/√Hz
1
+5V
–60
PI
50Ω
50Ω
PO
OPA2684
10MHz
50Ω
–5V
800Ω
–70
800Ω
5MHz
–80
1MHz
–90
100
1k
10k
100k
1M
10M
–8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5
Power at Load (PO each tone, dBm)
Frequency (Hz)
9
12pF
0.5dB Peaking
8
5pF
6
Normalized Gain (dB)
40
RS (Ω)
7
SMALL-SIGNAL BANDWIDTH vs CLOAD
RS vs CLOAD
50
30
20
100pF
3
+5V
75pF
RS
VI
0
VO
50Ω OPA2684
CL
1kΩ
–5V
800Ω
–3
10
1kΩ is
Optional
800Ω
1
10
1
100
CMRR and PSRR vs FREQUENCY
Open-Loop Transimpedance Gain (dBΩ)
60
50
+PSRR
40
–PSRR
30
20
10
0
105
106
Frequency (Hz)
107
108
120
0
20log (ZOL)
100
–30
80
–60
60
www.ti.com
–90
∠ ZOL
40
–120
20
–150
0
–180
102
OPA2684
SBOS239D
300
OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE
CMRR
104
100
Frequency (MHz)
70
103
33pF
10
CLOAD (pF)
102
50pF
20pF
–6
0
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
6
103
104
105
106
Frequency (Hz)
107
108
109
7
Open-Loop Phase (°)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
Inverting Current Noise
17pA/√Hz
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
OUTPUT CURRENT AND VOLTAGE LIMITATIONS
3
0.07
2
0.06
dG
0.05
1W Power
Limit
=1
00Ω
0.08
VO (V)
50
Ω
1
0
–1
0.04
–2
0.03
dP
0.02
–3
0.01
–4
0
–5
1
2
3
4
Each
Channel
–150
1W Power
Limit
Number of 150Ω Video Loads
0
IO (mA)
TYPICAL DC DRIFT OVER AMBIENT TEMPERATURE
SUPPLY AND OUTPUT CURRENT
vs AMBIENT TEMPERATURE
4
–100
–50
50
100
150
3.8
200
Output Current (mA)
2
1
Noninverting Input Bias Current
Input Offset Voltage
0
–1
–2
3.6
175
Supply Current
3.4
150
Sinking Output Current
125
3.2
Inverting Input Bias Current
–3
–4
3
100
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
Ambient Temperature (°C)
Ambient Temperature (°C)
125
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
SETTLING TIME
100
0.05
2V Step
See Figure 1
0.04
0.03
Output Impedance (Ω)
Error to Final Value (%)
100
0.02
0.01
0
–0.01
–0.02
1/2
OPA2684
10
ZO
800Ω
800Ω
1
0.01
–0.03
–0.04
0.001
–0.05
0
8
10
20
30
Time (ns)
40
50
100
60
1k
10k
100k
1M
10M
100M
Frequency (Hz)
OPA2684
www.ti.com
SBOS239D
Supply Current (mA)
Sourcing Output Current
3
Input Bias Currents (µA)
and Offset Voltage (mV)
=
RL
RL = 500Ω
Differential Gain (%)
Differential Phase (°)
4
L
Gain = +2
NTSC, Positive Video
0.09
R
5
0.10
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
8.0
8.0
3.2
6.4
6.4
6.4
2.4
4.8
4.8
4.8
1.6
3.2
1.6
0
–0.8
0
Output Voltage
Right-Scale
–1.6
See Figure 1
–1.6
–2.4
–3.2
–3.2
–4.8
Input Voltage
Left-Scale
–4.0
Input Voltage (1.6V/div)
0.8
Output Voltage (1.6V/div)
Input Voltage (0.8V/div)
8.0
3.2
3.2
Output Voltage
Right-Scale
1.6
1.6
0
0
–1.6
–1.6
–3.2
–3.2
–4.8
–6.4
–6.4
–8.0
–8.0
Input Voltage
Left-Scale
–4.8
See Figure 2
–6.4
–8.0
Time (100ns/div)
Time (100ns/div)
Input and Output Voltage Range (V)
INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
Input
Voltage
Range
±2
±3
Output
Voltage
Range
±4
±5
±6
± Supply Voltage (V)
OPA2684
SBOS239D
www.ti.com
9
Output Voltage (1.6V/div)
INVERTING OVERDRIVE RECOVERY
NONINVERTING OVERDRIVE RECOVERY
4.0
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, RL = 100Ω, unless otherwise noted.
DIFFERENTIAL PERFORMANCE
TEST CIRCUIT
DIFFERENTIAL SMALL-SIGNAL
FREQUENCY RESPONSE
6
+5V
VO = 200mVp-p
3
RG
VI
Normalized Gain (dB)
GD = 804Ω
RG
1/2
OPA2684
800Ω
RG
RL
800Ω
VO
G=1
0
G=2
–3
–6
–9
G=5
–12
G = 10
–15
–18
G = 20
–21
1/2
OPA2684
–24
1
10
–5V
DIFFERENTIAL LARGE-SIGNAL
FREQUENCY RESPONSE
9
–55
VO = 4Vp-p
GD = 2
f = 5MHz
Harmonic Distortion (dBc)
Normalized Gain (dB)
6
GD = 2
RL = 100Ω
VO = 1Vp-p
0
VO = 2Vp-p
–3
VO = 5Vp-p
–6
200
DIFFERENTIAL DISTORTION
vs LOAD RESISTANCE
VO = 0.2Vp-p
3
100
Frequency (MHz)
–9
–12
–60
3rd-Harmonic
–65
–70
–75
2nd-Harmonic
–80
–15
–85
–18
1
10
100
200
10
100
Frequency (Hz)
DIFFERENTIAL DISTORTION
vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
–55
VO = 4Vp-p
GD = 2
RL = 100Ω
–60
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
2nd-Harmonic
–65
–70
–75
3rd-Harmonic
–80
–85
–60
–65
f = 5MHz
GD = 2
RL = 100Ω
–70
3rd-Harmonic
–75
–80
–85
1
10
1
Frequency (MHz)
10
1k
Load Resistance (Ω)
10
Output Voltage (Vp-p)
OPA2684
www.ti.com
SBOS239D
TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, VS = 5V, G = +2, RF = 1.0kΩ, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
RF = 1kΩ
3
Normalized Gain (3dB/div)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
3
G = 50
RF = 1.0kΩ
G=1
G = 100
Normalized Gain (3dB/div)
6
0
G=2
–3
–6
G = 20
–9
G = 10
–12
0
–3
–6
G = –1
G = –2
G = –5
G = –10
G = –20
–9
–15
G=5
See Figure 3
See Figure 4
–12
–18
1
10
100
1
200
10
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
3
VO = 0.2Vp-p
0.5Vp-p
VO = 0.5Vp-p
0
6
1Vp-p
Gain (dB)
Gain (dB)
200
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
9
0.2Vp-p
100
Frequency (MHz)
Frequency (MHz)
3
2Vp-p
VO = 1Vp-p
–3
VO = 2Vp-p
–6
0
–9
–3
–12
10
100
200
1
10
Frequency (MHz)
NONINVERTING PULSE RESPONSE
200
INVERTING PULSE RESPONSE
1.6
0.4
1.6
0.3
1.2
0.3
1.2
0.2
0.8
0.1
0.4
0.2
Large-Signal Right Scale
0.1
0.8
0.4
Small-Signal Left Scale
0
0
–0.1
–0.4
–0.2
–0.8
–0.3
Output Voltage (200mV/div)
0.4
Output Voltage (400mV/div)
Output Voltage (200mV/div)
100
Frequency (MHz)
–1.2
0
–0.1
–0.4
Large-Signal Right Scale
–0.2
–0.3
See Figure 3
–0.8
–1.2
See Figure 4
–0.4
–1.6
Time (10ns/div)
–0.4
–1.6
Time (10ns/div)
OPA2684
SBOS239D
0
Small-Signal Left Scale
www.ti.com
11
Output Voltage (400mV/div)
1
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
At TA = +25°C, VS = 5V, G = +2, RF = 1.0kΩ, and RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
–50
–50
VO = 2Vp-p
f = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
VO = 2Vp-p
RL = 100Ω
–60
3rd-Harmonic
–65
–70
–75
–80
2nd-Harmonic
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–85
See Figure 3
–90
100
0.1
1k
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
20
3rd-Order Spurious Level (dBc)
–50
–60
3rd-Harmonic
–70
–80
See Figure 3
0.5
20MHz
–60
10MHz
–70
5MHz
–80
See Figure 3
–90
1
2
3
–15 –14 –13 –12 –11 –10 –9
Output Voltage (Vp-p)
2.9
–6
–5
–4 –3
0.16
G = +2
NTSC, Positive Video
0.14
Right-Scale
Supply Current
2.7
Left-Scale
Sourcing Output Current
70
2.6
Left-Scale
Sinking Output Current
60
Differential Gain (%)
Differential Phase (°)
2.8
Supply Current (mA)
80
–7
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
100
90
–8
Power at Load (each tone, dBm)
SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
Output Current (mA)
10
Frequency (MHz)
2nd-Harmonic
–90
1
Load Resistance (Ω)
–50
Harmonic Distortion (dBc)
See Figure 3
–90
2.5
0.12
0.10
dP
0.08
0.06
0.04
dG
0.02
50
2.4
–50
12
–25
0
25
50
75
Ambient Temperature (°C)
100
125
0
1
2
3
4
Number of 150Ω Video Loads
OPA2684
www.ti.com
SBOS239D
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
At TA = +25°C, VS = 5V, G = +2, RF = 1.0Ω, and RL = 100Ω, unless otherwise noted.
DIFFERENTIAL PERFORMANCE
TEST CIRCUIT
DIFFERENTIAL SMALL-SIGNAL
FREQUENCY RESPONSE
6
+5V
VO = 200mVp-p
RL = 100Ω
3
0.01µF
VI
0.01µF
1/2
OPA2684
RG
Normalized Gain (dB)
GD =
+2.5V
1kΩ
RG
1kΩ
RL
1kΩ
RG
VO
G=1
G=2
0
–3
–6
–9
G=5
–12
–15
–18
G = 20
–21
1/2
OPA2684
G = 10
–24
1
+2.5V
10
100
200
Frequency (MHz)
DIFFERENTIAL LARGE-SIGNAL
FREQUENCY RESPONSE
9
DIFFERENTIAL DISTORTION
vs LOAD RESISTANCE
–55
VO = 200mVp-p
VO = 4Vp-p
GD = 2
f = 5MHz
VO = 5Vp-p
GD = 2
RL = 100Ω
3
Harmonic Distortion (dBc)
Normalized Gain (dB)
6
VO = 2Vp-p
0
VO = 1Vp-p
–3
–6
–9
–12
–60
3rd-Harmonic
–65
–70
–75
2nd-Harmonic
–80
–15
–85
–18
1
10
100
200
10
Frequency (MHz)
DIFFERENTIAL DISTORTION vs FREQUENCY
–60
–65
1k
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
–55
VO = 2Vp-p
RL = 100Ω
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
100
Load Resistance (Ω)
2nd-Harmonic
–70
–75
–80
–60
–65
3rd-Harmonic
–70
–75
–80
3rd-Harmonic
–85
–85
1
10
1
Frequency (MHz)
OPA2684
SBOS239D
10
Output Voltage (Vp-p)
www.ti.com
13
APPLICATIONS INFORMATION
LOW-POWER, CURRENT-FEEDBACK OPERATION
The dual channel OPA2684 gives a new level of performance in low-power, current-feedback op amps. Using a
new input stage buffer architecture, the OPA2684 CFBPLUS
amplifier holds nearly constant AC performance over a wide
gain range. This closed-loop internal buffer gives a very low
and linearized impedance at the inverting node, isolating the
amplifier’s AC performance from gain element variations.
This allows both the bandwidth and distortion to remain
nearly constant over gain, moving closer to the ideal currentfeedback performance of gain bandwidth independence.
This low-power amplifier also delivers exceptional output
power—its ±4V swing on ±5V supplies with > 100mA output
drive gives excellent performance into standard video loads
or doubly-terminated 50Ω cables. This dual-channel device
can provide adequate drive for several emerging differential
driver applications with exceptional power efficiency. Single
+5V supply operation is also supported with similar bandwidths but reduced output power capability. For lower quiescent power in a dual CFBPLUS amplifier, consider the OPA2683
while for higher output power in a dual current-feedback op
amp, consider the OPA2691 or OPA2677.
Figure 2 shows the DC-coupled, gain of –1V/V, dual powersupply circuit used as the basis of the Inverting Typical
Characteristics for each channel. Inverting operation offers
several performance benefits. Since there is no commonmode signal across the input stage, the slew rate for inverting
operation is typically higher and the distortion performance is
slightly improved. An additional input resistor, RM, is included
in Figure 2 to set the input impedance equal to 50Ω. The
parallel combination of RM and RG set the input impedance.
As the desired gain increases for the inverting configuration,
RG is adjusted to achieve the desired gain, while RM is also
adjusted to hold a 50Ω input match. A point will be reached
where RG will equal 50Ω, RM is removed, and the input match
is set by RG only. With RG fixed to achieve an input match to
50Ω, increasing RF will increase the gain. This will, however,
reduce the achievable bandwidth as the feedback resistor
increases from its recommended value of 800Ω. If the source
does not require an input match to 50Ω, either adjust RM to
get the desired load, or remove it and let the RG resistor
alone provide the input load.
+5V
Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit used as the basis of the ±5V Electrical and
Typical Characteristics for each channel. For test purposes,
the input impedance is set to 50Ω with a resistor to ground,
and the output impedance is set to 50Ω with a series output
resistor. Voltage swings reported in the characteristics are
taken directly at the input and output pins while load powers
(dBm) are defined at a matched 50Ω load. For the circuit of
Figure 1, the total effective load will be 100Ω || 1600Ω = 94Ω.
Gain changes are most easily accomplished by simply resetting the RG value, holding RF constant at its recommended
value of 800Ω.
0.1µF
+
6.8µF
50Ω
1/2
OPA2684
50Ω Load
50Ω Source
RG
800Ω
RF
800Ω
VI
RM
53.6Ω
0.1µF
+
6.8µF
–5V
FIGURE 2. DC-Coupled, G = –1V/V, Bipolar Supply Specifications and Test Circuit.
+5V
0.1µF
+
These circuits show ±5V operation. The same circuit can be
applied with bipolar supplies from ±2.5V to ±6V. Internal
supply independent biasing gives nearly the same performance for the OPA2684 over this wide range of supplies.
Generally, the optimum feedback resistor value (for nominally flat frequency response at G = +2) will increase in value
as the total supply voltage across the OPA2684 is reduced
from ±5V.
6.8µF
VI
50Ω Source
RM
50Ω
50Ω
1/2
OPA2684
50Ω Load
RF
800Ω
RG
800Ω
0.1µF
+
6.8µF
–5V
FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply Specifications and Test Circuit.
14
See Figure 3 for the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis only for the +5V
Electrical and Typical Characteristics for each channel. The
key requirement of broadband single-supply operation is to
maintain input and output signal swings within the useable
voltage ranges at both the input and the output. The circuit
of Figure 3 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 10kΩ resistors) to
the noninverting input. The input signal is then AC-coupled
OPA2684
www.ti.com
SBOS239D
into this midpoint voltage bias. The input voltage can swing
to within 1.25V of either supply pin, giving a 2.5Vp-p input
signal range centered between the supply pins. The input
impedance of Figure 3 is set to give a 50Ω input match. If the
source does not require a 50Ω match, remove this and drive
directly into the blocking capacitor. The source will then see
the 5kΩ load of the biasing network. The gain resistor (RG)
is AC-coupled, giving the circuit a DC gain of +1, which puts
the noninverting input DC bias voltage (2.5V) on the output
as well. The feedback resistor value has been adjusted from
the bipolar ±5V supply condition to re-optimize for a flat
frequency response in +5V only, gain of +2, operation. On a
single +5V supply, the output voltage can swing to within
1.0V of either supply pin while delivering more than 70mA
output current giving 3V output swing into 100Ω (8dBm
maximum at a matched 50Ω load). The circuit of Figure 3
shows a blocking capacitor driving into a 50Ω output resistor
then into a 50Ω load. Alternatively, the blocking capacitor
could be removed if the load is tied to a supply midpoint or
to ground if the DC current required by the load is acceptable.
of a current-feedback amplifier, wideband operation is retained even under this condition.
The circuits of Figure 3 and 4 show single-supply operation
at +5V. These same circuits may be used up to single
supplies of +12V with minimal change in the performance of
the OPA2684.
+5V
0.1µF
+
6.8µF
10kΩ
10kΩ
0.1µF
1/2
OPA2684
0.1µF 50Ω
50Ω Load
50Ω Source
RF
1kΩ
RG
0.1µF 1kΩ
VI
RM
52.3Ω
+5V
0.1µF
+
FIGURE 4. AC-Coupled, G = –1V/V, Single-Supply Specifications and Test Circuit.
6.8µF
10kΩ
50Ω Source
0.1µF
DIFFERENTIAL INTERFACE APPLICATIONS
VI
RM
50Ω
10kΩ
1/2
OPA2684
0.1µF 50Ω
Dual op amps are particularly suitable to differential input to
differential output applications. Typically, these fall into either
Analog-to-Digital Converter (ADC) input interface or line
driver applications. Two basic approaches to differential I/O
are noninverting or inverting configurations. Since the output
is differential, the signal polarity is somewhat meaningless—
the noninverting and inverting terminology applies here to
where the input is brought into the OPA2684. Each has its
advantages and disadvantages. Figure 5 shows a basic
starting point for noninverting differential I/O applications.
50Ω Load
RF
1kΩ
RG
1kΩ
0.1µF
FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply Specifications and Test Circuit.
+VCC
Figure 4 shows the AC-coupled, single +5V supply, gain of
–1V/V circuit configuration used as a basis for the +5V
Typical Characteristics for each channel. In this case, the
midpoint DC bias on the noninverting input is also decoupled
with an additional 0.1µF decoupling capacitor. This reduces
the source impedance at higher frequencies for the
noninverting input bias current noise. This 2.5V bias on the
noninverting input pin appears on the inverting input pin and,
since RG is DC blocked by the input capacitor, will also
appear at the output pin. One advantage to inverting operation is that since there is no signal swing across the input
stage, higher slew rates and operation to even lower supply
voltages is possible. To retain a 1Vp-p output capability,
operation down to a 3V supply is allowed. At a +3V supply,
the input stage is saturated, but for the inverting configuration
1/2
OPA2684
RF
800Ω
VI
RG
RF
800Ω
VO
1/2
OPA2684
–VCC
FIGURE 5. Noninverting Differential I/O Amplifier.
OPA2684
SBOS239D
www.ti.com
15
This approach provides for a source termination impedance
that is independent of the signal gain. For instance, simple
differential filters may be included in the signal path right up
to the noninverting inputs without interacting with the gain
setting. The differential signal gain for the circuit of Figure 5 is:
AD = 1 + 2 • RF /RG
Since the OPA2684 is a CFBPLUS amplifier, its bandwidth is
principally controlled with the feedback resistor value, Figure 5
shows the recommended value of 800Ω. The differential
gain, however, may be adjusted with considerable freedom
using just the RG resistor. In fact, RG may be a reactive
network providing a very isolated shaping to the differential
frequency response. Since the inverting inputs of the OPA2684
are very low impedance closed-loop buffer outputs, the RG
element does not interact with the amplifier’s bandwidth,
wide ranges of resistor values and/or filter elements may be
inserted here with minimal amplifier bandwidth interaction.
Various combinations of single-supply or AC-coupled gain
can also be delivered using the basic circuit of Figure 5.
Common-mode bias voltages on the two noninverting inputs
pass on to the output with a gain of 1 since an equal DC
voltage at each inverting node creates no current through
RG. This circuit does show a common-mode gain of 1 from
input to output. The source connection should either remove
this common-mode signal if undesired (using an input transformer can provide this function), or the common-mode
voltage at the inputs can be used to set the output commonmode bias. If the low common-mode rejection of this circuit
is problem, the output interface may also be used to reject
that common-mode. For instance, most modern differential
input ADC’s reject common-mode signals very well while a
line driver application through a transformer will also attenuate the common-mode signal through to the line.
The two noninverting inputs provide an easy common-mode
control input. This is particularly easy if the source is
AC-coupled through either blocking caps or a transformer.
In either case, the common-mode input voltages on the two
noninverting inputs again have a gain of 1 to the output pins
giving particularly easy common-mode control for singlesupply operation. The OPA2684 used in this configuration
does constrain the feedback to the 800Ω region for best
frequency response. With RF fixed, the input resistors may be
adjusted to the desired gain but will also be changing the
input impedance as well. The high frequency common-mode
gain for this circuit from input to output will be the same as
for the signal gain. Again, if the source might include an
undesired common-mode signal, that could be rejected at
the input using blocking caps (for low frequency and DC
common-mode) or a transformer coupling.
DC-COUPLED SINGLE TO DIFFERENTIAL CONVERSION
The previous differential output circuits were set up to receive a differential input as well. A simple way to provide a
DC-coupled single to differential conversion using a dual op
amp is shown in Figure 7. Here, the output of the first stage
is simply inverted by the second to provide an inverting
version of a single amplifier design. This approach works well
for lower frequencies but will start to depart from ideal
differential outputs as the propagation delay and distortion of
the inverting stage adds significantly to that present at the
noninverting output pin.
+5V
1Vp-p
50Ω
Figure 6 shows a differential I/O stage configured as an
inverting amplifier. In this case, the gain resistors (RG)
become part of the input resistance for the source. This
provides a better noise performance than the noninverting
configuration but does limit the flexibility in setting the input
impedance separately from the gain.
1/2
OPA2684
800Ω
160Ω
800Ω
12Vp-p Differential
800Ω
+VCC
VCM
1/2
OPA2684
VI
RG
RF
800Ω
RG
RF
800Ω
1/2
OPA2684
–5V
VO
FIGURE 7. Single to Differential Conversion.
1/2
OPA2684
VCM
–VCC
FIGURE 6. Inverting Differential I/O Amplifier.
16
The circuit of Figure 7 is set up for a single-ended gain of 6
to the output of the first amplifier then an inverting gain of
–1 through the second stage to provide a total differential
gain of 12. See Figure 8 for the SSBW for the circuit of Figure 7.
Large-signal distortion at 12Vp-p output into the 100Ω differential load is ≤ 80dBc.
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Figure 9 designs the filter for a differential gain of 5 using the
OPA2684. The resistor values have been adjusted slightly to
account for the amplifier bandwidth effects.
SINGLE TO DIFFERENTIAL CONVERSION
24
While this circuit is bipolar, using ±5V supplies, it can easily
be adapted to single-supply operation. This is typically done
by providing a supply midpoint reference at the noninverting
inputs then adding DC blocking caps at each input and in
series with the amplifier gain resistor, RG. This will add two
real zeroes in the response transforming the circuit into a
bandpass. Figure 10 shows the frequency response for the
filter of Figure 9.
21
Gain (dB)
18
15
12
9
6
3
1
10
100
200
10MHz, 3RD-ORDER BUTTERWORTH, LOW PASS,
FREQUENCY RESPONSE
Frequency (MHz)
14
FIGURE 8. Small-Signal Bandwidth for Figure 7.
Differential Gain (dB)
11
DIFFERENTIAL ACTIVE FILTER
The OPA2684 can provide a very capable gain block for lowpower active filters. The dual design lends itself very well to
differential active filters. Where the filter topology is looking
for a simple gain function to implement the filter, the
noninverting configuration is preferred to isolate the filter
elements from the gain elements in the design. Figure 9
shows an example of a very low power 10MHz 3rd-order
Butterworth low-pass Sallen-Key filter. Often, these filters are
designed at an amplifier gain of 1 to minimize amplifier
bandwidth interaction with the desired filter shape. Since the
OPA2684 shows minimal bandwidth change with gain, this
would not be a constraint in this design. The example of
8
5
2
–1
–4
1
10
20
Frequency (MHz)
FIGURE 10. Frequency Response for 10MHz, 3rd-Order
Butterworth Low-Pass Filter.
100pF
50Ω
232Ω
+5V
20Ω
1/2
OPA2684
VI
75pF
50Ω
232Ω
20Ω
800Ω
357Ω
800Ω
357Ω
22pF
400Ω
VO
1/2
OPA2684
100pF
–5V
FIGURE 9. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter.
OPA2684
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17
SINGLE-SUPPLY, HIGH GAIN DIFFERENTIAL
ADC DRIVER
Where a very low power differential I/O interface to a moderate performance ADC is required, the circuit of Figure 11
may be considered. The circuit builds on the inverting differential I/O configuration of Figure 6 by adding the input
transformer and the output low-pass filter. The input transformer provides a single-to-differential conversion where the
input signal is still very low power—it also provides a gain of
2 and removes any common-mode signal from the inputs.
This single +5V design sets a midpoint bias from the supply
at each of the noninverting inputs.
reduces the voltage swing loss in the remaining discrete
matching resistor leaving more of the available voltage swing
at the input of the transformer. This typically will allow the
transformer turns ratio to be reduced, reducing the peak
output current required. All of this together can reduce the
power dissipated in the line driver while delivering a low
distortion DSL signal to the line.
DISTORTION vs FREQUENCY
–50
2Vp-p Output
This circuit also includes optional 500Ω pull-down resistors at
the output. With a 2.5V DC common-mode operating point
(set by VCM), this will add 5mA to ground in the output stage.
This essentially powers up the NPN side of the output stage
significantly reducing distortion. It is important for good 2ndorder distortion to connect the grounds of these two resistors
at the same point to minimize ground plane current for the
differential output signal. Figure 12 shows the measured
2nd- and 3rd-harmonic distortion for the circuit of Figure 11
with and without the pull-down resistors.
Less than –65dBc distortion is possible through 5MHz without the pull-down current while this extends to 10MHz using
the two 500Ω pull-down resistors.
3rd-Harmonic
Distortion (dBc)
–60
2nd-Harmonic
–70
No Pull-Down
3rd-Harmonic
–80
2nd-Harmonic
5mA/ch Pull-Down
–90
1
10
20
Frequency (MHz)
FIGURE 12. Measured Harmonic Distortion for the Circuit of
Figure 11.
SYNTHETIC IMPEDANCE DSL LINE DRIVER
The need for very low power DSL line drivers is well supported by the OPA2684 with its high (> 100mA) output
current, low (< 1.2V) headroom, and low supply current
(3.4mA). To further improve power efficiency, simple differential line drivers are often modified to produce a portion
of the output impedance through positive feedback. This
See Figure 13 for an example design for a +12V singlesupply SHDSL4 line driver where only 27% of the output
impedance is implemented with the physical (18.2Ω) output
resistors with the remaining 73% implemented with positive
feedback. This synthetic output impedance circuit feeds back
the transformer input voltage to the opposite inverting nodes.
+5V
10kΩ
VCM
0.1µF
10kΩ
1/2
OPA2684
Optional
ADC
500Ω
200Ω
800Ω
RS
200Ω
800Ω
RS
1:2
50Ω
Source
14.7dB
Noise Figure
Gain = 8V/V
18.1dB
1/2
OPA2684
CL
Optional
VCM
500Ω
FIGURE 11. Single-Supply Differential ADC Driver.
18
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DESIGN-IN TOOLS
+12V
DEMONSTRATION FIXTURES
2kΩ
Two printed circuit boards (PCBs) are available to assist in the
initial evaluation of circuit performance using the OPA2684 in
its two package styles. Both of these are offered free of charge
as unpopulated PCBs, delivered with a user’s guide. The
summary information for these fixtures is shown in Table I.
+6V
1/2
OPA2684
RF
800Ω
RO
18.2Ω
RP
1.07kΩ
RG
931Ω
2Vp-p
max
2kΩ
1:1
12.67Vp-p → 135Ω
V2 max
RP
1.07kΩ
RF
800Ω
PRODUCT
RO
18.2Ω
OPA2684ID
OPA2684IDCN
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
SO-8
SOT23-8
DEM-OPA-SO-2A
DEM-OPA-SOT-2A
SBOU003
SBOU001
TABLE I. Demonstration Fixtures by Package.
The demonstration fixtures can be requested at the Texas
Instruments web site (www.ti.com) through the OPA2684
product folder.
1/2
OPA2684
MACROMODELS
+6V
FIGURE 13. Synthetic Output Impedance xDSL Driver.
This example takes a 2Vp-p maximum differential input to a
12.67Vp-p maximum differential voltage on a 135Ω line using
a 1:1 transformer. For a nominal line at maximum target
power, each output swings a maximum 8Vp-p delivering a
peak 47mA current, on a 12V supply this leaves 2V headroom on each output with a total amplifier power dissipation
of 163mW. Figure 14 shows the distortion for a full scale
(12.67Vp-p on the line) and 1/2 scale sinusoid signal from
100kHz to 1MHz.
Computer simulation of circuit performance using SPICE is often
useful when analyzing the performance of analog circuits and
systems. This is particularly true for higher speed designs where
parasitic capacitance and inductance can have a major effect on
circuit performance. A SPICE model for the OPA2684 is available in the product folder on the TI web site (www.ti.com). This
is the single channel model for the OPA684—simply use two of
these to implement an OPA2684 simulation. These models do
a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not
do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between
the package types in their small-signal AC performance.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH
Any current-feedback op amp like the OPA2684 can hold high
bandwidth over signal-gain settings with the proper adjustment
of the external resistor values. A low-power part like the OPA4684
typically shows a larger change in bandwidth due to the significant contribution of the inverting input impedance to loop-gain
changes as the signal gain is changed. Figure 15 shows a
simplified analysis circuit for any current- feedback amplifier.
DIFFERENTIAL DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
–65
–70
3rd-Harmonic
VL = 12.7Vp-p
–75
2nd-Harmonic
VL = 12.7Vp-p
–80
VI
2nd-Harmonic
VL = 6.3Vp-p
–85
α
VO
–90
RI
3rd-Harmonic
VL = 6.3Vp-p
–95
0.1
iERR
Z(S) iERR
RF
1
Frequency (MHz)
RG
FIGURE 14. Harmonic Distortion for Figure 13.
FIGURE 15. Current-Feedback Transfer Function Analysis
Circuit.
OPA2684
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19
The key elements of this current-feedback op amp model
are:
α ⇒ Buffer gain from the noninverting input to the inverting
input
RI ⇒ Buffer output impedance
iERR ⇒ Feedback error current signal
Z(s) ⇒ Frequency dependent open-loop transimpedance
gain from iERR to VO
The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however,
set the CMRR for a single op amp differential amplifier
configuration. For the buffer gain α < 1.0, the CMRR = –20
• log(1 – α). The closed-loop input stage buffer used in the
OPA2684 gives a buffer gain more closely approaching 1.00
and this shows up in a slightly higher CMRR than previous
current-feedback op amps.
RI, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA2684 reduces this
element to approximately 4.0Ω using the loop gain of the
closed-loop input buffer stage. This significant reduction in
output impedance, on very low power, contributes significantly to extending the bandwidth at higher gains.
A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the
output through an internal frequency dependent
transimpedance gain. The Typical Characteristics show this
open-loop transimpedance response. This is analogous to
the open-loop voltage gain curve for a voltage-feedback op
amp. Developing the transfer function for the circuit of Figure 15
gives Equation 1:

R 
α 1 + F 
R

VO
α NG
G
=
=
VI

RF  1 + RF + RI NG
RF + RI 1 +

Z (S )
 RG 
1+
Z (S )
(1)


R 
NG = 1 + F  
 R G  

This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(s) were infinite over all frequencies, the
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation.
(2)
Z (S )
RF + RI NG
The OPA2684 is internally compensated to give a maximally
flat frequency response for RF = 800Ω at NG = 2 on ±5V
supplies. That optimum value goes to 1.0kΩ on a single +5V
supply. Normally, with a current-feedback amplifier, it is
possible to adjust the feedback resistor to hold this bandwidth up as the gain is increased. The CFBPLUS architecture
has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without
adjusting the feedback resistor value. The Typical Characteristics show the small-signal bandwidth over gain with a fixed
feedback resistor.
Putting a closed-loop buffer between the noninverting and
inverting inputs does bring some added considerations. Since
the voltage at the inverting output node is now the output of
a locally closed-loop buffer, parasitic external capacitance on
this node can cause frequency response peaking for the
transfer function from the noninverting input voltage to the
inverting node voltage. While it is always important to keep
the inverting node capacitance low for any current-feedback
op amp, it is critically important for the OPA2684. External
layout capacitance in excess of 2pF will start to peak the
frequency response. This peaking can be easily reduced by
then increasing the feedback resistor value—but it is preferable, from a noise and dynamic range standpoint, to keep
that capacitance low, allowing a close to nominal 800Ω
feedback resistor for flat frequency response. Very high
parasitic capacitance values on the inverting node (> 5pF)
can possibly cause input stage oscillation that cannot be
filtered by a feedback element adjustment.
An added consideration is that at very high gains, 2nd-order
effects in the inverting output impedance cause the overall
response to peak up. If desired, it is possible to retain a flat
frequency response at higher gains by adjusting the feedback resistor to higher values as the gain is increased. Since
the exact value of feedback that will give a flat frequency
response at high gains depends strongly in inverting and
output node parasitic capacitance values, it is best to experiment in the specific board with increasing values until the
desired flatness (or pulse response shape) is obtained. In
general, increasing RF (and adjusting RG then to the desired
gain) will move towards flattening the response, while decreasing it will extend the bandwidth at the cost of some
peaking. The OPA684 data sheet gives an example of this
optimization of RF versus Gain.
= Loop Gain
OUTPUT CURRENT AND VOLTAGE
If 20 • log(RF + NG • RI) were drawn on top of the open-loop
transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z(s) rolls
off to equal the denominator of Equation 2, at which point the
20
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier’s closed-loop
frequency response given by Equation 1 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG).
The OPA2684 provides output voltage and current capabilities that can support the needs of driving doubly-terminated
50Ω lines. For a 100Ω load at the gain of +2, (see Figure 1),
the total load is the parallel combination of the 100Ω load and
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the 1.6kΩ total feedback network impedance. This 94Ω load
will require no more than 40mA output current to support the
±3.8V minimum output voltage swing specified for 100Ω
loads. This is well under the specified minimum +120/–90mA
specifications over the full temperature range.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Voltage and Current Limitations plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA2684’s output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures will increase, decreasing their VBE’s (increasing the available output voltage
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the available output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To maintain maximum output stage linearity, no output shortcircuit protection is provided. This will not normally be a
problem since most applications include a series matching
resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin (8 pin packages) can destroy the
amplifier. If additional short-circuit protection is required,
consider a small-series resistor in the power-supply leads.
This will, under heavy output loads, reduce the available
output voltage swing. A 5Ω series resistor in each powersupply lead will limit the internal power dissipation to less
than 1W for an output short-circuit, while decreasing the
available output voltage swing only 0.25V for up to 50mA
desired load currents. Always place the 0.1µF power-supply
decoupling capacitors after these supply current limiting
resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC, including additional
external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA2684 can be very susceptible to decreased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The Typical Characteristics show the recommended RS vs
CLOAD and the resulting frequency response at the load. The
1kΩ resistor shown in parallel with the load capacitor is a
measurement path and may be omitted. The required series
resistor value may be reduced by increasing the feedback
resistor value from its nominal recommended value. This will
increase the phase margin for the loop gain, allowing a lower
series resistor to be effective in reducing the peaking due
capacitive load. SPICE simulation can be effectively used to
optimize this approach. Parasitic capacitive loads greater
than 5pF can begin to degrade the performance of the
OPA2684. Long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and add the
recommended series resistor as close as possible to the
OPA2684 output pin (see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA2684 provides very low distortion in a low-power
part. The CFBPLUS architecture also gives two significant
areas of distortion improvement. First, in operating regions
where the 2nd-harmonic distortion due to output stage
nonlinearities is very low (frequencies < 1MHz, low output
swings into light loads) the linearization at the inverting node
provided by the CFBPLUS design gives 2nd-harmonic distortions that extend into the –90dBc region. Previous currentfeedback amplifiers have been limited to approximately
–85dBc due to the nonlinearities at the inverting input. The
second area of distortion improvement comes in a distortion
performance that is largely gain independent. To the extent
that the distortion at a particular output power is output stage
dependent, 3rd-harmonics particularly, and to a lesser extend 2nd-harmonic distortion, is constant as the gain is
increased. This is due to the constant loop gain versus signal
gain provided by the CFBPLUS design. As shown in the
Typical Characteristics, while the 3rd-harmonic is constant
with gain, the 2nd-harmonic degrades at higher gains. This
is largely due to board parasitic issues. Slightly imbalanced
load return currents will couple into the gain resistor to cause
a portion of the 2nd-harmonic distortion. At high gains, this
imbalance has more gain to the output giving increased
2nd-harmonic distortion.
Relative to alternative amplifiers with < 2mA supply current,
the OPA2684 holds much lower distortion at higher frequencies (> 5MHz) and to higher gains. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
OPA2684
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21
lower 3rd-harmonic component. Focusing then on the 2ndharmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network—in the noninverting configuration (see Figure 1) this
is the sum of RF + RG, while in the inverting configuration it
is just RF. Also, providing an additional supply decoupling
capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases harmonic distortion directly. A low-power part like
the OPA2684 includes quiescent boost circuits to provide the
full-power bandwidth shown in the Typical Characteristics.
These act to increase the bias in a very linear fashion only
when high slew rate or output power are required. This also
acts to actually reduce the distortion slightly at higher output
power levels. The Typical Characteristics show the 2ndharmonic holding constant from 500mVp-p to 5Vp-p outputs
while the 3rd-harmonics actually decrease with increasing
output power.
The OPA2684 has an extremely low 3rd-order harmonic
distortion, particularly for light loads and at lower frequencies. This also gives low 2-tone, 3rd-order intermodulation
distortion as shown in the Typical Characteristics. Since the
OPA2684 includes internal power boost circuits to retain
good full-power performance at high frequencies and outputs, it does not show a classical 2-tone, 3rd-order
intermodulation intercept characteristic. Instead, it holds relatively low and constant 3rd-order intermodulation spurious
levels over power. The Typical Characteristics show this
spurious level as a dBc below the carrier at fixed center
frequencies swept over single-tone power at a matched 50Ω
load. These spurious levels drop significantly (> 12dB) for
lighter loads than the 100Ω used in that plot. Converter inputs
for instance will see ≤ 82dBc 3rd-order spurious to 10MHz for
full-scale inputs. For even lower 3rd-order intermodulation
distortion to much higher frequencies, consider the OPA2691.
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps.
The OPA2684 offers an excellent balance between voltage
and current noise terms to achieve low output noise in a low
power amplifier. The inverting current noise (17pA/√Hz) is
lower most other current-feedback op amps while the input
voltage noise (3.7nV/√Hz) is lower than any unity-gain stable,
comparable slew rate, voltage-feedback op amp. This low
input voltage noise was achieved at the price of higher
noninverting input current noise (9.4pA/√Hz). As long as the
AC source impedance looking out of the noninverting node is
less than 200Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage
noise and the two input current noise terms combine to give
low output noise under a wide variety of operating conditions.
Figure 16 shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms are taken
to be noise voltage or current density terms in either nV/√Hz
or pA/√Hz.
22
ENI
EO
OPA681
RS
IBN
ERS
RF
√4kTRS
4kT
RG
RG
IBI
√4kTRF
4kT = 1.6E –20J
at 290°K
FIGURE 16. Op Amp Noise Analysis Model.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms shown in Figure 16.
(3)
2
2
EO =  ENI2 + (IBNR S ) + 4kTRS  NG2 + (IBIRF ) + 4kTRFNG
Dividing this expression by the noise gain (NG = (1 + RF /RG))
will give the equivalent input referred spot noise voltage at
the noninverting input as shown in Equation 4.
(4)
2
4kTRF
2
I R 
EN = ENI2 + (IBNR S ) + 4kTRS +  BI F  +
 NG 
NG
Evaluating these two equations for the OPA2684 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 16.3nV/√Hz and a total equivalent input spot
noise voltage of 8.2 nV/√Hz. This total input referred spot
noise voltage is higher than the 3.7nV/√Hz specification for
the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. As the gain is increased, this fixed output
noise power term contributes less to the total output noise
and the total input referred voltage noise given by Equation 4
will approach just the 3.7nV/√Hz of the op amp itself. For
example, going to a gain of +20 in the circuit of Figure 1,
adjusting only the gain resistor to 42.1Ω, will give a total input
referred noise of 3.9nV/√Hz. A more complete description of
op amp noise analysis can be found in TI application note
AB-103, “Noise Analysis for High-Speed Op Amps”
(SBOA066), located at www.ti.com.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA2684 provides
exceptional bandwidth in high gains, giving fast pulse settling
but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high slew
rate voltage-feedback amplifiers. The two input bias currents,
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however, are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op
amps. Since the two input bias currents are unrelated in both
magnitude and polarity, matching the source impedance
looking out of each input to reduce their error contribution to
the output is ineffective. Evaluating the configuration of
Figure 1, using worst-case +25°C input offset voltage and the
two input bias currents, gives a worst-case output offset
range equal to:
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA2684 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a)
Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b)
Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power-plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capacitors. The power-supply connections should always be
decoupled with these capacitors. An optional supply decoupling capacitor (0.01µF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic
distortion performance. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may
be placed somewhat farther from the device and may be
shared among several devices in the same area of the
PCB.
c)
Careful selection and placement of external components will preserve the high -frequency performance
of the OPA2684. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composition axially-leaded resistors can also provide good highfrequency performance. Again, keep their leads and
PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the
most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close
as possible to the output pin. Other network components, such as noninverting input termination resistors,
should also be placed close to the package. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing
its value will reduce the peaking at higher gains, while
decreasing it will give a more peaked frequency response at lower gains. The 800Ω feedback resistor used
in the Electrical Characteristics at a gain of +2 on ±5V
supplies is a good starting point for design. Note that an
800Ω feedback resistor, rather than a direct short, is
required for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even
in the unity-gain follower configuration to control stability.
±(NG • VOS) + (IBN • RS / 2 • NG) ± (IBI • RF)
where NG = noninverting signal gain
= ±(2 • 3.8mV) ± (11µA • 25Ω • 2) ± (800Ω • 17mA)
= ±7.6mV + 0.55mV ± 13.6mV
= ±21.75mV
While the last term, the inverting bias current error, is
dominant in this low-gain circuit, the input offset voltage will
become the dominant DC error term as the gain exceeds
5V/V. Where improved DC precision is required in a highspeed amplifier, consider the OPA656 single and OPA2822
dual voltage-feedback amplifiers.
THERMAL ANALYSIS
The OPA2684 will not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition PDL = VS2/(4 • RL)
where RL includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
TJ using an OPA2684IDCN (SOT23-8 package) in the circuit
of Figure 1 operating at the maximum specified ambient
temperature of +85°C with both outputs driving a grounded
100Ω load to 2.5VDC.
PD = 10V • 3.9mA + 2 • (52 /(4 • (100Ω || 1.6kΩ))) = 172mW
Maximum TJ = +85°C + (0.172W • 150°C/W) = 111°C
This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst-case output stage power in
both channels simultaneously was assumed in this calculation.
OPA2684
SBOS239D
www.ti.com
23
d)
24
Connections to other wideband devices on the board
may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the
total capacitive load and set RS from the plot of recommended Rs vs CLOAD. Low parasitic capacitive loads
(< 5pF) may not need an RS since the OPA2684 is
nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally not
necessary on board, and in fact a higher impedance
environment will improve distortion, as shown in the
distortion versus load plots. With a characteristic board
trace impedance defined based on board material and
trace dimensions, a matching series resistor into the
trace from the output of the OPA2684 is used, as well as
a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor
and the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA2684 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If the
6dB attenuation of a doubly-terminated transmission line
is unacceptable, a long trace can be series-terminated
at the source end only. Treat the trace as a capacitive
load in this case and set the series resistor value as
shown in the plot of Rs vs CLOAD. This will not preserve
signal integrity as well as a doubly-terminated line. If the
input impedance of the destination device is low, there
will be some signal attenuation due to the voltage divider
formed by the series output into the terminating impedance.
e)
Socketing a high-speed part like the OPA2684 is not
recommended. The additional lead length and pin-topin capacitance introduced by the socket can create an
extremely troublesome parasitic network which can make
it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering
the OPA2684 onto the board.
INPUT AND ESD PROTECTION
The OPA2684 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table where an absolute maximum 13V across
the supply pins is reported. All device pins have limited ESD
protection using internal diodes to the power supplies as
shown in Figure 17.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (for example, in systems with ±15V
supply parts driving into the OPA2684), current-limiting series resistors should be added into the two inputs. Keep
these resistor values as low as possible since high values
degrade both noise performance and frequency response.
+VCC
External
Pin
Internal
Circuitry
–VCC
FIGURE 17. Internal ESD Protection.
OPA2684
www.ti.com
SBOS239D
Revision History
DATE
REVISION
7/08
D
5/06
C
PAGE
SECTION
2
Abs Max Ratings
3, 4
Electrical Characteristics,
Power Supply
19
Design-In Tools
DESCRIPTION
Changed Storage Temperature Range from −40°C to +125C to
−65°C to +125C.
Added minimum supply voltage. Changed min and max quiescent current
values from total to per channel.
Board part numbers changed.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
OPA2684
SBOS239D
www.ti.com
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2684ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
2684
OPA2684IDCNT
ACTIVE
SOT-23
DCN
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A84
OPA2684IDCNTG4
ACTIVE
SOT-23
DCN
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A84
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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