Texas Instruments | Quad, Low-Power, Current-Feedback Operational Amplifier (Rev. G) | Datasheet | Texas Instruments Quad, Low-Power, Current-Feedback Operational Amplifier (Rev. G) Datasheet

Texas Instruments Quad, Low-Power, Current-Feedback Operational Amplifier (Rev. G) Datasheet
OPA
OPA
468
4
468
OPA4684
4
®
SBOS240G – JUNE 2002 – REVISED JULY 2008
www.ti.com
Quad, Low-Power, Current-Feedback
Operational Amplifier
FEATURES
APPLICATIONS
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MINIMAL BANDWIDTH CHANGE VERSUS GAIN
170MHz BANDWIDTH AT G = +2
> 120MHz BANDWIDTH TO GAIN > +10
LOW DISTORTION: < –78dBc at 5MHz
HIGH OUTPUT CURRENT: 120mA
SINGLE +5V TO +12V SUPPLY OPERATION
DUAL ±2.5 TO ±6.0V SUPPLY OPERATION
LOW SUPPLY CURRENT: 1.7mA/ch
DESCRIPTION
The OPA4684 provides a new level of performance in lowpower, wideband, current-feedback (CFB) amplifiers. This
CFBPLUS amplifier is among the first to use an internally
closed-loop input buffer stage that enhances performance
significantly over earlier low-power CFB amplifiers. This new
architecture provides many of the benefits of a more ideal
CFB amplifier while retaining the benefits of very low power
operation. The closed-loop input stage buffer gives a very
low and linearized impedance path at the inverting input to
sense the feedback error current. This improved inverting
input impedance retains exceptional bandwidth to much
higher gains and improves harmonic distortion over earlier
solutions limited by inverting input linearity. Beyond simple
high-gain applications, the OPA4684 CFBPLUS amplifier permits the gain setting element to be set with considerable
LOW-POWER BROADCAST VIDEO DRIVERS
EQUALIZING FILTERS
SAW FILTER HIGH-GAIN POST AMPLIFIERS
MULTICHANNEL SUMMING AMPLIFIERS
WIDEBAND DIFFERENTIAL CHANNELS
ANALOG-TO-DIGITAL CONVERTERS INPUT
DRIVERS
● MULTIPLE POLE ACTIVE FILTERS
● OPA4658 LOW-POWER UPGRADE
freedom from amplifier bandwidth interaction. This allows
frequency response peaking elements to be added, multiple
input inverting summing circuits to have greater bandwidth,
and low-power line drivers to meet the demanding requirements of studio cameras and broadcast video.
The output capability of the OPA4684 also sets a new mark
in performance for low-power current-feedback amplifiers.
Delivering a full ±4VPP swing on ±5V supplies, the OPA4684
also has the output current to support > ±3V swing into 50Ω.
This minimal output headroom requirement is complemented
by a similar 1.2V input stage headroom giving exceptional
capability for single +5V operation.
The OPA4684’s low 6.8mA supply current is precisely trimmed
at 25°C. This trim, along with low shift over temperature and
supply voltage, gives a very robust design over a wide range
of operating conditions.
BW (MHz) vs GAIN
6
V+
+
Z(S) IERR
V–
IERR
RF
VO
Normalized Gain (3dB/div)
1 of 4 Channels
0
–3
Low-Power
G=5
–6
–9
–12
G = 10
G = 20
–15
–18
–21
RG
G=1
G=2
3
G = 50
G = 100
RF = 800Ω
–24
10
Amplifier
(patented design)
100
200
MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation ................................. See Thermal Information
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: ID, IDBV ......................... –65°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +150°C
ESD Rating: HBM ............................................................................ 2000V
CDM ........................................................................... 1500V
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
OPA4684 RELATED PRODUCTS
SINGLES
OPA683
OPA684
OPA691
OPA695
DUALS
TRIPLES
FEATURES
OPA2683
OPA2684
OPA2691
—
—
OPA3684
OPA3691
—
Very Low-Power CFBPLUS
Low-Power CFBPLUS
High Slew Rate CFB
> 500MHz CFB
PACKAGE/ORDERING INFORMATION(1)
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA4684
SO-14
D
–40°C to +85°C
OPA4684
"
"
"
"
"
OPA4684ID
OPA4684IDR
Rails, 58
Tape and Reel, 2500
OPA4684
TSSOP-14
PW
–40°C to +85°C
OPA4684
OPA4684IPWT
Tape and Reel, 250
"
"
"
"
"
OPA4684IPWR
Tape and Reel, 2500
PRODUCT
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI web site
at www.ti.com.
PIN CONFIGURATION
Top View
SO, TSSOP
Output A
1
–Input A
2
A
14
Output D
13
–Input D
+Input D
D
+Input A
3
12
+V
4
11
+Input B
5
B
–V
10
+Input C
C
–Input B
6
9
–Input C
Output B
7
8
Output C
OPA4684
2
OPA4684
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SBOS240G
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RF = 800Ω, RL = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted.
OPA4684ID, IPW
TYP
PARAMETER
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (VO = 0.5VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
All Hostile Crosstalk, Input-Referred
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Common-Mode Input Range(5) (CMIR)
Common-Mode Rejection Ratio (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Voltage Output Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Minimum Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (–PSRR)
TEMPERATURE RANGE
Specification: ID, IPW
Thermal Resistance, θJA
D
SO-14
PW TSSOP-14
CONDITIONS
+25°C
G = +1, RF = 800Ω
G = +2, RF = 800Ω
G = +5, RF = 800Ω
G = +10, RF = 800Ω
G = +20, RF = 800Ω
G = +2, VO = 0.5VPP, RF = 800Ω
RF = 800Ω, VO = 0.5VPP
G = +2, VO = 4VPP
G = –1, VO = 4V Step
G = +2, VO = 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 4VStep
G = +2, f = 5MHz, VO = 2VPP
RL = 100Ω
RL ≥ 1kΩ
RL = 100Ω
RL ≥ 1kΩ
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4VPP, RL = 150Ω
G = +2, NTSC, VO = 1.4VPP, RL = 150Ω
3 Channels Driven at 5MHz, 1VPP
4th Channel Measured
250
170
138
120
95
19
1.4
90
780
750
3
6.8
VO = 0V, RL = 1kΩ
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
120
118
117
16
4.8
14
5.9
14
6.3
675
680
650
660
575
650
–59
–66
–66
–82
4.1
11
18
–59
–65
–65
–81
4.2
12
18.5
160
typ
min
typ
typ
typ
min
max
typ
min
min
typ
typ
C
B
C
C
C
B
B
C
B
B
C
C
–58
–65
–65
–81
4.4
12.5
19
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
deg
dB
max
max
max
max
max
max
max
typ
typ
typ
B
B
B
B
B
B
B
C
C
C
155
±4.6
±12
±14.5
±25
±18.5
±35
153
±4.8
±12
±15
±30
±19.5
±40
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±3.65
52
±3.6
52
V
dB
kΩ || pF
Ω
min
min
typ
typ
A
A
C
C
120
–100
±3.9
115
–95
±3.8
110
–90
V
mA
mA
Ω
min
min
min
typ
A
A
A
C
±6
±6
±6
1.8
1.6
54
1.9
1.55
53
1.95
1.45
53
V
V
V
mA
mA
dB
typ
max
min
max
min
typ
C
A
C
A
A
A
–40 to +85
°C
typ
C
100
110
°C/W
°C/W
typ
typ
C
C
–67
–82
–70
–84
3.7
9.4
17
0.04
0.02
–52
±4.0
±5.0
±13
±5.0
±17
±3.65
Open-Loop, DC
±3.75
60
50 || 2
4.0
1kΩ Load
VO = 0
VO = 0
G = +2, f = 100kHz
±4.1
160
–120
0.006
±3.9
±5
VS = ±5V/per Channel
VS = ±5V/per Channel
Input-Referred
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
V/µs
ns
ns
355
±1.5
VCM = 0V
UNITS
±1.4
1.7
1.7
60
Junction-to-Ambient
53
NOTES: (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit, junction temperature = ambient
+7°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and
simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input
common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
OPA4684
SBOS240G
www.ti.com
3
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
RF = 1kΩ, RL = 100Ω to VS/2, and G = +2, (see Figure 3 for AC performance only), unless otherwise noted.
OPA4684ID, IPW
TYP
PARAMETER
AC PERFORMANCE (see Figure 3)
Small-Signal Bandwidth (VO = 0.5VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
All Hostile X-Talk, Input-Referred
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Refection Ratio (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Specified Single-Supply Operating Voltage
Max Single-Supply Operating Voltage
Min Single-Supply Operating Voltage
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
CONDITIONS
+25°C
G = +1, RF = 1.3kΩ
G = +2, RF = 1.3kΩ
G = +5, RF = 1.3kΩ
G = +10, RF = 1.3kΩ
G = +20, RF = 1.3kΩ
G = +2, VO < 0.5Vp-p, RF = 1.3kΩ
RF = 1.3kΩ, VO < 0.5VPP
G = 2, VO = 2VPP
G = 2, VO = 2V Step
G = 2, VO = 0.5V Step
G = 2, VO = 2VStep
G = 2, f = 5MHz, VO = 2VPP
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4VPP, RL = 150Ω
G = +2, NTSC, VO = 1.4VPP, RL = 150Ω
3-Channels Driven at 5MHz, 1VPP
4th Channel Measured
140
110
100
90
75
21
0.5
86
300
4.3
5.3
VO = VS/2, RL = 1kΩ to VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
–65
–84
–65
–74
3.7
9.4
17
0.04
0.07
–52
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
86
85
82
12
2.6
11
3.4
10
3.7
300
290
280
–60
–62
–64
–70
4.1
11
18
–59
–61
–63
–70
4.2
12
18.5
160
UNITS
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
typ
min
min
typ
typ
min
max
typ
min
typ
typ
C
B
C
C
C
B
B
C
B
C
C
–59
–61
–63
–69
4.4
12.5
19
dBc
dBc
dBc
dBc
nV/ √Hz
pA/ √Hz
pA/ √Hz
%
deg
dB
max
max
max
max
max
max
max
typ
typ
typ
B
B
B
B
B
B
B
C
C
C
155
±4.1
±12
±14.5
±25
±14.5
±25
153
±4.3
±12
±15
±30
±16
±30
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
355
±1.0
±3.5
±5
±13
±5
±13
1.32
3.68
51
1.35
3.65
50
1.38
3.62
50
Open-Loop
1.25
3.75
58
50 || 1
5
V
V
dB
kΩ || pF
Ω
max
min
min
typ
typ
A
A
A
C
C
RL = 1kΩ to VS/2
RL = 1kΩ to VS/2
VO = VS/2
VO = VS/2
G = +2, f = 100kHz
4.10
0.9
80
70
0.006
3.9
1.1
65
55
3.9
1.1
60
50
3.8
1.2
55
45
V
V
mA
mA
Ω
min
max
min
min
typ
A
A
A
A
C
12
12
12
1.55
1.30
1.55
1.20
1.55
1.15
V
V
V
mA
mA
dB
typ
max
min
max
min
typ
C
A
C
A
A
C
–40 to +85
°C
typ
C
100
110
°C/W
°C/W
typ
typ
C
C
VCM = VS/2
5
VS = +5V/per Channel
VS = +5V/per Channel
Input-Referred
TEMPERATURE RANGE
Specification: ID, IPW
Thermal Resistance, θJA Junction-to-Ambient
D
SO-14
PW TSSOP-14
2.8
1.45
1.45
58
NOTES: (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit, junction temperature = ambient
+3°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and
simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input
common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
4
OPA4684
www.ti.com
SBOS240G
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
VO = 0.5VPP
RF = 800Ω
3
G=1
G=2
0
–3
–6
G=5
G = 10
–9
G = 20
–12
G = 50
–15
See Figure 1
VO = 0.5VPP
RF = 800Ω
0
–3
–6
See Figure 2
G = 100
–18
–12
1
10
100
200
1
10
Frequency (MHz)
9
200
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
3
G = +2
RL = 100Ω
VO = 0.5VPP
G = –1
RL = 100Ω
VO = 0.5VPP
0
Gain (dB)
6
Gain (dB)
100
Frequency (MHz)
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
VO = 1VPP
3
1VPP
–3
2VPP
5VPP
–6
VO = 2VPP
0
VO = 5VPP
–9
See Figure 1
–3
See Figure 2
–12
1
10
100
200
1
10
Frequency (MHz)
1.6
G = –1
1.2
Large-Signal Right Scale
0.2
0.8
0.4
Small-Signal Left Scale
0
0
–0.2
–0.4
–0.4
–0.8
–0.6
Output Voltage (200mV/div)
0.6
Output Voltage (400mV/div)
G = +2
–1.2
0.6
1.2
0.4
0.8
0.2
0.4
0
0
Small-Signal Left Scale
–0.2
–0.4
Large-Signal Right Scale
–0.4
–0.6
–0.8
–1.2
See Figure 2
See Figure 1
–0.8
–1.6
–0.8
–1.6
Time (10ns/div)
Time (10ns/div)
OPA4684
SBOS240G
200
INVERTING PULSE RESPONSE
0.8
1.6
0.4
100
Frequency (MHz)
NONINVERTING PULSE RESPONSE
0.8
Output Voltage (200mV/div)
G = –1
G = –2
G = –5
G = –10
G = –16
–9
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5
Output Voltage (400mV/div)
Normalized Gain (3dB/div)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
3
Normalized Gain (3dB/div)
6
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
–50
–50
VO = 2VPP
f = 5MHz
G = +2
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
VO = 2VPP
RL = 100Ω
–65
–70
2nd-Harmonic
–75
3rd-Harmonic
–80
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–85
See Figure 1
–90
See Figure 1
–90
100
0.1
1k
1
–50
VO = 2VPP
RL = 100Ω
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
f = 5MHz
RL = 100Ω
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–90
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–90
0.5
1
2.5
5
Output Voltage (VPP)
3.0
3.5
4.0
4.5
5.0
Supply Voltage (±V)
5.5
6.0
HARMONIC DISTORTION vs INVERTING GAIN
HARMONIC DISTORTION vs NONINVERTING GAIN
–50
–50
–55
–55
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
20
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
–50
–60
–65
–70
3rd-Harmonic
–75
–80
2nd-Harmonic
–60
–65
–70
3rd-Harmonic
–75
–80
–85
–85
–90
–90
1
10
1
20
10
20
Inverting Gain (V/V)
Gain (V/V)
6
10
Frequency (MHz)
Load Resistance (Ω)
OPA4684
www.ti.com
SBOS240G
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
INPUT VOLTAGE AND CURRENT NOISE DENSITY
–50
100
20MHz
3rd-Order Spurious Level (dBc)
Noninverting Current Noise
9.4pA/√Hz
10
Voltage Noise
3.7nV/√Hz
+5V
–60
PI
50Ω
50Ω
PO
OPA4684
50Ω
–5V
800Ω
–70
10MHz
800Ω
5MHz
–80
1MHz
1
–90
100
1k
10k
100k
1M
10M
–8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5
Power at Load (each tone, dBm)
Frequency (Hz)
9
12pF
0.5dB Peaking
30
20
5pF
100pF
3
+5V
75pF
RS
VI
0
VO
50Ω OPA4684
CL
1kΩ
50pF
–5V
800Ω
–3
10
33pF
800Ω
20pF
–6
0
1
10
1
100
10
CMRR and PSRR vs FREQUENCY
Open-Loop Transimpedance Gain (dBΩ)
CMRR
60
50
+PSRR
40
–PSRR
30
20
10
0
1k
10k
100k
1M
Frequency (Hz)
10M
100M
OPA4684
SBOS240G
300
OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE
70
100
100
Frequency (MHz)
CLOAD (pF)
Power-Supply Rejection Ratio (dB)
8
6
Normalized Gain (dB)
RS (Ω)
40
Common-Mode Rejection Ratio (dB)
7
SMALL-SIGNAL BANDWIDTH vs CLOAD
RS vs CLOAD
50
6
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120
0
20log (ZOL)
100
–30
80
–60
∠ ZOL
60
–90
40
–120
20
–150
0
Open-Loop Phase (°)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
Inverting Current Noise
17pA/√Hz
–180
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
1G
7
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
0.07
2
VO (V)
0.06
dG
0.05
=1
00Ω
3
L
4
0.08
1W Power
Limit
R
Gain = +2
NTSC, Positive Video
0.09
50
Ω
1
0
–1
0.04
0.03
–2
dP
0.02
–3
0.01
–4
0
–5
1
2
3
4
Each
Channel
–150
1W Power
Limit
Number of 150Ω Video Loads
0
IO (MA)
TYPICAL DC DRIFT OVER AMBIENT TEMPERATURE
SUPPLY AND OUTPUT CURRENT
vs AMBIENT TEMPERATURE
–100
–50
50
100
150
7.6
200
4
Output Current (mA)
2
1
Noninverting Input Bias Current
Input Offset Voltage
0
–1
–2
7.2
175
Supply Current
6.8
150
Sinking Output Current
125
6.4
Inverting Input Bias Current
–3
6.0
100
–4
–50
–25
0
25
50
75
100
125
–25
Ambient Temperature (°C)
100
125
–20
Crosstalk, Input-Referred (dB)
2V Step
See Figure 1
0.04
% Error to Final Value
25
50
75
Ambient Temperature (°C)
ALL HOSTILE CROSSTALK
SETTLING TIME
0.05
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–25
1VPP Output
3-Channels, 100Ω Load
–30
–35
–40
–45
–50
–55
–60
–65
–0.05
–70
0
8
0
10
20
30
Time (ns)
40
50
0.1
60
1
10
100
Frequency (MHz)
OPA4684
www.ti.com
SBOS240G
Supply Current (mA)
Sourcing Output Current
3
Input Bias Currents (µA)
and Offset Voltage (mV)
=
RL
RL = 500Ω
Differential Gain (%)
Differential Phase (°)
OUTPUT CURRENT AND VOLTAGE LIMITATIONS
5
0.10
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.
8.0
3.2
6.4
6.4
6.4
2.4
4.8
4.8
4.8
1.6
3.2
0.8
1.6
0
0
Output Voltage
Right Scale
–0.8
–1.6
See Figure 1
–1.6
–2.4
–3.2
–4.8
Input Voltage
Left Scale
–3.2
–4.0
Input Voltage (1.6V/div)
8.0
3.2
3.2
Output Voltage
Right Scale
1.6
0
–1.6
–1.6
–3.2
–3.2
–4.8
–6.4
–6.4
–8.0
–8.0
See Figure 2
–6.4
–8.0
Time (100ns/div)
INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
100
Input
Voltage
Range
Output Impedance (Ω)
Input and Output Voltage Range
–4.8
Input Voltage
Left Scale
Time (100ns/div)
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
1.6
0
Output
Voltage
Range
1/4
OPA4684
10
ZO
800Ω
800Ω
1
0.01
0.001
±2
±3
±4
±5
±6
100
Supply Voltage (±V)
10k
100k
1M
10M
100M
Frequency (Hz)
OPA4684
SBOS240G
1k
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9
Output Voltage (1.6V/div)
INVERTING OVERDRIVE RECOVERY
8.0
Output Voltage (1.6V/div)
Input Voltage (0.8V/div)
NONINVERTING OVERDRIVE RECOVERY
4.0
TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2, RF = 1kΩ, and RL = 100Ω to VS/2, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
G = 50
RF = 1kΩ
3
Normalized Gain (3dB/div)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
3
RF = 1.0kΩ
G=1
G = 100
Normalized Gain (3dB/div)
6
0
G=2
–3
–6
G = 20
–9
G = 10
–12
0
–3
–6
G = –1
G = –2
G = –5
G = –10
G = –20
–9
–15
G=5
See Figure 3
See Figure 4
–12
–18
1
10
100
1
200
10
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
200
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
9
3
0.2VPP
VO = 0.2VPP
0.5VPP
VO = 0.5VPP
0
6
1VPP
Gain (dB)
Gain (dB)
100
Frequency (MHz)
Frequency (MHz)
3
2VPP
VO = 1VPP
–3
VO = 2VPP
–6
0
–9
–3
–12
10
100
200
1
10
Frequency (MHz)
200
INVERTING PULSE RESPONSE
1.6
0.4
1.6
0.3
1.2
0.3
1.2
0.2
0.8
0.1
0.4
0.2
Large-Signal Right Scale
0.1
0.8
0.4
Small-Signal Left Scale
0
0
–0.1
–0.4
–0.2
–0.8
–0.3
–1.2
Output Voltage (200mV/div)
0.4
Output Voltage (400mV/div)
Output Voltage (200mV/div)
NONINVERTING PULSE RESPONSE
0
0
Small-Signal Left Scale
–0.1
–0.4
Large-Signal Right Scale
–0.2
–0.3
See Figure 3
–0.8
–1.2
See Figure 4
–0.4
–1.6
Time (10ns/div)
10
100
Frequency (MHz)
–0.4
–1.6
Time (10ns/div)
OPA4684
www.ti.com
SBOS240G
Output Voltage (400mV/div)
1
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
At TA = +25°C, G = +2, RF = 1kΩ, and RL = 100Ω to VS/2, unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs LOAD RESISTANCE
–50
–50
VO = 2VPP
RL = 100Ω
VO = 2VPP
f = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
–60
–65
3rd-Harmonic
–70
–75
–80
2nd-Harmonic
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–85
See Figure 3
See Figure 3
–90
–90
100
0.1
1k
1
10
Load Resistance (Ω)
Frequency (MHz)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
–50
20
–50
3rd-Order Spurious Level (dBc)
20MHz
Harmonic Distortion (dBc)
3rd-Harmonic
–60
2nd-Harmonic
–70
–80
–90
See Figure 3
0.5
–60
10MHz
–70
5MHz
–80
See Figure 3
–90
1
2
3
–15 –14 –13 –12 –11 –10 –9
Output Voltage (VPP)
SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
5.8
Right Scale
Supply Current
–6
–5
–4 –3
0.16
G = +2
NTSC, Positive Video
0.14
5.4
Left Scale
Sourcing Output Current
30
5.2
Left Scale
Sinking Output Current
60
5.0
50
4.8
Differential Gain (%)
Differential Phase (°)
5.6
Supply Current (mA)
Output Current (mA)
80
–7
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
100
90
–8
Power at Load (each tone, dBm)
0.12
0.10
dP
0.08
0.06
dG
0.04
0.02
–50
–25
0
25
50
75
Ambient Temperature (°C)
100
0
125
2
3
4
Number of 150Ω Video Loads
OPA4684
SBOS240G
1
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11
APPLICATIONS INFORMATION
LOW-POWER CURRENT-FEEDBACK OPERATION
The quad-channel OPA4684 gives a new level of performance in low-power current-feedback op amps. Using a new
input stage buffer architecture, the OPA4684 CFBPLUS amplifier holds nearly constant AC performance over a wide gain
range. This closed-loop internal buffer gives a very low and
linearized impedance at the inverting node, isolating the
amplifier’s AC performance from gain element variations.
This low impedance allows both the bandwidth and distortion
to remain nearly constant over gain, moving closer to the
ideal current feedback performance of gain bandwidth independence. This low-power amplifier also delivers exceptional
output power—its ±4V swing on ±5V supplies with > 100mA
output drive gives excellent performance into standard video
loads or doubly-terminated 50Ω cables. Single +5V supply
operation is also supported with similar bandwidths but with
reduced output power capability. For lower quiescent power
in a CFBPLUS amplifier, consider the OPA683 family; for
higher output power, consider the OPA691 family.
mode signal across the input stage, the slew rate for inverting
operation is typically higher and the distortion performance is
slightly improved. An additional input resistor, RM, is included
in Figure 2 to set the input impedance equal to 50Ω. The
parallel combination of RM and RG set the input impedance.
As the desired gain increases for the inverting configuration,
RG is adjusted to achieved the desired gain, while RM is also
adjusted to hold a 50Ω input match. A point will be reached
where RG will equal 50Ω, RM is removed, and the input match
is set by RG only. With RG fixed to achieve an input match to
50Ω, increasing RF will increase the gain. This will, however,
quickly reduce the achievable bandwidth as the feedback
resistor increases from its recommended value of 800Ω. If
the source does not require an input match to 50Ω, either
adjust RM to get the desired load, or remove RM and allow the
RG resistor alone provide the input load.
+5V
0.1µF
Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit used as the basis of the ±5V Electrical and
Typical Characteristics for each channel. For test purposes,
the input impedance is set to 50Ω with a resistor to ground
and the output impedance is set to 50Ω with a series output
resistor. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins while load
powers (dBm) are defined at a matched 50Ω load. For
the circuit of Figure 1, the total effective load will be
100Ω || 1600Ω = 94Ω. Gain changes are most easily accomplished by simply resetting the RG value, holding RF constant
at its recommended value of 800Ω.
0.1µF
+
50Ω
1/4
OPA4684
50Ω Load
RF
800Ω
RG
800Ω
0.1µF
+
6.8µF
–5V
FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply Specifications and Test Circuit.
Figure 2 shows the DC-coupled, gain of –1V/V, dual powersupply circuit used as the basis of the Inverting Typical
Characteristics for each channel. Inverting operation offers
several performance benefits. Since there is no common-
12
50Ω
1/4
OPA4684
50Ω Load
50Ω Source
RG
800Ω
RF
800Ω
VI
RM
53.6Ω
0.1µF
+
6.8µF
–5V
These circuits show ±5V operation. The same circuits can be
applied with bipolar supplies from ±2.5V to ±6V. Internal
supply independent biasing gives nearly the same performance for the OPA4684 over this wide range of supplies.
Generally, the optimum feedback resistor value (for nominally flat frequency response at G = +2) will increase in value
as the total supply voltage across the OPA4684 is reduced.
6.8µF
VI
RM
50Ω
6.8µF
FIGURE 2. DC-Coupled, G = –1V/V, Bipolar Supply Specifications and Test Circuit.
+5V
50Ω Source
+
See Figure 3 for the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis for the +5V only
Electrical and Typical Characteristics for each channel. The
key requirement of broadband single-supply operation is to
maintain input and output signal swings within the usable
voltage ranges at both the input and the output. The circuit
of Figure 3 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 10kΩ resistors) to
the noninverting input. The input signal is then AC-coupled
into this midpoint voltage bias. The input voltage can swing
to within 1.25V of either supply pin, giving a 2.5VPP input
signal range centered between the supply pins. The input
impedance of Figure 3 is set to give a 50Ω input match. If the
source does not require a 50Ω match, remove this and drive
OPA4684
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SBOS240G
directly into the blocking capacitor. The source will then see
the 5kΩ load of the biasing network as a load. The gain
resistor (RG) is AC-coupled, giving the circuit a DC gain of +1,
which puts the noninverting input DC bias voltage (2.5V) on
the output as well. The feedback resistor value has been
adjusted from the bipolar ±5V supply condition to re-optimize
for a flat frequency response in +5V only, gain of +2,
operation. On a single +5V supply, the output voltage can
swing to within 1.0V of either supply pin while delivering more
than 70mA output current—easily giving a 3VPP output swing
into 100Ω (8dBm maximum at the matched 50Ω load). The
circuit of Figure 3 shows a blocking capacitor driving into a
50Ω output resistor, then into a 50Ω load. Alternatively, the
blocking capacitor could be removed if the load is tied to a
supply midpoint or to ground if the DC current required by the
load is acceptable.
The circuits of Figure 3 and 4 show single-supply operation
at +5V. These same circuits may be used up to single
supplies of +12V with minimal change in the performance of
the OPA4684.
+5V
0.1µF
+
6.8µF
10kΩ
1/4
0.1µF 50Ω
10kΩ OPA4684
0.1µF
50Ω Load
50Ω Source
DIS
RF
1.3kΩ
RG
0.1µF 1.3kΩ
VI
RM
52.3Ω
+5V
0.1µF
50Ω Source
+
FIGURE 4. AC-Coupled, G = –1V/V, Single-Supply Specifications and Test Circuit.
6.8µF
10kΩ
0.1µF
VI
RM
50Ω
10kΩ
1/4
OPA4684
DIFFERENTIAL INTERFACE APPLICATIONS
0.1µF 50Ω
50Ω Load
RF
1kΩ
RG
1kΩ
0.1µF
Dual and quad op amps are particularly suitable to differential
input to differential output applications. Typically, these fall into
either analog-to-digital converter (ADC) input interface or line
driver applications. Two basic approaches to differential I/O
are noninverting or inverting configurations. Since the output is
differential, the signal polarity is somewhat meaningless—the
noninverting and inverting terminology applies here to where
the input is brought into the OPA4684. Each has its advantages and disadvantages. Figure 5 shows a basic starting
point for noninverting differential I/O applications.
FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply Specifications and Test Circuit.
Figure 4 shows the AC-coupled, single +5V supply, gain of
–1V/V circuit configuration used as a basis for the inverting
+5V only Typical Characteristics for each channel. In this
case, the midpoint DC bias on the noninverting input is also
decoupled with an additional 0.1µF capacitor. This reduces
the source impedance at higher frequencies for the
noninverting input bias current noise. This 2.5V bias on the
noninverting input pin appears on the inverting input pin and,
since RG is DC-blocked by the input capacitor, will also
appear at the output pin. One advantage to inverting operation is that since there is no signal swing across the input
stage, higher slew rates and operation to even lower supply
voltages is possible. To retain a 1VPP output capability,
operation down to a 3V supply is allowed. At a +3V supply,
the input stage is saturated, but for the inverting configuration
of a current-feedback amplifier, wideband operation is retained even under this condition.
+VCC
1/4
OPA4684
RF
800Ω
VI
RF
800Ω
VO
1/4
OPA4684
–VCC
FIGURE 5. Noninverting Differential I/O Amplifier.
OPA4684
SBOS240G
RG
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13
This approach provides for a source termination impedance
that is independent of the signal gain. For instance, simple
differential filters may be included in the signal path right up
to the noninverting inputs without interacting with the amplifier gain. The differential signal gain for the circuit of
Figure 5 is:
VO/VI = AD = 1 + 2 • RF/RG
Since the OPA4684 is a CFBPLUS amplifier, its bandwidth is
principally controlled with the feedback resistor value; Figure 5
shows the recommended value of 800Ω. However, the gain
may be adjusted with considerable freedom using just the RG
resistor. In fact, RG may be a reactive network providing a
very isolated shaping to the differential frequency response.
Since the inverting inputs of the OPA4684 are very low
impedance closed-loop buffer outputs, the RG element does
not interact with the amplifier’s bandwidth—wide ranges of
resistor values and/or filter elements may be inserted here
with minimal amplifier bandwidth interaction.
Various combinations of single-supply or AC-coupled gains
can also be delivered using the basic circuit of Figure 5.
Common-mode bias voltages on the two noninverting inputs
pass on to the output with a gain of 1 since an equal DC
voltage at each inverting node creates no current through
RG, giving that voltage a common-mode gain of 1 to the
output.
Figure 6 shows a differential I/O stage configured as an
inverting amplifier. In this case, the gain resistors (RG)
become the input resistance for the source. This provides a
better noise performance than the noninverting configuration, but does limit the flexibility in setting the input impedance separately from the gain.
The two noninverting inputs provide an easy common-mode
control input. This is particularly useful if the source is ACcoupled through either blocking caps or a transformer. In
either case, the common-mode input voltages on the two
noninverting inputs again have a gain of 1 to the output pins,
giving an easy common-mode control for single-supply operation. The OPA4684 used in this configuration does constrain the feedback to the 800Ω region for best frequency
response. With RF fixed, the input resistors may be adjusted
to the desired gain but will also be changing the input
impedance as well. The differential gain for this circuit is:
VO/VI = –RF/RG
LOW-POWER VIDEO LINE DRIVER APPLICATIONS
For low-power, video line driving, the OPA4684 provides the
output current and linearity to support four channels of either
single video lines, or up to four video lines in parallel on each
output. Figure 7 shows a typical ±5V supply video line driver
application where only one channel is shown and only a
single line is being driven. The improved 2nd-harmonic
distortion of the CFBPLUS architecture, along with the
OPA4684’s high output current and voltage, gives exceptional differential gain and phase performance for a lowpower solution. As the Typical Characteristics show, a single
video load indicates a dG/dP of 0.04%/0.02°. Multiple loads
may be driven on each output, with minimal x-talk, while the
dG/dP is still < 0.1%/0.1° for up to 4 parallel video loads.
+5V
Power-supply decoupling not shown.
VIDEOIN
75Ω
1/4
OPA4684
+VCC
Coax 75Ω Load
800Ω
800Ω
VCM
1/4
OPA4684
RG
75Ω
–5V
FIGURE 7. Gain of +2 Video Cable Driver.
RF
800Ω
DC-COUPLED SINGLE-TO-DIFFERENTIAL CONVERSION
VI
RG
RF
800Ω
1/4
OPA4684
VCM
–VCC
FIGURE 6. Inverting Differential I/O Amplifier.
14
VO
The previous differential output circuits were set up to
receive a differential input as well as provide a differential
output. Figure 8 shows one way to provide a single to
differential conversion, with DC coupling, and independent
output common-mode control using a quad op amp.
The circuit of Figure 8 provides several useful features for
isolating the input signal from the final outputs. Using the first
amplifier as a simple noninverting stage gives an independent adjustment on RI (to set the source loading) while the
gain can be easily adjusting in this stage using the RG
resistor. Bandwidth is relatively independent of gain setting
in the OPA4684. The next stage allows a separate output
common-mode level to be set up. The desired output com-
OPA4684
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SBOS240G
mon-mode voltage, VCM, is cut in half and applied to the
noninverting input of the 2nd stage. The signal path in this
stage sees a gain of –1 while this (1/2 • VCM) voltage sees a
gain of +2. The output of this 2nd stage is then the original
common-mode voltage plus the inverted signal from the
output of the first stage. The 2nd stage output appears
directly at the output of the noninverting final stage. The
inverting node of the inverting output stage is also biased to
the common-mode voltage, equal to the common-mode
voltage appearing at the output of the 2nd stage, creating no
current flow and placing the desired VCM at the output of this
stage as well.
differential active filters. Where the filter topology is looking
for a simple gain function to implement the filter, the
noninverting configuration is preferred to isolate the filter
elements from the gain elements in the design. Figure 9
shows an example of a very low-power, 10MHz, 4th-order
Butterworth, low-pass Sallen-Key filter. Often, these filters
are designed at an amplifier gain of 1 to minimize amplifier
bandwidth interaction with the desired filter shape. Since the
OPA4684 shows minimal bandwidth change with gain, this
feature would not be a constraint in this design. The example
of Figure 9 designs the filter for a differential gain of 4 in each
differential stage. This DC-coupled design gives a signal gain
of 16V/V in the passband with a f–3dB at 10MHz. The design
places the higher Q stage first to allow the lower Q 2nd stage
to roll off the peaked noise of the first stage. The resistor
values have been adjusted slightly to account for the amplifier group delay.
LOW-POWER, DIFFERENTIAL I/O, 4th-ORDER ACTIVE FILTER
The OPA4684 can give a very capable gain block for lowpower active filters. The quad design lends itself very well to
+5V
VCM
1/4
OPA4684
1kΩ
VCM
2
VI
RI
1/4
OPA4684
0.1µF
800Ω
1kΩ
800Ω
1/4
OPA4684
800Ω
800Ω
800Ω
50Ω
800Ω
)
RG
–VI (1 +
800Ω
)
RG
VCM
1/4
OPA4684
RG
+VI (1 +
800Ω
–5V
FIGURE 8. High Gain, DC-Coupled, Single to Differential Conversion.
100pF
100pF
+5V
66.5Ω
49.9Ω
249Ω
392Ω
VO/VI = 16V/V
f–3dB = 10MHz
1/4
OPA4684
1/4
OPA4684
100pF
100pF
800Ω
VI
800Ω
534Ω
800Ω
100pF
100pF
1/4
OPA4684
249Ω
VO
534Ω
800Ω
66.5Ω
PD = 68mW
49.9Ω
1/4
OPA4684
392Ω
100pF
100pF
GD = 4, WO = 2π 10MHz, Q = 1.31
–5V
GD = 4, WO = 2π 10MHz, Q = 0.54
FIGURE 9. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter.
OPA4684
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15
While this circuit is bipolar, using ±5V supplies, it can easily
be adapted to single-supply operation. This is typically done
by providing a supply midpoint reference at the noninverting
inputs then adding DC-blocking caps at each input and in
series with the amplifier gain resistor, RG. This will add two
real zeroes in the response, transforming this circuit into a
bandpass. Figure 10 shows the frequency response for the
filter of Figure 9.
27
Differential Gain (dB)
24
21
18
15
12
9
LOW-POWER DSL TRANSCEIVER INTERFACE
6
With four amplifiers available, the quad OPA4684 can meet
the needs for both differential driver and receiver in a lowpower xDSL line interface design. Figure 11 shows a simplified design example. Two amplifiers are used as a noninverting
differential driver while the other two implement the driver
echo cancellation and receiver amplifier function. This example shows a single +12V design where the drive side is
taking a 2VPP maximum input from the transmit filter
and providing a differential gain of 7, giving a maximum
14VPP differential output swing. This is coupled through 50Ω
matching resistors and a 1:1 transformer to give a maximum
7VPP on a 100Ω line. This 7VPP corresponds to a 10dBm line
power with a 3.5 crest factor.
3
The differential receiver is configured as an inverting summing stage where the outputs of the driver are cancelled prior
to appearing at the output of the receive amplifiers. This is
done by summing the output voltages for the drive amplifiers
0
1
10
Frequency (MHz)
100
FIGURE 10. Low-Power, Differential 4th-Order, 10MHz Butterworth
Response.
and their attenuated and inverted levels (at the transformer
input) into the inverting inputs of each receiver amplifier. The
resistor values are set in Figure 11 to give perfect drive signal
cancellation if the drive signal is attenuated by 1/2, going
from the drive amplifier outputs to the transformer input. The
signal received through the transformer has a gain of 1
through the receive amplifiers. Higher gain could easily be
provided by scaling the resistors summing into the inverting
inputs of the receiver amplifiers down while keeping the
same ratio between them.
+12V
1/4
OPA4684
10kΩ
900Ω
Transmit
Filter
50Ω
1:1
+6V
2VPP
VCM
100Ω
Line
14VPP
300Ω
10dBm
3.5 Crest Factor
50Ω
900Ω
10kΩ
1/4
OPA4684
1.6kΩ
AFE
1.6kΩ
800Ω
800Ω
VCM
1/4
OPA4684
800Ω
Receiver
Filter
800Ω
1/4
OPA4684
VCM
FIGURE 11. Low-Power, XDSL Transceiver Design.
16
OPA4684
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DUAL-CHANNEL, DIFFERENTIAL ADC DRIVER
–50
The circuit of Figure 12 is particularly suitable for a moderate
resolution dual ADC used as I/Q samplers. The optional
500Ω resistors to ground on each amplifier output can be
added to improve the 2nd- and 3rd-harmonic distortion by
> 15dB if higher dynamic range is required. Figure 13 shows
the harmonic distortion for the circuit of Figure 12 with and
without these pull-down resistors. The 5mA added output
stage current significantly improves linearity if that is required. The measured 2nd-harmonic distortion is consistently lower than the 3rd-harmonics for this balanced differential design. It is particularly helpful for this low-power
design if there are no grounds in the signal path after the lowlevel signal at the transformer input. The two pull-down
resistors do show a signal path ground and should be
connected at the same physical point to ground, in order to
eliminate imbalanced ground return currents from degrading
2nd-harmonic distortion.
2VPP Output
Harmonic Distortion (dBc)
Where a low-power, single-supply, interface to a differential
input +5V ADC is required, the circuit of Figure 12 can
provide a high dynamic range, medium gain interface for
dual high-performance ADCs. The circuit of Figure 12 uses
two amplifiers in the differential inverting configuration. The
common-mode voltage is set on the noninverting inputs to
the supply midscale. In this example, the input signal is
coupled in through a 1:2 transformer. This provides both
signal gain, single to differential conversion, and a reduction
in noise figure. To show a 50Ω input impedance at the input
to the transformer, two 200Ω resistors are required on the
transformer secondary. These two resistors are also the
amplifier gain elements. Since the same DC voltage appears
on both inverting nodes in the circuit of Figure 12, no DC
current will flow through the transformer, giving a DC gain of
1 to the output for this common-mode voltage, VCM.
3rd-Harmonic
–60
2nd-Harmonic
–70
No Pull-Down
3rd-Harmonic
–80
2nd-Harmonic
5mA/Ch Pull-Down
–90
1
10
20
Frequency (MHz)
FIGURE 13. Harmonic Distortion vs Frequency.
DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to assist in
the initial evaluation of circuit performance using the OPA4684
in its two package options. Both of these are offered free of
charge as unpopulated PCBs, delivered with a user's guide.
The summary information for these fixtures is shown in
Table I.
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA4684ID
OPA4684IPW
SO-14
TSSOP-14
DEM-OPA-SO-4A
DEM-OPA-TSSOP-4A
SBOU016
SBOU017
TABLE I. Demonstration Fixtures by Package.
The demonstration fixtures can be requested at the Texas
Instruments web site (www.ti.com) through the OPA4684
product folder.
+5V
10kΩ
VCM
0.1µF
10kΩ
1/4
OPA4684
Dual ADC
500Ω
1:2
200Ω
800Ω
RS
200Ω
800Ω
RS
50Ω
Source
CL
14.7dB
Noise Figure
1 of 2
Channels
1/4
OPA4684
VCM
500Ω
Gain = 8V/V
18.1dB
FIGURE 12. Single-Supply Differential ADC Driver (1 of 2 Channels).
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17
MACROMODELS
Computer simulation of circuit performance using SPICE is
often useful in predicting the performance of analog circuits
and systems. This is particularly true for Video and RF
amplifier circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. Check the TI
web site (www.ti.com) for SPICE macromodels within the
OPA4684 product folder. These models do a good job of
predicting small-signal AC and transient performance under
a wide variety of operating conditions. They do not do as well
in predicting distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types
in their small-signal AC performance.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH
approaching 1.00; this shows up in a slightly higher CMRR
than previous current-feedback op amps.
RI, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA4684 reduces this
element to approximately 4.0Ω using the local loop gain of
the input buffer stage. This significant reduction in output
impedance, on very low power, contributes powerfully to
extending the bandwidth at higher gains.
A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the
output through an internal frequency-dependent
transimpedance gain. The Typical Characteristics show this
open-loop transimpedance response. This is analogous to
the open-loop voltage gain curve for a voltage-feedback op
amp. Developing the transfer function for the circuit of Figure 14
gives Equation 1:
(1)
Any current-feedback op amp like the OPA4684 can hold
high bandwidth over signal-gain settings with the proper
adjustment of the external resistor values. A low-power part
like the OPA4684 typically shows a larger change in bandwidth due to the significant contribution of the inverting input
impedance to loop-gain changes as the signal gain is changed.
Figure 14 shows a simplified analysis circuit for any currentfeedback amplifier.
VO
=
VI

R 
α 1 + F 
 RG 
α NG
=
R

F + RI NG
R 
RF + RI 1 + F  1 +
Z (S )
 RG 
1+
Z (S )


R 
NG = 1 + F  
R


G  
VI
This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(S) were infinite over all frequencies, the
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation.
α
VO
RI
iERR
Z(S) iERR
RF
RG
Z (S )
RF + RI NG
FIGURE 14. Current-Feedback Transfer Function Analysis
Circuit.
The key elements of this current-feedback op amp model
are:
α ⇒ Buffer gain from the noninverting input to the inverting input
RI ⇒ Buffer output impedance
iERR ⇒ Feedback error current signal
Z(S) ⇒ Frequency-dependent open-loop transimpedance gain
from iERR to VO
The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however,
set the CMRR for a single op amp differential
amplifier configuration. For the buffer gain α < 1.0, the
CMRR = –20 • log(1 – α). The closed-loop input stage buffer
used in the OPA4684 gives a buffer gain more closely
18
= Loop Gain
(2)
If 20 • log(RF + NG • RI) were drawn on top of the open-loop
transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z(S) rolls off
to equal the denominator of Equation 2 at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier’s closed-loop
frequency response given by Equation 1 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage feedback op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG).
The OPA4684 is internally compensated to give a maximally
flat frequency response for RF = 800Ω at NG = 2 on ±5V
supplies. That optimum value goes to 1.0kΩ on a single +5V
supply. Normally, with a current-feedback amplifier, it is
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possible to adjust the feedback resistor to hold this bandwidth up as the gain is increased. The CFBPLUS architecture
has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without
adjusting the feedback resistor value. The Typical Characteristics show the small-signal bandwidth over gain with a fixed
feedback resistor.
Putting a closed-loop buffer between the noninverting and
inverting inputs does bring some added considerations. Since
the voltage at the inverting output node is now the output of
a locally closed-loop buffer, parasitic external capacitance on
this node can cause frequency response peaking for the
transfer function from the noninverting input voltage to the
inverting node voltage. While it is always important to keep
the inverting node capacitance low for any current-feedback
op amp, it is critically important for the OPA4684. External
layout capacitance in excess of 2pF will start to peak the
frequency response. This peaking can be easily reduced by
then increasing the feedback resistor value—but it is preferable, from a noise and dynamic range standpoint, to keep
that capacitance low, allowing a close to nominal 800Ω
feedback resistor for flat frequency response. Very high
parasitic capacitance values on the inverting node (> 5pF)
can possibly cause input stage oscillation that cannot be
filtered by a feedback element adjustment.
At very high gains, 2nd-order effects in the inverting output
impedance cause the overall response to peak up. If desired,
it is possible to retain a flat frequency response at higher
gains by adjusting the feedback resistor to higher values as
the gain is increased. Since the exact value of feedback that
will give a flat frequency response depends strongly in
inverting and output node parasitic capacitance values, it is
best to experiment in the specific board with increasing
values until the desired flatness (or pulse response shape) is
obtained. In general, increasing RF (and then adjusting RG to
the desired gain) will move towards flattening the response,
while decreasing it will extend the bandwidth at the cost of
some peaking.
OUTPUT CURRENT AND VOLTAGE
The OPA4684 provides output voltage and current capabilities that can support the needs of driving doubly-terminated
50Ω lines. For a 100Ω load at the gain of +2, (see Figure 1),
the total load is the parallel combination of the 100Ω load and
the 1.6kΩ total feedback network impedance. This 94Ω load
will require no more than 40mA output current to support
the ±3.8V minimum output voltage swing specified for
100Ω loads. This is well under the specified minimum
+110mA/–90mA output current specifications over the full
temperature range.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Voltage and Current Limitations curve in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA4684’s output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures will increase, decreasing their VBEs (increasing the available output voltage
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the available output voltage and current will always be greater than
that shown in the over temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To maintain maximum output stage linearity, no output shortcircuit protection is provided. This will not normally be a
problem since most applications include a series-matching
resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to a power-supply
pin will, in most cases, destroy the amplifier. If additional
short-circuit protection is required, consider a small-series
resistor in the power-supply leads. This will, under heavy
output loads, reduce the available output voltage swing. A 5Ω
series resistor in each power-supply lead will limit the internal
power dissipation to less than 1W for an output short-circuit
while decreasing the available output voltage swing only
0.25V for up to 50mA desired load currents. This slight drop
in available swing is more if multiple channels are driving
heavy loads simultaneously. Always place the 0.1µF powersupply decoupling capacitors after these supply current limiting resistors, directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA4684 can be very susceptible to decreased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
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19
The Typical Characteristics show the recommended RS vs
CLOAD and the resulting frequency response at the load. The
1kΩ resistor shown in parallel with the load capacitor is a
measurement path and may be omitted. Parasitic capacitive
loads greater than 5pF can begin to degrade the performance of the OPA4684. Long PCB traces, unmatched cables,
and connections to multiple devices can easily cause this
value to be exceeded. Always consider this effect carefully,
and add the recommended series resistor as close as possible to the OPA4684 output pin (see the Board Layout
Guidelines section).
DISTORTION PERFORMANCE
The OPA4684 provides very low distortion in a low-power
part. The CFBPLUS architecture also gives two significant
areas of distortion improvement. First, in operating regions
where the 2nd-harmonic distortion due to output stage
nonlinearities is very low (frequencies < 1MHz, low output
swings into light loads), the linearization at the inverting node
provided by the CFBPLUS design gives 2nd-harmonic distortions that extend into the –90dBc region. Previous currentfeedback amplifiers have been limited to approximately
–85dBc due to the nonlinearities at the inverting input. The
second area of distortion improvement comes in a distortion
performance that is largely gain independent. To the extent
that the distortion at a particular output power is output stage
dependent, 3rd-harmonics particularly, and to a lesser extent
2nd-harmonic distortion, is constant as the gain is increased.
This is due to the constant loop gain versus signal gain
provided by the CFBPLUS design. As shown in the Typical
Characteristic curves, while the 3rd-harmonic is constant
with gain, the 2nd-harmonic degrades at higher gains. This
is largely due to board parasitic issues. Slightly imbalanced
load return currents will couple into the gain resistor to cause
a portion of the 2nd-harmonic distortion. At high gains, this
imbalance has more gain to the output giving reduced 2ndharmonic distortion. Differential stages using two of the
channels together can reduce this 2nd-harmonic issue enormously getting back to an essentially gain independent
distortion.
Relative to alternative amplifiers with < 2mA/ch supply current, the OPA4684 holds much lower distortion at higher
frequencies (> 5MHz) and to higher gains. Generally, until
the fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
lower 3rd-harmonic component. Focusing then on the 2ndharmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network—in the noninverting configuration (see Figure 1) this
is the sum of RF + RG, while in the inverting configuration it
is just RF. Also, providing an additional supply decoupling
capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
high slew rate or output power are required. This also acts to
actually reduce the distortion slightly at higher output power
levels. The Typical Characteristic curves show the 2ndharmonic holding constant from 500mVPP to 5VPP outputs
while the 3rd-harmonics actually decrease with increasing
output power.
The OPA4684 has an extremely low 3rd-order harmonic
distortion, particularly for light loads and at lower frequencies. This also gives low 2-tone, 3rd-order intermodulation
distortion as shown in the Typical Characteristic curves.
Since the OPA4684 includes internal power boost circuits to
retain good full-power performance at high frequencies and
outputs, it does not show a classical 2-tone, 3rd-order
intermodulation intercept characteristic. Instead, it holds relatively low and constant 3rd-order intermodulation spurious
levels over power. The Typical Characteristic curves show
this spurious level as a dBc below the carrier at fixed center
frequencies swept over single-tone power at a matched 50Ω
load. These spurious levels drop significantly (> 12dB) for
loads lighter than the 100Ω used in the 2-Tone, 3rd-Order
Intermodulation Distortion curve. Converter inputs, for instance, will see < –82dBc 3rd-order spurious to 10MHz for
full-scale inputs. For even lower 3rd-order intermodulation
distortion to much higher frequencies, consider the OPA2691
dual or OPA691 and OPA695 single-channel current-feedback amplifiers.
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps.
The OPA4684 offers an excellent balance between voltage
and current noise terms to achieve low output noise in a lowpower amplifier. The inverting current noise (17pA/√Hz) is
comparable to most other current-feedback op amps while
the input voltage noise (3.7nV/√Hz) is lower than any unitygain stable, comparable slew rate, voltage-feedback op amp.
This low input voltage noise was achieved at the price of
higher noninverting input current noise (9.4pA/√Hz). As long
as the AC source impedance looking out of the noninverting
node is less than 200Ω, this current noise will not contribute
significantly to the total output noise. The op amp input
voltage noise and the two input current noise terms combine
to give low output noise under a wide variety of operating
conditions. Figure 15 shows the op amp noise analysis
model with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current density
terms in either nV/√Hz or pA/√Hz.
ENI
1/4
OPA4684
RS
RF
ERS
√ 4kTRS
In most op amps, increasing the output voltage swing increases harmonic distortion directly. A low-power part like
the OPA4684 includes quiescent boost circuits to provide the
large-signal bandwidth in the Electrical Characteristics. These
act to increase the bias in a very linear fashion only when
EO
IBN
RG
4kT
RG
IBI
√ 4kTRF
4kT = 1.6E –20J
at 290°K
FIGURE 15. Op Amp Noise Analysis Model.
20
OPA4684
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The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms presented in Figure 12.
(3)
configuration of Figure 1, using worst-case +25°C input offset
voltage and the two input bias currents, gives a worst-case
output offset range equal to:
±(NG • VOS(MAX)) + (IBN • RS/2 • NG) ± (IBI • RF)
where NG = noninverting signal gain
= ±(2 • 4.0mV) ± (13µA • 25Ω • 2) ± (800Ω • 17µA)
EO
2
2
=  ENI2 + (IBNR S ) + 4kTRS  GN2 + (IBIRF ) + 4kTRF GN
Dividing this expression by the noise gain (GN = (1+RF/RG))
will give the equivalent input referred spot noise voltage at
the noninverting input, as shown in Equation 4.
(4)
2
I R 
4kTRF
2
EN = ENI2 + (IBNR S ) + 4kTRS +  BI F  +
GN
 GN 
= ±8mV + 0.65mV ± 13.6mV
= ±22.3mV
While the last term, the inverting bias current error, is
dominant in this low-gain circuit, the input offset voltage will
become the dominant DC error term as the gain exceeds
5V/V. Where improved DC precision is required in a highspeed amplifier, consider the OPA656 single and OPA4820
quad voltage-feedback amplifiers.
THERMAL ANALYSIS
Evaluating these two equations for the OPA4684 circuit and
component values presented in Figure 1 will give a total
output spot noise voltage of 16.3nV/√Hz and a total equivalent input spot noise voltage of 8.1nV/√Hz. This total input
referred spot noise voltage is higher than the 3.7nV/√Hz
specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current
noise times the feedback resistor. As the gain is increased,
this fixed output noise power term contributes less to the
total output noise and the total input referred voltage noise
given by Equation 3 will approach just the 3.7nV/√Hz of the
op amp itself. For example, going to a gain of +20 in the
circuit of Figure 1, adjusting only the gain resistor to 42.1Ω,
will give a total input referred noise of 3.9nV/√Hz. A more
complete description of op amp noise analysis can be found
in the Texas Instruments application note, AB-103, Noise
Analysis for High Speed Op Amps (SBOA066), available for
download at www.ti.com.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA4684 provides
exceptional bandwidth in high gains, giving fast pulse settling
but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high slew
rate voltage-feedback amplifiers. However, the two input
bias currents are somewhat higher and are unmatched.
Whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband currentfeedback op amps. Since the two input bias currents are
unrelated in both magnitude and polarity, matching the
source impedance looking out of each input to reduce their
error contribution to the output is ineffective. Evaluating the
The OPA4684 will not require external heatsinking or airflow
most applications. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 150°C.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL depends on the required
output signal and load; for a grounded resistive load, PDL
would be at a maximum when the output is fixed at a voltage
equal to 1/2 either supply voltage (for equal bipolar supplies).
Under this condition PDL = VS2/(4 • RL), where RL includes
feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
TJ using an OPA4684IPW (TSSOP-14 package) in the circuit
of Figure 1 operating at the maximum specified ambient
temperature of +85°C with all channels driving a grounded
100Ω load to 2.5VDC.
PD = 10V • 7.8mA + 4 • (52 /(4 • (100Ω  1.6kΩ))) = 144mW
Maximum TJ = +85°C + (0.144W • 110°C/W) = 101°C.
This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst-case output stage power
was assumed in this calculation with all four channels running maximum output power simultaneously.
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21
BOARD LAYOUT GUIDELINES
design. Note that a 800Ω feedback resistor, rather than
a direct short, is required for the unity-gain follower
application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability.
Achieving optimum performance with a high-frequency amplifier like the OPA4684 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a)
Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b)
Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power-plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capacitors. The power-supply connections should always be
decoupled with these capacitors. An optional supply decoupling capacitor (0.01µF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic
distortion performance. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequencies,
should also be used on the main supply pins. These
may be placed somewhat farther from the device and
may be shared among several devices in the same area
of the PCB.
c)
Careful selection and placement of external components will preserve the high-frequency performance
of the OPA4684. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composition axially-leaded resistors can also provide good highfrequency performance. Again, keep their leads and
PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the
most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close
as possible to the output pin. The quad amplifier pinout
allows each output and inverting input to be connected
by the feedback element with virtually no trace length.
Other network components, such as noninverting input
termination resistors, should also be placed close to the
package. The frequency response is primarily determined by the feedback resistor value as described
previously. Increasing its value will reduce the peaking
at higher gains, while decreasing it will give a more
peaked frequency response at lower gains. The 800Ω
feedback resistor used in the Typical Characteristics at
a gain of +2 on ±5V supplies is a good starting point for
22
d)
Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the
trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power
planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended
R S vs C LOAD . Low parasitic capacitive loads
(< 5pF) may not need an RS since the OPA4684 is
nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally not
necessary on board, and in fact a higher impedance
environment will improve distortion; see the distortion
versus load plots. With a characteristic board trace
impedance defined based on board material and trace
dimensions, a matching series resistor into the trace
from the output of the OPA4684 is used, as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance
will be the parallel combination of the shunt resistor and
the input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. The high output voltage and current capability of the OPA4684 allows multiple destination devices to
be handled as separate transmission lines, each with
their own series and shunt terminations. If the 6dB
attenuation of a doubly-terminated transmission line is
unacceptable, a long trace can be series-terminated at
the source end only. Treat the trace as a capacitive load
in this case and set the series resistor value as shown
in the plot of RS vs CLOAD. This will not preserve signal
integrity as well as a doubly-terminated line. If the input
impedance of the destination device is low, there will be
some signal attenuation due to the voltage divider formed
by the series output into the terminating impedance.
e)
Socketing a high-speed part like the OPA4684 is not
recommended. The additional lead length and pin-topin capacitance introduced by the socket can create an
extremely troublesome parasitic network, which can
make it almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by soldering the OPA4684 onto the board.
OPA4684
www.ti.com
SBOS240G
INPUT AND ESD PROTECTION
The OPA4684 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table where an absolute maximum 13V across
the supply pins is reported. All device pins have limited ESD
protection using internal diodes to the power supplies, as
shown in Figure 16.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (for example, in systems with ±15V
supply parts driving into the OPA4684), current limiting
series resistors should be added into the two inputs. Keep
these resistor values as low as possible since high values
degrade both noise performance and frequency response.
+VCC
External
Pin
–VCC
FIGURE 16. Internal ESD Protection.
OPA4684
SBOS240G
Internal
Circuitry
www.ti.com
23
Revision History
DATE
REVISION
7/08
G
6/06
F
PAGE
SECTION
2
Abs Max Ratings
3, 4
Electrical Characteristics,
Power Supply
17
Design-In Tools
24
Applications Information
DESCRIPTION
Changed Storage Temperature Range from −40°C to +125C to
−65°C to +125C.
Added minimum supply voltage. Changed min and max quiescent current
values from total to per channel.
Demonstration fixture numbers changed.
Added Revision History table.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
24
OPA4684
www.ti.com
SBOS240G
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA4684ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4684
OPA4684IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4684
OPA4684IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA4684
OPA4684IPWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
4684
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA4684 :
• Military: OPA4684M
NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA4684IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
OPA4684IPWT
TSSOP
PW
14
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA4684IDR
SOIC
D
14
2500
367.0
367.0
38.0
OPA4684IPWT
TSSOP
PW
14
250
210.0
185.0
35.0
Pack Materials-Page 2
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