Texas Instruments | Wideband, Low-Distortion, Fully Differential Amplifiers (Rev. D) | Datasheet | Texas Instruments Wideband, Low-Distortion, Fully Differential Amplifiers (Rev. D) Datasheet

Texas Instruments Wideband, Low-Distortion, Fully Differential Amplifiers (Rev. D) Datasheet
DGN-8
DGK-8
THS4504
THS4505
D-8
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
23
•
•
•
Fully Differential Architecture
Bandwidth: 260 MHz
Slew Rate: 1800 V/µs
IMD3: –73 dBc at 30 MHz
OIP3: 29 dBm at 30 MHz
Output Common-Mode Control
Wide Power-Supply Voltage Range: 5 V, ±5 V,
12 V, 15 V
Input Common-Mode Range Shifted to Include
the Negative Power-Supply Rail
Power-Down Capability (THS4504)
Evaluation Module Available
•
•
•
•
High Linearity Analog-to-Digital Converter
Preamplifier
Wireless Communication Receiver Chains
Single-Ended to Differential Conversion
Differential Line Driver
Active Filtering of Differential Signals
VIN−
1
8
VIN+
VOCM
2
7
PD
VS+
3
6
VS−
VOUT+
4
5
VOUT−
RELATED DEVICES
DESCRIPTION
DEVICE (1)
The THS4504 and THS4505 are high-performance,
fully differential amplifiers from Texas Instruments.
The THS4504, featuring power-down capability, and
the THS4505, without power-down capability, set new
performance standards for fully differential amplifiers
with unsurpassed linearity, supporting 12-bit
operation through 40 MHz. Package options include
the SOIC-8 and the MSOP-8 with PowerPAD™ for a
smaller footprint, enhanced ac performance, and
improved thermal dissipation capability.
(1)
DESCRIPTION
THS4504/5
260 MHz, 1800 V/µs, VICR Includes VS–
THS4500/1
370 MHz, 2800 V/µs, VICR Includes VS–
THS4502/3
370 MHz, 2800 V/µs, Centered VICR
THS4120/1
3.3 V, 100 MHz, 43 V/µs, 3.7 nV/√Hz
THS4130/1
15 V, 150 MHz, 51 V/µs, 1.3 nV/√Hz
THS4140/1
15 V, 160 MHz, 450 V/µs, 6.5 nV/√Hz
THS4150/1
15 V, 150 MHz, 650 V/µs, 7.6 nV/√Hz
Even numbered devices feature power-down capability
APPLICATION CIRCUIT DIAGRAM
8.2 pF
499 Ω
5V
50 Ω
VS
0.1 µF
487 Ω
24.9 Ω
+
53.6 Ω
5V
10 µF
-
ADC
12 Bit/80 MSps
IN
VOCM
1 µF
-
IN
+
24.9 Ω
Vref
523 Ω
499 Ω
8.2 pF
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2008, Texas Instruments Incorporated
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage, VS
16.5 V
Input voltage, VI
±VS
Output current, IO
150 mA
Differential input voltage, VID
4V
Continuous power dissipation
See Package Dissipation Ratings table
Maximum junction temperature, TJ
+150°C
Maximum junction temperature, continuous operation, long-term reliability, TJ
(2)
+125°C
Storage temperature range, Tstg
–65°C to +150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
+300°C
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS
(1)
(2)
POWER RATING (2)
PACKAGE
θJC (°C/W)
θJA (°C/W) (1)
TA ≤ +25°C
TA = +85°C
D (8-pin)
38.3
97.5
1.02 W
410 mW
DGN (8-pin)
4.7
58.4
1.71 W
685 mW
DGK (8-pin)
54.2
260
385 mW
154 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long
term reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX
Supply voltage
Dual supply
Single supply
4.5
Operating free-air temperature, TA
2
Submit Documentation Feedback
–40
±5
±7.5
5
15
+85
UNIT
V
°C
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
THS4504
THS4505
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
ORDERING INFORMATION (1)
PACKAGED DEVICES
PACKAGE TYPE
PACKAGE MARKINGS
SOIC-8
—
MSOP-8
ASZ
MSOP-8-PP (2)
BDB
SOIC-8
—
MSOP-8
ATA
MSOP-8-PP (2)
BDC
TRANSPORT MEDIA, QUANTITY
Power-down
THS4504D
THS4504DR
THS4504DGK
THS4504DGKR
THS4504DGN
THS4504DGNR
Rails, 75
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Rails, 80
Tape and Reel, 2500
Non-power-down
THS4505D
THS4505DR
THS4505DGK
THS4505DGKR
THS4505DGN
THS4505DGNR
(1)
(2)
Rails, 75
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Rails, 80
Tape and Reel, 2500
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The PowerPAD is electrically isolated from all other pins.
PIN ASSIGNMENTS
D, DGK, AND DGN
THS4504
(TOP VIEW)
D, DGK, AND DGN
THS4505
(TOP VIEW)
V IN-
1
8
V IN+
V IN-
1
8
V IN+
V OCM
2
7
PD
V OCM
2
7
NC
V S+
3
6
V S-
V S+
3
6
V S-
V OUT+
4
5
V OUT-
V OUT+
4
5
V OUT-
See Note A.
NC = No Internal Connection
A. The devices with the power-down option default to the ON state if no signal is applied to the PD pin.
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
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THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5 V
VS = ±5 V, RF = RG = 499 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
PARAMETER
TEST CONDITIONS
TYP
+25°C
OVER TEMPERATURE
0°C to
+70°C
+25°C
–40°C to
+85°C
UNIT
MIN/
TYP/
MAX
AC PERFORMANCE
G = 1, PIN = –20 dBm,
RF = 499 Ω
260
MHz
Typ
G = 2, PIN = –20 dBm,
RF = 499 Ω
110
MHz
Typ
G = 5, PIN = –20 dBm,
RF = 499 Ω
40
MHz
Typ
G = 10, PIN = –20 dBm,
RF = 499 Ω
20
MHz
Typ
Gain-bandwidth product
G > +10
210
MHz
Typ
Bandwidth for 0.1-dB flatness
PIN = –20 dBm
65
MHz
Typ
Large-signal bandwidth
G = 1, VP = 2 V
250
MHz
Typ
Slew rate
4 VPP Step
1800
V/µs
Typ
Rise time
2 VPP Step
0.8
ns
Typ
Fall time
2 VPP Step
1
ns
Typ
Settling time to 0.01%
VO = 4 VPP
100
ns
Typ
0.1%
VO = 4 VPP
20
ns
Typ
Harmonic distortion
G = 1, VO = 2 VPP
f = 8 MHz
–79
dBc
Typ
f = 30 MHz
–66
dBc
Typ
f = 8 MHz
–93
dBc
Typ
f = 30 MHz
–65
dBc
Typ
Third-order intermodulation
distortion
VO = 2 VPP, fC= 30 MHz,
RF = 499 Ω,
200 kHz tone spacing
–73
dBc
Typ
Third-order output intercept point
fC = 30 MHz, Rf = 499 Ω,
Referenced to 50 Ω
29
dBm
Typ
Input voltage noise
f > 1 MHz
8
nV/√Hz
Typ
Input current noise
f > 100 kHz
2
pA/√Hz
Typ
Overdrive recovery time
Overdrive = 5.5 V
60
ns
Typ
Small-signal bandwidth
2nd harmonic
3rd harmonic
Typ
DC PERFORMANCE
Open-loop voltage gain
55
52
50
50
dB
Min
Input offset voltage
–4
–7/–1
–8/0
–9/+1
mV
Max
±10
±10
µV/°C
Typ
4
4.6
5
5.2
µA
Max
±10
±10
nA/°C
Typ
0.5
1
2
2
µA
Max
±40
±40
nA/°C
Typ
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
4
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Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
THS4504
THS4505
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
VS = ±5 V, RF = RG = 499 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNIT
MIN/
TYP/
MAX
INPUT
Common-mode input range
–5.7/2.6
–5.4/2.3
–5.1/2
–5.1/2
V
Min
Common-mode rejection ratio
80
74
70
70
dB
Min
Input impedance
7
Ω || pF
Typ
Min
10 || 1
OUTPUT
Differential output voltage swing
RL = 1 kΩ
±8
±7.6
±7.4
±7.4
V
Differential output current drive
RL = 20 Ω
130
110
100
100
mA
Min
Output balance error
PIN = –20 dBm, f = 100 kHz
–65
dB
Typ
Closed-loop output impedance
(single-ended)
f = 1 MHz
0.1
Ω
Typ
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
RL = 400 Ω
200
MHz
Typ
Slew rate
2 VPP Step
92
V/µs
Typ
Minimum gain
1
0.98
0.98
0.98
V/V
Min
Maximum gain
1
1.02
1.02
1.02
V/V
Max
–0.4
–4.6/+3.8
–6.6/+5.8
–7.6/+6.8
mV
Max
100
150
170
170
µA
Max
±4
±3.7
±3.4
±3.4
Common-mode offset voltage
Input bias current
VOCM = 2.5 V
Input voltage range
Input impedance
25 || 1
V
Min
kΩ || pF
Typ
Maximum default voltage
VOCM left floating
0
0.05
0.10
0.10
V
Max
Minimum default voltage
VOCM left floating
0
–0.05
–0.10
–0.10
V
Min
Specified operating voltage
±5
±7.5
±7.5
±7.5
V
Max
Maximum quiescent current
16
20
23
25
mA
Max
Minimum quiescent current
16
13
11
9
mA
Min
Power-supply rejection (±PSRR)
80
76
73
70
dB
Min
POWER SUPPLY
POWER-DOWN (THS4504 ONLY)
Enable voltage threshold
Device enabled ON above –2.9 V
–2.9
V
Min
Disable voltage threshold
Device disabled OFF below
–4.3 V
–4.3
V
Max
Power-down quiescent current
800
1000
1200
1200
µA
Max
Input bias current
200
240
260
260
µA
Max
Input impedance
50 || 1
kΩ || pF
Typ
Turn-on time delay
1000
ns
Typ
Turn-off time delay
800
ns
Typ
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
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THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = 5 V
VS = 5 V, RF = RG = 499 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C
to
+85°C
UNIT
MIN/TYP/
MAX
AC PERFORMANCE
G = 1, PIN = –20 dBm, RF = 499 Ω
210
MHz
Typ
G = 2, PIN = –20 dBm, RF = 499 Ω
120
MHz
Typ
G = 5, PIN = –20 dBm, RF = 499 Ω
40
MHz
Typ
G = 10, PIN = –20 dBm, RF = 499 Ω
20
MHz
Typ
Gain-bandwidth product
G > +10
200
MHz
Typ
Bandwidth for 0.1-dB
flatness
PIN = –20 dBm
100
MHz
Typ
Large-signal bandwidth
G = 1, VP = 1 V
200
MHz
Typ
Slew rate
2 VPP Step
900
V/µs
Typ
Rise time
2 VPP Step
1.1
ns
Typ
Fall time
2 VPP Step
1
ns
Typ
Settling time to 0.01%
VO = 2 V Step
100
ns
Typ
0.1%
VO = 2 V Step
20
ns
Typ
Harmonic distortion
G = 1, VO = 2 VPP
Small-signal bandwidth
Typ
f = 8 MHz,
–77
dBc
Typ
f = 30 MHz
–56
dBc
Typ
f = 8 MHz
–74
dBc
Typ
f = 30 MHz
–57
dBc
Typ
Third-order intermodulation
distortion
VO = 2 VPP, fC = 30 MHz,
RF = 499 Ω,
200 kHz tone spacing
–72
dBc
Typ
Third-order output
intercept point
fC = 30 MHz, RF = 499 Ω,
Referenced to 50 Ω
28
dBm
Typ
Input voltage noise
f > 1 MHz
8
nV/√Hz
Typ
Input current noise
f > 100 kHz
2
pA/√Hz
Typ
Overdrive recovery time
Overdrive = 5.5 V
60
ns
Typ
dB
Min
Max
2nd harmonic
3rd harmonic
DC PERFORMANCE
Open-loop voltage gain
54
51
49
49
Input offset voltage
–4
–7/–1
–8/0
–9/+1
mV
±10
±10
µV/°C
Typ
5
5.2
µA
Max
±10
±10
nA/°C
Typ
1.2
1.2
µA
Max
±20
±20
nA/°C
Typ
Average offset voltage drift
Input bias current
4
4.6
0.5
0.7
Average bias current drift
Input offset current
Average offset current drift
6
Submit Documentation Feedback
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
THS4504
THS4505
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
VS = 5 V, RF = RG = 499 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
TYP
PARAMETER
OVER TEMPERATURE
TEST CONDITIONS
+25°C
+25°C
0°C to
+70°C
–40°C
to
+85°C
UNIT
MIN/TYP/
MAX
–0.7/2.6
–0.4/2.3
–0.1/2
–0.1/2
V
Min
80
74
70
70
INPUT
Common-mode input range
Common-mode rejection ratio
107 || 1
Input impedance
dB
Min
Ω || pF
Typ
Min
OUTPUT
Differential output voltage swing
RL = 1 kΩ, Referenced to 2.5 V
±3.3
±3
±2.8
±2.8
V
Output current drive
RL = 20 Ω
110
90
80
80
mA
Min
Output balance error
PIN = –20 dBm, f = 100 kHz
–38
dB
Typ
Closed-loop output
impedance (single-ended)
f = 1 MHz
0.1
Ω
Typ
MHz
Typ
V/µs
Typ
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
RL = 400 Ω
160
Slew rate
2 VPP Step
80
Minimum gain
1
0.98
0.98
0.98
V/V
Min
Maximum gain
1
1.02
1.02
1.02
V/V
Max
0.4
–2.6/3.4
–4.2/5.4
–5.6/6.4
mV
Max
Common-mode offset
voltage
Input bias current
VOCM = 2.5 V
Input voltage range
Input impedance
1
2
3
3
µA
Max
1/4
1.2/3.8
1.3/3.7
1.3/3.7
V
Min
kΩ || pF
Typ
Maximum default voltage
VOCM left floating
25 || 1
2.5
2.55
2.6
2.6
V
Max
Minimum default voltage
VOCM left floating
2.5
2.45
2.4
2.4
V
Min
Specified operating voltage
5
15
15
15
V
Max
Maximum quiescent current
14
17
19
21
mA
Max
Minimum quiescent current
14
11
10
8
mA
Min
Power-supply rejection (+PSRR)
75
72
69
66
dB
Min
POWER SUPPLY
POWER-DOWN (THS4504 ONLY)
Enable voltage threshold
Device enabled ON above 2.1 V
2.1
V
Min
Disable voltage threshold
Device disabled OFF below
0.7 V
0.7
V
Max
µA
Max
Power-down quiescent
current
600
800
1200
1200
Input bias current
100
125
140
140
µA
Max
Input impedance
50 || 1
kΩ || pF
Typ
Turn-on time delay
1000
ns
Typ
Turn-off time delay
800
ns
Typ
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
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THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small-signal unity-gain frequency response
1
Small-signal frequency response
2
0.1-dB gain flatness frequency response
3
Large-signal frequency response
4
Harmonic distortion (single-ended input to differential output) vs Frequency
5
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
6, 7
Harmonic distortion (single-ended input to differential output) vs Load resistance
8
Third order intermodulation distortion (single-ended input to differential output) vs Frequency
9
Third order output intercept point vs Frequency
10
Slew rate vs Differential output voltage step
11
Settling time
12, 13
Large-signal transient response
14
Small-signal transient response
15
Overdrive recovery
16, 17
Voltage and current noise vs Frequency
18
Rejection ratios vs Frequency
19
Rejection ratios vs Case temperature
20
Output balance error vs Frequency
21
Open-loop gain and phase vs Frequency
22
Open-loop gain vs Case temperature
23
Input bias offset current vs Case temperature
24
Quiescent current vs Supply voltage
25
Input offset voltage vs Case temperature
26
Common-mode rejection ratio vs Input common-mode range
27
Output voltage vs Load resistance
28
Closed-loop output impedance vs Frequency
29
Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage
30
Small-signal frequency response at VOCM
31
Output offset voltage at VOCM vs Output common-mode voltage
32
Quiescent current vs Power-down voltage
33
Turn-on and turn-off delay times
34
Single-ended output impedance in power-down vs Frequency
35
Power-down quiescent current vs Case temperature
36
Power-down quiescent current vs Supply voltage
37
8
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THS4504
THS4505
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
Table of Graphs (5 V)
FIGURE
Smal-signal unity-gain frequency response
38
Small-signal frequency response
39
0.1-dB gain flatness frequency response
40
Large signal frequency response
41
Harmonic distortion (single-ended input to differential output) vs Frequency
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
42
43, 44
Harmonic distortion (single-ended input to differential output) vs Load resistance
45
Third-order intermodulation distortion vs Frequency
46
Third-order intercept point vs Frequency
47
Slew rate vs Differential output voltage step
48
Settling time
49, 50
Overdrive recovery
51, 52
Large-signal transient response
53
Small-signal transient response
54
Voltage and current noise vs Frequency
55
Rejection ratios vs Frequency
56
Rejection ratios vs Case temperature
57
Output balance error vs Frequency
58
Open-loop gain and phase vs Frequency
59
Open-loop gain vs Case temperature
60
Input bias offset current vs Case temperature
61
Quiescent current vs Supply voltage
62
Input offset voltage vs Case temperature
63
Common-mode rejection ratio vs Input common-mode range
64
Output voltage vs Load resistance
65
Closed-loop output impedance vs Frequency
66
Harmonic distortion (single-ended and differential input) vs Output common-mode voltage
67
Small-signal frequency response at VOCM
68
Output offset voltage vs Output common-mode voltage
69
Quiescent current vs Power-down voltage
70
Turn-on and turn-off delay times
71
Single-ended output impedance in power-down vs Frequency
72
Power-down quiescent current vs Case temperature
73
Power-down quiescent current vs Supply voltage
74
Copyright © 2002–2008, Texas Instruments Incorporated
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Product Folder Link(s): THS4504 THS4505
9
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL FREQUENCY
RESPONSE
1
22
0.5
20
−1
−1.5
−2
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN = −20 dBm
VS = ±5 V
−3
0.1
1
16
Gain = 5
14
12
10
8
Gain = 2
6
4
2
10
100
0
−2
0.1
1000
f − Frequency − MHz
−0.25
−0.3
1
10
100
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
Harmonic Distortion − dBc
−10
−20
−30
−40
−50
−60
−70
HD2
−80
−5
0.1
1
10
100
1000
−20
−30
−40
−50
−60
−70
HD2
−80
−90
HD3
−100
0.1
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
−10
−90
HD3
−100
1
10
0
100
0.5
1
1.5 2
2.5 3
3.5 4
4.5
5
VO − Output Voltage Swing − V
f − Frequency − MHz
f − Frequency − MHz
Figure 4.
Figure 5.
Figure 6.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
LOAD RESISTANCE
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
0
Harmonic Distortion − dBc
HD2
−70
−80
HD3
−90
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
VS = ±5 V
−10
−60
Third-Order Intermodulation Distortion − dBc
0
Single Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
−20
−30
−40
HD3, 30 MHz
−50
HD2, 30 MHz
−60
−70
HD2, 8 MHz
−80
−90
−100
0
1000
0
0
RL = 800 Ω
VO = 2 VPP
VS = ±5 V
Gain = 1, Rf = 499 Ω
−50
100
f − Frequency − MHz
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
5
−40
10
1
HARMONIC DISTORTION
vs
FREQUENCY
0
Harmonic Distortion − dBc
1000
LARGE-SIGNAL FREQUENCY
RESPONSE
Gain = 2, Rf = 1.8 kΩ
−30
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = ±5 V
−0.2
Figure 3.
10
−20
−0.15
f − Frequency − MHz
Gain = 5, Rf = 1.8 kΩ
−10
−0.1
Figure 2.
Gain = 10, Rf = 1.8 kΩ
15
RL = 800 Ω
Rf =499 Ω
PIN = −20 dBm
VS = ±5 V
−0.05
Figure 1.
25
20
Rf = 499 Ω
0
Harmonic Distortion − dBc
−2.5
−4
Large Signal Gain − dB
0.05
Gain = 10
0.1 dB Gain Flatness − dB
−0.5
−3.5
0.5
1
1.5 2
2.5
3
3.5 4
4.5
VO − Output Voltage Swing − V
Figure 7.
10
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
18
0
Small Signal Gain − dB
Small Signal Unity Gain − dB
SMALL-SIGNAL UNITY-GAIN
FREQUENCY
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5
HD3, 8 MHz
−100
0
400
800
1200
1600
RL − Load Resistance − Ω
−30
−40
−50
−60
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = ±5 V
VO = 2 VPP
−70
−80
VO = 1 VPP
−90
200 kHz Tone Spacing
−100
10
100
f − Frequency − MHz
Figure 8.
Figure 9.
Copyright © 2002–2008, Texas Instruments Incorporated
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THS4505
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: ±5 V (continued)
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP
1800
1600
200 kHz Tone Spacing
40
Normalized to 50 W
30
Normalized to 200 W
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = ±5 V
1400
Rising Edge
1.0
Rise
1200
1000
800
600
400
RL = 800 W
10
0 0.5
40
60
80
100
1
1.5
2
2.5
3 3.5
4
4.5
-1.5
5
25
30
SMALL-SIGNAL TRANSIENT
RESPONSE
−1
Falling Edge
0.4
1.5
0.3
1
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0.5
0
−0.5
−1
25
30
35
−2
−100
40
6
2
5
1
0.5
0
0
VI − Input Voltage − V
1.5
−1
−0.5
−2
−1
−3
−1.5
−4
−2
Single-Ended Output Voltage − V
2.5
1
0
100
200
300
400
−0.2
−0.4
−100
500
0
100
2
100
2
1
0
0
−1
−1
−2
−3
−2
−4
−3
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − µs
t − Time − µs
Figure 16.
500
OVERDRIVE RECOVERY
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
400
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
3
3
300
Figure 15.
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
4
200
t − Time − ns
Figure 14.
−5
−6
−2.5
−5
−0.1
t − Time − ns
OVERDRIVE RECOVERY
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
0
Hz
20
Figure 17.
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
Vn − Voltage Noise − nV/
15
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0.1
−0.3
VI − Input Voltage − V
10
0.2
Hz
0
2
VO − Output Voltage − V
VO − Output Voltage − V
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
1
5
Single-Ended Output Voltage − V
20
LARGE-SIGNAL TRANSIENT
RESPONSE
Figure 13.
0
15
SETTLING TIME
t − Time − ns
2
10
Figure 12.
−1.5
3
5
0
Figure 11.
−2
4
Falling Edge
Figure 10.
2
5
-0.5
t - Time - ns
Rising Edge
0
f = 1 MHz
VS = ± 5 V
VO − Differential Output Voltage Step − V
3
−3
RF = 499 W
0
-1.0
0
0
20
Gain = 1
RL = 800 W
200
200 kHz Tone Spacing
0
0.5
I n − Current Noise − pA/
20
1.5
Fall
V - Output Voltage - VO
50
Gain = 1, RF = 499 W
VO = 2 VPP, VS = ±5 V
f - Frequency - MHz
VO − Output Voltage − V
SETTLING TIME
2000
60
SR − Slew Rate − V/ µ s
OIP3 - Third-Order Output Intercept Point - dBm
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Vn
10
In
1
0.01
0.1
1
10
100
1000
10 k
f − Frequency − kHz
Figure 18.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
REJECTION RATIOS
vs
CASE TEMPERATURE
90
50
CMMR
PSRR−
40
30
20
10
0
80
60
40
1
10
f − Frequency − MHz
RL = 800 Ω
VS = ±5 V
100
−40
−50
−60
−80
0.1
1
10
100
f − Frequency − MHz
Figure 20.
Figure 21.
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
INPUT BIAS AND OFFSET
CURRENT
vs
CASE TEMPERATURE
58
3.4
RL = 800 Ω
VS = ±5 V
57
0
30
−60
Phase
−90
Open-Loop Gain − dB
−30
Phase − °
56
40
20
3.3
I IB − Input Bias Current − µ A
30
PIN = −30 dBm
RL = 800 Ω
VS = ±5 V
50
55
54
53
52
51
−120
10
50
0.1
1
10
−150
1000
100
0
VS = ±5 V
IIB−
−0.01
−0.02
3.2
IIB+
3.1
−0.03
3
−0.04
2.9
−0.05
2.8
−0.06
IOS
2.7
−0.07
2.6
−0.08
−0.09
2.5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
49
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
f − Frequency − MHz
Figure 23.
Figure 24.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
5
VS = ±5 V
VOS − Input Offset Voltage − mV
TA = 85°C
20
TA = 25°C
15
TA = −40°C
10
5
0
0 0.5
1
1.5
2
2.5
3
3.5
4 4.5
VS − Supply Voltage − ±V
Figure 25.
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5
4
3
2
1
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
CMRR − Common-Mode Rejection Ratio − dB
Figure 22.
25
Quiescent Current − mA
−30
Figure 19.
Gain
12
−20
Case Temperature − °C
60
0
0.01
−10
−70
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−10
0.1
PSRR+
20
RL = 800 Ω
VS = ±5 V
Output Balance Error − dB
Rejection Ratios − dB
60
PIN = 16 dBm
RL = 800 Ω
Rf = 499 Ω
VS = ±5 V
0
CMMR
100
70
Rejection Ratios − dB
10
120
PSRR+
80
Open-Loop Gain − dB
OUTPUT BALANCE ERROR
vs
FREQUENCY
I OS − Input Offset Current − µ A
REJECTION RATIOS
vs
FREQUENCY
110
VS = ±5 V
100
90
80
70
60
50
40
30
20
10
0
−10
−6 −5 −4 −3 −2 −1 0
1
2
3
4
5
6
Input Common-Mode Voltage Range − V
Figure 26.
Figure 27.
Copyright © 2002–2008, Texas Instruments Incorporated
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THS4505
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: ±5 V (continued)
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
5
3
2
VS = ±5 V
TA = −40 to 85°C
1
0
−1
−2
−3
−4
−5
10
100
1000
10
−40
Single-Ended to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
VS = ±5 V
−50
HD3, 30 MHz
−10
Gain = 1
RL = 400 Ω
Rf = 499 Ω
VI = −4 dBm
VS = ±5 V
−20
Harmonic Distortion − dBc
ZO − Closed Loop Output Impedance − Ω
1
−30
−70
HD2, 8 MHz
−80
HD2, 3 MHz
−90
0.1
0.1
10000
RL − Load Resistance − Ω
1
10
f − Frequency − MHz
HD2, 30 MHz
−60
−100
−3.5 −2.5 −1.5 −0.5
100
0.5
1.5
2.5
3.5
VOCM − Output Common-Mode Voltage − V
Figure 28.
Figure 29.
Figure 30.
SMALL-SIGNAL FREQUENCY
RESPONSE AT VOCM
OUTPUT OFFSET VOLTAGE AT VOCM
vs
OUTPUT COMMON-MODE
VOLTAGE
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
30
600
3
1
VOS − Output Offset Voltage − mV
Gain = 1
RL = 400 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = ±5 V
2
0
25
400
Quiescent Current − mA
VO − Output Voltage − V
0
100
4
Small Signal Frequency Response at VOCM − dB
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE
VOLTAGE
200
0
−200
−1
20
15
10
5
−400
−2
−600
−3
1
10
100
1000
f − Frequency − MHz
0
−5
−5 −4 −3 −2 −1
0
1
2
3
4
VOC − Output Common-Mode Voltage − V
Power-Down Voltage − V
Figure 32.
Figure 33.
Figure 31.
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER-DOWN
vs
FREQUENCY
TURN-ON AND
TURN-OFF DELAY TIME
0.01
Current
0
−1
−2
−3
−4
−5
−6
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
102
103
Quiescent Current − mA
Powerdown Voltage Signal − V
0.02
ZO− Single-Ended Output Impedance
in Powerdown − Ω
1500
0.03
0
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0
5
1200
900
600
300
0
0.1
Figure 34.
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VI = −1 dBm
VS = ±5 V
1
10
100
1000
f − Frequency − MHz
Figure 35.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
1000
RL = 800 Ω
VS = ±5 V
900
Power-Down Quiescent Current − µ A
Power-Down Quiescent Current − µ A
1000
800
700
600
500
400
300
200
100
RL = 800 Ω
900
800
700
600
500
400
300
200
100
0
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5 1
1.5 2
2.5 3
3.5 4
4.5 5
VS − Supply Voltage − ±V
Case Temperature − °C
Figure 36.
Figure 37.
TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNITY-GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
1
22
−1
−2
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN = −20 dBm
VS = 5 V
−3
0.1
1
16
Gain = 5
14
12
10
8
Gain = 2
6
4
2
10
100
0
−2
0.1
1000
RL = 800 Ω
Rf = 499 Ω
PIN = −20 dBm
VS = 5 V
1
f − Frequency − MHz
−0.1
−0.15
−0.2
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = 5 V
−0.25
−0.3
10
100
1
1000
10
100
Figure 39.
Figure 40.
LARGE-SIGNAL FREQUENCY
RESPONSE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
FREQUENCY
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = 5 V
Gain = 5, Rf = 1.8 kΩ
10
Gain = 2, Rf = 1.8 kΩ
5
Gain = 1, Rf = 1.8 kΩ
0
−20
−30
−40
−50
−10
Harmonic Distortion − dBc
−10
Harmonic Distortion − dBc
Gain = 10, Rf = 1.8 kΩ
20
RL = 800 Ω
VO = 2 VPP
VS = 5 V
−60
HD3
−70
−80
HD2
−90
1
10
100
1000
f − Frequency − MHz
Figure 41.
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−20
−30
−40
−50
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
−60
HD3
−70
−80
HD2
−90
−100
−5
1000
f − Frequency − MHz
f − Frequency − MHz
0
0.1
Rf = 499 Ω
−0.05
Figure 38.
25
Large Signal Gain − dB
0.1 dB Gain Flatness − dB
Small Signal Gain − dB
Small Signal Unity Gain − dB
0
18
0
−4
14
0.05
Gain = 10
20
15
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
0
0.5
1
1.5
2
2.5
3
3.5
4
VO − Output Voltage Swing − V
−100
0.1
1
10
100
f − Frequency − MHz
Figure 42.
Figure 43.
Copyright © 2002–2008, Texas Instruments Incorporated
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THS4505
www.ti.com ......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: 5 V (continued)
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = 5 V
−40
−50
HD2
−60
−70
HD3
−80
−20
−30
−40
−60
−70
−80
−90
−100
HD3, 8 MHz
−90
0
0.5
1
1.5
2
2.5
3
3.5
0
400
800
1200
1600
Figure 45.
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP
60
80
100
Figure 47.
SETTLING TIME
Single-Ended Output Voltage − V
2
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = 5 V
−1
Falling Edge
−2
0
0.5
1
1.5
2
2.5
3
3.5
3
2
5
10
15
20
25
30
35
40
-0.5
Falling Edge
-1.5
4
Figure 50.
5
10
15
20
Figure 48.
Figure 49.
25
30
OVERDRIVE RECOVERY
2.5
6
2
5
1.5
1
0.5
0
0
−1
−0.5
−2
−1
−3
−1.5
−4
−2
−2.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − µs
t − Time − ns
0
t - Time - ns
1
0
f = 1 MHz
VS = 5 V
VO − Differential Output Voltage Step − V
−5
0
RF = 499 W
0
-1.0
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
4
Gain= 1
RL = 800 W
0.5
OVERDRIVE RECOVERY
Rising Edge
−3
Rise
5
3
0
100
SETTLING TIME
200
f − Frequency − MHz
1
200 kHz Tone Spacing
−100
10
Rising Edge
400
0
40
−90
1.0
600
0
20
VO = 1 VPP
−80
Fall
800
RL = 800 Ω
0
−70
V - Output Voltage - VO
Normalized to 200 Ω
10
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
1000
30
20
−60
VO = 2 VPP
Figure 46.
VI − Input Voltage − V
40
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
−50
1.5
1200
Gain = 1
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
200 kHz Tone Spacing
Normalized to 50 Ω
50
Single-Ended Input to
Differential Output
−40
f − Frequency − MHz
Figure 44.
60
−30
RL − Load Resistance − Ω
SR − Slew Rate − V/ µ s
OIP − Third-Order Output Intersept Point − dBm
3
HD2, 8 MHz
−100
4
VO − Output Voltage Swing − V
VO − Output Voltage − V
HD2, 30 MHz
HD3, 30 MHz
−50
Figure 51.
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
Single-Ended Output Voltage − V
−30
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−20
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
VS = ±5 V
−10
3
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
4
3
2
2
1
1
0
0
−1
−1
−2
−3
VI − Input Voltage − V
0
−10
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
LOAD RESISTANCE
Third-Order Intermodulation Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−2
−4
−5
−6
−3
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − µs
Figure 52.
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TYPICAL CHARACTERISTICS: 5 V (continued)
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0
−0.5
−1
0.2
0
−0.1
−0.2
0
100
200
300
400
−0.4
−100
500
In
0
100
200
300
400
1
0.01
500
OUTPUT BALANCE ERROR
vs
FREQUENCY
0
CMMR
PIN = 16 dBm
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
−10
60
50
CMMR
PSRR−
30
20
PSRR−
80
PSRR+
60
40
20
RL = 800 Ω
VS = 5 V
RL = 800 Ω
VS = 5 V
100
−20
−30
−40
−50
−60
−70
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−10
1
10
f − Frequency − MHz
Output Balance Error − dB
Rejection Ratios − dB
70
−80
0.1
1
Case Temperature − °C
10
Figure 57.
Figure 58.
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
INPUT BIAS AND OFFSET
CURRENT
vs
CASE TEMPERATURE
50
40
56
55
0
Phase − °
−30
−60
30
Phase
−90
20
−120
10
Open-Loop Gain − dB
PIN = −30 dBm
RL = 800 Ω
VS = 5 V
3.75
57
30
Gain
RL = 800 Ω
VS = 5 V
3.50
IIB - Input Bias Current - mA
60
54
53
52
51
50
49
48
47
1
10
100
−150
1000
f − Frequency − MHz
Figure 59.
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100
f − Frequency − MHz
Figure 56.
0.1
10 k
REJECTION RATIOS
vs
CASE TEMPERATURE
100
0
0.01
1000
REJECTION RATIOS
vs
FREQUENCY
120
0.1
100
Figure 55.
PSRR+
0
10
Figure 54.
80
10
1
f − Frequency − kHz
Figure 53.
90
40
0.1
t − Time − ns
t − Time − ns
16
Vn
10
3.25
3.00
0
VS = 5 V
0.01
IIB+
0.02
IIB-
2.75
0.04
2.50
2.25
0.03
0.05
IOS
0.06
2.00
0.07
1.75
0.08
1.50
0.09
IOS - Input Offset Current - mA
−2
−100
Rejection Ratios − dB
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0.1
−0.3
−1.5
Open-Loop Gain − dB
Vn − Voltage Noise − nV/
1
100
Hz
1.5
0.3
I n − Current Noise − pA/
0.4
Hz
2
0.5
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
SMALL-SIGNAL TRANSIENT
RESPONSE
VO − Output Voltage − V
VO − Output Voltage − V
LARGE-SIGNAL TRANSIENT
RESPONSE
0.1
1.25
-40-30-20-10 0 10 20 30 40 50 60 70 80 90
46
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature - °C
Case Temperature − °C
Figure 60.
Figure 61.
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TYPICAL CHARACTERISTICS: 5 V (continued)
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
25
5
VS = 5 V
VOS − Input Offset Voltage − mV
TA = 85°C
TA = 25°C
15
TA = −40°C
10
5
4
3
2
1
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
0
0 0.5
1
1.5
2
2.5
3
3.5
4 4.5
5
70
60
50
40
30
20
10
0
−10
−1
1
2
3
4
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE
VOLTAGE
100
3
2
VS = ±5 V
TA = −40 to 85°C
1
0
−1
−2
−3
−4
100
1000
0
Gain = 1
RL = 400 Ω
Rf = 499 Ω
VIN = −4 dBm
VS = 5 V
10
−20
HD2, 30 MHz
−30
HD3, 30 MHz
−40
−50
−60
−70
−80
0.1
0.1
10000
1
10
f − Frequency − MHz
100
HD2,
8 MHz
1
1.5
HD3, 8 MHz
2
2.5
3
3.5
Figure 66.
Figure 67.
SMALL-SIGNAL FREQUENCY
RESPONSE
AT VOCM
OUTPUT OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE
VOLTAGE
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
800
25
3
VS = 5 V
600
Quiescent Current − mA
VOS − Output Offset Voltage − mV
0
400
200
0
−200
−1
4
VOC − Output Common-Mode Voltage − V
Figure 65.
Gain = 1
RL = 400 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = 5 V
5
Single-Ended to
Differential Output
Gain = 1, VO = 2 VPP
Rf = 499 Ω, VS = 5 V
−10
1
RL − Load Resistance − Ω
1
0
Input Common-Mode Range − V
Figure 64.
ZO − Closed Loop Output Impedance − Ω
VO − Output Voltage − V
80
Figure 63.
4
2
VS = 5 V
90
Figure 62.
5
−5
10
110
100
Case Temperature − °C
VS − Supply Voltage − ±V
Harmonic Distortion − dBc
Quiescent Current − mA
20
Small Signal Frequency Response at VOCM − dB
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
CMRR − Common-Mode Rejection Ratio − dB
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
−400
20
15
10
5
−600
−2
−800
0
0 0.5
−3
1
10
100
1000
1
1.5
2
2.5
3
3.5
4
4.5
5
VOC − Output Common-Mode Voltage − V
f − Frequency − MHz
Figure 68.
Figure 69.
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0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage − V
Figure 70.
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TYPICAL CHARACTERISTICS: 5 V (continued)
SINGLE-ENDED OUTPUT
IMPEDANCE
IN POWER-DOWN
vs
FREQUENCY
TURN-ON AND TURN-OFF
DELAY TIME
0
0
−1
−2
−3
−4
−5
1200
102
900
600
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN = −1 dBm
VS = 5 V
300
0
0.1
−6
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
Power-Down Quiescent Current − µ A
0.01
Quiescent Current − mA
0.02
Current
800
1500
ZO− Single-Ended Output Impedance
in Power Down − Ω
Power-Down Voltage Signal − V
0.03
POWER-DOWN QUIESCENT
CURRENT
vs
CASE TEMPERATURE
103
1
10
100
1000
f − Frequency − MHz
Figure 71.
700
RL = 800 Ω
VS = 5 V
600
500
400
300
200
100
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 72.
Figure 73.
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
Power-Down Quiescent Current − µ A
1000
900
800
700
600
500
400
300
200
100
0
0
0.5 1
1.5 2
2.5 3
3.5 4
4.5 5
VS − Supply Voltage − V
Figure 74.
18
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APPLICATION INFORMATION
•
Additional Reference Material
FULLY DIFFERENTIAL AMPLIFIERS
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems,
including
immunity
to
external
common-mode noise, suppression of even-order
nonlinearities, and increased dynamic range. Fully
differential amplifiers not only serve as the primary
means of providing gain to a differential signal chain,
but also provide a monolithic solution for converting
single-ended signals into differential signals for
easier, higher performance processing. The THS4500
family of amplifiers contains the flagship products in
Texas
Instruments'
expanding
line
of
high-performance
fully
differential
amplifiers.
Information
on
fully
differential
amplifier
fundamentals, as well as implementation-specific
information, is presented in the applications section of
this data sheet to provide a better understanding of
the operation of the THS4500 family of devices, and
to simplify the design process for designs using these
amplifiers.
The THS4504 and THS4505 are intended to be
low-cost alternatives to the THS4500/1/2/3 devices.
From a topology standpoint, the THS4504/5 have the
same architecture as the THS4500/1. Specifically, the
input common-mode range is designed to include the
negative power supply rail.
Applications Section
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential
Amplifiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
Setting the Output Common-Mode Voltage With
the VOCM Input
Saving Power with Power-Down Functionality
Linearity:
Definitions,
Terminology,
Circuit
Techniques, and Design Tradeoffs
An Abbreviated Analysis of Noise in Fully
Differential Amplifiers
Printed-Circuit Board Layout Techniques for
Optimal Performance
Power Dissipation and Thermal Considerations
Power-Supply Decoupling Techniques and
Recommendations
Evaluation
Fixtures,
Spice
Models,
and
Applications Support
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
Fully differential amplifiers are typically packaged in
eight-pin packages as shown in the diagram. The
device pins include two inputs (VIN+,VIN–), two outputs
(VOUT–,VOUT+), two power supplies (VS+, VS–), an
output common-mode control pin (VOCM), and an
optional power-down pin (PD).
VIN-
1
8
VIN+
VOCM
2
7
PD
VS+
3
6
VS-
VOUT+
4
5
VOUT-
Figure 75. Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in
the figure. The functionality of a fully differential
amplifier can be imagined as two inverting amplifiers
that share a common noninverting terminal (though
the voltage is not necessarily fixed). For more
information on the basic theory of operation for fully
differential amplifiers, refer to the Texas Instruments
application note titled Fully Differential Amplifiers
(SLOA054).
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the
four devices. The input common-mode range of the
THS4504/5 is the same as the THS4500/1. The
THS4502
and
THS4503
have
an
input
common-mode range that is centered around midrail,
and the THS4500 and THS4501 have an input
common-mode range that is shifted to include the
negative power supply rail. Selection of one or the
other is determined by the nature of the application.
Specifically, the THS4500 and THS4501 are
designed for use in single-supply applications where
the input signal is ground-referenced, as depicted in
Figure 76. The THS4502 and THS4503 are designed
for use in single-supply or split-supply applications
where the input signal is centered between the
power-supply voltages, as depicted in Figure 77.
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RF1
RG1
RS
+VS
RT
VS
VIN+(1 - b) - VIN-(1 - b) + 2VOCMb
VOUT+ =
VOCM
VOUT- =
+ +
-
2b
-VIN+(1 - b) + VIN-(1 - b) + 2VOCMb
(1)
2b
(2)
VN = VIN-(1 - b) + VOUT+b
(3)
Where:
RG2
RF2
b=
Figure 76. Application Circuit for the THS4500 and
THS4501, Featuring Single-Supply Operation with
a Ground-Referenced Input Signal
RG
R F + RG
(4)
VP = VIN+(1 - b) + VOUT-b
(5)
NOTE:
RG1
RS
+VS
RT
VS
The equations denote the
device inputs as VN and
VP, and the circuit inputs
as VIN+ and VIN–.
RF1
VOCM
+ - +
-VS
RG2
RF
RG
VIN+
VP
RF2
VOCM
Figure 77. Application Circuit for the THS4500 and
THS4501, Featuring Split-Supply Operation with
an Input Signal Referenced at the Midrail
VN
VIN-
Equation 1 to Equation 5 allow calculation of the
required input common-mode range for a given set of
input conditions.
The equations allow calculation of the input commonmode range requirements given information about the
input signal, the output voltage swing, the gain, and
the output common-mode voltage. Calculating the
maximum and minimum voltage required for VN and
VP (the amplifier input nodes) determines whether or
not the input common-mode range is violated or not.
Four equations are required. Two calculate the output
voltages and two calculate the node voltages at VN
and VP (note that only one of these needs calculation,
as the amplifier forces a virtual short between the two
nodes).
RG
VOUT-
+ - +
VOUT+
RF
Figure 78. Diagram for Input Common-Mode
Range Equations
Table 1 and Table 2 show the input common-mode
range requirements for two different input scenarios,
an input referenced around the negative rail and an
input referenced around midrail. The tables highlight
the differing requirements on input common-mode
range, and illustrate reasoning for choosing either the
THS4500/1 or the THS4502/3. For signals referenced
around the negative power supply, the THS4500/1
should be chosen since its input common-mode
range includes the negative supply rail. For all other
situations, the THS4502/3 offers slightly improved
distortion and noise performance for applications with
input signals centered between the power-supply
rails.
Table 1. Negative-Rail Referenced
20
Gain (V/V)
VIN+ (V)
VIN– (V)
VIN (VPP)
VOCM (V)
VOD (VPP)
VNMIN (V)
1
–2.0 to 2.0
0
4
2.5
4
0.75
1.75
2
–1.0 to 1.0
0
2
2.5
4
0.5
1.167
4
–0.5 to 0.5
0
1
2.5
4
0.3
0.7
8
–0.25 to 0.25
0
0.5
2.5
4
0.167
0.389
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CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values
in this section provide the optimum high-frequency
performance (lowest distortion, flat frequency
response). Since the THS4500 family of amplifiers is
developed with a voltage-feedback architecture, the
choice of resistor values does not have a dominant
effect on bandwidth, unlike a current-feedback
amplifier. However, resistor choices do have
second-order effects. For optimal performance, the
following feedback resistor values are recommended.
In higher gain configurations (gain greater than two),
the feedback resistor values have much less effect on
the high-frequency performance. Example feedback
and gain resistor values are given in the section on
basic design considerations (Table 3).
requirements, determine the value of the gain
resistors, directly impacting the input impedance of
the entire circuit. While there are no strict rules about
resistor selection, these trends can provide qualitative
design guidance.
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers provide designers with a
great deal of flexibility in a wide variety of
applications. This section provides an overview of
some common circuit configurations and gives some
design guidelines. Designing the interface to an ADC,
driving lines differentially, and filtering with fully
differential amplifiers are a few of the circuits that are
covered.
Amplifier loading, noise, and the flatness of the
frequency response are three design parameters that
should be considered when selecting feedback
resistors. Larger resistor values contribute more noise
and can induce peaking in the ac response in low
gain configurations, and smaller resistor values can
load the amplifier more heavily, resulting in a
reduction in distortion performance. In addition,
feedback resistor values, coupled with gain
Table 2. Midrail Referenced
Gain (V/V)
VIN+ (V)
VIN– (V)
VIN (VPP)
VOCM (V)
VOD (VPP)
VNMIN (V)
VNMAX (V)
1
0.5 to 4.5
2.5
4
2.5
4
2
3
2
1.5 to 3.5
2.5
2
2.5
4
2.16
2.83
4
2.0 to 3.0
2.5
1
2.5
4
2.3
2.7
8
2.25 to 2.75
2.5
0.5
2.5
4
2.389
2.61
Table 3. Resistor Values for Balanced Operation in Various Gain Configurations
VOD
VIN
R2 & R4 (Ω)
R1 (Ω)
R3 (Ω)
RT (Ω)
1
392
412
383
54.9
1
499
523
487
53.6
2
392
215
187
60.4
2
1.3 k
665
634
52.3
5
1.3 k
274
249
56.2
5
3.32 k
681
649
52.3
10
1.3 k
147
118
64.9
10
6.81 k
698
681
52.3
Gain
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•
BASIC DESIGN CONSIDERATIONS
The circuits in Figure 76 through Figure 78 are used
to highlight basic design considerations for fully
differential amplifier circuit designs.
Equations for calculating fully differential amplifier
resistor values in order to obtain balanced operation
in the presence of a 50-Ω source impedance are
given in Equation 6 through Equation 9.
1
RT =
R2
R2 = R4
K=
K
R1
12(1 + K)
1
R3 = R1 - (RS || RT)
RS
R3
•
•
(6)
b1 =
VOD
VS
VOD
VIN
R1
R1 + R2
=2
=2
b2 =
R3 + RT || RS
R3 + RT || RS + R4
1 - b2
RT
b1 + b2
RT + RS
(7)
(8)
1 - b2
b1 + b2
(9)
For more detailed information about balance in fully
differential amplifiers, see the Fully Differential
Amplifiers, referenced at the end of this data sheet.
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
The THS4500 family of amplifiers are designed
specifically
to
interface
to
today's
highest-performance analog-to-digital converters.
This section highlights the key concerns when
interfacing to an ADC and provides example
ADC/fully differential amplifier interface circuits.
Key design concerns when interfacing to an
analog-to-digital converter:
• Terminate the input source properly. In
high-frequency receiver chains, the source
feeding the fully differential amplifier requires a
specific load impedance (for example, 50 Ω).
• Design a symmetric printed-circuit board (PCB)
layout. Even-order distortion products are heavily
influenced by layout, and careful attention to a
symmetric layout will minimize these distortion
products.
• Minimize inductance in power-supply decoupling
traces and components. Poor power-supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power-supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the
current loop.
22
•
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•
•
•
•
•
Use separate analog and digital power supplies
and grounds. Noise (bounce) in the power
supplies (created by digital switching currents) can
couple directly into the signal path, and
power-supply noise can create higher distortion
products as well.
Use care when filtering. While an RC low-pass
filter may be desirable on the output of the
amplifier to filter broadband noise, the excess
loading can negatively impact the amplifier
linearity. Filtering in the feedback path does not
have this effect.
AC-coupling allows easier circuit design. If
dc-coupling is required, be aware of the excess
power dissipation that can occur due to
level-shifting the output through the output
common-mode voltage control.
Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop
fully differential amplifiers drive a specific output
voltage regardless of the load impedance present.
Terminating the output of a fully differential
amplifier with a heavy load adversely effects the
amplifier's linearity.
Comprehend the VOCM input drive requirements.
Determine if the ADC voltage reference can
provide the required amount of current to move
VOCM to the desired value. A buffer may be
needed.
Decouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can
act as an antenna. A large decoupling capacitor
on this node eliminates this problem.
Be cognizant of the input common-mode range. If
the input signal is referenced around the negative
power supply rail (e.g., around ground on a single
5 V supply), then the THS4500/1 accommodates
the input signal. If the input signal is referenced
around midrail, choose the THS4502/3 for the
best operation.
Packaging makes a difference at higher
frequencies. If possible, choose the smaller,
thermally-enhanced MSOP package for the best
performance. As a rule, lower junction
temperatures provide better performance. If
possible, use a thermally-enhanced package,
even if the power dissipation is relatively small
compared to the maximum power dissipation
rating to achieve the best results.
Comprehend the effect of the load impedance
seen by the fully differential amplifier when
performing
system-level
intercept
point
calculations. Lighter loads (such as those
presented by an ADC) allow smaller intercept
points to support the same level of intermodulation
distortion performance.
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EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at
the output of the data converter. Two representative
circuits shown below highlight single-supply operation
and split supply operation. Specific feedback resistor,
gain resistor, and feedback capacitor values are not
specified, as their values depend on the frequency of
interest. Information on calculating these values can
be found in the applications material above.
Figure 81 illustrates the THS4500 family of devices
used as high speed line drivers. For line driver
applications, close attention must be paid to thermal
design constraints due to the typically high level of
power dissipation.
CG
RS
RG
RF
15 V
RT
VS
RISO
+
VOCM
RL
+
RISO
RF
RG
CS
VDD
THS4504
-
0.1 mF
CF
-
CS
VOD = 26 VPP
CG
RS
RG
RF
5V
VS
Figure 81. Fully Differential Line Driver with High
Output Swing
RT
5V
10 mF
1 mF
RISO
+
VOCM
+
-
IN ADS5410
12-Bit/80 MSPS
IN
CM
THS4503
5V
RG
0.1 mF
RISO
10 mF 0.1 mF
0.1 mF
RF
CF
Figure 79. Using the THS4503 with the ADS5410
CF
RS
RG
RF
5V
VS
RT
5V
10 mF
+
0.1 mF
RISO
1 mF
Similar to their single-ended counterparts, fully
differential amplifiers have the ability to couple
filtering functionality with voltage gain. Numerous filter
topologies can be based on fully differential
amplifiers. Several of these are outlined in A
Differential Circuit Collection (SLOA064), referenced
at the end of this data sheet. The circuit in Figure 82
depicts a simple two-pole low-pass filter applicable to
many different types of systems. The first pole is set
by the resistors and capacitors in the feedback paths,
and the second pole is set by the isolation resistors
and the capacitor across the outputs of the isolation
resistors.
IN ADS5421
14-Bit/40 MSPS
IN
CM
-
VOCM
-
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
+
THS4501
CF1
RISO
RG
RG1
RS
RF1
RF
VS
RISO
RT
+
-
CF
-
0.1 mF
C
VO
+
RG2
RISO
RF2
Figure 80. Using the THS4501 with the ADS5421
CF2
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers.
Their high power supply voltage rating (16.5 V
absolute maximum) allows operation on a single 12-V
or a single 15-V supply. The high supply voltage,
coupled with the ability to provide differential outputs
enables the ability to drive 26 VPP into reasonably
heavy loads (250 Ω or greater). The circuit in
Figure 82. A Two-Pole, Low-Pass Filter Design
Using a Fully Differential Amplifier with Poles
Located at P1 = (2×RFCF)–1 in Hz and
P2 = (4×RISOC)–1 in Hz
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Often times, filters like these are used to eliminate
broadband noise and out-of-band distortion products
in signal acquisition systems. It should be noted that
the increased load placed on the output of the
amplifier by the second low-pass filter has a
detrimental effect on the distortion performance. The
preferred method of filtering is using the feedback
network, as the typically smaller capacitances
required at these points in the circuit do not load the
amplifier nearly as heavily in the pass-band.
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
The output common-mode voltage pin provides a
critical function to the fully differential amplifier; it
accepts an input voltage and reproduces that input
voltage as the output common-mode voltage. In other
words, the VOCM input provides the ability to level-shift
the outputs to any voltage inside the output voltage
swing of the amplifier.
A description of the input circuitry of the VOCM pin is
shown below to facilitate an easier understanding of
the VOCM interface requirements. The VOCM pin has
two 50-kΩ resistors between the power supply rails to
set the default output common-mode voltage to
midrail. A voltage applied to the VOCM pin alters the
output common-mode voltage as long as the source
has the ability to provide enough current to overdrive
the two 50-kΩ resistors. This phenomenon is
depicted in the VOCM equivalent circuit diagram.
Current drive is especially important when using the
reference voltage of an analog-to-digital converter to
drive VOCM. Output current drive capabilities differ
from part to part, so a voltage buffer may be
necessary in some applications.
for the sole purpose of filtering any high frequency
noise that could couple into the signal path through
the VOCM circuitry. A 0.1-µF or 1-µF capacitance is a
reasonable value for eliminating a great deal of
broadband interference, but additional, tuned
decoupling capacitors should be considered if a
specific source of electromagnetic or radio frequency
interference is present elsewhere in the system.
Information on the ac performance (bandwidth, slew
rate) of the VOCM circuitry is included in the
specification table and graph section.
Since the VOCM pin provides the ability to set an
output common-mode voltage, the ability for
increased power dissipation exists. While this does
not pose a performance problem for the amplifier, it
can cause additional power dissipation of which the
system designer should be aware. The circuit shown
in Figure 84 demonstrates an example of this
phenomenon. For a device operating on a single 5-V
supply with an input signal referenced around ground
and an output common-mode voltage of 2.5 V, a dc
potential exists between the outputs and the inputs of
the device. The amplifier sources current into the
feedback network in order to provide the circuit with
the proper operating point. While there are no serious
effects on the circuit performance, the extra power
dissipation may need to be included in the system
power budget.
I1 =
DC Current Path to Ground
RG1
RS
RF1
5V
RT
VS
+
VS+
VOCM = 2.5 V
R = 50 kW
IIN =
VOCM
IIN
VOCM
RF1 + RG1 + RS || RT
-
+
2VOCM - VS+ - VSRG2
R
R = 50 kW
I2 =
VS-
Figure 83. Equivalent Input Circuit for VOCM
2.5-V DC
RF2
RS
2.5-V DC
DC Current Path to Ground
VOCM
RF2 + RG2
Figure 84. Depiction of DC Power Dissipation
Caused by Output Level-Shifting in a DC-Coupled
Circuit
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal.
As shown in the equivalent circuit diagram, the VOCM
input has a high impedance associated with it,
dictated by the two 50-kΩ resistors. While the high
impedance allows for relaxed drive requirements, it
also allows the pin and any associated printed-circuit
board traces to act as an antenna. For this reason, a
decoupling capacitor is recommended on this node
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The THS4500 family of fully differential amplifiers
contains devices that come with and without the
power-down option. Even-numbered devices have
power-down capability, which is described in detail
here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (i.e. an internal pullup resistor is present),
putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
enable threshold voltage, the device is on. Below the
disable threshold voltage, the device is off. Behavior
in between these threshold voltages is not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The
THS4500
family
of
devices
features
unprecedented distortion performance for monolithic
fully differential amplifiers. This section focuses on
the fundamentals of distortion, circuit techniques for
reducing nonlinearity, and methods for equating
distortion of fully differential amplifiers to desired
linearity specifications in RF receiver chains.
Amplifiers are generally thought of as linear devices.
In other words, the output of an amplifier is a linearly
scaled version of the input signal applied to it. In
reality, however, amplifier transfer functions are
nonlinear. Minimizing amplifier nonlinearity is a
primary design goal in many applications.
Intercept points are specifications that have long
been used as key design criteria in the RF
communications world as a metric for the
intermodulation distortion performance of a device in
the signal chain (for example, amplifiers, mixers,
etc.). Use of the intercept point, rather than strictly the
intermodulation distortion, allows for simpler
system-level calculations. Intercept points, like noise
figures, can be easily cascaded back and forth
through a signal chain to determine the overall
receiver chain intermodulation distortion performance.
The relationship between intermodulation distortion
and intercept point is depicted in Figure 85 and
Figure 86.
PO
PO
∆fc = fc − f1
Power
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
∆fc = f2 − fc
IMD3 = PS − PO
PS
fc − 3∆f
PS
f1 fc
f2
fc + 3∆f
f − Frequency − MHz
Figure 85. 2-Tone and 3rd-Order Intermodulation
Products
Due to the intercept point's ease of use in system
level calculations for receiver chains, it has become
the
specification
of
choice
for
guiding
distortion-related design decisions. Traditionally,
these systems use primarily class-A, single-ended RF
amplifiers as gain blocks. These RF amplifiers are
typically designed to operate in a 50-Ω environment,
just like the rest of the receiver chain. Since intercept
points are given in dBm, this implies an associated
impedance (50 Ω).
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As can be seen in the equation, when a higher
impedance is used, the same level of intermodulation
distortion performance results in a lower intercept
point. Therefore, it is important to comprehend the
impedance seen by the output of the fully differential
amplifier when selecting a minimum intercept point.
The graphic below shows the relationship between
the strict definition of an intercept point with a
normalized, or equivalent, intercept point for the
THS4504.
1X
OIP3
PO
IMD3
IIP3
3X
PIN
(dBm)
PS
Figure 86. Graphical Representation of 2-Tone
and 3rd-Order Intercept Point
OIP − Third-Order Output Intersept Point − dBm
3
POUT
(dBm)
60
Gain = 1
Rf = 499 Ω
VO = 2 VPP
VS = ± 5 V
200 kHz Tone Spacing
Normalized to 50 Ω
50
40
30
20
Normalized to 200 Ω
RL = 800 Ω
10
0
0
20
40
60
80
100
f − Frequency − MHz
However, with a fully differential amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to their outputs regardless of the impedance present,
it is important to comprehend this when evaluating
the intercept point of a fully differential amplifier. The
THS4500 series of devices yields optimum distortion
performance when loaded with 200 Ω to 1 kΩ, very
similar to the input impedance of an analog-to-digital
converter over its input frequency band. As a result,
terminating the input of the ADC to 50 Ω can actually
be detrimental to system performance.
This discontinuity between open-loop, class-A
amplifiers and closed-loop, class-AB amplifiers
becomes apparent when comparing the intercept
points of the two types of devices. Equation 10 gives
the definition of an intercept point, relative to the
intermodulation distortion.
|IMD3|
OIP3 = PO +
2
(10)
PO = 10 log
2
VPdiff
2RL x 0.001
(11)
NOTE: Po is the output power of a single tone, RL is
the differential load resistance, and VP(diff) is the
differential peak voltage for a single tone.
26
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Figure 87. Equivalent 3rd-Order Intercept Point for
the THS4504
Comparing specifications between different device
types becomes easier when a common impedance
level is assumed. For this reason, the intercept points
on the THS4500 family of devices are reported
normalized to a 50-Ω load impedance.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is
analogous to noise analysis in single-ended
amplifiers. The same concepts apply. Below, a
generic circuit diagram consisting of a voltage source,
a termination resistor, two gain setting resistors, two
feedback resistors, and a fully differential amplifier is
shown, including all the relevant noise sources. From
this circuit, the noise factor (F) and noise figure (NF)
are calculated. The figures indicate the appropriate
scaling factor for each of the noise sources in two
different cases. The first case includes the
termination resistor, and the second, simplified case
assumes that the voltage source is properly
terminated by the gain-setting resistors. With these
scaling factors, the amplifier's input noise power (NA)
can be calculated by summing each individual noise
source with its scaling factor. The noise delivered to
the amplifier by the source (NI) and input noise power
are used to calculate the noise factor and noise figure
as shown in Equation 23 through Equation 27.
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Ni
eg
NA
Rg
Si
Scaling Factors for Individual
Noise Sources Assuming No Termination
Resistance is Used (for example, RT is open)
ef
Rf
(eni)
en
Ni
RG
2
Rs
+
Rt
So
fully-diff
amp
−
ini
es
No
2
(ini)
2
(iii)
R
2
G
R
2
G
et
4kTRF
iii
eg
Rg
+
RF
No
RG +
4kTRG
(18)
2
RF
(21)
2
RG
2´
RG +
Figure 88. Noise Sources in a Fully
Differential Amplifier Circuit
2
(20)
ef
Rf
RS
(19)
RG
2´
2
RG
RS
2
(22)
Input Noise With a Termination Resistor:
2
2RTRG
Scaling Factors for Individual
Noise Sources Assuming a Finite
Value Termination Resistor
RT + 2RG
Ni = 4kTRS
RS +
RG
2
(eni)
2
+
RF
2
RG
RG +
R
(iii)2
RG2
2(RS + RT)
(12)
(14)
2RSRG
RS + 2RG
RT +
4kTRF
4kTRG
2´
Ni = 4kTRS
2RG
2RSRG
RS + 2RG
RG
RS + 2RG
Noise Factor and Noise Figure Calculations
NA = S (Noise Source ´ Scale Factor)
NA
F=1+
NI
(25)
NF = 10 log (F)
(27)
(26)
2
(16)
RG
RG +
(24)
(15)
RF
2´
(23)
2
(13)
2
4kTRF
RT + 2RG
Input Noise Assuming No Termination Resistor:
R SR T
2
G
(ini)
2RTRG
2
RSRT
2(RS + RT)
(17)
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PC BOARD LAYOUT TECHNIQUES FOR
OPTIMAL PERFORMANCE
Achieving optimum performance with a high
frequency amplifier-like devices in the THS4500
family requires careful attention to board layout
parasitic and external component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance (< 0.25”) from the
power-supply pins to high-frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power-supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board. The primary goal is to
minimize
the
impedance
seen
in
the
differential-current return paths.
• Careful selection and placement of external
components preserve the high frequency
performance of the THS4500 family. Resistors
should be a very low reactance type.
Surface-mount resistors work best and allow a
tighter overall layout. Metal-film and carbon
composition, axially-leaded resistors can also
provide good high frequency performance. Again,
keep their leads and PC board trace length as
short as possible. Never use wirewound type
resistors in a high-frequency application. Since the
output pin and inverting input pins are the most
sensitive to parasitic capacitance, always position
the feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed close
to the gain-setting resistors. Even with a low
parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately
0.2 pF in shunt with the resistor. For resistor
values > 2.0 kΩ, this parasitic capacitance can
28
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•
•
•
•
add a pole and/or a zero below 400 MHz that can
effect circuit operation. Keep resistor values as
low as possible, consistent with load driving
considerations.
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils) should
be used, preferably with ground and power planes
opened up around them. Estimate the total
capacitive load and determine if isolation resistors
on the outputs are necessary. Low parasitic
capacitive loads (< 4 pF) may not need an RS
since the THS4500 family is nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrinsic
to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance
environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined based on board
material and trace dimensions, a matching series
resistor into the trace from the output of the
THS4500 family is used as well as a terminating
shunt resistor at the input of the destination
device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device: this
total effective impedance should be set to match
the trace impedance. If the 6-dB attenuation of a
doubly
terminated
transmission
line
is
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high speed part like the THS4500
family is not recommended. The additional lead
length and pin-to-pin capacitance introduced by
the socket can create an extremely troublesome
parasitic network which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS4500 family parts directly onto the board.
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PowerPAD DESIGN CONSIDERATIONS
PowerPAD PCB LAYOUT CONSIDERATIONS
The
THS4500
family
is
available
in
a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 89(a) and Figure 89(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 89(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad.
1. Prepare the PCB with a top side etch pattern as
shown in Figure 90. There should be etch for the
leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 13 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS4500 family IC. These additional vias
may be larger than the 13-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered so that wicking is not a
problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer.
Therefore, the holes under the THS4500 family
PowerPAD
package
should
make
their
connection to the internal ground plane with a
complete
connection
around
the
entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 89. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 90. View of Thermally Enhanced Package
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POWER DISSIPATION AND THERMAL
CONSIDERATIONS
PD − Maximum Power Dissipation − W
3.5
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute
maximum junction temperature of +150°C is
exceeded. For best performance, design for a
maximum junction temperature of +125°C. Between
+125°C and +150°C, damage does not occur, but the
performance of the amplifier begins to degrade.
For systems where heat dissipation is more critical,
the THS4500 family of devices is offered in an
MSOP-8 with PowerPAD. The thermal coefficient for
the MSOP PowerPAD package is substantially
improved over the traditional SOIC. Maximum power
dissipation levels are depicted in the graph for the
two packages. The data for the DGN package
assumes a board layout that follows the PowerPAD
layout guidelines referenced above and detailed in
the PowerPAD application notes in the Additional
Reference Materialsection at the end of the data
sheet.
2.5
2
8-Pin D Package
1.5
1
0.5
0
−40
The thermal characteristics of the device are dictated
by the package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
Tmax - TA
PDmax =
qJA
(28)
Where:
PDmax is the maximum power dissipation in the
amplifier (W).
TMAX is the absolute maximum junction
temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
ambient air (°C/w).
8-Pin DGN Package
3
−20
0
20
40
60
TA − Ambient Temperature − °C
80
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
Figure 91. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however,
the load capacitance should be isolated by two
isolation resistors in series with the output. The
requisite isolation resistor size depends on the value
of the capacitance, but 10 Ω to 25 Ω is a good place
to begin the optimization process. Larger isolation
resistors decrease the amount of peaking in the
frequency response induced by the capacitive load,
but this comes at the expense of larger voltage drop
across the resistors, increasing the output swing
requirements of the system.
RF
VS
RG
RS
+
VS
RT
-
+
-VS
RG
RISO
CL
RISO
RISO = 10 - 25 W
RF
Figure 92. Use of Isolation Resistors with a
Capacitive Load
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POWER-SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
C4
C0805
R4
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of
performance.
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along
power-supply return current paths.
4. Recommended values for power supply
decoupling include 10-µF and 0.1-µF capacitors
for each supply. A 1000-pF capacitor can be
used across the supplies as well for extremely
high-frequency return currents, but often is not
required.
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, an evaluation board
has been developed for the THS4500 family of fully
differential amplifiers. The evaluation board can be
obtained by ordering through the Texas Instruments
web site, www.ti.com, or through your local Texas
Instruments sales representative. The schematic for
the evaluation board is shown in Figure 93 with
default component values. Unpopulated footprints are
shown to provide insight into design flexibility.
R0805
VS
J1
C1
R1
C0805
C2
R1206
C0805
R2
1
PD
U1
THS450X
R6
4
7
R0805
3
_
R0805
R0805
R3
8
+
2
5
6
VOCM
PwrPad
C5
C0805
C7
C0805
R0805
R7
J2
J2
J3
J3
C6
C0805
S
VR5 R0805
C3
C0805
J2
R8
R0805
J3
R9
R0805
R0805
R9
J4
4
3
5
R11
R1206
6
1
T1
Figure 93. Simplified Schematic of the Evaluation
Board. Power-Supply Decoupling, VOCM, and
Power-Down Circuitry not Shown
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the THS4500 family of devices is available
through the Texas Instruments web site (www.ti.com).
The Product Information Center (PIC) is available for
design assistance and detailed product information.
These models do a good job of predicting
small-signal ac and transient performance under a
wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between
the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
Submit Documentation Feedback
31
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
ADDITIONAL REFERENCE MATERIAL
•
•
•
•
•
•
•
PowerPAD Made Easy, application brief, (SLMA004).
PowerPAD Thermally-Enhanced Package, technical brief, (SLMA002).
Karki, James. Fully Differential Amplifiers.application report, (SLOA054D).
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and
Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, (SLOA064).
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, (SLOA072).
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog
Applications Journal, July 2001.
Revision History
Changes from Revision C (March 2004) to Revision D .................................................................................................. Page
•
•
•
•
•
•
•
•
•
•
•
32
Updated document format ..................................................................................................................................................... 1
Added footnote 1 to Ordering Information table .................................................................................................................... 3
Changed x-axis of Figure 12................................................................................................................................................ 11
Changed x-axis of Figure 49................................................................................................................................................ 15
Changed two to four in first sentece of the Input Common-Mode Voltage Range and the THS4500 Family section ........ 19
Deleted figure from Basic Design Considerations section................................................................................................... 22
Changed cross-references in first sentence of Basic Design Considerations section to Figure 76 through Figure 78 ...... 22
Changed below to in Figure 82 in first paragraph of Filtering with Fully Differential Amplifiers section.............................. 23
Removed reference to nonexistant table in second paragraph of Setting the Output Common-Mode Voltage with the
VOCM Input section................................................................................................................................................................ 24
Added titles to Figure 85, Figure 86, and Figure 87 ............................................................................................................ 25
Changed THS4502 to THS4504 in last sentence of eighth paragraph in the Linearity: Definitions, Terminology,
Circuit Techniques, and Design Tradeoffs section .............................................................................................................. 25
Submit Documentation Feedback
Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4504D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4504
THS4504DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ASZ
THS4504DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BDB
THS4504DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BDB
THS4504DGNRG4
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BDB
THS4504DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4504
THS4505D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4505
THS4505DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ATA
THS4505DGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ATA
THS4505DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BDC
THS4505DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BDC
THS4505DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4505
THS4505DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4505
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS4504DGNR
Package Package Pins
Type Drawing
SPQ
HVSSOP
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4504DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THS4505DGNR
HVSSOP
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4505DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4504DGNR
HVSSOP
DGN
8
2500
364.0
364.0
27.0
THS4504DR
SOIC
D
8
2500
350.0
350.0
43.0
THS4505DGNR
HVSSOP
DGN
8
2500
364.0
364.0
27.0
THS4505DR
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.846
1.646
TYPICAL
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.846)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(2.15)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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