Texas Instruments | High-Output-Drive Operational Amplifier With Shutdown (Rev. D) | Datasheet | Texas Instruments High-Output-Drive Operational Amplifier With Shutdown (Rev. D) Datasheet

Texas Instruments High-Output-Drive Operational Amplifier With Shutdown (Rev. D) Datasheet
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
HIGH-OUTPUT-DRIVE OPERATIONAL AMPLIFIERS
WITH SHUTDOWN
FEATURES
1
• Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
• Extended Temperature Performance of
–55°C to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree (1)
• High Output Drive . . . >300 mA
• Rail-To-Rail Output
• Unity-Gain Bandwidth . . . 2.7 MHz
• Slew Rate . . . 1.5 V/µs
• Supply Current . . . 700 µA/Per Channel
• Supply Voltage Range . . . 2.5 V to 6 V
• Universal Op Amp EVM
TLV4112
D OR DGN PACKAGE
(TOP VIEW)
23
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
1OUT
1IN−
1IN+
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN−
2IN+
P0029-01
DESCRIPTION
The TLV411x single-supply operational amplifiers
provide output currents in excess of 300 mA at 5 V.
This enables standard pin-out amplifiers to be used
as high current buffers or in coil driver applications.
The TLV4110 and TLV4113 come with a shutdown
feature.
The TLV411x is available in the ultra-small MSOP
PowerPAD™ package, which offers the exceptional
thermal impedance required for amplifiers delivering
high current levels.
All TLV411x devices are offered in SOIC (single and
dual) and MSOP PowerPAD (dual).
FAMILY PACKAGE TABLE
PACKAGE TYPES
DEVICE
NUMBER OF
CHANNELS
MSOP
SOIC
TLV4110
1
8
8
Yes
TLV4111
1
8
8
–
TLV4112
2
8
8
–
TLV4113
2
10
14
Yes
SHUTDOWN
UNIVERSAL EVM BOARD
See the EVM Selection Guide (SLOU060)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Parts, Microsim PSpice are trademarks of MicroSim Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
3.0
1.0
VDD = 3 V
2.8
TA = 1255C
2.7
TA = −405C
2.6
TA = 05C
2.5
TA = 255C
2.4
2.3
TA = 705C
2.2
VDD = 3 V
0.9
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
2.9
2.1
TA = 705C
0.8
TA = 255C
0.7
TA = 05C
0.6
TA = −405C
0.5
TA = 1255C
0.4
0.3
0.2
0.1
2.0
0.0
0
50
100
150
200
250
300
IOH − High-Level Output Current − mA
0
50
100
150
200
250
300
IOL − Low-Level Output Current − mA
G004
G005
TLV4110 AND TLV4111 AVAILABLE OPTIONS
TA
PACKAGED DEVICES
MSOP
SMALL OUTLINE (D) (1)
–55°C to 125°C
(1)
(2)
(3)
TLV4110MDREP
(2)
SMALL OUTLINE
(DGN) (1)
(3)
BTB
TLV4111MDGNREP (3)
BTC
TLV4110MDGNREP
TLV4111MDREP (3)
SYMBOL
(3)
The R designation indicates package is taped and reeled.
In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the
RMS value is less than 350 mW.
Product preview.
TLV4112 AND TLV4113 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
–55°C to 125°C
(1)
(2)
(3)
2
SMALL OUTLINE
(D) (1) (2)
TLV4112MDREP (3)
TLV4113MDREP
(3)
MSOP
SMALL OUTLINE
(DGN) (1)
SYMBOL
SMALL OUTLINE
(DGQ) (1)
TLV4112MDGNREP (3)
BTD
–
–
–
–
TLV4113MDGQREP
BTE
SYMBOL
The R designation indicates package is taped and reeled.
In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the
RMS value is less than 350 mW.
Product preview.
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
TLV411X PACKAGE PINOUTS
TLV4110
D OR DGN PACKAGE
(TOP VIEW)
NC
IN−
IN+
GND
1
8
2
7
3
6
4
5
TLV4111
D OR DGN PACKAGE
(TOP VIEW)
SHDN
VDD
OUT
NC
NC
IN−
IN+
GND
1
8
2
7
3
6
4
5
NC
VDD
OUT
NC
1
2
3
4
5
10
9
8
7
6
1OUT
1IN−
1IN+
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN−
2IN+
TLV4113
D OR DGN PACKAGE
(TOP VIEW)
TLV4113
DGQ PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
GND
1SHDN
TLV4112
D OR DGN PACKAGE
(TOP VIEW)
VDD+
2OUT
2IN−
2IN+
2SHDN
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
NC − No internal connection
P0029-02
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage (2)
VID
Differential input voltage
VI
Input voltage range
IO
Output current (3)
IO
Continuous RMS output current (each output of amplifier)
IO
7V
±VDD
±VDD
800 mA
Peak output current (each output of
amplifier
TJ ≤ 105°C
350 mA
TJ ≤ 150°C
110 mA
TJ ≤ 105°C
500 mA
TJ ≤ 150°C
155 mA
Continuous total power dissipation
TA
Operating free-air temperature range
TJ
Maximum junction temperature
Tstg
Storage temperature range
See Dissipation Rating Table
–55°C to 125°C
150°C
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to GND.
To prevent permanent damage, the die temperature must not exceed the maximum junction temperature.
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
3
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
Estimated Years of Life
100
10
1
120
125
130
135
140
145
150
155
160
Continous TJ − 5C
Figure 1. TLV4113MDGQ Wirebond Life
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
D (8)
38.3
176
710 mW
142 mW
D (14)
26.9
122.3
1022 mW
204.4 mW
4.7
52.7
2.37 W
474.4 mW
4.7
52.3
2.39 W
478 mW
DGN (8) (1)
DGQ (10)
(1)
4
(1)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
TA = 25°C
POWER RATING
See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (SLMA002), for more information on
the PowerPAD package. The thermal data was measured on a PCB layout, based on information in the section entitled Texas
Instruments Recommended Board for PowerPAD, on page 33 of SLMA002.
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Supply voltage
VICR
Common-mode input voltage range
TA
Operating free-air temperature
V(on)
Shutdown turnon/off voltage level
(1)
V(off)
(1)
MAX
UNIT
2.5
6
0
VDD – 1.5
V
–55
125
°C
VDD = 3 V
2.1
VDD = 5 V
3.8
V
V
VDD = 3 V
0.9
VDD = 5 V
1.65
V
Relative to GND
ELECTRICAL CHARACTERISTICS
at recommended operating conditions, VDD = 3 V and 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA (1)
MIN
TYP
MAX
175
3500
UNIT
DC PERFORMANCE
VIO
Input offset voltage
αVIO
Offset voltage drift
CMRR
VIC = VDD/2, VO = VDD/2 , RL = 100 Ω,
RS = 50 Ω
Common-mode rejection ratio
Full range
4000
25°C
3
VDD = 3 V, RS = 50 Ω, VIC = 0 to 2 V
25°C
63
VDD = 5 V, RS = 50 Ω, VIC = 0 to 4 V
25°C
68
RL = 100 Ω
VDD = 3 V
RL = 10 kΩ
AVD
25°C
Large-signal differential voltage
amplification
RL = 100 Ω
VDD = 5 V
RL = 10 kΩ
25°C
78
Full range
67
25°C
85
Full range
75
25°C
88
Full range
75
25°C
90
Full range
85
µV
µV/°C
dB
84
100
dB
94
110
INPUT CHARACTERISTICS
25°C
IIO
Input offset current
IIB
Input bias current
ri(d)
Differential input resistance
CIC
Common-mode input capacitance
(1)
0.3
Full range
25°C
0.3
Full range
f = 100 Hz
25
1000
50
2000
pA
pA
25°C
1000
GΩ
25°C
5
pF
Full range is –55°C to 125°C.
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
5
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA (1)
MIN
TYP
25°C
2.7
2.97
Full range
2.6
25°C
2.6
Full range
2.5
MAX
UNIT
OUTPUT CHARACTERISTICS
IOH = –10 mA
VDD = 3 V,
VIC = VDD/2
IOH = –100 mA
VOH
High-level output voltage
IOH = –10 mA
VDD = 5 V,
VIC = VDD/2
IOH = –100 mA
IOL = 10 mA
VOL
Low-level output voltage
VDD = 3 V and 5 V,
VIC = VDD/2
IOL = 100 mA
Measured at 0.5 V
from rail
IO
Output current
IOS
Short-circuit output current
VDD = 3 V
VDD = 5 V
Sourcing
Sinking
25°C
4.7
Full range
4.6
25°C
4.6
Full range
4.5
25°C
V
2.73
4.96
V
4.76
0.03
Full range
0.1
0.2
25°C
0.33
Full range
0.4
V
0.55
±220
25°C
mA
±320
800
25°C
mA
800
POWER SUPPLY
IDD
Supply current (per channel)
PSRR
(1)
6
Power supply rejection ratio
(ΔVDD / ΔVIO)
VO = VDD/2
25°C
700
Full range
1000
1500
VDD = 2.7 to 3.3 V, No load
VIC = VDD/2 V
25°C
69
Full range
65
VDD = 4.5 to 5.5 V, No load
VIC = VDD/2 V
25°C
69
Full range
65
82
79
µA
dB
dB
Full range is –55°C to 125°C.
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA (1)
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
GBWP
SR
φM
ts
Gain bandwidth product
RL = 100 Ω, CL = 10 pF
Slew rate at unity gain
Vo(pp) = 2.5 V,
RL = 100 Ω,
CL = 10 pF
VDD = 3 V
VDD = 5 V
25°C
2.7
25°C
0.8
Full range
0.4
25°C
Full range
1
1.57
V/µs
1.57
0.5
Phase margin
RL = 100 Ω, CL = 10 pF
25°C
66
Gain margin
RL = 100 Ω, CL = 10 pF
25°C
16
Settling time
V(STEP)pp = 1 V,
AV = –1,
CL = 10 pF,
RL = 100 Ω
25°C
0.1%
0.01%
MHz
dB
0.7
µs
1.3
NOISE/DISTORTION PERFORMANCE
THD+N
Total harmonic distortion, plus noise
Vn
Equivalent input noise voltage
In
Equivalent input noise current
VO(pp) = VDD/2 V,
RL = 100 Ω,
f = 100 Hz
f = 100 Hz
f = 10 Hz
f = 1 Hz
AV = 1
AV = 10
0.025
25°C
AV = 100
0.035
0.15
25°C
55
nV/√Hz
10
25°C
0.31
25°C
3.4
fA/√Hz
SHUTDOWN CHARACTERISTICS
IDD(SHDN)
Supply current in shutdown mode (per
SHDN = 0 V
channel) (TLV4110, TLV4113)
t(ON)
Amplifier turnon time (2)
t(Off)
Amplifier turnoff time (2)
(1)
(2)
RL = 100 Ω
Full range
25°C
10
15
1
3.3
µA
µs
Full range is –55°C to 125°C.
Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
7
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
vs Common-mode input voltage
CMRR
Common-mode rejection ratio
vs Frequency
VOH
High-level output voltage
vs High-level output current
5, 7
VOL
Low-level output voltage
vs Low-level output current
6, 8
Zo
Output impedance
vs Frequency
9
IDD
Supply current
vs Supply voltage
10
kSVR
Power supply voltage rejection ratio
vs Frequency
11
AVD
Differential voltage amplification and phase
vs Frequency
12
Gain-bandwidth product
vs Supply voltage
13
vs Supply voltage
14
vs Temperature
15
Total harmonic distortion+noise
vs Frequency
16
Equivalent input voltage noise
vs Frequency
17
Phase margin
vs Capacitive load
SR
Slew rate
Vn
2, 3
4
18
Voltage-follower signal pulse response
19, 20
Inverting large-signal pulse response
21
Small-signal inverting pulse response
22
Crosstalk
vs Frequency
23
Shutdown forward and reverse isolation
24
Shutdown supply current
vs Free-air temperature
25
Shutdown supply current/output voltage
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6000
120
CMRR − Common-Mode Rejection Ratio − dB
VDD = 5 V
TA = 25°C
4000
VIO − Input Offset Voltage − µV
4000
VIO − Input Offset Voltage − µV
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
6000
VDD = 3 V
TA = 25°C
2000
0
−2000
2000
0
−2000
−4000
−4000
−6000
−0.4 0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
VICR − Common-Mode Input Voltage − V
Figure 2.
8
26
Submit Documentation Feedback
−6000
−0.2 0.4
1.0
1.6
2.2
2.8
3.4
4.0
4.6
VICR − Common-Mode Input Voltage − V
G001
100
90
80
70
60
50
40
100
5.2
VDD = 3 V
TA = 25°C
110
1k
10k
100k
1M
10M
f − Frequency − Hz
G003
G002
Figure 3.
Figure 4.
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.0
VDD = 3 V
2.8
TA = 1255C
2.7
TA = −405C
2.6
TA = 05C
2.5
TA = 255C
2.4
2.3
TA = 705C
2.2
150
200
250
0.3
0.2
300
TA = 1255C
4.7
TA = −405C
4.6
TA = 05C
TA = 255C
4.5
TA = 705C
4.4
4.3
4.2
4.0
50
100
150
200
250
300
IOL − Low-Level Output Current − mA
G004
0
50
100
150
200
250
300
IOH − High-Level Output Current − mA
G005
Figure 5.
Figure 6.
Figure 7.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
OUTPUT IMPEDANCE
vs
FREQUENCY
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
100
G006
1200
VDD = 3 V and 5 V
TA = 25°C
VDD = 5 V
0.9
4.8
4.1
0
1.0
AV = 1
VI = VDD/2 V
TA = 1255C
1000
0.7
TA = 705C
0.6
TA = 05C
0.5
TA = 255C
TA = −405C
0.4
TA = 1255C
0.3
IDD − Supply Current − µA
0.8
Zo − Output Impedance − Ω
VOL − Low-Level Output Voltage − V
TA = 1255C
0.4
0.0
100
TA = −405C
0.5
2.0
50
TA = 05C
0.6
0.1
IOH − High-Level Output Current − mA
TA = 255C
0.7
VDD = 5 V
4.9
TA = 705C
0.8
2.1
0
5.0
VDD = 3 V
0.9
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
2.9
VOH − High-Level Output Voltage − V
3.0
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
10
A = 100
1
0.2
TA = 705C
800
TA = 255C
TA = 05C
600
TA = −405C
400
200
A = 10
0.1
A=1
0.1
100
0.0
50
100
150
200
250
300
100k
1M
10M
0
1
2
3
4
5
6
VDD − Supply Voltage − V
G008
G009
Figure 8.
Figure 9.
Figure 10.
POWER-SUPPLY REJECTION
RATIO
vs
FREQUENCY
DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE
vs
FREQUENCY
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
120
80
70
60
50
40
30
20
10
10k
100k
1M
10M
3.5
Phase
80
90
60
40
45
Gain
20
0
−20
−40
100
1k
4.0
135
100
Phase Margin − °
VDD = 3 V and 5 V
RF = 1 kΩ
RI = 100 Ω
VI = 0 V
TA = 25°C
90
AVD − Differential Voltage Amplification − dB
PSRR − Power Supply Rejection Ratio − V
10k
G007
100
0
100
0
1k
f − Frequency − Hz
IOL − Low-Level Output Current − mA
0
VDD = 3 V and 5 V
RF = 100 kΩ
CL = 10 pF
TA = 25°C
1k
Gain-Bandwidth Product − MHz
0
3.0
2.5
2.0
1.5
1.0
0.5
10k
100k
1M
−45
10M
f − Frequency − Hz
G011
0.0
2.5
RL = 100 Ω
CL = 10 pF
f = 1 kHz
TA = 25°C
AV = Open Loop
3.0
f − Frequency − Hz
Figure 11.
Copyright © 2006–2008, Texas Instruments Incorporated
3.5
4.0
4.5
5.0
VDD − Supply Voltage − V
G010
Figure 12.
5.5
G012
Figure 13.
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
9
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
SLEW RATE
vs
SUPPLY VOLTAGE
1.75
SR+
1.50
SR+
SR − Slew Rate − V/µs
1.25
SR−
1.00
0.75
SR−
1.25
1.00
0.75
0.50
0.50
0.25
0.25
0.00
2.5
0.00
−40 −25 −10 5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD − Supply Voltage − V
50
65
80
1
A = 100
0.1
A = 10
A=1
0.01
10
95 110 125
100
1k
100k
10k
f − Frequency − Hz
G015
G014
Figure 15.
Figure 16.
EQUIVALENT INPUT VOLTAGE
NOISE
vs
FREQUENCY
PHASE MARGIN
vs
CAPACITIVE LOAD
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
100
80
VDD = 3 V
5
VI − Input Voltage − V
90
140
VDD = 3 V and 5 V
TA = 25°C
RL = 100
Phase Margin − °
70
VDD = 5 V
100
80
60
RL = 600
RNULL = 20
60
40
RNULL = 20
30
40
RNULL = 0
20
RNULL = 0
20
10
100
1k
10k
0
10
100k
4
VI
3
2
1
0
50
100
f − Frequency − Hz
1k
10k
100k
VO
4
3
VDD = 5 V
RL = 100 Ω
CL = 10 pF
TA = 25°C
AV = 1
2
1
0
−2
0
2
4
6
8
10
12
t − Time − µs
Capacitive Load − pF
G016
Figure 17.
Figure 18.
Figure 19.
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
INVERTING LARGE-SIGNAL
PULSE RESPONSE
SMALL-SIGNAL INVERTING
PULSE RESPONSE
2.45
VO
2.55
2.45
0.0
0.2
0.4
0.6
2
1
VDD = 5 V
RL = 100 Ω
CL = 50 pF
TA = 25°C
VI = 2.5 V
AV = −1
0
−1
−2
VI
2.54
VI
2.50
VDD = 5 V
RL = 100 Ω
CL = 50 pF
TA = 25°C
VI = 2.5 V
AV = −1
2.46
2.42
5
VDD = 5 V
RL = 100 Ω
CL = 10 pF
TA = 25°C
VI = 100 mV
AV = 1
2.50
VI − Input Voltage − V
VI − Input Voltage − V
2.50
0.8
1.0
1.2
1.4
t − Time − µs
G019
Figure 20.
Submit Documentation Feedback
VO − Output Voltage − V
2.55
2.40
−0.2
2.58
3
VI
14
G018
G017
2.60
VI − Input Voltage − V
35
VDD = 5 V
RL = 100 Ω
VO(PP) = VDD/2
AV = 1, 10, and 100
Figure 14.
0
10
VO − Output Voltage − V
20
TA − Free-Air Temperature − °C
G013
160
120
VDD = 3 V and 5 V
RL = 100 Ω
CL = 10 pF
AV = 1
VO − Output Voltage − V
SR − Slew Rate − V/µs
1.50
VO − Output Voltage − V
1.75
Vn − Equivalent Input Voltage Noise − nV//Hz
10
2.00
RL = 100 Ω
CL = 10 pF
AV = 1
THD+N − Total Harmonic Distortion + Noise − %
2.00
10
TOTAL HARMONIC
DISTORTION+NOISE
vs
FREQUENCY
SLEW RATE
vs
TEMPERATURE
4
3
2
1
VO
0
−1
0
1
2
3
4
5
t − Time − µs
6
7
8
2.54
2.50
VO
2.46
2.42
−0.2
0.2
G020
Figure 21.
0.6
1.0
1.4
1.8
t − Time − µs
2.2
2.6
3.0
G021
Figure 22.
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
CROSSTALK
vs
FREQUENCY
0
0
−20
−40
−60
−80
VI = 4 VPP
−40
−80
−100
VI = 2 VPP
100
1k
10k
100k
VI = 0.1 VPP
−120
−140
−160
10
VI = 2.5 VPP
100
f − Frequency − Hz
VDD = 3 V and 5 V
VI = VDD/2
No Load
14
−60
−100
−120
10
16
VDD = 3 V and 5 V
RL = 100 Ω
CL = 50 pF
TA = 25°C
AV = 1
IDD − Shutdown Supply Current − µA
VDD = 3 V and 5 V
RL = 100 Ω
All Channels
Shutdown F/R Isolation − dB
Crosstalk − dB
−20
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SHUTDOWN FORWARD AND
REVERSE ISOLATION
12
10
8
6
4
2
0
1k
10k
100k
1M
−2
−40 −25 −10 5
10M
G023
Figure 24.
IDD(SD) − Shutdown Supply Current − µA
VO − Output Voltage − V
SHDN − Shutdown Pulse − V
Figure 23.
20
35
50
65
80
95 110 125
TA − Free-Air Temperature − °C
f − Frequency − Hz
G022
G024
Figure 25.
SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE
4
3
2
1
SD
0
2
VDD = 3 V
RL = 100 Ω
CL = 10 pF
TA = 25°C
VI = VDD/2
AV = 1
1.5
1
0.5
VO
0
6
IDD(SD)
4
2
0
−2
−20
0
20
40
60
80
100
120
t − Time − µs
G025
Figure 26.
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
11
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
SHUTDOWN FUNCTION
Two members of the TLV411x family (TLV4110/3) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to just nano amps
per channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. In order to save
power in shutdown mode, an external pullup resistor is required; therefore, to enable the amplifier, the shutdown
terminal must be pulled high. When the shutdown terminal is left floating, care should be taken to ensure that
parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into
shutdown.
DRIVING A CAPACITIVE LOAD
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device's
phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than
1 nF, it is recommended that a resistor be placed in series ®NULL) with the output of the amplifier, as shown in
Figure 27. A maximum value of 20 Ω is recommended for most applications.
RF
RG
Input
−
RF
RG
RNULL
Output
+
RL
RNULL
−
Input
Output
+
Snubber
CLOAD
RL
CL
C
(a)
(b)
S0048-03
Figure 27. Driving a Capacitive Load
OFFSET VOLTAGE
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage.
RF
IIB−
RG
+
VI
RS
−
VO
+
IIB+
VOO + VIO
ǒ ǒ ǓǓ
1)
R
F
RG
" IIB) RS
ǒ ǒ ǓǓ
1)
R
F
RG
" IIB* RF
S0094-01
Figure 28. Output Offset Voltage Model
12
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
_
Rnull
+
RL
CL
S0095-01
Figure 29.
GENERAL POWER DESIGN CONSIDERATIONS
When driving heavy loads at high junction temperatures there is an increased probability of electromigration
affecting the long-term reliability of ICs. Therefore, to avoid this issue:
• The output current must be limited (at these high-junction temperatures).
OR
• The junction temperature must be limited.
The maximum continuous output current at a die temperature 150°C will be 1/3 of the current at 105°C.
The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from
the die to the ambient and power dissipated within the IC.
TJ = TA + θJA × PDIS
Where:
PDIS is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across
the output of the IC.
θJA is the thermal impedance between the junction and the ambient temperature of the IC.
TJ is the junction temperature.
TA is the ambient temperature.
Reducing one or more of these factors results in a reduced die temperature. The 8-pin SOIC (small outline
integrated circuit) has a thermal impedance from junction to ambient of 176°C/W. For this reason it is
recommended that the maximum power dissipation of the 8-pin SOIC package be limited to 350 mW, with peak
dissipation of 700 mW as long as the RMS value is less than 350 mW.
The use of the MSOP PowerPAD™ dramatically reduces the thermal impedance from junction to case. And, with
correct mounting, the reduced thermal impedance greatly increases the IC's permissible power dissipation and
output current handling capability. For example, the power dissipation of the PowerPAD™ is increased to above
1 W. Sinusoidal and pulse-width modulated output signals also increase the output current capability. The
equivalent dc current is proportional to the square-root of the duty cycle:
I
DC(EQ)
+I
Cont
Ǹ(duty cycle)
(1)
CURRENT DUTY CYCLE
AT PEAK RATED CURRENT
EQUIVALENT DC CURRENT
AS A PERCENTAGE OF PEAK
100
100
70
84
50
71
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
13
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
Note that, with an operational amplifier, a duty cycle of 70% often results in the op-amp sourcing current 70% of
the time and sinking current 30%; therefore, the equivalent dc current is still 0.84 times the continuous current
rating at a particular junction temperature.
GENERAL PowerPAD DESIGN CONSIDERATIONS
The TLV411x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset lead frame upon which the die is mounted [see Figure 30(a) and Figure 30(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 30(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the previously awkward mechanical methods of heat sinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
M0031-01
Figure 30. Views of Thermally Enhanced DGN Package
14
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
1. Prepare the PCB with a top-side etch pattern, as shown in Figure 31. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in
diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLV411x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the TLV411x PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLV411x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
Thermal Pad Area
Single or Dual
68 mils × 70 mils) with 5 vias
(Via diameter = 13 mils
M0032−01
Figure 31. PowerPAD PCB Etch and Via Pattern
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
15
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D – JUNE 2006 – REVISED MAY 2008............................................................................................................................................................... www.ti.com
For a given θJA, the maximum power dissipation is shown in Figure 32 and is calculated by the following formula:
ǒ
T
P
Where:
PD
TMAX
TA
θJA
D
+
–T
MAX A
q
JA
Ǔ
= Maximum power dissipation of TLV411x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
= θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
(2)
4.0
TJ = 150°C
Maximum Power Dissipation − W
3.5
3.0
DGN Package
Low-K Test PCB
θJA = 52.7°C/W
2.5
2.0
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1.5
1.0
0.5
0.0
−55 −40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
G026
NOTE: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 32. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θJA decreases and the heat-dissipation capability increases. The currents and voltages shown in these
graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents
and voltages should be used to choose the proper package.
16
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008
MACROMODEL INFORMATION
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™ The Boyle macromodel (see Note 3) and subcircuit in Figure 33 are generated using the
TLV411x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations
of the following key parameters can be generated to a tolerance of 20% (in most cases).
• Common-mode rejection ratio
• Maximum positive output voltage swing
• Phase margin
• Maximum negative output voltage swing
• DC output resistance
• Slew rate
• AC output resistance
• Quiescent power dissipation
• Short-circuit output current limit
• Input bias current
• Open-loop voltage amplification
• Unity-gain frequency
NOTE 3: G.R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State
Circuits, SC-9, 353 (1974).
3
VDD
99
+
rd1
rp
rd2
rss
egnd
css
c1
11
IN+
+
D
vb
−
53
ga
gcm
ro1
ioff
OUT
iss
ve
+ 54
90
dln
+
hlim
−
+
dc
−
dlp
91
10
4
−
8
S
dp
GND
vlim
6
+
−
G
S
c2
r2
9
vc
D
G
IN−
7
+
12
1
2
ro2
fb
−
vlp
−
5
92
−
vln
+
de
* TLV4112_5V operational amplifier ”macromodel” subcircuit
* updated using Model Editor release 9.1 on 01/18/00 at 15:50
Model Editor is an OrCAD product.
*
* connections: non−inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
|| | | |
.subckt TLV4112_5V
12345
*
c1
11
12
2.2439E−12
c2
6
7
10.000E−12
css
10
99
454.55E−15
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
+ 33.395E6 −1E3 1E3 33E6 −33E6
ga
6
0
11
12 168.39E−6
gcm
0
6
10
99 168.39E−12
iss
hlim
ioff
j1
J2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
*$
10
90
0
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
4
dc
13.800E−6
0
vlim 1K
6
dc
75E−9
2
10 jx1
1
10 jx2
9
100.00E3
11
5.9386E3
12
5.9386E3
5
10
99
10
4
3.3333E3
99
14.493E6
0
dc 0
53
dc .86795
4
dc .86795
8
dc 0
0
dc 300
92
dc 300
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
NJF(Is=150.00E−12 Beta=2.0547E−3 +Vto=−1)
NJF(Is=150.00E−12 Beta=2.0547E−3 + Vto=−1)
S0096-01
Figure 33. Boyle Macromodel and Subcircuit
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
17
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV4113MDGQREP
ACTIVE
HVSSOP
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
BTE
V62/06646-04ZE
ACTIVE
HVSSOP
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
BTE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
OTHER QUALIFIED VERSIONS OF TLV4113-EP :
• Catalog: TLV4113
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV4113MDGQREP
Package Package Pins
Type Drawing
SPQ
HVSSOP
2500
DGQ
10
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV4113MDGQREP
HVSSOP
DGQ
10
2500
358.0
335.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising