Texas Instruments | Advanced LinCOMS Rail-to-Rail Output Wide-Input-Voltage Micropower Dual Op Amps (Rev. A) | Datasheet | Texas Instruments Advanced LinCOMS Rail-to-Rail Output Wide-Input-Voltage Micropower Dual Op Amps (Rev. A) Datasheet

Texas Instruments Advanced LinCOMS Rail-to-Rail Output Wide-Input-Voltage Micropower Dual Op Amps (Rev. A) Datasheet
  SGLS175A − AUGUST 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D
D
D
D
D
description
1OUT
1IN −
1IN +
VDD − /GND
1
8
2
7
3
6
4
5
VDD +
2OUT
2IN −
2IN +
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
VDD = 5 V
VOH − High-Level Output Voltage − V
D
D
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Output Swing Includes Both Supply Rails
Extended Common-Mode Input Voltage
Range . . . 0 V to 4.5 V (Min) With 5-V Single
Supply
No Phase Inversion
Low Noise . . . 18 nV/√Hz Typ at f = 1 kHz
Low Input Offset Voltage
950 µV Max at TA = 25°C (TLV2422A)
Low Input Bias Current . . . 1 pA Typ
Micropower Operation . . . 50 µA Per
Channel
600-Ω Output Drive
D PACKAGE
(TOP VIEW)
4
TA = −40°C
TA = 25°C
3
The TLV2422 and TLV2422A are dual low-voltage
operational amplifiers from Texas Instruments.
2
TA = 85°C
The common-mode input voltage range for this
device has been extended over the typical CMOS
amplifiers making them suitable for a wide range
1
of applications. In addition, the devices do not
TA = 125°C
phase invert when the common-mode input is
driven to the supply rails. This satisfies most
0
4
8 12 16 20 24 28 32 36 40
0
design requirements without paying a premium
for rail-to-rail input performance. They also exhibit
IOH − High-Level Output Current − mA
rail-to-rail output performance for increased
Figure 1
dynamic range in single- or split-supply
applications. This family is fully characterized at
3-V and 5-V supplies and is optimized for low-voltage operation. The TLV2422 only requires 50 µA of supply
current per channel, making it ideal for battery-powered applications. The TLV2422 also has increased output
drive over previous rail-to-rail operational amplifiers and can drive 600-Ω loads for telecom applications.
Other members in the TLV2422 family are the high-power, TLV2442, and low-power, TLV2432, versions.
The TLV2422, exhibiting high input impedance and low noise, is excellent for small-signal conditioning for
high-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels and
low-voltage operation, these devices work well in hand-held monitoring and remote-sensing applications. In
addition, the rail-to-rail output feature with single- or split-supplies makes this family a great choice when
interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV2422A is available with
a maximum input offset voltage of 950 µV.
If the design requires single operational amplifiers, see the TI TLV2211/21/31. This is a family of rail-to-rail output
operational amplifiers in the SOT-23 package. Their small size and low power consumption, make them ideal
for high density, battery-powered equipment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Copyright  2008, Texas Instruments Incorporated
!"#$ %" & '##% & "! (')* %" %+
#" '%& "!"#$ %" &(! %"& (# %, %#$& "! - & &%#'$%&
&% # . ## %/+ #" '%" (#"&&0 "& "% && #*/ *' %&%0 "! ** ( # $%#&+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
 SGLS175A − AUGUST 2003 − REVISED APRIL 2008
ORDERING INFORMATION{
TA
−40°C to 125°C
VIOmax
AT 25°C
950 µV
PACKAGE}
SOIC (D)
Tape and reel
ORDERABLE
PART NUMBER
TLV2422AQDRQ1
TOP-SIDE
MARKING
2422AQ
2.5 mV
SOIC (D)
Tape and reel
TLV2422QDRQ1
2422Q1
† For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VB2
IN+
IN−
VB1
Q2
R1
Q1
Q23
Q22
Q4
Q3
R9
R2
Q5
Q7
Q6
VB3
R3
Q25
Q24
equivalent schematic (each amplifier)
Q9
Q8
R4
Q27
Q26
Q12
Q11
VB4
Q10
C1
Q13
D1
Q30
Q29
Q14
VB3
Q17
Q16
Q15
Q33
Q32
Q31
Q19
R6
R5
Q18
R10
Q35
Q34
Q37
C3
C2
VB2
Q36
R8
Q21
Q20
R7
VB4
OUT
VDD−/GND
VDD+
Transistors
Diodes
Resistors
Capacitors
69
5
26
6
COMPONENT
COUNT
1 1 1
11 1 1 SGLS175 − AUGUST 2003
3
 2
SGLS175 − AUGUST 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage, VI (any input, see Note 1): C and I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current out of VDD − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD − .
2. Differential voltages are at IN+ with respect to IN −. Excessive current flows if input is brought below VDD − − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
TA = 125
125°C
C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
145 mW
recommended operating conditions
MIN
MAX
Supply voltage, VDD ±
2.7
10
V
Input voltage range, VI
VDD −
VDD −
VDD + − 0.8
VDD + − 0.8
V
Common-mode input voltage, VIC
Operating free-air temperature, TA
−40
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
UNIT
V
°C
 2
SGLS175 − AUGUST 2003
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
TA†
TEST CONDITIONS
TLV2422-Q1
MIN
25°C
VIO
Input offset voltage
αVIO
Temperature
coefficient of input
offset voltage
Input offset voltage
long-term drift (see
Note 4)
IIO
Input offset current
IIB
Input bias current
VOH
VOL
Common-mode input
voltage range
High-level output
voltage
Low-level output
voltage
300
2000
VIC = 0,
0.003
0.003
µV/mo
25°C
0.5
1
VIC = 0,
IOL = 250 µA
A
0.5
60
Full range
0
to
2.2
−0.25
to
2.75
1
300
0
to
2.5
2.97
25°C
2.75
−0.25
to
2.75
V
2.75
0.05
25°C
0.2
Full range
0.05
0.2
0.5
2
V
2.5
25°C
6
pA
2.97
2.5
25°C
pA
60
0
to
2.2
25°C
Full range
60
150
300
0
to
2.5
Full range
60
150
25°C
IOL = 100 µA
µV
V
25°C
RS = 50 Ω
IOH = − 500 µA
A
950
1800
UNIT
µV/°C
V/°C
Full range
IOH = − 100 µA
300
MAX
2
Full range
|VIO| ≤ 5 mV,
TYP
2
Full range
VDD ± = ± 1.5 V,
RS = 50 Ω
MIN
2500
25°C
VICR
MAX
Full range
VIC = 0,
VO = 0,
TLV2422A-Q1
TYP
10
V
0.5
6
10
AVD
Large-signal
differential voltage
amplification
25°C
700
700
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
25°C
130
130
Ω
CMRR
Common-mode
rejection ratio
VIC = VICR min, VO = 1.5 V,
RS = 50 Ω
kSVR
Supply-voltage
rejection ratio
(∆VDD/∆VIO)
VDD = 2.7 V to 8 V,
VIC = VDD /2,
No load
IDD
Supply current
VO = 1.5 V,
RL = 10 kه
VIC = 1.5 V,
VO = 1 V to 2 V
RL = 1 Mه
AV = 10
No load
25°C
70
Full range
70
25°C
80
Full range
80
2
83
70
V/mV
83
dB
70
95
80
95
dB
25°C
Full range
80
100
150
175
100
150
175
µA
† Full range is − 40°C to 125°C for Q level part.
‡ Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
 2
SGLS175 − AUGUST 2003
operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
VO = 1.1 V to 1.9 V,
CL = 100 pF‡
SR
Slew rate at unity gain
Vn
Equivalent input noise voltage
VN(PP)
Peak-to-peak equivalent input noise voltage
In
Equivalent input noise current
THD + N
ts
φm
6
25°C
0.01
0.02
Full
range
0.008
100
23
f = 0.1 Hz to 1 Hz
25°C
2.7
f = 0.1 Hz to 10 Hz
25°C
4
25°C
0.6
AV = 1,
CL = 100 pF‡
Settling time
AV = − 1,
Step = 0.5 V to 2.5 V,
RL = 10 kه,
CL = 100 pF‡
RL = 10 kه,
POST OFFICE BOX 655303
UNIT
MAX
V/µs
25°C
VO(PP) = 1 V,
RL = 10 kه,
Gain margin
† Full range is − 40°C to 125°C for Q level part.
‡ Referenced to 1.5 V
TYP
25°C
Maximum output-swing bandwidth
Phase margin at unity gain
MIN
f = 1 kHz
AV = 1
Total harmonic distortion plus noise
TLV2422-Q1,
TLV2422A-Q1
f = 10 Hz
VO = 0.5 V to 2.5 V,
f = 1 kHz,
RL = 10 kه
f = 10 kHz,
CL = 100 pF‡
Gain-bandwidth product
BOM
RL = 10 kه,
TA†
nV/√Hz
µV
V
fA√Hz
0.25%
25°C
AV = 10
RL = 10 kه,
1.8%
25°C
46
kHz
25°C
8.3
kHz
To 0.1%
8.6
µss
25°C
To 0.01%
CL = 100 pF‡
• DALLAS, TEXAS 75265
16
25°C
62°
25°C
11
dB
 2
SGLS175 − AUGUST 2003
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TA†
TEST CONDITIONS
TLV2422-Q1
MIN
25°C
VIO
Input offset voltage
αVIO
Temperature
coefficient of input
offset voltage
Input offset voltage
long-term drift (see
Note 4)
IIO
Input offset current
IIB
Input bias current
VOH
VOL
Common-mode input
voltage range
High-level output
voltage
Low-level output
voltage
300
2000
VIC = 2.5 V,
0.003
0.003
µV/mo
25°C
0.5
1
VIC = 2.5 V,
IOL = 500 µA
A
0.5
60
Full range
0
to
4.2
−0.25
to
4.75
1
300
0
to
4.5
4.97
25°C
4.75
−0.25
to
4.75
V
4.75
0.04
25°C
0.15
Full range
0.04
0.15
0.5
3
V
4.5
25°C
8
pA
4.97
4.5
25°C
pA
60
0
to
4.2
25°C
Full range
60
150
300
0
to
4.5
Full range
60
150
25°C
IOL = 100 µA
µV
V
25°C
RS = 50 Ω
IOH = − 1 mA
950
1800
UNIT
µV/°C
V/°C
Full range
IOH = − 100 µA
300
MAX
2
Full range
|VIO| ≤ 5 mV,
TYP
2
Full range
VDD ± = ± 2.5 V,
RS = 50 Ω
MIN
2500
25°C
VICR
MAX
Full range
VIC = 0,
VO = 0,
TLV2422A-Q1
TYP
12
V
0.5
8
12
AVD
Large-signal
differential voltage
amplification
25°C
1000
1000
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
25°C
130
130
Ω
CMRR
Common-mode
rejection ratio
VIC = VICR min, VO = 2.5 V,
RS = 50 Ω
kSVR
Supply-voltage
rejection ratio
(∆VDD/∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD /2,
No load
IDD
Supply current
VO = 2.5 V,
RL = 10 kه
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 1 Mه
AV = 10
No load
25°C
70
Full range
70
25°C
80
Full range
80
3
90
70
V/mV
90
dB
70
95
80
95
dB
25°C
Full range
80
100
150
175
100
150
175
µA
† Full range is − 40°C to 125°C for Q level part.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
 2
SGLS175 − AUGUST 2003
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
SR
TEST CONDITIONS
VO = 1.5 V to 3.5 V,
CL = 100 pF‡
Slew rate at unity gain
Vn
Equivalent input noise voltage
VN(PP)
Peak-to-peak equivalent input noise voltage
In
Equivalent input noise current
THD + N
Total harmonic distortion plus noise
BOM
ts
φm
RL = 10 kه,
TYP
25°C
0.01
0.02
Full
range
0.008
f = 1 kHz
25°C
18
f = 0.1 Hz to 1 Hz
25°C
1.9
f = 0.1 Hz to 10 Hz
25°C
2.8
25°C
0.6
Gain-bandwidth product
f = 10 kHz,
CL = 100 pF‡
RL =10 kه,
Maximum output-swing bandwidth
VO(PP) = 2 V,
RL = 10 kه,
AV = 1,
CL = 100 pF‡
Settling time
AV = − 1,
Step = 1.5 V to 3.5 V,
RL = 10 kه,
CL = 100 pF‡
RL = 10 kه,
POST OFFICE BOX 655303
UNIT
MAX
V/µs
100
nV/√Hz
µV
V
fA√Hz
0.24%
25°C
AV = 10
1.7%
25°C
52
kHz
25°C
5.3
kHz
To 0.1%
8.5
µss
25°C
To 0.01%
CL = 100 pF‡
† Full range is − 40°C to 125°C for Q level part.
‡ Referenced to 2.5 V
8
MIN
25°C
AV = 1
Gain margin
TLV2422-Q1,
TLV2422A-Q1
f = 10 Hz
VO = 1.5 V to 3.5 V,
f = 1 kHz,
RL = 10 kه
Phase margin at unity gain
TA†
• DALLAS, TEXAS 75265
15.5
25°C
66°
25°C
11
dB
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
vs Common-mode input voltage
2,3
4,5
αVIO
IIB/IIO
Input offset voltage temperature coefficient
Distribution
6,7
Input bias and input offset currents
vs Free-air temperature
VOH
VOL
High-level output voltage
vs High-level output current
9,11
Low-level output voltage
vs Low-level output current
10,12
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
13
IOS
Short-circuit output current
vs Supply voltage
vs Free-air temperature
14
15
VID
Differential input voltage
vs Output voltage
16,17
Differential gain
vs Load resistance
18
Large-signal differential voltage amplification
8
AVD
Differential voltage amplification
vs Frequency
vs Free-air temperature
19,20
21,22
zo
Output impedance
vs Frequency
23,24
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
25
26
kSVR
Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
27,28
29
IDD
Supply current
vs Supply voltage
30
SR
Slew rate
vs Load capacitance
vs Free-air temperature
31
32
VO
VO
Inverting large-signal pulse response
33,34
Voltage-follower large-signal pulse response
35,36
VO
VO
Inverting small-signal pulse response
37,38
Voltage-follower small-signal pulse response
39,40
Vn
Equivalent input noise voltage
vs Frequency
Noise voltage (referred to input)
Over a 10-second period
Total harmonic distortion plus noise
vs Frequency
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
Phase margin
vs Frequency
vs Load capacitance
19,20
48
Gain margin
vs Load capacitance
49
Unity-gain bandwidth
vs Load capacitance
50
THD + N
φm
B1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41, 42
43
44,45
46
47
9
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2422
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2422
INPUT OFFSET VOLTAGE
20
18
Percentage of Amplifiers − %
16
14
Percentage of Amplifiers − %
452 Amplifiers from 1 Wafer Lot
VDD = 3 V
RL = 10 kΩ
TA = 25°C
12
10
8
6
4
454 Amplifiers from 1 Wafer Lot
VDD = 5 V
RL = 10 kΩ
TA = 25°C
15
10
5
2
0
0
−0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
−0.4 −0.3 −0.2 −0.1 0
VIO − Input Offset Voltage − mV
Figure 2
Figure 3
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
2
2
VDD = 3 V
VDD = 5 V
1.5
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−0.5
1
0.5
0
−0.5
−1
−1.5
0
0.5
1
1.5
2
2.5
3
VIC − Common-Mode Input Voltage − V
−2
−0.5
0
0.5
1
1.5
2
2.5
Figure 5
POST OFFICE BOX 655303
3
3.5
4
4.5
VIC − Common-Mode Input Voltage − V
Figure 4
10
0.1 0.2 0.3 0.4 0.5 0.6
VIO − Input Offset Voltage − mV
• DALLAS, TEXAS 75265
5
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2422 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2422 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
25
32 Amplifiers From 1 Wafer Lot
VDD = ± 1.5 V
TA = 25°C to 125°C
20
15
10
5
0
−4
32 Amplifiers From 1 Wafer Lot
VDD = ± 2.5 V
TA = 25°C to 125°C
20
Percentage of Amplifiers − %
Percentage of Amplifiers − %
25
2
3
−3
−2
−1
0
1
αVIO − Temperature Coefficient − µV / °C
15
10
5
0
4
−4
2
3
−3
−2
−1
0
1
αVIO − Temperature Coefficient − µV / °C
Figure 7
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
INPUT BIAS AND INPUT OFFSET CURRENTS
vs
FREE-AIR TEMPERATURE
3
200
VDD = ± 2.5 V
VDD = 3 V
VOH − High-Level Output Voltage − V
I IB and I IO − Input Bias and Input Offset Currents − pA
Figure 6
4
160
120
IIB
80
40
2.5
TA = 85°C
2
TA = 0°C
1.5
TA = 125°C
1
TA = 25°C
0.5
IIO
0
−55
0
−40
0
25
70
85
125
TA − Free-Air Temperature − °C
0
3
6
9
12
15
IOH − High-Level Output Current − mA
Figure 8
Figure 9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
1.6
5
VDD = 3 V
VDD = 5 V
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
1.4
1.2
TA = 125°C
1
TA = 85°C
0.8
0.6
0.4
TA = 25°C
0.2
TA = −40°C
4
TA = 25°C
3
2
TA = 85°C
1
TA = 125°C
TA = −40°C
0
0
1
2
3
4
0
5
0
IOL − Low-Level Output Current − mA
4
12
8
Figure 10
1
TA = 125°C
0.8
TA = 85°C
0.4
TA = 25°C
TA = −40°C
0
1
2
3
4
5
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
VOH − High-Level Output Voltage − V
VDD = 5 V
0
28
32
36
40
5
RL = 10 kΩ
TA = 25°C
VDD = 5 V
4
3
VDD = 3 V
2
1
0
102
IOL − Low-Level Output Current − mA
103
104
f − Frequency − Hz
Figure 12
12
24
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
1.2
0.2
20
Figure 11
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
16
IOH − High-Level Output Current − mA
Figure 13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
105
106
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
8
30
VO = VDD/2
VIC = VDD/2
TA = 25°C
20
VID = −100 mV
I OS − Short-Circuit Output Current − mA
I OS − Short-Circuit Output Current − mA
25
15
10
5
0
−5
−10
−15
−20
−25
−30
2
3
4
5
6
7
8
9
6
4
2
VDD = 5 V
0
−2
−4
−6
VID = 100 mV
−8
−55
10
−40
Figure 14
85
125
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
1000
1000
VDD = 3 V
RL = 10 kΩ
TA = 25°C
800
VID − Differential Input Voltage − µV
VID − Differential Input Voltage − µV
70
Figure 15
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
800
25
0
TA − Free-Air Temperature − °C
VDD − Supply Voltage − V
600
400
200
0
−200
−400
−600
−800
600
VDD = 5 V
RL = 10 kΩ
TA = 25°C
400
200
0
−200
−400
−600
−800
−1000
0
0.5
1
1.5
2
2.5
3
−1000
0
VO − Output Voltage − V
1
2
3
4
5
VO − Output Voltage − V
Figure 16
Figure 17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
 SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL GAIN
vs
LOAD RESISTANCE
10000
Differential Gain − V/mV
1000
VID = 5 V
VID = 3 V
100
10
1
10
100
1000
RL − Load Resistance − kΩ
Figure 18
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
50
AVD − Large-Signal Differential
Voltage Amplification − dB
30
135
20
PHASE
90
10
45
0
GAIN
−10
0
−20
−30
−45
−40
−50
103
104
105
f − Frequency − Hz
Figure 19
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
−90
106
φ m − Phase Margin − °
40
180
VDD = 3 V
RL = 10 kΩ
CL = 100 pF
2
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
60
180
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AVD − Large-Signal Differential
Voltage Amplification − dB
40
135
PHASE
30
90
20
45
10
0
GAIN
−10
0
−20
φ m − Phase Margin − °
50
−45
−30
−40
103
104
−90
106
105
f − Frequency − Hz
Figure 20
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
10000
VDD = 3 V
AVD − Differential Voltage Amplication − V/mV
AVD − Differential Voltage Amplication − V/mV
10000
RL = 1 MΩ
1000
100
RL = 10 kΩ
10
1
−75
−50
−25
0
25
50
75
100
125
VDD = 5 V
RL = 1 MΩ
1000
100
RL = 10 kΩ
10
1
−75
−50
TA − Free-Air Temperature − °C
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 21
Figure 22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
1000
AV = 100
AV = 10
z o − Output Impedance − Ω
z o − Output Impedance − Ω
AV = 100
100
AV = 1
10
AV = 10
100
AV = 1
10
VDD = 3 V
TA = 25°C
VDD = 5 V
TA = 25°C
1
102
103
1
102
105
104
103
f − Frequency − Hz
Figure 23
Figure 24
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
94
TA = 25°C
CMRR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
100
80
60
VDD = 5 V
40
VDD = 3 V
20
0
102
103
104
105
106
93
92
VDD = 5 V
91
90
VDD = 3 V
89
88
87
86
85
84
−55
−40
f − Frequency − Hz
0
25
70
85
TA − Free-Air Temperature − °C
Figure 25
16
105
104
f − Frequency − Hz
Figure 26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
120
VDD = 3 V
TA = 25°C
KSVR − Supply-Voltage Rejection Ratio − dB
KSVR − Supply-Voltage Rejection Ratio − dB
120
100
KSVR+
80
60
KSVR−
40
20
0
101
103
102
104
105
VDD = 5 V
TA = 25°C
100
KSVR+
80
60
KSVR−
40
20
0
101
106
103
102
f − Frequency − Hz
Figure 27
105
106
Figure 28
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
100
160
VDD = 2.7 V to 8 V
VO = VDD/2
No Load
140
TA = −40°C
98
I DD − Supply Current − µ A
k SVR − Supply-Voltage Rejection Ratio − dB
104
f − Frequency − Hz
96
94
TA = 25°C
120
100
TA = 85°C
80
60
40
92
20
90
−55
−40
0
25
70
85
125
0
0
1
2
TA − Free-Air Temperature − °C
3
4
5
6
7
8
9
10
VDD − Supply Voltage − V
Figure 29
Figure 30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
SLEW RATE
vs
LOAD CAPACITANCE
SLEW RATE
vs
FREE-AIR TEMPERATURE
0.03
0.025
30
VDD = 3 V
AV = −1
TA = 25°C
SR − Slew Rate − V/ms
SR − Slew Rate − V/µs
25
SR−
0.02
SR+
0.015
0.01
20
15
10
0.005
0
102
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
104
103
105
5
−55
106
−40
CL − Load Capacitance − pF
0
Figure 31
1500
3
1000
2
VO − Output Voltage − mV
VO − Output Voltage − mV
4
500
0
−500
−2000
−1000
VDD = 3 V
RL = 10 kΩ
CL = 100 pF
AV = −1
TA = 25°C
−600
0
0
−1
−2
200
600
1000
−4
−1000
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = −1
TA = 25°C
−600
t − Time − µs
−200
0
200
t − Time − µs
Figure 34
Figure 33
18
125
1
−3
−200
85
INVERTING LARGE-SIGNAL
PULSE RESPONSE
2000
−1500
70
Figure 32
INVERTING LARGE-SIGNAL
PULSE RESPONSE
−1000
25
TA − Free-Air Temperature − °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
600
1000
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
2000
1000
1500
VO − Output Voltage − mV
VO − Output Voltage − mV
1500
2000
VDD = 3 V
RL = 10 kΩ
CL = 100 pF
AV = 1
TA = 25°C
500
0
−500
−1000
−1500
1000
500
0
−500
−1000
−1500
−2000
−1000
−600
−200
0
200
600
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
TA = 25°C
−2000
−1000
1000
−600
−200
t − Time − µs
INVERTING SMALL-SIGNAL
PULSE RESPONSE
300
VO − Output Voltage − mV
VO − Output Voltage − mV
1000
400
VDD = 3 V
RL = 10 kΩ
CL = 100 pF
AV = −1
TA = 25°C
100
0
−100
−200
−300
−400
−5
600
INVERTING SMALL-SIGNAL
PULSE RESPONSE
400
200
200
Figure 36
Figure 35
300
0
t − Time − µs
200
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = −1
TA = 25°C
100
0
−100
−200
−300
−4
−3
−2
−1
0
1
2
3
4
5
−400
−5
−4
t − Time − µs
−3
−2
−1
0
1
2
3
4
5
t − Time − µs
Figure 38
Figure 37
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
400
200
300
VO − Output Voltage − mV
VO − Output Voltage − mV
300
400
VDD = 3 V
RL = 10 kΩ
CL = 100 pF
AV = 1
TA = 25°C
100
0
−100
−200
−300
−400
−5
200
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
TA = 25°C
100
0
−100
−200
−300
−4
−3
−2
−1
0
1
2
3
4
−400
−5
5
−4
−3
−2
t − Time − µs
1
2
3
4
5
Figure 40
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
120
120
VDD = 3 V
TA = 25°C
Vn − Equivalent Input Noise Voltage − nV/ Hz
Vn − Equivalent Input Noise Voltage − nV/ Hz
0
t − Time − µs
Figure 39
100
80
60
40
20
0
10
102
103
104
VDD = 5 V
TA = 25°C
100
80
60
40
20
0
10
f − Frequency − Hz
102
103
f − Frequency − Hz
Figure 41
20
−1
Figure 42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
104
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
NOISE VOLTAGE OVER A 10-SECOND PERIOD
1000
Over a 10 Second Period
800
600
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
Noise Voltage − nV
400
200
0
−200
−400
−600
−800
−1000
−1200
0
1
2
3
4
6
5
8
7
10
9
t − Time − s
Figure 43
100
VDD = 3 V
RL = 10 kΩ
TA = 25°C
10
1
AV = 10
AV = 1
0.1
0.01
101
102
103
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
THD +N − Total Harmonic Distortion Plus Noise − %
THD +N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
104
105
100
VDD = 5 V
RL = 10 kΩ
TA = 25°C
10
1
AV = 10
AV = 1
0.1
0.01
0.001
101
102
103
f − Frequency − Hz
f − Frequency − Hz
Figure 44
Figure 45
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
104
105
21
 2
SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
80
80
RL = 10 kΩ
CL = 100 pF
f = 10 kHz
TA = 25°C
Gain-Bandwidth Product − kHz
Gain-Bandwidth Product − kHz
70
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
f = 10 kHz
70
60
50
40
30
60
50
40
30
20
10
20
3
5
4
6
7
0
−50
8
0
−25
VDD − Supply Voltage − V
25
50
Figure 46
GAIN MARGIN
vs
LOAD CAPACITANCE
120
40
RL = 10 kΩ
TA = 25°C
Rnull = 500
100
RL = 10 kΩ
TA = 25°C
Rnull = 500
Rnull = 1000
30
80
Gain Margin − dB
φ m − Phase Margin − °
125
Figure 47
PHASE MARGIN
vs
LOAD CAPACITANCE
60
40
Rnull = 1000
Rnull = 200
20
Rnull = 100
Rnull = 200
10
Rnull = 100
20
Rnull = 0
Rnull = 0
0
10
102
103
104
105
0
10
CL − Load Capacitance − pF
102
103
Figure 49
POST OFFICE BOX 655303
104
CL − Load Capacitance − pF
Figure 48
22
100
75
TA − Free-Air Temperature − °C
• DALLAS, TEXAS 75265
105
 SGLS175 − AUGUST 2003
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
60
B1 − Unity-Gain Bandwidth − kHz
2
50
40
30
20
10
0
10
102
103
104
105
CL − Load Capacitance − pF
Figure 50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TLV2422QDRG4Q1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
2422Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
OTHER QUALIFIED VERSIONS OF TLV2422-Q1 :
• Catalog: TLV2422
• Military: TLV2422M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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