Texas Instruments | Advanced LinCMOS Rail-to-Rail Very Low Power Operational Amplifiers (Rev. B) | Datasheet | Texas Instruments Advanced LinCMOS Rail-to-Rail Very Low Power Operational Amplifiers (Rev. B) Datasheet

Texas Instruments Advanced LinCMOS Rail-to-Rail Very Low Power Operational Amplifiers (Rev. B) Datasheet
  SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D
D
D
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Output Swing includes Both Supply Rails
Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
Fully Specified for Both Single-Supply and
Split-Supply Operation
D Low Power . . . 500 µA Max
D Common-Mode Input Voltage Range
Includes Negative Rail
D Low Input Offset Voltage
D
D
950 µV Max at TA = 25°C (TLC2262A)
Macromodel Included
Performance Upgrade for the TS27M2/M4
and TLC27M2/M4
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
description
60
V n − Equivalent Input Noise Voltage − nV/
VN
nv//HzHz
The TLC2262 and TLC2264 are dual and
quadruple operational amplifiers from Texas
Instruments. Both devices exhibit rail-to-rail
output performance for increased dynamic range
in single- or split-supply applications. The
TLC226x family offers a compromise between the
micropower TLC225x and the ac performance of
the TLC227x. It has low supply current for
battery-powered applications, while still having
adequate ac performance for applications that
demand it. The noise performance has been
dramatically improved over previous generations
of CMOS amplifiers. Figure 1 depicts the low level
of noise voltage for this CMOS amplifier, which
has only 200 µA (typ) of supply current per
amplifier.
50
VDD = 5 V
RS = 20 Ω
TA = 25°C
40
30
20
10
The TLC226x, exhibiting high input impedance
0
10
102
103
104
and low noise, are excellent for small-signal
f
−
Frequency
−
Hz
conditioning for high-impedance sources, such as
piezoelectric transducers. Because of the microFigure 1
power dissipation levels, these devices work well
in hand-held monitoring and remote-sensing
applications. In addition, the rail-to-rail output feature with single or split supplies makes this family a great
choice when interfacing with analog-to-digital converters (ADCs). For precision applications, the TLC226xA
family is available and has a maximum input offset voltage of 950 µV. This family is fully characterized at 5 V
and ± 5 V.
The TLC2262/4 also makes great upgrades to the TLC27M2/L4 or TS27M2/L4 in standard designs. They offer
increased output dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set
allows them to be used in a wider range of applications. For applications that require higher output drive and
wider input voltage range, see the TLV2432 and TLV2442. If your design requires single amplifiers, please see
the TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package.
Their small size and low power consumption, make them ideal for high density, battery-powered equipment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Copyright  2008 Texas Instruments Incorporated
!"#$! % &""$ % ! '&()$! $*
"! &$% !!"# $! %'$!% '" $+ $"#% ! % %$"&#$%
%$ " ,""$-* "! &$! '"!%%. !% !$ %%")- )& $%$. ! )) '"#$"%*
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
ORDERING INFORMATION†
VIOmax
AT 25°C
TA
−40°C to 125°C
PACKAGE}
950 µV
SOIC (D)
Tape and reel
2.5 mV
SOIC (D)
Tape and reel
950 µV
TSSOP (PW)
Tape and reel
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TLC2262AQDRQ1§
TLC2262QDRQ1§
2262AQ1
2262AQ1
2262Q1
2.5 mV
TSSOP (PW)
Tape and reel
TLC2262AQPWRQ1§
TLC2262QPWRQ1§
950 µV
SOIC (D)
Tape and reel
TLC2264AQDRQ1
2264AQ1
2.5 mV
SOIC (D)
Tape and reel
TLC2264QDRQ1
2264Q1
950 µV
TSSOP (PW)
Tape and reel
TLC2264AQPWRQ1
2264AQ1
2.5 mV
TSSOP (PW)
Tape and reel
TLC2264QPWRQ1
2262Q1
2264Q1
† For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ Product Preview.
TLC2262, TLC2262A
D OR PW PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VDD − /GND
2
1
8
2
7
3
6
4
5
TLC2264, TLC2264A
D OR PW PACKAGE
(TOP VIEW)
VDD +
2OUT
2IN −
2IN +
POST OFFICE BOX 655303
1OUT
1IN −
1IN +
VDD +
2IN +
2IN −
2OUT
• DALLAS, TEXAS 75265
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN +
VDD − / GND
3IN +
3IN −
3OUT
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
equivalent schematic (each amplifier)
VDD +
Q3
Q6
Q9
Q12
Q14
Q16
IN +
OUT
C1
IN −
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
Q5
R3
R4
Q7
Q8
Q10
Q11
R1
R2
VDD −/ GND
ACTUAL DEVICE COMPONENT COUNT†
TLC2262
TLC2264
Transistors
COMPONENT
38
76
Resistors
28
56
9
18
Diodes
Capacitors
3
6
† Includes both amplifiers and all ESD, bias, and trim circuitry
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Supply voltage, VDD − (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
Input voltage, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD− − 0.3 V to VDD+
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current out of VDD − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or PW package . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD − .
2. Differential voltages are at IN+ with respect to IN −. Excessive current flows if input is brought below VDD − − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
TA = 125
125°C
C
POWER RATING
D−8
725 mW
5.8 mW/°C
464 mW
377 mW
145 mW
D−14
950 mW
7.6 mW/°C
608 mW
494 mW
190 mW
PW−14
750 mW
6.0 mW/°C
480 mW
389 mW
150 mW
recommended operating conditions
MIN
MAX
Supply voltage, VDD ±
± 2.2
±8
V
Input voltage range, VI
VDD −
VDD −
VDD + − 1.5
VDD + − 1.5
V
Common-mode input voltage, VIC
Operating free-air temperature, TA
−40
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
UNIT
V
°C
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
TEST CONDITIONS
High-level output
voltage
25°C
VDD ± = ± 2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω
AVD
Large-signal differential
voltage amplification
300
2500
µV
0.003
0.003
µV/mo
25°C
0.5
0.5
Full range
800
800
1
1
800
0 to 4
−0.3
to 4.2
800
0 to 4
0 to
3.5
25°C
IOL = 500 µA
950
1500
UNIT
25°C
|VIO| ≤ 5 mV
VIC = 2.5 V,
300
MAX
µV/°C
25°C
IOL = 50 µA
TYP
5
25°C
IOH = − 100 µA
MIN
5
125°C
VIC = 2.5 V,
Low-level output
voltage
MAX
125°C
RS = 50 Ω
Ω,,
TLC2262A-Q1
TYP
3000
Full range
IOH = − 400 µA
VOL
TLC2262-Q1
MIN
Full range
IOH = − 20 µA
VOH
TA†
25°C
4.85
4.82
25°C
4.7
Full range
4.5
4.99
4.94
4.85
4.94
4.82
4.85
4.7
V
4.85
4.5
25°C
0.01
25°C
0.09
Full range
0.01
0.15
0.09
0.15
25°C
pA
V
0 to
3.5
4.99
Full range
−0.3
to 4.2
pA
0.8
0.15
1
0.7
VIC = 2.5 V,
IOL = 4 mA
RL = 50 kه
25°C
80
VIC = 2.5 V,
VO = 1 V to 4 V
Full range
50
RL = 1 Mه
25°C
550
550
Full range
1.2
100
0.15
V
1
1.2
80
170
50
V/mV
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
240
240
Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 2.7 V, VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
kSVR
Supply-voltage rejection
ratio (∆VDD /∆VIO)
VDD = 4.4 V to 16 V,
VIC = VDD /2,
No load
25°C
80
Full range
80
IDD
Supply current
VO = 2.5 V,
Full range
25°C
No load
83
70
83
dB
70
95
80
95
dB
80
400
500
500
400
500
500
µA
A
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
RL = 50 kه,
TLC2262-Q1
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
MAX
TLC2262A-Q1
MIN
TYP
0.35
0.55
Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
CL = 100 pF‡
Equivalent input
noise voltage
f = 10 Hz
25°C
40
40
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kه
AV = 1
THD + N
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF‡
RL = 50 kه,
Maximum outputswing bandwidth
VO(PP) = 2 V,
RL = 50 kه,
AV = 1,
CL = 100 pF‡
Settling time
AV = − 1,
Step = 0.5 V to 2.5 V,
RL = 50 kه,
CL = 100 pF‡
SR
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kه,
UNIT
V/µs
0.25
nV/√Hz
µV
V
fA√Hz
0.017%
0.017%
0.03%
0.03%
25°C
0.82
0.82
MHz
25°C
185
185
kHz
6.4
6.4
14.1
14.1
25°C
56°
56°
25°C
11
11
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF‡
Gain margin
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
6
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage longterm drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
TA†
TEST CONDITIONS
25°C
VO = 0,
IO = 4 mA
RL = 50 kΩ
VO = ± 4 V
0.003
µV/mo
25°C
0.5
1
800
−5
to 4
−5.3
to 4
800
−5
to 4
−5
to 3.5
4.82
25°C
4.7
Full range
4.5
25°C
−4.85
Full range
−4.85
4.85
4.85
4.7
Full range
50
4.94
V
4.85
4.5
−4.99
−4.91
−4.85
−4.91
−4.85
−4.3
−4
−3.8
80
pA
V
4.82
−4
25°C
pA
4.99
4.94
−4.99
25°C
−5.3
to 4.2
−5
to 3.5
4.99
Full range
Full range
800
1
4.85
25°C
0.5
800
25°C
RL = 1 MΩ
µV
0.003
25°C
IO = 500 µA
VIC = 0,
950
1500
UNIT
25°C
Full range
IO = 50 µA
300
MAX
µV/°C
|VIO| ≤ 5 mV
IO = − 100 µA
TYP
5
25°C
RS = 50 Ω
Ω,
MIN
5
25°C
VIC = 0,
AVD
2500
125°C
VIC = 0,
Large-signal differential
voltage amplification
300
125°C
IO = − 400 µA
Maximum negative peak
VOM −
output voltage
MAX
3000
Full range
VIC = 0,
RS = 50 Ω
TLC2262A-Q1
TYP
Full range
IO = − 20 µA
Maximum positive peak
VOM +
output voltage
TLC2262-Q1
MIN
V
−4.3
−3.8
200
80
200
50
V/mV
25°C
1000
1000
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
220
220
Ω
CMRR
Common-mode
rejection ratio
VIC = − 5 V to 2.7 V,
VO = 0,
RS = 50 Ω
25°C
75
Full range
75
kSVR
Supply-voltage rejection
ratio (∆VDD ± /∆VIO)
VDD = 4.4 V to 16 V,
VIC = VDD /2, No load
25°C
80
Full range
80
IDD
Supply current
VO = 0,
Full range
25°C
No load
88
75
88
dB
75
95
80
95
dB
80
425
500
500
425
500
500
A
µA
† Full range is −40°C to 125°C for Q suffix.
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST CONDITIONS
TLC2262-Q1
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
MAX
TLC2262A-Q1
MIN
TYP
0.35
0.55
MAX
UNIT
Slew rate at unity
gain
VO = ± 2 V,
CL = 100 pF
Equivalent input
noise voltage
f = 10 Hz
25°C
43
43
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.8
0.8
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = ± 2.3 V,
RL = 50 kΩ,
kΩ
f = 20 kHz
AV = 1
0.014%
0.014%
THD + N
0.024%
0.024%
Gain-bandwidth
product
f =10 kHz,
CL = 100 pF
RL = 50 kΩ,
25°C
0.73
0.73
MHz
Maximum outputswing bandwidth
VO(PP) = 4.6 V,
RL = 50 kΩ,
AV = 1,
CL = 100 pF
25°C
85
85
kHz
7.1
7.1
Settling time
AV = − 1,
Step = − 2.3 V to 2.3 V,
RL = 50 kΩ,
CL = 100 pF
16.5
16.5
25°C
57°
57°
25°C
11
11
SR
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ,
RL = 50 kΩ,
nV/√Hz
µV
V
fA√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF
Gain margin
† Full range is −40°C to 125°C for Q suffix.
8
V/µs
0.25
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
TEST CONDITIONS
High-level output voltage
25°C
VDD ± = ± 2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω
AVD
Large-signal differential
voltage amplification
300
2500
µV
0.003
0.003
µV/mo
25°C
0.5
0.5
Full range
800
800
1
1
800
0
to 4
−0.3
to 4.2
800
0
to 4
0
to 3.5
25°C
IOL = 500 µA
950
1500
UNIT
25°C
|VIO| ≤ 5 mV
VIC = 2.5 V,
300
MAX
µV/°C
25°C
IOL = 50 µA
TYP
2
25°C
IOH = − 100 µA
MIN
2
125°C
VIC = 2.5 V,
Low-level output voltage
MAX
125°C
RS = 50 Ω
Ω,
TLC2264A-Q1
TYP
3000
Full range
IOH = − 400 µA
VOL
TLC2264-Q1
MIN
Full range
IOH = − 20 µA
VOH
TA†
25°C
4.85
4.82
25°C
4.7
Full range
4.5
4.99
4.94
4.85
4.94
4.82
4.85
4.7
V
4.85
4.5
25°C
0.01
25°C
0.09
Full range
0.01
0.15
0.09
0.15
25°C
pA
V
0
to 3.5
4.99
Full range
−0.3
to 4.2
pA
0.8
0.15
1
0.7
VIC = 2.5 V,
IOL = 4 mA
RL = 50 kه
25°C
80
VIC = 2.5 V,
VO = 1 V to 4 V
Full range
50
RL = 1 Mه
25°C
550
550
Full range
1.2
100
0.15
V
1
1.2
80
170
50
V/mV
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
240
240
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V,
RS = 50 Ω
VO = 2.5 V,
kSVR
Supply-voltage rejection
ratio (∆VDD /∆VIO)
VDD = 4.4 V to 16 V,
IDD
Supply current
(four amplifiers)
VO = 2.5 V,
25°C
70
Full range
70
25°C
80
25°C
No load
Full range
83
70
83
dB
70
95
0.8
80
1
1
95
0.8
dB
1
1
mA
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
RL = 50 kه,
TLC2264-Q1
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
TLC2264A-Q1
MAX
MIN
TYP
0.35
0.55
MAX
UNIT
Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
CL = 100 pF‡
Equivalent input
noise voltage
f = 10 Hz
25°C
40
40
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kه
AV = 1
0.017%
0.017%
THD + N
0.03%
0.03%
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF‡
RL = 50 kه,
25°C
0.71
0.71
MHz
Maximum outputswing bandwidth
VO(PP) = 2 V,
RL = 50 kه,
AV = 1,
CL = 100 pF‡
25°C
185
185
kHz
6.4
6.4
Settling time
AV = − 1,
Step = 0.5 V to 2.5 V,
RL = 50 kه,
CL = 100 pF‡
14.1
14.1
25°C
56°
56°
25°C
11
11
SR
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kه,
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF‡
Gain margin
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
10
V/µs
0.25
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA†
TLC2264-Q1
MIN
25°C
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage
long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
VO = 0,
AVD
1500
µV
V
0.003
0.003
µV/mo
25°C
0.5
0.5
800
Full range
−5
to 4
25°C
4.85
Full range
4.82
25°C
4.7
Full range
4.5
800
−5
to 4
IO = 50 µA
25°C
IO = 500 µA
A
25°C
−4.85
VIC = 0,
Full range
−4.85
pA
V
4.99
4.94
4.85
4.94
4.82
4.85
4.7
V
4.85
4.5
−4.99
−4
−5.3
to 4.2
−5
to 3.5
4.99
VIC = 0,
Full range
−5.3
to 4.2
−5
to 3.5
IO = − 100 µA
A
pA
1
800
25°C
25°C
800
1
IO = − 20 µA
VO = ± 4 V
950
25°C
25°C
IO = 4 mA
300
UNIT
µV/°C
V/°C
125°C
RS = 50 Ω,
|VIO| ≤ 5 mV
MAX
2
125°C
VIC = 0,
Large-signal differential
voltage amplification
2500
TYP
2
Full range
A
IO = − 400 µA
Maximum negative peak
VOM −
output voltage
300
MIN
3000
25°C
Maximum positive peak
VOM +
output voltage
MAX
Full range
VIC = 0,
RS = 50 Ω
TLC2264A-Q1
TYP
−4.99
−4.91
−4.85
−4.91
−4.85
−4.3
−4
−3.8
V
−4.3
−3.8
25°C
80
200
RL = 50 kΩ
Full range
50
80
200
RL = 1 MΩ
25°C
1000
1000
50
V/mV
ri(d)
Differential input resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
220
220
Ω
CMRR
Common-mode
rejection ratio
VIC = − 5 V to 2.7 V,
VO = 0,
RS = 50 Ω
kSVR
Supply-voltage rejection
ratio (∆VDD ± /∆VIO)
VDD± = ±ā 2.2 V to ±ā 8 V,
VIC = VDD /2, No load
IDD
Supply current
(four amplifiers)
VO = 0,
No load
25°C
75
Full range
75
25°C
80
Full range
80
25°C
Full range
88
75
88
dB
75
95
80
95
dB
80
0.85
1
1
0.85
1
1
mA
† Full range is −40°C to 125°C for Q suffix.
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST CONDITIONS
TLC2264-Q1
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
MAX
TLC2264A-Q1
MIN
TYP
0.35
0.55
Slew rate at unity
gain
VO = ± 2 V,
CL = 100 pF
Equivalent input
noise voltage
f = 10 Hz
25°C
43
43
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.8
0.8
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = ± 2.3 V,
RL = 50 kΩ,
kΩ
f = 20 kHz
AV = 1
THD + N
Gain-bandwidth
product
f =10 kHz,
CL = 100 pF
RL = 50 kΩ,
Maximum outputswing bandwidth
VO(PP) = 4.6 V,
RL = 50 kΩ,
AV = 1,
CL = 100 pF
Settling time
AV = − 1,
Step = − 2.3 V to 2.3 V,
RL = 50 kΩ,
CL = 100 pF
SR
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ,
RL = 50 kΩ,
UNIT
V/µs
0.25
0.014%
0.014%
0.024%
0.024%
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
25°C
0.73
0.73
MHz
25°C
70
70
kHz
7.1
7.1
16.5
16.5
25°C
57°
57°
25°C
11
11
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF
Gain margin
† Full range is −40°C to 125°C for Q suffix.
12
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
vs Common-mode input voltage
αVIO
IIB/IIO
Input offset voltage temperature coefficient
Distribution
Input bias and input offset currents
vs Free-air temperature
12
VI
Input voltage range
vs Supply voltage
vs Free-air temperature
13
14
VOH
VOL
High-level output voltage
vs High-level output current
15
Low-level output voltage
vs Low-level output current
16, 17
VOM +
VOM −
Maximum positive output voltage
vs Output current
18
Maximum negative output voltage
vs Output current
19
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
20
IOS
Short-circuit output current
vs Supply voltage
vs Free-air temperature
21
22
VO
Output voltage
vs Differential input voltage
Differential gain
vs Load resistance
AVD
Large-signal differential voltage amplification
vs Frequency
vs Free-air temperature
26, 27
28, 29
zo
Output impedance
vs Frequency
30, 31
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
32
33
kSVR
Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
34, 35
36
IDD
Supply current
vs Supply voltage
vs Free-air temperature
37, 38
39, 40
SR
Slew rate
vs Load capacitance
vs Free-air temperature
41
42
VO
Vn
THD + N
φm
B1
2−5
6, 7
8 − 11
23, 24
25
Inverting large-signal pulse response
43, 44
Voltage-follower large-signal pulse response
45, 46
Inverting small-signal pulse response
47, 48
Voltage-follower small-signal pulse response
49, 50
Equivalent input noise voltage
vs Frequency
Noise voltage (referred to input)
Over a 10-second period
53
Integrated noise voltage
vs Frequency
54
Total harmonic distortion plus noise
vs Frequency
55
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
56
57
Phase margin
vs Frequency
vs Load capacitance
26, 27
58
Gain margin
vs Load capacitance
59
Unity-gain bandwidth
vs Load capacitance
60
Overestimation of phase margin
vs Load capacitance
61
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51, 52
13
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC2262
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC2262
INPUT OFFSET VOLTAGE
25
25
1274 Amplifiers From 2 Wafer Lots
VDD± = ± 5 V
TA = 25°C
20
Percentage of Amplifiers − %
Precentage of Amplifiers − %
1274 Amplifiers From 2 Wafer Lots
VDD± = ± 2.5 V
TA = 25°C
15
10
5
20
15
10
5
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
0
−1.6
1.6
Figure 2
DISTRIBUTION OF TLC2264
INPUT OFFSET VOLTAGE
16
Percentage of Amplifiers − %
Percentage of Amplifiers − %
20
2272 Amplifiers From 2 Wafer Lots
VDD ± = ± 2.5 V
TA = 25°C
12
8
4
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
1.6
2272 Amplifiers From 2 Wafer Lots
VDD ± = ± 5 V
TA = 25°C
16
12
8
4
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
Figure 5
Figure 4
14
1.6
Figure 3
DISTRIBUTION OF TLC2264
INPUT OFFSET VOLTAGE
20
−0.8
0
0.8
VIO − Input Offset Voltage − mV
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.6
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
VDD = 5 V
RS = 50 Ω
TA = 25°C
VVIO
IO − Input Offset Voltage − mV
VVIO
IO − Input Offset Voltage − mV
1
0.5
0
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
−0.5
−1
−1
0
1
2
3
4
VDD± = ± 5 V
RS = 50 Ω
TA = 25°C
0.5
0
−0.5
−1
−6 −5 −4 −3 −2 −1 0
5
VIC − Common-Mode Input Voltage − V
1
2
3
4
5
VIC − Common-Mode Input Voltage − V
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
Figure 6
Figure 7
DISTRIBUTION OF TLC2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT †
DISTRIBUTION OF TLC2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT †
30
25
Percentage of Amplifiers − %
Percentage of Amplifiers − %
25
30
128 Amplifiers From 2 Wafer Lots
VDD± = ± 2.5 V
P Package
TA = 25°C to 125°C
20
15
10
5
0
−5
128 Amplifiers From 2 Wafer Lots
VDD± = ± 5 V
P Package
TA = 25°C to 125°C
20
15
10
5
−4 −3 −2 −1 0
1
2
3
4
αVIO − Temperature Coefficient − µV / °C
5
0
−5
−4 −3 −2 −1 0
1
2
3
4
αVIO − Temperature Coefficient − µV / °C
Figure 8
5
Figure 9
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT†
DISTRIBUTION OF TLC2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT†
35
35
128 Amplifiers From
2 Wafer Lots
VDD ± = ± 2.5 V
N Package
TA = 25°C to 125°C
25
30
Percentage of Amplifiers − %
Percentage of Amplifiers − %
30
128 Amplifiers From
2 Wafer Lots
VDD ± = ± 5 V
N Package
TA = 25°C
to 125°C
20
15
10
25
20
15
10
5
5
0
0
−5
−4
−3
−2
−1
0
1
2
3
4
−5
5
−4
αVIO − Temperature Coefficient of
Input Offset Voltage − µV / °C
−3
0
1
2
3
4
INPUT BIAS AND INPUT OFFSET CURRENTS†
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE RANGE
vs
SUPPLY VOLTAGE
450
10
VDD± = ± 2.5 V
VIC = 0 V
VO = 0
RS = 50 Ω
400
350
RS = 50 Ω
TA = 25°C
8
300
IIB
250
200
150
100
50
IIO
6
4
2
0
| VIO | ≤ 5 mV
−2
−4
−6
−8
−10
0
25
45
65
85
105
TA − Free-Air Temperature − °C
125
2
Figure 12
3
6
7
4
5
| VDD ± | − Supply Voltage − V
Figure 13
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
5
Figure 11
V
VII − Input Voltage Range − V
IIO − Input Bias and Input Offset Currents − pA
IIIB
IB and IIO
−1
αVIO − Temperature Coefficient of
Input Offset Voltage − µV / °C
Figure 10
ÁÁ
ÁÁ
−2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
8
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
INPUT VOLTAGE RANGE†‡
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
5
6
VDD = 5 V
VOH − High-Level Output Voltage − V
VOH
VDD = 5 V
V
VII − Input Voltage Range − V
4
ÁÁ
ÁÁ
3
| VIO | ≤ 5 mV
2
1
ÁÁ
ÁÁ
0
−1
−75 −55 −35 −15 5
25 45 65 85
TA − Free-Air Temperature − °C
105 125
5
4
TA = 125°C
3
TA = 25°C
2
TA = − 40°C
1
0
0
500
1000 1500 2000 2500 3000
| IOH| − High-Level Output Current − µA
Figure 14
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
1.4
1.2
VDD = 5 V
TA = 25°C
1
V
VOL
OL − Low-Level Output Voltage − V
VOL
VOL − Low-Level Output Voltage − V
3500
Figure 15
LOW-LEVEL OUTPUT VOLTAGE‡
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
TA = − 55°C
VIC = 1.25 V
VIC = 0
0.8
0.6
VIC = 2.5 V
ÁÁ
ÁÁ
0.4
0.2
VDD = 5 V
VIC = 2.5 V
1.2
TA = 125°C
1
0.8
TA = 25°C
0.6
TA = − 40°C
TA = − 55°C
0.4
0.2
0
0
0
1
2
3
4
5
IOL − Low-Level Output Current − mA
0
1
2
3
4
5
6
IOL − Low-Level Output Current − mA
Figure 16
Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
MAXIMUM POSITIVE OUTPUT VOLTAGE†
vs
OUTPUT CURRENT
MAXIMUM NEGATIVE OUTPUT VOLTAGE†
vs
OUTPUT CURRENT
VVOM
OM ++ − Maximum Positive Output Voltage − V
VDD± = ± 5 V
5
TA = − 55°C
4
TA = 125°C
3
TA = 25°C
2
ÁÁ
ÁÁ
ÁÁ
TA = − 40°C
1
0
0
500
1000
1500
2000
2500
3000
3500
| IO | − Output Current − µA
VOM −
VOM
− − Maximum Negative Output Voltage − V
−3.8
6
VDD ± = ± 5 V
VIC = 0
−4
TA = 125°C
−4.2
TA = 25°C
−4.4
TA = − 40°C
TA = − 55°C
−4.6
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
−4.8
−5
0
1
2
VDD± = ± 5 V
7
6
VDD = 5 V
4
3
2
1
I OS − Short-Circuit Output Current − mA
IOS
VO(PP)
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
RL = 10 kΩ
TA = 25°C
8
0
103
10
VID = − 100 mV
8
VO = 0
TA = 25°C
6
4
2
0
VID = 100 mV
−2
−4
104
105
106
2
f − Frequency − Hz
3
4
5
6
7
| VDD ± | − Supply Voltage − V
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
Figure 20
Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
6
12
10
ÁÁ
ÁÁ
ÁÁ
5
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE†‡
vs
FREQUENCY
5
4
Figure 19
Figure 18
9
3
IO − Output Current − mA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
8
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT †
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE‡
vs
DIFFERENTIAL INPUT VOLTAGE
5
VO = 0
VDD± = ± 5 V
12
VDD = 5 V
RL = 50 kΩ
VIC = 2.5 V
TA = 25°C
11
10
9
4
VO − Output Voltage − V
IIOS
OS − Short-Circuit Output Current − mA
13
VID = − 100 mV
8
7
1
0
−1
VID = 100 mV
−2
3
2
1
−3
−4
−75
−50
−25
0
25
50
75
100
0
0
250 500 750 1000
−1000 −750 −500 −250
VID − Differential Input Voltage − µV
125
TA − Free-Air Temperature − °C
Figure 22
Figure 23
DIFFERENTIAL GAIN‡
vs
LOAD RESISTANCE
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VO − Output Voltage − V
3
104
VDD± = ± 5 V
VIC = 0 V
RL = 50 kΩ
TA = 25°C
VO(PP) = 2 V
TA = 25°C
Differential Gain − V/ mV
5
1
−1
103
102
VDD± = ± 5 V
VDD = 5 V
10
−3
−5
0
250 500 750 1000
−1000 −750 −500 −250
VID − Differential Input Voltage − µV
1
103
Figure 24
104
105
RL − Load Resistance − kΩ
106
Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
60
180°
VDD = 5 V
CL= 100 pF
TA = 25°C
135°
40
Phase Margin
20
ÁÁ
ÁÁ
ÁÁ
90°
45°
Gain
0
0°
−20
φom
m − Phase Margin
80
−45°
−40
10 3
10 4
10 5
10 6
−90°
10 7
f − Frequency − Hz
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
60
180°
VDD± = ± 5 V
CL = 100 pF
TA = 25°C
135°
40
Phase Margin
20
ÁÁ
ÁÁ
ÁÁ
45°
Gain
0
0°
−20
−40
10 3
−45°
10 4
10 5
10 6
f − Frequency − Hz
Figure 27
20
90°
POST OFFICE BOX 655303
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−90°
10 7
φom
m − Phase Margin
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
80
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
104
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
104
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†
vs
FREE-AIR TEMPERATURE
RL = 1 MΩ
103
RL = 50 kΩ
ÁÁ
ÁÁ
102
ÁÁ
ÁÁ
RL = 10 kΩ
101
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
RL = 1 MΩ
103
RL = 50 kΩ
102
RL = 10 kΩ
101
−75 −50
125
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 29
Figure 28
OUTPUT IMPEDANCE‡
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
1000
VDD± = ± 5 V
TA = 25°C
z o − Output Impedance − 0
zo
Ω
VDD = 5 V
TA = 25°C
z o − Output Impedance − 0
zo
Ω
VDD± = ± 5 V
VIC = 0 V
VO = ± 4 V
100
AV = 100
10
AV = 10
1
100
10
AV = 10
1
AV = 1
0.1
102
AV = 100
AV = 1
103
104
105
f − Frequency − Hz
106
0.1
102
Figure 30
103
104
105
f − Frequency − Hz
106
Figure 31
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
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 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO†‡
vs
FREE-AIR TEMPERATURE
COMMON-MODE REJECTION RATIO†
vs
FREQUENCY
90
CMRR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
100
VDD± = ± 5 V
80
VDD = 5 V
60
40
20
0
101
102
103
104
105
VDD± = ± 5 V
88
86
84
VDD = 5 V
82
80
−75
106
f − Frequency − Hz
−50 −25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 32
Figure 33
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
100
VDD = 5 V
TA = 25°C
KSVR
k SVR − Supply-Voltage Rejection Ratio − dB
KSVR
k SVR − Supply-Voltage Rejection Ratio − dB
100
80
kSVR +
60
kSVR −
40
20
ÁÁ
ÁÁ
ÁÁ
0
−20
101
102
103
104
f − Frequency − Hz
105
106
ÁÁ
ÁÁ
ÁÁ
VDD± = ± 5 V
TA = 25°C
80
kSVR +
60
kSVR −
40
20
0
−20
101
Figure 34
102
103
104
f − Frequency − Hz
105
Figure 35
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
125
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106
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TLC2262
SUPPLY CURRENT †
vs
SUPPLY VOLTAGE
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
600
VO = 0
No Load
VDD ± = ± 2.2 V to ± 8 V
VO = 0
500
IDD
µA
I DD − Supply Current − uA
k
KSVR
SVR − Supply-Voltage Rejection Ratio − dB
110
105
100
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
95
90
−75
TA = − 55°C
400
TA = 25°C
TA = 125°C
TA = 40°C
300
200
100
0
−50
−25
0
25
50
75
100
0
125
1
2
3
4
5
6
7
8
| VDD ± | − Supply Voltage − V
TA − Free-Air Temperature − °C
Figure 36
Figure 37
TLC2264
SUPPLY CURRENT †
vs
SUPPLY VOLTAGE
TLC2262
SUPPLY CURRENT †‡
vs
FREE-AIR TEMPERATURE
1200
600
VO = 0
No Load
VDD± = ± 5 V
VO = 0
500
TA = − 55°C
µA
IDD
I DD − Supply Current − uA
IDD
µA
I DD − Supply Current − uA
1000
800
TA = 25°C
TA = 125°C
TA = 40°C
600
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
400
200
0
0
1
2
3
4
5
6
7
8
| VDD ± | − Supply Voltage − V
400
VDD = 5 V
VO = 2.5 V
300
200
100
0
−75
−50 −25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 39
Figure 38
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
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23
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TLC2264
SUPPLY CURRENT †‡
vs
FREE-AIR TEMPERATURE
SLEW RATE‡
vs
LOAD CAPACITANCE
1
1200
VDD ± = ± 5 V
VO = 0
0.8
SR − Slew Rate − V/
v/us
µs
1000
µA
IDD
I DD − Supply Current − uA
VDD = 5 V
AV = − 1
TA = 25°C
800
VDD = 5 V
VO = 2.5 V
600
ÁÁ
ÁÁ
400
SR −
0.6
SR +
0.4
0.2
200
0
−75
−50
−25
0 25
50
75 100
TA − Free-Air Temperature − °C
0
101
125
102
103
CL − Load Capacitance − pF
Figure 40
Figure 41
SLEW RATE†‡
vs
FREE-AIR TEMPERATURE
INVERTING LARGE-SIGNAL PULSE
RESPONSE‡
5
1.2
VO
VO − Output Voltage − V
SR − Slew Rate − v/uss
V/ µ
1
SR −
0.8
SR +
0.6
0.4
0.2
0
−75
104
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
4 A = −1
V
TA = 25°C
3
2
1
0
−50 −25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
0
2
4
6
8
10
12
14
16
18
t − Time − µs
Figure 43
Figure 42
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
24
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20
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
INVERTING LARGE-SIGNAL PULSE
RESPONSE
5
5
VDD± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
VO
VO − Output Voltage − V
3
2
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
4
VO
VO − Output Voltage − V
4
1
0
−1
−2
3
2
1
−3
−4
−5
0
0
2
4
6
8
10 12
t − Time − µs
14
16
18
0
20
2
4
Figure 44
2
18
20
2.65
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
2.6
VO
VO − Output Voltage − V
VO
VO − Output Voltage − V
3
16
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
VDD± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
4
8
10 12 14
t − Time − µs
Figure 45
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
5
6
1
0
−1
−2
−3
2.55
2.5
2.45
−4
−5
2.4
0
2
4
6
8
10 12
t − Time − µs
14
16
18
20
0
2
Figure 46
4
6
8
10 12
t − Time − µs
14
16
18
20
Figure 47
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
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25
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
INVERTING SMALL-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
2.65
VDD± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
50
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
2.6
VO
VO − Output Voltage − V
VO
VO − Output Voltage − mV
100
0
−50
2.55
2.5
2.45
2.4
−100
0
2
4
6
8
10
12
14
16
18
20
0
2
4
t − Time − µs
Figure 48
V n − Equivalent Input Noise Voltage − nV/
VN
nv//HzHz
VO
VO − Output Voltage − V
−50
−100
2
4
6
18
20
8
10 12
t − Time − µs
14
16
18
20
50
VDD = 5 V
RS = 20 Ω
TA = 25°C
40
30
20
10
0
101
102
103
f − Frequency − Hz
Figure 51
Figure 50
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
26
16
60
0
0
14
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
VDD ± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
50
8
10 12
t − Time − µs
Figure 49
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
100
6
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 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD†
1000
VDD± = ± 5 V
RS = 20 Ω
50 TA = 25°C
750
500
Noise Voltage − nV
V n − Equivalent Input Noise Voltage − nv//Hz
VN
nV/ Hz
60
40
30
20
250
0
−250
−500
10
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
−750
−1000
0
101
102
103
f − Frequency − Hz
104
0
2
4
6
t − Time − s
Figure 52
TOTAL HARMONIC DISTORTION PLUS NOISE†
vs
FREQUENCY
THD + N − Total Harmonic Distortion Plus Noise − %
Integrated Noise Voltage − µ V
100
Calculated Using Ideal Pass-Band Filter
Low Frequency = 1 Hz
TA = 25°C
10
1
101
102
103
f − Frequency − Hz
10
Figure 53
INTEGRATED NOISE VOLTAGE
vs
FREQUENCY
0.1
100
8
104
105
0.1
AV = 100
0.01
AV = 10
AV = 1
VDD = 5 V
RL = 50 kΩ
TA = 25°C
0.001
101
102
103
104
105
f − Frequency − Hz
Figure 54
Figure 55
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
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 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
GAIN-BANDWIDTH PRODUCT †‡
vs
FREE-AIR TEMPERATURE
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
1200
f = 10 kHz
RL = 50 kΩ
CL = 100 pF
900 TA = 25°C
VDD = 5 V
f = 10 kHz
CL = 100 pF
Gain-Bandwidth Product − kHz
Gain-Bandwidth Product − kHz
940
860
820
780
1000
800
600
740
0
1
2
3
5
4
7
6
400
−75
8
−50
−25
Figure 56
50
75
100
125
GAIN MARGIN
vs
LOAD CAPACITANCE
20
TA = 25°C
TA = 25°C
60°
15
Gain Margin − dB
Rnull = 100 Ω
φom
m − Phase Margin
25
Figure 57
PHASE MARGIN
vs
LOAD CAPACITANCE
75°
0
TA − Free-Air Temperature − °C
| VDD ± | − Supply Voltage − V
Rnull = 50 Ω
45°
30°
Rnull = 20 Ω
50 kΩ
15°
50 kΩ
VI
0°
101
Rnull = 100 Ω
10
Rnull = 50 Ω
5
−
+
VDD −
Rnull = 20 Ω
Rnull = 10 Ω
VDD +
Rnull
CL
Rnull = 10 Ω
Rnull = 0
10 2
10 3
CL − Load Capacitance − pF
Rnull = 0
10 4
0
101
Figure 58
10 2
10 3
CL − Load Capacitance − pF
Figure 59
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
28
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10 4
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH†
vs
LOAD CAPACITANCE
OVERESTIMATION OF PHASE MARGIN†
vs
LOAD CAPACITANCE
1000
14°
TA = 25°C
12°
Overestimation of Phase Margin
B1 − Unity-Gain Bandwidth − kHz
TA = 25°C
800
600
ÁÁ
ÁÁ
400
200
101
Rnull = 100 Ω
10°
8°
Rnull = 50 Ω
6°
4°
Rnull = 10 Ω
Rnull = 20 Ω
2°
10 2
10 3
CL − Load Capacitance − pF
10 4
0
101
Figure 60
10 2
10 3
CL − Load Capacitance − pF
10 4
Figure 61
† See application information
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29
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
driving large capacitive loads
The TLC226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 58
and Figure 59 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 62) improves the gain and phase margins
when driving large capacitive loads. Figure 58 and Figure 59 show the effects of adding series resistances of
10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
ǒ
∆Θ m1 + tan –1 2 × π × UGBW × R
null
×C
Ǔ
L
(1)
Where :
∆Θ m1 + improvement inphasemargin
UGBW + unity-gain bandwidth frequency
R null + output seriesresistance
C L + load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 60). To
use equation 1, UGBW must be approximated from Figure 60.
Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 61. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
F +
1
1 ) g m × R null
(2)
Where :
F + factor reducingfrequencyof pole
g m + small-signal output transconductance (typically 4.83 × 10 – 3 mhos)
R null + output series resistance
For the TLC226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with CL: at CL = 10 pF, use 70 MHz, at CL = 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the equation in equation 1 to better approximate the
improvement in phase margin.
30
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 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
driving large capacitive loads (continued)
ȱ
ȧ
Ȳ
ȳ
ȧ
ȴ
∆Θ m2 + tan –1 UGBW – tan –1
ǒF × P2Ǔ
ǒ
Ǔ
UGBW
P2
(3)
Where :
∆Θ m2 + reduction in phase margin
UGBW + unity-gain bandwidth frequency
F + factor from equation 2
P 2 + unadjusted pole (70 MHz@10 pF, 7 MHz@100 pF, etc.)
Using these equations with Figure 60 and Figure 61 enables the designer to choose the appropriate output
series resistance to optimize the design of circuits driving large capacitive loads.
50 kΩ
VDD +
50 kΩ
VI
−
Rnull
+
CL
VDD −/ GND
Figure 62. Series-Resistance Circuit
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31
 SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 63 are generated using
the TLC226x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
3
VCC +
9
RSS
10
J1
DP
VC
J2
IN +
11
RD1
VAD
DC
12
C1
R2
−
53
HLIM
−
+
C2
6
−
−
+
+
GCM
GA
−
RD2
−
RO1
DE
5
+
VE
.SUBCKT TLC226x 1 2 3 4 5
C1
11
12
3.560E−12
C2
6
7
15.00E−12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 21.04E6 −30E6 30E6 30E6 −30E6
GA
6
0
11
12 47.12E−6
GCM
0
6
10
99 4.9E−9
ISS
3
10
DC 8.250E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
OUT
RD1
60
11
21.22E3
RD2
60
12
21.22E3
R01
8
5
120
R02
7
99
120
RP
3
4
26.04E3
RSS
10
99
24.24E6
VAD
60
4
−.6
VB
9
0
DC 0
VC
3
53
DC .65
VE
54
4
DC .65
VLIM
7
8
DC 0
VLP
91
0
DC 1.4
VLN
0
92
DC 9.4
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=281E−6
+ VTO= −.065)
.ENDS
Figure 63. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
32
−
VLIM
8
54
4
91
+
VLP
7
60
+
−
+ DLP
90
RO2
VB
IN −
VCC −
92
FB
−
+
ISS
RP
2
1
DLN
EGND +
POST OFFICE BOX 655303
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VLN
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC2264AQPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2264AQ
TLC2264AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2264AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2264A-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Catalog: TLC2264A
• Military: TLC2264AM
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC2264AQPWRG4Q1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2264AQPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC2264AQPWRG4Q1
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2264AQPWRQ1
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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