Texas Instruments | Precision, High-Speed Transimpedance Amplifier (Rev. G) | Datasheet | Texas Instruments Precision, High-Speed Transimpedance Amplifier (Rev. G) Datasheet

Texas Instruments Precision, High-Speed Transimpedance Amplifier (Rev. G) Datasheet
OPA380
OPA2380
SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
Precision, High-Speed
Transimpedance Amplifier
FEATURES
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DESCRIPTION
> 1MHz TRANSIMPEDANCE BANDWIDTH
EXCELLENT LONG-TERM VOS STABILITY
BIAS CURRENT: 50pA (max)
OFFSET VOLTAGE: 25µV (max)
DYNAMIC RANGE: 4 to 5 Decades
DRIFT: 0.1µV/°C (max)
GAIN BANDWIDTH: 90MHz
QUIESCENT CURRENT: 7.5mA
SUPPLY RANGE: 2.7V to 5.5V
SINGLE AND DUAL VERSIONS
MicroSize PACKAGE: MSOP-8
APPLICATIONS
D
D
D
D
PHOTODIODE MONITORING
PRECISION I/V CONVERSION
OPTICAL AMPLIFIERS
CAT-SCANNER FRONT-END
+5V
7
OPA380
6
VOUT
(0V to 4.4V)
RP
(Optional
Pulldown
Resistor)
Photodiode
1MΩ
The signal bandwidth of a transimpedance amplifier depends
largely on the GBW of the amplifier and the parasitic
capacitance of the photodiode, as well as the feedback
resistor. The 90MHz GBW of the OPA380 enables a transimpedance bandwidth of > 1MHz in most configurations. The
OPA380 is ideally suited for fast control loops for power level
on an optical fiber.
As a result of the high precision and low-noise characteristics
of the OPA380, a dynamic range of 4 to 5 decades can be
achieved. For example, this capability allows the
measurement of signal currents on the order of 1nA, and up
to 100µA in a single I/V conversion stage. In contrast to
logarithmic amplifiers, the OPA380 provides very wide
bandwidth throughout the full dynamic range. By using an
external pull-down resistor to –5V, the output voltage range
can be extended to include 0V.
RF
2
The OPA380 family of transimpedance amplifiers provides
high-speed (90MHz Gain Bandwidth [GBW]) operation, with
extremely high precision, excellent long-term stability, and
very low 1/f noise. It is ideally suited for high-speed
photodiode applications. The OPA380 features an offset
voltage of 25µV, offset drift of 0.1µV/°C, and bias current of
50pA. The OPA380 far exceeds the offset, drift, and noise
performance that conventional JFET op amps provide.
67pF
−5V
100kΩ
3
75pF
4
The OPA380 (single) is available in MSOP-8 and SO-8
packages. The OPA2380 (dual) is available in the
miniature MSOP-8 package. They are specified from
–40°C to +125°C.
OPA380 RELATED DEVICES
PRODUCT
FEATURES
OPA300
150MHz CMOS, 2.7V to 5.5V Supply
OPA350
500µV VOS, 38MHz, 2.5V to 5V Supply
OPA335
10µV VOS, Zero-Drift, 2.5V to 5V Supply
OPA132
16MHz GBW, Precision FET Op Amp, ±15V
OPA656/7
230MHz, Precision FET, ±5V
LOG112
LOG amp, 7.5 decades, ±4.5V to ±18V Supply
LOG114
LOG amp, 7.5 decades, ±2.25V to ±5.5V Supply
IVC102
Precision Switched Integrator
DDC112
Dual Current Input, 20-Bit ADC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2003-2007, Texas Instruments Incorporated
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC DISCHARGE SENSITIVITY
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Signal Input Terminals(2), Voltage . . . . . . . . . . −0.5V to (V+) + 0.5V
Current . . . . . . . . . . . . . . . . . . . . . ±10mA
Short-Circuit Current(3) . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature Range . . . . . . . . . . . . . . . −40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . 2000V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) Input terminals are diode clamped to the power-supply rails. Input
signals that can swing more than 0.5V beyond the supply rails
should be current limited to 10mA or less.
(3) Short-circuit to ground; one amplifier per package.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE-LEAD
OPA380
MSOP-8
AUN
OPA380
SO-8
OPA380A
OPA2380
MSOP-8
BBX
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see
the TI web site at www.ti.com.
PIN ASSIGNMENTS
Top View
OPA2380
OPA380
NC (1)
1
8
NC (1)
−In
2
7
+In
3
V−
4
Out A
1
8
V+
V+
− In A
2
7
Out B
6
Out
+In A
3
6
− In B
5
NC (1)
V−
4
5
+In B
MSOP-8, SO-8
NOTES: (1) NC indicates no internal connection.
2
PACKAGE
MARKING
PRODUCT
MSOP-8
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: OPA380 (SINGLE), VS = 2.7V to 5.5V
Boldface limits apply over the temperature range, TA = −40°C to +125°C.
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA380
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
Drift
vs Power Supply
Over Temperature
Long-Term Stability(1)
Channel Separation, dc
INPUT BIAS CURRENT
Input Bias Current
Over Temperature
Input Offset Current
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Voltage Noise Density, f = 10kHz
Input Voltage Noise Density, f > 1MHz
Input Current Noise Density, f = 10kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
CONDITION
VOS
dVOS/dT
PSRR
MIN
VS = +5V, VCM = 0V
VS = +2.7V to +5.5V, VCM = 0V
VS = +2.7V to +5.5V, VCM = 0V
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time, 0.01%(3)
Overload Recovery Time(4)(5)
OUTPUT
Voltage Output Swing from Positive Rail
Voltage Output Swing from Negative Rail
Voltage Output Swing from Positive Rail
Voltage Output Swing from Negative Rail
Output Current
Short-Circuit Current
Capacitive Load Drive
Open-Loop Output Impedance
POWER SUPPLY
Specified Voltage Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified and Operating Range
Storage Range
Thermal Resistance
MSOP-8, SO-8
MAX
UNITS
4
0.03
2.4
25
0.1
10
10
µV
µV/°C
µV/V
µV/V
See Note (1)
1
IB
VCM = VS/2
IOS
VCM = VS/2
en
en
en
in
VS = +5V, VCM = 0V
VS = +5V, VCM = 0V
VS = +5V, VCM = 0V
VS = +5V, VCM = 0V
VCM
CMRR
(V−) < VCM < (V+) – 1.8V
AOL
0.1V < VO < (V+) − 0.7V, VS = 5V, VCM = VS/2
0.1V < VO < (V+) − 0.6V, VS = 5V, VCM = VS/2,
TA = −40°C to +85°C
0V < VO < (V+) − 0.7V, VS = 5V, VCM = 0V,
RP = 2kΩ to −5V(2)
0V < VO < (V+) − 0.6V, VS = 5V, VCM = 0V,
RP = 2kΩ to −5V(2), TA = −40°C to +85°C
µV/V
3
±50
Typical Characteristics
6
±100
V−
100
pA
pA
µVPP
nV/√Hz
nV/√Hz
fA/√Hz
3
67
5.8
10
INPUT IMPEDANCE
Differential Capacitance
Common-Mode Resistance and Inverting Input
Capacitance
OPEN-LOOP GAIN
Open-Loop Voltage Gain
TYP
110
(V+) − 1.8V
V
dB
1.1
pF
1013 || 3
Ω || pF
110
130
dB
110
130
dB
106
120
dB
106
120
dB
90
80
2
100
MHz
V/µs
µs
ns
CL = 50pF
GBW
SR
tS
G = +1
VS = +5V, 4V Step, G = +1
VIN × G = > VS
RL = 2kΩ
RL = 2kΩ
RP = 2kΩ to −5V(2)
RP = 2kΩ to −5V(2)
IOUT
ISC
CLOAD
RO
VS
IQ
f = 1MHz, IO = 0A
400
600
60
100
400
600
−20
0
See Typical Characteristics
150
See Typical Characteristics
40
2.7
IO = 0A
7.5
−40
−65
mV
mV
mV
mV
mA
Ω
5.5
9.5
10
V
mA
mA
+125
+150
°C
°C
qJA
150
°C/W
(1) 300-hour life test at 150°C demonstrated randomly distributed variation approximately equal to measurement repeatability of 1µV.
(2) Tested with output connected only to RP, a pulldown resistor connected between VOUT and −5V, as shown in Figure 5. See also applications section, Achieving
Output Swing to Ground.
(3) Transimpedance frequency of 1MHz.
(4) Time required to return to linear operation.
(5) From positive rail.
3
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: OPA2380 (DUAL), VS = 2.7V to 5.5V
Boldface limits apply over the temperature range, TA = −40°C to +125°C.
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA2380
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
Drift
vs Power Supply
Over Temperature
Long-Term Stability(1)
Channel Separation, dc
INPUT BIAS CURRENT
Input Bias Current, Inverting Input
Noninverting Input
Over Temperature
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Voltage Noise Density, f = 10kHz
Input Voltage Noise Density, f > 1MHz
Input Current Noise Density, f = 10kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
CONDITION
VOS
dVOS/dT
PSRR
MIN
VS = +5V, VCM = 0V
VS = +2.7V to +5.5V, VCM = 0V
VS = +2.7V to +5.5V, VCM = 0V
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time, 0.01%(3)
Overload Recovery Time(4)(5)
OUTPUT
Voltage Output Swing from Positive Rail
Voltage Output Swing from Negative Rail
Voltage Output Swing from Positive Rail
Voltage Output Swing from Negative Rail
Output Current
Short-Circuit Current
Capacitive Load Drive
Open-Loop Output Impedance
POWER SUPPLY
Specified Voltage Range
Quiescent Current (per amplifier)
Over Temperature
TEMPERATURE RANGE
Specified and Operating Range
Storage Range
Thermal Resistance
MSOP-8
MAX
UNITS
4
0.03
2.4
25
0.1
10
10
µV
µV/°C
µV/V
µV/V
See Note (1)
1
IB
IB
VCM = VS/2
VCM = VS/2
en
en
en
in
VS = +5V, VCM = 0V
VS = +5V, VCM = 0V
VS = +5V, VCM = 0V
VS = +5V, VCM = 0V
VCM
CMRR
(V−) < VCM < (V+) – 1.8V
AOL
0.12V < VO < (V+) − 0.7V, VS = 5V, VCM = VS/2
0.12V < VO < (V+) − 0.6V, VS = 5V, VCM = VS/2,
TA = −40°C to +85°C
0V < VO< (V+) − 0.7V, VS = 5V, VCM = 0V,
RP = 2kΩ to −5V(2)
0V < VO < (V+) − 0.6V, VS = 5V, VCM = 0V,
RP = 2kΩ to −5V(2), TA = −40°C to +85°C
µV/V
3
±50
3
±200
Typical Characteristics
V−
95
pA
pA
µVPP
nV/√Hz
nV/√Hz
fA/√Hz
3
67
5.8
10
INPUT IMPEDANCE
Differential Capacitance
Common-Mode Resistance and Inverting Input
Capacitance
OPEN-LOOP GAIN
Open-Loop Voltage Gain
TYP
105
(V+) − 1.8V
V
dB
1.1
pF
1013 || 3
Ω || pF
110
130
dB
110
130
dB
106
120
dB
106
120
dB
90
80
2
100
MHz
V/µs
µs
ns
CL = 50pF
GBW
SR
tS
G = +1
VS = +5V, 4V Step, G = +1
VIN × G = > VS
RL = 2kΩ
RL = 2kΩ
RP = 2kΩ to −5V(2)
RP = 2kΩ to −5V(2)
IOUT
ISC
CLOAD
RO
VS
IQ
f = 1MHz, IO = 0A
400
600
80
120
400
600
−20
0
See Typical Characteristics
150
See Typical Characteristics
40
2.7
IO = 0A
7.5
−40
−65
mV
mV
mV
mV
mA
Ω
5.5
9.5
10
V
mA
mA
+125
+150
°C
°C
qJA
150
°C/W
(1) 300-hour life test at 150°C demonstrated randomly distributed variation approximately equal to measurement repeatability of 1µV.
(2) Tested with output connected only to RP, a pulldown resistor connected between VOUT and −5V, as shown in Figure 5. See also applications section, Achieving
Output Swing to Ground.
(3) Transimpedance frequency of 1MHz.
(4) Time required to return to linear operation.
(5) From positive rail.
4
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TYPICAL CHARACTERISTICS: VS = +2.7V to +5.5V
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
POWER−SUPPLY REJECTION RATIO AND
COMMON−MODE REJECTION vs FREQUENCY
OPEN−LOOP GAIN AND PHASE vs FREQUENCY
Gain
100
160
45
140
120
0
80
−45
Phase
−90
60
40
−135
20
−180
0
−225
−20
−270
100M
10
100
1k
10k
100k
1M
10M
Phase (_)
Open−Loop Gain (dB)
120
90
PSRR, CMRR (dB)
140
100
80
PSRR
60
40
20
0
CMRR
−20
0.1
1
10
INPUT VOLTAGE NOISE SPECTRAL DENSITY
1k
10k
100k
1M
10M 100M
QUIESCENT CURRENT vs TEMPERATURE
1000
8
Quiescent Current (mA)
7
100
10
VS = +5.5V
6
5
4
VS = +2.7V
3
2
1
1
0
10
100
1k
10k
100k
1M
−40 −25
10M
0
Frequency (Hz)
25
50
75
100
125
Temperature (_ C)
QUIESCENT CURRENT vs SUPPLY VOLTAGE
INPUT BIAS CURRENT vs TEMPERATURE
8
1000
Input Bias Current (pA)
7
Quiescent Current (mA)
Input Voltage Noise (nV/√(Hz)
100
Frequency (Hz)
Frequency (Hz)
6
5
4
3
100
10
2
1
1
2.7
3.0
3.5
4.0
4.5
Supply Voltage (V)
5.0
5.5
−40 −25
0
25
50
75
100
125
Temperature (_C)
5
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TYPICAL CHARACTERISTICS: VS = +2.7V to +5.5V (continued)
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
INPUT BIAS CURRENT
vs INPUT COMMON−MODE VOLTAGE
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(V+)
25
(V+) −1
15
10
Output Swing (V)
Input Bias Current (pA)
20
−IB
5
0
−5
+IB
−10
−15
(V+) −2
+125_C
+25_ C −40_ C
(V−) +2
(V−) +1
−20
−25
(V−)
0
0.5
1.0
1.5
2.0
2.5
3.0
0
3.5
50
100
150
Output Current (mA)
Input Common−Mode Voltage (V)
SHORT−CIRCUIT CURRENT vs TEMPERATURE
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
200
150
100
+ISC
Population
Short−Circuit Current (mA)
VS = 5V
50
0
−50
−ISC
−100
−150
−40 −25
0
25
50
75
100
−25 −20 −15 −10
125
Temperature (_C)
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
−5
0
5
10
Offset Voltage (µV)
15
20
25
GAIN BANDWIDTH vs POWER SUPPLY VOLTAGE
Population
Gain Bandwidth (MHz)
95
90
85
80
75
70
−0.10 −0.08 −0.06 −0.04 −0.02
0
0.02
0.04
Offset Voltage Drift (µV/_C)
6
0.06
0.08
0.1
2.5
3.5
4.5
Power Supply Voltage (V)
5.5
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VS = +2.7V to +5.5V (continued)
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
TRANSIMPEDANCE AMP CHARACTERISTIC
140
Transimpedance Gain (V/A in dB)
Circuit for Transimpedance Amplifier Characteristic curves on this page.
CF
RF
CSTRAY
OPA380
120
110
RF = 1MΩ
90
80
R F = 100kΩ
70
60
RF = 10kΩ
50
RF = 1kΩ
RF = 1MΩ
100
90
80
R F = 100kΩ
70
60
RF = 10kΩ
50
Transimpedance Gain (V/A in dB)
Transimpedance Gain (V/A in dB)
CF = 18pF
10M
100M
TRANSIMPEDANCE AMP CHARACTERISTIC
CDIODE = 50pF
RF = 10MΩ
120
110
CF = 0.5pF
CF = 1.5pF
CF = 4pF
RF = 1kΩ
CF = 12pF
CSTRAY (parasitic) = 0.2pF
20
100
1k
10k
100k
1M
Frequency (Hz)
10M
CDIODE = 20pF
RF = 10MΩ
130
120
110
RF = 1MΩ
100
90
R F = 100kΩ
CF = 1pF
80
RF = 10kΩ
70
60
40
CF = 2.5pF
RF = 1kΩ
50
CF = 7pF
CSTRAY (parasitic) = 0.2pF
30
100
100M
1k
10k
100k
1M
Frequency (Hz)
10M
100M
TRANSIMPEDANCE AMP CHARACTERISTIC
TRANSIMPEDANCE AMP CHARACTERISTIC
140
140
CDIODE = 10pF
RF = 10MΩ
130
Transimpedance Gain (V/A in dB)
Transimpedance Gain (V/A in dB)
CF = 5pF
140
130
120
110
RF = 1MΩ
100
R F = 100kΩ
CF = 0.5pF
80
RF = 10kΩ
70
60
CF = 2pF
RF = 1kΩ
50
40
CF = 2pF
40
30
TRANSIMPEDANCE AMP CHARACTERISTIC
140
90
CF = 0.5pF
100
CSTRAY (parasitic) = 0.2pF
20
100
1k
10k
100k
1M
Frequency (Hz)
CDIODE
40
30
CDIODE = 100pF
RF = 10MΩ
130
CF = 5pF
CSTRAY (parasitic) = 0.2pF
30
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
CDIODE = 1pF
RF = 10MΩ
130
120
RF = 1MΩ
110
100
90
R F = 100kΩ
CF = 0.5pF
80
RF = 10kΩ
70
RF = 1kΩ
CF = 1pF
60
50
CSTRAY (parasitic) = 0.2pF
40
100
1k
10k
CF = 2.5pF
100k
1M
Frequency (Hz)
10M
100M
7
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: VS = +2.7V to +5.5V (continued)
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
50
SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
50
2.5pF
2.5pF
45
45
10kΩ
+5V
35
Overshoot (%)
Overshoot (%)
40
RS
30
V OUT
O PA 38 0
25
RP = 2kΩ
C
20
−5 V
15
10kΩ
35
+2.5V
30
RS
C
20
No RS
5
0
RS = 100Ω
0
10
100
1000
10
100
1000
Load Capacitance (pF)
Load Capacitance (pF)
OVERLOAD RECOVERY
SMALL−SIGNAL STEP RESPONSE
3. 2pF
VOUT
RL = 2kΩ
5 0k Ω
VP = −5V
+5V
V OUT
I IN
1.6 m A
VP = 0V
2 kΩ
50mV/div
2V/div
RF = 2kΩ
−2.5V
10
RS = 100Ω
5
VP
0.8mA/div 0
0
VO U T
OPA380
25
15
No RS
10
40
IIN
Time (100ns/div)
Time (100ns/div)
LARGE−SIGNAL STEP RESPONSE
CHANNEL SEPARATION vs INPUT FREQUENCY
140
RL = 2kΩ
Channel Separation (dB)
1V/div
120
2.5pF
10kΩ
2.5V
2kΩ
100
80
60
40
20
− 2.5V
0
Time (100ns/div)
10
100
1k
10k
100k
Frequency (Hz)
8
1M
10M
100M
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www.ti.com
SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
APPLICATIONS INFORMATION
BASIC OPERATION
The OPA380 is a high-performance transimpedance
amplifier with very low 1/f noise. As a result of its unique
architecture, the OPA380 has excellent long-term input
voltage offset stability—a 300-hour life test at 150°C
demonstrated
randomly
distributed
variation
approximately equal to measurement repeatability of
1µV.
The OPA380 performance results from an internal
auto-zero amplifier combined with a high-speed
amplifier. The OPA380 has been designed with circuitry
to improve overload recovery and settling time over a
traditional composite approach. It has been specifically
designed and characterized to accommodate circuit
options to allow 0V output operation (see Figure 3).
The OPA380 is used in inverting configurations, with the
noninverting input used as a fixed biasing point.
Figure 1 shows the OPA380 in a typical configuration.
Power-supply pins should be bypassed with 1µF ceramic
or tantalum capacitors. Electrolytic capacitors are not
recommended.
OPERATING VOLTAGE
The OPA380 series op amps are fully specified from
2.7V to 5.5V over a temperature range of −40°C to
+125°C. Parameters that vary significantly with operating voltages or temperature are shown in the Typical
Characteristics.
INTERNAL OFFSET CORRECTION
The OPA380 series op amps use an auto-zero topology
with a time-continuous 90MHz op amp in the signal
path. This amplifier is zero-corrected every 100µs using
a proprietary technique. Upon power-up, the amplifier
requires approximately 400µs to achieve specified VOS
accuracy, which includes one full auto-zero cycle of
approximately 100µs and the start-up time for the bias
circuitry. Prior to this time, the amplifier will function
properly but with unspecified offset voltage.
This design has virtually no aliasing and very low noise.
Zero correction occurs at a 10kHz rate, but there is very
little fundamental noise energy present at that
frequency due to internal filtering. For all practical
purposes, any glitches have energy at 20MHz or higher
and are easily filtered, if required. Most applications are
not sensitive to such high-frequency noise, and no
filtering is required.
CF
INPUT VOLTAGE
RF
+5V
1µF
λ
OPA380
VOUT(1)
(0.5V to 4.4V)
The input common-mode voltage range of the OPA380
series extends from V− to (V+) – 1.8V. With input
signals above this common-mode range, the amplifier
will no longer provide a valid output value, but it will not
latch or invert.
INPUT OVERVOLTAGE PROTECTION
VBIAS = 0.5V
NOTE: (1) VOUT = 0.5V in dark conditions.
Figure 1. OPA380 Typical Configuration
Device inputs are protected by ESD diodes that will
conduct if the input voltages exceed the power supplies
by more than approximately 500mV. Momentary
voltages greater than 500mV beyond the power supply
can be tolerated if the current is limited to 10mA. The
OPA380 series feature no phase inversion when the
inputs extend beyond supplies if the input is current
limited.
9
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
OUTPUT RANGE
ACHIEVING OUTPUT SWING TO GROUND
The OPA380 is specified to swing within at least 600mV
of the positive rail and 100mV of the negative rail with
a 2kΩ load with excellent linearity. Swing to the negative
rail while maintaining good linearity can be extended to
0V—see the section, Achieving Output Swing to
Ground. See the Typical Characteristic curve, Output
Voltage Swing vs Output Current.
Some applications require output voltage swing from
0V to a positive full-scale voltage (such as +4.096V)
with excellent accuracy. With most single-supply op
amps, problems arise when the output signal
approaches 0V, near the lower output swing limit of a
single-supply op amp. A good single-supply op amp
may swing close to single-supply ground, but will not
reach 0V.
The OPA380 can swing slightly closer than specified to
the positive rail; however, linearity will decrease and a
high-speed overload recovery clamp limits the amount
of positive output voltage swing available, as shown in
Figure 2.
The output of the OPA380 can be made to swing to
ground, or slightly below, on a single-supply power
source. This extended output swing requires the use of
another resistor and an additional negative power
supply. A pull-down resistor may be connected between
the output and the negative supply to pull the output
down to 0V. See Figure 3.
OFFSET VOLTAGE vs OUTPUT VOLTAGE
20
VS = 5V
15
VOS (µV)
10
RP = 2kΩ connected to −5V
RF
5
λ
0
V+ = +5V
−5
RL = 2kΩconnected to VS /2
−10
OPA380
VOUT
Effect of clamp
−15
RP = 2kΩ
−20
V− = Gnd
0
1
2
3
4
5
VOUT (V)
VP = −5V
Negative Supply
Figure 2. Effect of High-Speed Overload
Recovery Clamp on Output Voltage
OVERLOAD RECOVERY
The OPA380 has been designed to prevent output
saturation. After being overdriven to the positive rail, it
will typically require only 100ns to return to linear
operation. The time required for negative overload
recovery is greater, unless a pull-down resistor
connected to a more negative supply is used to extend
the output swing all the way to the negative rail—see the
following section, Achieving Output Swing to Ground.
10
Figure 3. Amplifier with Optional Pull-Down
Resistor to Achieve VOUT = 0V
The OPA380 has an output stage that allows the output
voltage to be pulled to its negative supply rail using this
technique. However, this technique only works with
some types of output stages. The OPA380 has been
designed to perform well with this method. Accuracy is
excellent down to 0V. Reliable operation is assured over
the specified temperature range.
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
the desired transimpedance gain (RF);
BIASING PHOTODIODES IN SINGLE-SUPPLY
CIRCUITS
The +IN input can be biased with a positive DC voltage
to offset the output voltage and allow the amplifier
output to indicate a true zero photodiode measurement
when the photodiode is not exposed to any light. It will
also prevent the added delay that results from coming
out of the negative rail. This bias voltage appears
across the photodiode, providing a reverse bias for
faster operation. An RC filter placed at this bias point will
reduce noise, as shown in Figure 4. This bias voltage
can also serve as an offset bias point for an ADC with
range that does not include ground.
the Gain Bandwidth Product (GBW) for the
OPA380 (90MHz).
With these three variables set, the feedback capacitor
value (CF) can be set to control the frequency response.
CSTRAY is the stray capacitance of RF, which is 0.2pF for
a typical surface-mount resistor.
To achieve a maximally flat, 2nd-order, Butterworth
frequency response, the feedback pole should be set
to:
1
+
2pR FǒCF ) CSTRAYǓ
Ǹ4pRGBWC
F
(1)
TOT
Bandwidth is calculated by:
CF(1)
< 1pF
Ǹ2pRGBWC
f *3dB +
F
RF
10MΩ
OPA380
0.1µF
(2)
These
equations
will
result
in
maximum
transimpedance bandwidth. For even higher
transimpedance bandwidth, the high-speed CMOS
OPA300 (SBOS271 (180MHz GBW)), or the OPA656
(SBOS196 (230MHz GBW)) may be used.
V+
λ
Hz
TOT
VOUT
100kΩ
For additional information, refer to Application Bulletin
AB−050 (SBOA055), Compensate Transimpedance
Amplifiers Intuitively, available for download at
www.ti.com.
+VBias
CF(1)
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
RF
10MΩ
Figure 4. Filtered Reverse Bias Voltage
CSTRAY(2)
TRANSIMPEDANCE AMPLIFIER
Wide bandwidth, low input bias current, and low input
voltage and current noise make the OPA380 an ideal
wideband photodiode transimpedance amplifier.
Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the
circuit to increase at high frequency.
The key elements to a transimpedance design are
shown in Figure 5:
the total input capacitance (CTOT), consisting of the
photodiode capacitance (CDIODE) plus the parasitic
common-mode and differential-mode input
capacitance (3pF + 1.1pF for the OPA380);
+5V
λ
CTOT(3)
VOUT
OPA380
RP (optional
pulldown resistor)
−5V
NOTE: (1) CF is optional to prevent gain peaking.
(2) CSTRAY is the stray capacitance of RF
(typically, 0.2pF for a surface−mount resistor).
(3) CTOT is the photodiode capacitance plus OPA380
input capacitance.
Figure 5. Transimpedance Amplifier
11
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
TRANSIMPEDANCE BANDWIDTH AND
NOISE
(a)
Limiting the gain set by RF can decrease the noise
occurring at the output of the transimpedance circuit.
However, all required gain should occur in the
transimpedance stage, since adding gain after the
transimpedance amplifier generally produces poorer
noise performance. The noise spectral density
produced by RF increases with the square-root of RF,
whereas the signal increases linearly. Therefore,
signal-to-noise ratio is improved when all the required
gain is placed in the transimpedance stage.
Total noise increases with increased bandwidth. Limit
the circuit bandwidth to only that required. Use a
capacitor, CF, across the feedback resistor, RF, to limit
bandwidth, even if not required for stability if total output
noise is a concern.
Figure 6a shows the transimpedance circuit without any
feedback capacitor. The resulting transimpedance gain
of this circuit is shown in Figure 7. The –3dB point is
approximately 10MHz. Adding a 16pF feedback
capacitor (Figure 6b) will limit the bandwidth and result
in a –3dB point at approximately 1MHz (see Figure 7).
Output noise will be further reduced by adding a filter
(RFILTER and CFILTER) to create a second pole (Figure
6c). This second pole is placed within the feedback loop
to maintain the amplifier’s low output impedance. (If the
pole was placed outside the feedback loop, an
additional buffer would be required and would
inadvertently increase noise and dc error).
R F = 10kΩ
C STRAY = 0.2pF
λ
VBIAS
(b)
RF = 10kΩ
CSTRAY = 0.2pF
CF = 16pF
λ
ǒRDIODE ) RFǓ
2pRDIODER FǒC TOT ) C FǓ
VOUT
OPA380
VBIAS
(c)
RF = 10kΩ
CSTRAY = 0.2pF
Using RDIODE to represent the equivalent diode
resistance, and CTOT for equivalent diode capacitance
plus OPA380 input capacitance, the noise zero, fZ, is
calculated by:
fZ +
VOUT
OPA380
CF = 21pF
R FILTER
= 100Ω
λ
OPA380
VOUT
CFILTER
= 796pF
(3)
VBIAS
Figure 6. Transimpedance Circuit Configurations
with Varying Total and Integrated Noise Gain
12
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SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
500
CDIODE = 10pF
Integrated Output Noise (µVrms)
Transimpedance Gain (dB)
110
See Figure 6a
80
−3dB BW at 1MHz
50
See Figure 6c
20
See Figure 6b
−10
100
CDIODE = 10pF
400
419µV
See Figure 6a
300
200
See Figure 6b
100
86µV
See Figure 6c
30µV
0
1k
10k
100k
1M
10M
1
100M
10
100
Frequency (Hz)
1k
10k 100k
Frequency (Hz)
1M
10M
100M
Figure 7. Transimpedance Gains for Circuits in
Figure 6
Figure 9. Integrated Output Noise for Circuits in
Figure 6
The effect of these circuit configurations on output noise
is shown in Figure 8 and on integrated output noise in
Figure 9. A 2-pole Butterworth filter (maximally flat in
passband) is created by selecting the filter values using
the equation:
Figure 10 shows the effect of diode capacitance on
integrated output noise, using the circuit in Figure 6c.
C FRF + 2C FILTERR FILTER
(4)
For additional information, refer to Noise Analysis of
FET Transimpedance Amplifiers (SBOA060), and
Noise Analysis for High-Speed Op Amps (SBOA066),
available for download from the TI web site.
with:
79µV
1
80
2p ǸRFR FILTERCFC FILTER
(5)
The circuit in Figure 6b rolls off at 20dB/decade. The
circuit with the additional filter shown in Figure 6c rolls
off at 40dB/decade, resulting in improved noise
performance.
Integrated Output Noise (µVrms)
f *3dB +
CDIODE
= 100pF
CDIODE
= 50pF
60
CDIODE
= 20pF
0
Output Noise (nV/√Hz)
35µV
30µV
27µV
20
See Figure 6c
300
50µV
CDIODE
= 10pF
CDIODE
= 1pF
0
CDIODE = 10pF
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
200
Figure 10. Integrated Output Noise for Various
Values of CDIODE for Circuit in Figure 6c
See Figure 6a
100
See Figure 6b
See Figure 6c
0
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 8. Output Noise for Circuits in Figure 6
13
"#$
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www.ti.com
SBOS291G − NOVEMBER 2003 − REVISED SEPTEMBER 2007
BOARD LAYOUT
CAPACITIVE LOAD AND STABILITY
Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting input).
This capacitance causes the voltage noise of the op
amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to
reverse-bias a photodiode can significantly reduce its
capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a small
photodiode.
The OPA380 series op amps can drive up to 500pF pure
capacitive load. Increasing the gain enhances the
amplifier’s ability to drive greater capacitive loads (see
the Typical Characteristic curve, Small-Signal
Overshoot vs Capacitive Load).
Circuit board leakage can degrade the performance of
an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that
encircles the summing junction and is driven at the
same voltage can help control leakage, as shown in
Figure 11.
RF
One method of improving capacitive load drive in the
unity-gain configuration is to insert a 10Ω to 20Ω
resistor in series with the load. This reduces ringing with
large capacitive loads while maintaining DC accuracy.
DRIVING FAST 16-BIT ANALOG-TO-DIGITAL
CONVERTERS (ADC)
The OPA380 series is optimized for driving a fast 16-bit
ADC such as the ADS8411. The OPA380 op amp
buffers the converter’s input capacitance and resulting
charge injection while providing signal gain. Figure 12
shows the OPA380 in a single-ended method of
interfacing the ADS8411 16-bit, 2MSPS ADC. For
additional information, refer to the ADS8411 data sheet.
λ
OPA380
VOUT
CF
RF
Guard Ring
15Ω
ADS8411
OPA380
Figure 11. Connection of Input Guard
6800pF
OTHER WAYS TO MEASURE SMALL
CURRENTS
Logarithmic amplifiers are used to compress extremely
wide dynamic range input currents to a much narrower
range. Wide input dynamic ranges of 8 decades, or
100pA to 10mA, can be accommodated for input to a
12-bit ADC. (Suggested products: LOG101, LOG102,
LOG104, and LOG112.)
RC Values shown are optimized for the
ADS8411 values may vary for other ADCs.
Figure 12. Driving 16-Bit ADCs
CF
Extremely small currents can be accurately measured
by integrating currents on a capacitor. (Suggested
product: IVC102.)
Low-level currents can be converted to high-resolution
data words. (Suggested product: DDC112.)
For further information on the range of products
available, search www.ti.com using the above specific
model names or by using keywords transimpedance
and logarithmic.
RF
R1
VIN
OPA380
VOUT
(Provides high−speed amplification
with very low offset and drift.)
Figure 13. OPA380 Inverting Gain Configuration
14
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
OPA2380AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
BBX
OPA2380AIDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
BBX
OPA2380AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
BBX
OPA2380AIDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
BBX
OPA380AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
380A
OPA380AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
380A
OPA380AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
AUN
OPA380AIDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
AUN
OPA380AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
AUN
OPA380AIDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
AUN
OPA380AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
380A
OPA380AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
380A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Mar-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA2380AIDGKR
VSSOP
DGK
8
OPA2380AIDGKT
VSSOP
DGK
OPA380AIDGKR
VSSOP
DGK
OPA380AIDGKT
VSSOP
OPA380AIDR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Mar-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2380AIDGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
OPA2380AIDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA380AIDGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
OPA380AIDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA380AIDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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