Texas Instruments | 350-MHz Low-Noise High-Speed Amplifiers (Rev. C) | Datasheet | Texas Instruments 350-MHz Low-Noise High-Speed Amplifiers (Rev. C) Datasheet

Texas Instruments 350-MHz Low-Noise High-Speed Amplifiers (Rev. C) Datasheet
THS4021
THS4022
www.ti.com
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
FEATURES
1
THS4021
D and DGN Package
(Top View)
• Ultralow 1.5-nV/√Hz Voltage Noise
• High Speed:
– 350-MHz Bandwidth (G = 10, –3 dB)
– 470-V/μs Slew Rate
– 40-ns Settling Time (0.1%)
• Stable at a Gain of 10 (–9) or Greater
• High Output Drive, IO = 100 mA (typ)
• Excellent Video Performance:
– 17-MHz Bandwidth (0.1 dB, G = 10)
– 0.02% Differential Gain
– 0.08° Differential Phase
• Very Low Distortion:
– THD = –68 dBc (f = 1 MHz, RL = 150 Ω)
• Wide Range of Power Supplies:
– VCC = ±5 V to ±15 V
• Available in Standard SOIC or MSOP
PowerPAD™ Package
• Evaluation Module Available
23
THS4022
D and DGN Package
(Top View)
NULL
1
8
NULL
1OUT
1
8
VCC+
IN–
2
7
VCC+
1IN–
2
7
2OUT
IN+
VCC–
3
6
6
5
1IN+
–VCC
3
4
OUT
NC
4
5
2IN–
2IN+
NC - No internal connection
Cross Section View Showing
PowerPAD Option (DGN)
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
The THS4021 and THS4022 are ultralow voltage
noise, high-speed voltage feedback amplifiers that
are ideal for applications requiring low voltage noise,
including
communication
and
imaging.
The
single-amplifier THS4021 and the dual-amplifier
THS4022 offer very good ac performance with
350-MHz bandwidth, 470-V/μs slew rate, and 40-ns
settling time (0.1%). The THS4021 and THS4022 are
stable at gains of 10 (–9) or greater. These amplifiers
have a high drive capability of 100 mA and draw only
7.8-mA supply current per channel. With total
harmonic distortion (THD) of –68 dBc at f = 1 MHz,
the THS4021 and THS4022 are ideally suited for
applications requiring low distortion.
In − Current Noise − pA//Hz
DESCRIPTION
Vn − Voltage Noise − nV//Hz
100
VCC = ± 15 V and ± 5 V
TA = 25°C
10
Vn
In
1
10
100
1k
10k
100k
f − Frequency − Hz
G001
Figure 1.
RELATED DEVICES
DEVICE
DESCRIPTION
THS4011/4012
290-MHz Low-Distortion High-Speed Amplifiers
THS4031/4032
100-MHz Low-Noise High-Speed Amplifiers
THS4061/4062
180-MHz High-Speed Amplifiers
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated
THS4021
THS4022
www.ti.com
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
CAUTION: The THS4021 and THS4022 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
AVAILABLE OPTIONS (1)
PACKAGED DEVICES
TA
0°C to 70°C
–40°C to 85°C
(1)
(2)
NUMBER OF
CHANNELS
PLASTIC
SMALL OUTLINE (2)
(D)
PLASTIC MSOP (2)
(DGN)
MSOP SYMBOL
EVALUATION
MODULE
1
THS4021CD
THS4021CDGN
ACK
THS4021EVM
2
THS4022CD
THS4022CDGN
ACA
THS4022EVM
1
THS4021ID
THS4021CIDGN
ACL
–
2
THS4022ID
THS4022CIDGN
ACB
–
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (for example, THS4021CDGN).
FUNCTIONAL BLOCK DIAGRAMS
Null
2
1
8
IN–
6
OUT
3
IN+
S0273-01
Figure 2. THS4021—Single Channel
VCC
1IN–
1OUT
1IN+
2IN–
2OUT
2IN+
–VCC
S0274-01
Figure 3. THS4022—Dual Channel
2
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Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
THS4021
THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VCC
Supply voltage
±16.5
V
VI
Input voltage
±VCC
V
IO
Output current
150
mA
VIO
Differential input voltage
±4
V
Continuous total power dissipation
TJ
TA
Tstg
See Dissipation Ratings table
Maximum junction temperature
0 to 70
I-suffix
°C
–40 to 85
Storage temperature
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
°C
150
Operating free-air temperature: C-suffix
–65 to 150
°C
300
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
θJA
(°C/W)
θJC
(°C/W)
TA = 25°C
POWER RATING
D (1)
167
38.3
740 mW
DGN (2)
58.4
4.7
2.14 W
PACKAGE
(1)
(2)
This data was taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the θJA is 95°C/W with a
power rating at TA = 25°C of 1.32 W.
This data was taken using 2-oz. (0.071-mm thick) trace and copper pad on a 3-in. × 3-in. (7.62-cm × 7.62-cm) PCB, with the device
soldered directly to the board. For further information, see the Application Information section of this data sheet.
RECOMMENDED OPERATING CONDITIONS
MIN
Dual supply
VCC+ and VCC–
Supply voltage
TA
Operating free-air temperature
NOM
MAX
±4.5
±16
Single supply
9
32
C-suffix
0
70
–40
85
I-suffix
UNIT
V
°C
ELECTRICAL CHARACTERISTICS
at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic Performance
VCC = ±15 V
Small-signal bandwidth
(–3 dB)
Bandwidth for 0 1-dB flatness
Full power bandwidth (1)
(1)
(2)
VCC = ±15 V
VCC = ±5 V
BW
SR
VCC = ±5 V
Slew rate (2)
VCC = ±15 V
VCC = ±5 V
Gain = 10
Gain = 20
Gain = 10
VO(pp) = 20 V, VCC = ±15 V
VCC = ±5 V, 5-V step
280
80
70
17
MHz
17
3.7
VO(pp) = 5 V, VCC = ±5 V
VCC = ±15 V, 10-V step
350
11.8
Gain = 10
470
370
V/μs
Full-power bandwidth = slew rate / 2π VO(Peak).
Slew rate is measured from an output level range of 25% to 75%.
Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
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3
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
PARAMETER
Settling time to 0.1%
ts
Settling time to 0.01%
TEST CONDITIONS
VCC = ±15 V, 5-V step
VCC = ±5 V, 2-V step
VCC = ±15 V, 5-V step
VCC = ±5 V, 2-V step
MIN
TYP
MAX
UNIT
40
Gain = –10
50
ns
145
Gain = –10
150
Noise/Distortion Performance
THD
VO(pp) = 2 V, f = 1 MHz,
gain = 2, VCC = ±15 V
RL = 150 Ω
–68
RL = 1 kΩ
–77
VO(pp) = 2 V, f = 1 MHz,
gain = 2, VCC = ±5 V
RL = 150 Ω
–69
RL = 1 kΩ
–78
Total harmonic distortion
dBc
Vn
Input voltage noise
VCC = ±5 V or ±15 V, f > 10 kHz
1.5
nV/√Hz
In
Input current noise
VCC = ±5 V or ±15 V, f > 10 kHz
2
pA/√Hz
XT
Differential gain error
Gain = 2, NTSC, 40 IRE
modulation, ±100 IRE ramp
VCC = ±15
0.02%
VCC = ±5 V
0.02%
Differential phase error
Gain = 2, NTSC, 40 IRE
modulation, ±100 IRE ramp
VCC = ±15
0.08
VCC = ±5 V
0.06
Channel-to-channel crosstalk
(THS4022 only)
VCC = ±5 V or ±15 V, f = 1 MHz
°
–60
dB
DC Performance
VCC = ±15 V, VO = ±10 V,
RL = 1 kΩ
TA = 25°C
40
TA = full range
35
VCC = ±5 V, VO = ±2.5 V,
RL = 250 Ω
TA = 25°C
20
TA = full range
15
Open-loop gain
VOS
TA = 25°C
Input offset voltage
Input bias current
IOS
Input offset current
Offset current drift
0.5
2
3
TA = full range
VCC = ±5 V or ±15 V
V/mV
35
TA = full range
Offset voltage drift
IIB
60
μV/°C
15
TA = 25°C
3
TA = full range
6
6
TA = 25°C
30
TA = full range
250
400
TA = full range
0.3
mV
μA
nA
nA/°C
Input Characteristics
VCC = ±15 V
±13.8
±14.3
VCC = ±5 V
±3.8
±4.3
74
95
dB
1
MΩ
1.5
pF
VICR
Common-mode input voltage
range
CMRR
Common-mode rejection ratio VCC = ±15 V, VICR = ±12 V, TA = full range
ri
Input resistance
Ci
Input capacitance
V
Output Characteristics
VO
Output voltage swing
VCC = ±15 V
RL = 250 Ω
±12
±12.5
VCC = ±5 V
RL = 150 Ω
±3
±3.3
±13
±13.5
±3.4
±3.8
80
100
50
75
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
IO
Output current
ISC
Short-circuit current (3)
VCC = ±15 V
RO
Output resistance (3)
Open loop
(3)
4
VCC = ±5 V
RL = 1 kΩ
RL = 20 Ω
V
mA
150
mA
13
Ω
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily
loaded or shorted. See the Absolute Maximum Ratings table of this data sheet for more information.
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
Dual supply
Supply voltage operating
range
VCC
33
V
10
11
TA = 25°C
VCC = ±5 V
Power-supply rejection ratio
7.8
TA = full range
Supply current (per amplifier)
PSRR
±16.5
9
TA = 25°C
VCC = ±15 V
ICC
±4.5
Single supply
6.7
mA
9
TA = full range
10.5
VCC = ±5 V or ±15 V, TA = full range
80
95
dB
TYPICAL CHARACTERISTICS
CROSSTALK
vs
FREQUENCY
OPEN LOOP GAIN AND PHASE RESPONSE
vs
FREQUENCY
10
VCC = ± 5 V & ±15 V
Gain
−20
−30
−40
−50
−60
−70
−80
1M
10M
0
100
100M
80
−30
−60
60
Phase
40
−90
20
−120
0
−150
−20
1k
1G
10k
1M
100k
f − Frequency − Hz
Figure 5.
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
DISTORTION
vs
OUTPUT VOLTAGE
−10
RL = 1 kΩ
−80
−10
VCC = ± 15 V
RL = 1 kΩ
G = 10
f = 1 MHz
−30
RL = 150 Ω
DISTORTION
vs
OUTPUT VOLTAGE
VCC = ± 15 V
RL = 150 Ω
G = 10
f = 1 MHz
−30
Distortion − dBc
VCC = ± 15 V
Gain = 10
VO(PP) = 2 V
Distortion − dBc
THD − Total Harmonic Distortion − dBc
−40
−70
−180
1G
G003
Figure 4.
−60
100M
f − Frequency − Hz
G002
−50
10M
Phase − 5
Crosstalk − dB
−10
30
120
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
Open Loop Gain − dB
0
−50
2nd Harmonic
−70
−50
2nd Harmonic
−70
3rd Harmonic
−90
−90
−90
3rd Harmonic
−100
100k
−110
1M
−110
0
10M
5
10
15
VO − Output Voltage − V
f − Frequency − Hz
G004
Figure 6.
20
G005
Figure 7.
Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
0
5
10
15
VO − Output Voltage − V
20
G006
Figure 8.
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5
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
DISTORTION
vs
FREQUENCY
−70
2nd Harmonic
−80
3rd Harmonic
−90
−100
100k
1M
−70
−80
−90
1M
f − Frequency − Hz
G008
DISTORTION
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
−70
3rd Harmonic
RF = 220 Ω
1M
20
RF = 150 Ω
15
VCC = ± 15 V
Gain = 10
RL = 150 Ω
VO(PP) = 400 mV
10
10k
10M
f − Frequency − Hz
1M
100k
10M
100M
Figure 13.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
30
VCC = ± 5 V
Gain = 10
RL = 150 Ω
VO(PP) = 400 mV
100k
Output Amplitude − dB
RF = 220 Ω
20
VCC = ±15 V
RF = 1 kΩ
Gain = 20
RL = 150 Ω
VO(PP) = 400 mV
1G
f − Frequency − Hz
25
20
15
10
100k
1G
G012
0.6
RF = 220 Ω
VCC = ±5 V
Gain = 20
RL = 150 Ω
VO(PP) = 400 mV
1M
RF = 1 kΩ
0.4
0.2
0.0
VCC = ± 5 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
−0.2
−0.4
−0.6
10M
G013
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100M
1-V STEP RESPONSE
100M
0
1G
50
100 150 200 250 300 350 400
t − Time − ns
f − Frequency − Hz
Figure 15.
10M
Figure 14.
RF = 6.2 kΩ
25
1M
f − Frequency − Hz
0.8
RF = 6.2 kΩ
100M
15
10
10k
1G
30
10M
RF = 150 Ω
G011
Figure 12.
1M
RF = 220 Ω
20
f − Frequency − Hz
G010
Output Amplitude − dB
Output Amplitude − dB
Output Amplitude − dB
Distortion − dBc
25
2nd Harmonic
−90
6
G009
Figure 11.
−60
10
100k
10M
Figure 10.
25
15
1M
f − Frequency − Hz
Figure 9.
VCC = ± 5 V
RL = 150 Ω
G = 10
VO(PP) = 2 V
−100
100k
3rd Harmonic
f − Frequency − Hz
−40
−80
−80
−100
100k
10M
G007
−50
2nd Harmonic
−70
−90
3rd Harmonic
−100
100k
10M
VCC = ± 15 V
RL = 150 Ω
G = 10
VO(PP) = 2 V
−60
2nd Harmonic
Distortion − dBc
−60
−50
VCC = ± 5 V
RL = 1 kΩ
G = 10
VO(PP) = 2 V
VO − Output Voltage − V
Distortion − dBc
−60
DISTORTION
vs
FREQUENCY
−50
VCC = ± 15 V
RL = 1 kΩ
G = 10
VO(PP) = 2 V
Distortion − dBc
−50
DISTORTION
vs
FREQUENCY
G015
G014
Figure 16.
Figure 17.
Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
THS4021
THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
5-V STEP RESPONSE
1-V STEP RESPONSE
6
0.6
1
0
−1
VCC = ± 5 V
Gain = −10
RF = 220 Ω
RL = 150 Ω
−2
50
0.4
0.2
0.0
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
−0.2
−0.4
0
−2
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150
−6
0
100 150 200 250 300 350 400
2
−4
−0.6
−3
0
4
VO − Output Voltage − V
VO − Output Voltage − V
2
VO − Output Voltage − V
10-V STEP RESPONSE
0.8
3
50
100 150 200 250 300 350 400
0
400
Figure 20.
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
3.30
14
−0.15
−0.20
VCC = ± 15 V
−0.25
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
12
3.20
3.15
3.10
3.05
3.00
−40
100
TA = 25°C
3.25
|VO| − Output Voltage − |V|
IIB − Input Bias Current − µA
VCC = ± 5 V
−0.10
RL = 1 kΩ
10
8
RL = 150 Ω
6
4
2
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
G019
100
5
7
9
11
13
+VCC − Supply Voltage − V
G020
Figure 21.
Figure 22.
Figure 23.
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
15
500
G018
Figure 19.
VCC = ± 5 V & ±15 V
15
G021
11
14
TA = 25°C
VCC = ± 15 V
RL = 250 Ω
12
|VO| − Output Voltage − |V|
13
11
9
7
5
10
VCC = ± 15 V
RL = 1 kΩ
8
6
VCC = ± 5 V
RL = 1 kΩ
4
VCC = ± 5 V
RL = 150 Ω
2
3
5
7
9
11
13
+VCC − Supply Voltage − V
0
−40
15
G022
10
TA=85°C
9
8
TA=25°C
7
6
TA=−40°C
5
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
Figure 24.
ICC − Supply Current − mA
VIO − Input Offset Voltage − mV
300
Figure 18.
−0.05
VICR − Common−Mode Input Voltage − +V
200
t − Time − ns
G017
G016
−0.30
−40
100
t − Time − ns
t − Time − ns
100
G023
Figure 25.
Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
5
7
9
11
13
+VCC − Supply Voltage − V
15
G024
Figure 26.
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
PSRR − Power Supply Rejection Ratio − dB
Vn − Voltage Noise − nV//Hz
In − Current Noise − pA//Hz
100
VCC = ± 15 V and ± 5 V
TA = 25°C
10
Vn
In
1
10
100
1k
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
10k
100k
0
VCC = ±15 V & ±5 V
−10
−20
−VCC
−30
−40
+VCC
−50
−60
−70
−80
100k
1M
10M
1G
f − Frequency − Hz
f − Frequency − Hz
G026
G025
Figure 27.
8
100M
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COMMON MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
Figure 28.
0
−10
VCC = ±15 V or ±5 V
RF = 20 kΩ
VI(PP) = 2 V
−20
−30
−40
−50
−60
100k
1M
10M
100M
1G
f − Frequency − Hz
G027
Figure 29.
Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
APPLICATION INFORMATION
Theory of Operation
The THS402x is a high-speed operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fT of
several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 30.
(7) VCC+
(6) OUT
IN– (2)
IN+ (3)
(4) VCC–
NULL (1)
NULL (8)
S0276-01
Figure 30. THS4021 Simplified Schematic
Noise Calculations and Noise Figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals, where
signal-to-noise ratio (SNR) is very important. The noise model for the THS402x is shown in Figure 31. This
model includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
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eRs
RS
en
Noiseless
eni
+
_
eno
IN+
eRf
RF
eRg
IN–
RG
S0277-01
Figure 31. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
ni
+
Ǹ
ǒenǓ ) ǒIN+
2
R
Ǔ
S
2
ǒ
) IN−
ǒR F ø
R
ǓǓ
G
2
ǒ
) 4 kTR s ) 4 kT R ø R
F
G
Ǔ
where:
k = Boltzmann’s constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273 + °C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
e no + e
ni
A
V
ǒ
+ e ni 1 )
Ǔ
RF
(noninverting case)
RG
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, see the Noise Analysis in Operational Amplifier Circuits application
report (SLVA043).
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF +
10
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ȱ e 2ȳ
10logȧ ni ȧ
ȧ 2ȧ
ȲǒeRsǓ ȴ
Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
ǒ
2
ȱ
ǒen Ǔ ) ǒIN+
ȧ
NF + 10logȧ1 )
4 kTR
ȧ
S
ȧ
Ȳ
R
Ǔ
2 ȳ
Ǔ
S
ȧ
ȧ
ȧ
ȧ
ȴ
Figure 32 shows the noise figure graph for the THS402x.
NOISE FIGURE
vs
SOURCE RESISTANCE
16
14
f = 10 kHz
TA = 25°C
Noise Figure − dB
12
10
8
6
4
2
0
10
100
1k
10k
Source Resistance − Ω
G028
Figure 32. Noise Figure vs Source Resistance
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Product Folder Link(s): THS4021 THS4022
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THS4022
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Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS402x has been internally compensated to maximize its bandwidth and
slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device phase margin, leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 33. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1 kW
50 W
Input
_
20 W
Output
THS402x
CLOAD
+
S0278-01
Figure 33. Driving a Capacitive Load
Offset Nulling
The THS402x has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4021. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This
is shown in Figure 34.
VCC+
0.1 mF
+
THS402x
_
10 kW
0.1 mF
VCC–
S0279-01
Figure 34. Offset Nulling Schematic
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
Offset Voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The schematic and formula of Figure 35 can be used to calculate the output offset
voltage.
RG
RF
IIB–
–
VOS
+
RS
+
–
VIO
IIB+
æ
R ö
VOS = (± VIO ± IIB + ´ RS )ç 1 + F ÷ ± IIB - ´ RF
ç
RG ÷ø
è
S0280-01
Figure 35. Output Offset Voltage Model
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 36).
RG
RF
–
VO
VI
+
R1
C1
f-3dB =
1
2pR1C1
VO æ
R öæ
1
ö
= ç 1 + F ÷÷ ç
÷
VI çè
RG ø è 1 + sR1C1 ø
S0281-01
Figure 36. Single-Pole Low-Pass Filter
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THS4022
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Circuit Layout Considerations
To achieve the levels of high-frequency performance of the THS402x, follow proper printed-circuit board
high-frequency design techniques. A general set of guidelines is given as follows. In addition, a THS402x
evaluation board is available to use as a guide for layout or for evaluating the device performance.
• Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low-inducance ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
• Proper power-supply decoupling—Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-μF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inch (2.54 mm) between the device power terminals and the ceramic
capacitors.
• Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often produces stability problems. Surface-mount packages soldered directly to
the PCB is the best implementation.
• Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance
at the input of the amplifier.
• Surface-mount passive components—Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
General Thermal Pad Design Considerations
The THS402x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 37(a) and Figure 37(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 37(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a design breakthrough, combining the small area and ease of the surface
mount assembly method to eliminate the previously difficult mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
M0031-01
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 37. Views of Thermally Enhanced DGN Package
Although there are many ways to heatsink this device properly, the following steps illustrate the recommended
approach.
Thermal pad area = 68 mils ´ 70 mils (1.73 mm ´1.78 mm) with 5 vias.
Via diameter = 13 mils (0.33 mm).
M0032-02
Figure 38. Thermal Pad PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 38. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0.33 mm) in diameter. Keep
them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These vias
help dissipate the heat generated by the THS402xDGN IC. These additional vias may be larger than the
13-mil (0.33-mm) diameter vias directly under the thermal pad. They can be larger because they are not in
the thermal pad area to be soldered, so wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS402xDGN package should connect to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
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7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS402xDGN IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
The actual thermal performance achieved with the THS402xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches
(7.62 cm × 7.62 cm), then the expected thermal coefficient, θJA, is about 58.4°C/W. For comparison, the
non-PowerPAD version of the THS402x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is
shown in Figure 39 and is calculated by the following formula:
ǒ
T
P
D
+
–T
MAX A
q
JA
Ǔ
where:
PD = Maximum power dissipation of THS402x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
Maximum Power Dissipation − W
3.0
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
2.5
SOIC Package
High-K Test PCB
θJA = 98°C/W
2.0
TJ = 150°C
1.5
1.0
0.5
SOIC Package
Low-K Test PCB
θJA = 167°C/W
0.0
−40
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
100
G029
NOTE: Results are with no air flow and PCB size = 3 in. × 3 in. (7.62 cm × 7.62 cm).
Figure 39. Maximum Power Dissipation vs Free-Air Temperature
More-complete details of the thermal pad installation process and thermal management techniques can be found
in the PowerPAD Thermally Enhanced Package application report (SLMA002).
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially with multiamplifier devices. Because these devices have linear output stages (Class A-B), most of the
heat dissipation is at low output voltages with high output currents. Figure 40 through Figure 43 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient temperature
increases, the limit lines shown drop accordingly. The area under each respective limit line is considered the safe
operating area. Any condition above this line exceeds the amplifier limits and failure may result. When using VCC
= ±5 V, there is generally not a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC
package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these
graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat
dissipation. But the device should always be soldered to a copper plane to use fully the heat dissipation
properties of the thermal pad. The SOIC package, on the other hand, is highly dependent on how it is mounted
on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation
capability increases. The currents and voltages shown in these graphs are for the total package. For the
dual-amplifier package (THS4022), the sum of the RMS output currents and voltages should be used to choose
the proper package. The graphs shown assume that both amplifier outputs are identical.
THS4021
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
VCC = ± 5 V
Tj = 150°C
TA = 50°C
180
1k
Maximum Output
Current Limit Line
|IO| − Maximum RMS Output Current − mA
|IO| − Maximum RMS Output Current − mA
200
THS4021
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
160
140
Package With
θJA < = 120°C/W
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
40
20
Safe Operating
Area
0
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Maximum Output
Current Limit Line
DGN Package
θJA = 58.4°C/W
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Safe Operating
Area
10
0
1
2
3
4
|VO| − RMS Output Voltage − V
5
0
G030
Figure 40.
3
6
9
12
|VO| − RMS Output Voltage − V
15
G031
Figure 41.
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THS4021
THS4022
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THS4022
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
1k
Maximum Output
Current Limit Line
Package With
θJA ≤ 60°C/W
|IO| − Maximum RMS Output Current − mA
|IO| − Maximum RMS Output Current − mA
200
THS4022
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
160
140
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
Safe Operating Area
40
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
SO-8 Package
θJA = 98°C/W
High-K Test PCB
20
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
10
DGN Package
θJA = 58.4°C/W
Safe Operating Area
0
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
1
0
1
2
3
4
|VO| − RMS Output Voltage − V
5
0
3
Submit Documentation Feedback
6
9
12
|VO| − RMS Output Voltage − V
G032
Figure 42.
18
Maximum Output
Current Limit Line
15
G033
Figure 43.
Copyright © 1999–2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
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THS4022
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SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
Evaluation Board
Evaluation boards are available for the THS4021 (literature number SLOP129) and THS4022 (literature number
SLOP231). These boards have been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the THS4021 evaluation board is shown in Figure 44. The circuitry
has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For
more information, see the THS4021 High-Speed Operational Amplifier Evaluation Module user’s guide
(SLOU063) or the THS4022 Dual High-Speed Operational Amplifier Evaluation Module user’s guide (SLOU064).
To order the evaluation board, contact your local TI sales office or distributor or visit the Texas Instruments Web
site at www.ti.com.
VCC+
+
C3
0.1 mF
R4
1 kW
C2
6.8 mF
NULL
+
IN+
R5
49.9 W
THS4021
R3
49.9 W
OUT
_
NULL
R2
49.9 W
C4
0.1 mF
+
C1
6.8 mF
IN–
VCC–
S0282-01
Figure 44. THS4021 Evaluation Board
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PACKAGE OPTION ADDENDUM
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6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4021CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
4021C
THS4021CDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ACK
THS4021CDGNG4
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ACK
THS4021CDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ACK
THS4021ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4021I
THS4021IDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACL
THS4021IDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACL
THS4021IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4021I
THS4022CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
4022C
THS4022CDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ACA
THS4022CDGNG4
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ACA
THS4022CDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ACA
THS4022ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4022I
THS4022IDGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
-40 to 85
ACB
THS4022IDGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
-40 to 85
ACB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
THS4021CDGNR
HVSSOP
DGN
8
2500
330.0
12.4
THS4021IDGNR
HVSSOP
DGN
8
2500
330.0
THS4021IDR
SOIC
D
8
2500
330.0
THS4022CDGNR
HVSSOP
DGN
8
2500
THS4022IDGNR
HVSSOP
DGN
8
2500
5.3
3.4
1.4
8.0
12.0
Q1
12.4
5.3
3.4
1.4
8.0
12.0
Q1
12.4
6.4
5.2
2.1
8.0
12.0
Q1
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4021CDGNR
HVSSOP
DGN
8
2500
358.0
335.0
35.0
THS4021IDGNR
HVSSOP
DGN
8
2500
358.0
335.0
35.0
THS4021IDR
SOIC
D
8
2500
350.0
350.0
43.0
THS4022CDGNR
HVSSOP
DGN
8
2500
350.0
350.0
43.0
THS4022IDGNR
HVSSOP
DGN
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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