Texas Instruments | TLV7211, TLV7211A CMOS Comparators With Rail-to-Rail Input and Push-Pull Output (Rev. B) | Datasheet | Texas Instruments TLV7211, TLV7211A CMOS Comparators With Rail-to-Rail Input and Push-Pull Output (Rev. B) Datasheet

Texas Instruments TLV7211, TLV7211A CMOS Comparators With Rail-to-Rail Input and Push-Pull Output (Rev. B) Datasheet
TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
Parameters Specified at 2.7-V, 5-V, and 15-V
Supplies
Supply Current 7 µA (Typ) at 5 V
Response Time 4 µs (Typ) at 5 V
Push-Pull Output
Input Common-Mode Range Beyond
VCC– and VCC+
Low Input Current
D PACKAGE
(TOP VIEW)
NC
IN–
IN+
VCC–
1
2
8
7
3
6
4
5
Battery-Powered Products
Notebooks and PDAs
Mobile Communications
Alarm and Security Circuits
Direct Sensor Interface
Replaces Amplifiers Used as Comparators
With Better Performance and Lower Current
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
NC
VCC+
OUT
NC
OUT
VCC+
IN+
1
5
OUT
VCC+
IN+
VCC–
2
3
4
IN–
1
6
2
5
3
4
NC
VCC–
IN–
NC – No internal connection
DESCRIPTION/ORDERING INFORMATION
The TLV7211 and TLV7211A are micropower CMOS comparators available in the space-saving SOT-23-5
package. This makes the comparators ideal for space- and weight-critical designs. The TLV7211A features an
input offset voltage of 5 mV, and the TLV7211 features an input offset voltage of 15 mV.
The main benefits of the SOT-23-5 package are most apparent in small portable electronic devices, such as
mobile phones, pagers, notebook computers, personal digital assistants, and PCMCIA cards. The rail-to-rail
input voltage makes the TLV7211 or TLV7211A a good choice for sensor interfacing, such as light detector
circuits, optical and magnetic sensors, and alarm and status circuits.
The SOT-23-5 package's small size allows it to fit into tight spaces on PC boards.
ORDERING INFORMATION
TA
VOS
(MAX)
PACKAGE (1)
SOIC – D
5 mV
SOT-23-5 – DBV
SOT (SC-70) – DCK
–40°C to 85°C
SOIC – D
15 mV
SOT-23-5 – DBV
SOT (SC-70) – DCK
(1)
(2)
ORDERABLE PART NUMBER
Reel of 2500
TLV7211AIDR
Tube of 75
TLV7211AID
Reel of 3000
TLV7211AIDBVR
Reel of 3000
TLV7211AIDCKR
Reel of 250
TLV7211AIDCKT
Reel of 2500
TLV7211IDR
Tube of 75
TLV7211ID
Reel of 3000
TLV7211IDBVR
Reel of 3000
TLV7211IDCKR
Reel of 250
TLV7211IDCKT
TOP-SIDE MARKING (2)
7211AI
YBN_
Y8_
TY7211
YBK_
Y7_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
FUNCTIONAL BLOCK DIAGRAM
IN–
OUT
IN+
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
VCC+ – VCC–
MAX
Supply voltage (2)
UNIT
16
V
±Supply
voltage
V
VID
Differential input voltage (3)
VI
Input voltage range (any input)
VCC– – 0.3
VCC+ + 0.3
V
VO
Output voltage range
VCC– – 0.3
VCC+ + 0.3
V
ICC
Supply current
40
mA
II
Input current
±5
mA
IO
Output current
±30
mA
D package
θJA
Package thermal impedance (4) (5)
TJ
Operating virtual junction temperature
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
97
DBV package
206
DCK package
259
–65
°C/W
150
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND.
Differential voltages are at IN+ with respect to IN–.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
ESD Protection
Human-Body Model
TYP
UNIT
2000
V
Recommended Operating Conditions
2
MIN
MAX
VCC+ – VCC–
Supply voltage
2.7
15
V
TJ
Operating virtual junction temperature
–40
85
°C
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UNIT
TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
2.7-V Electrical Characteristics
VCC+ = 2.7 V, VCC– = GND, VCM = VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TJ
TLV7211A
MIN
25°C
TLV7211
TYP
MAX
3
5
MIN
TYP
MAX
3
15
UNIT
VOS
Input offset voltage
TCVOS
Input offset voltage
temperature drift
25°C
1
1
Input offset voltage
average drift (1)
25°C
3.3
3.3
µV/month
IB
Input current
25°C
0.04
0.04
pA
IOS
Input offset current
25°C
0.02
0.02
pA
CMRR
Common-mode
rejection ratio
0 ≤ VCM ≤ 2.7 V
25°C
75
75
dB
PSRR
Power-supply rejection
ratio
2.7 V ≤ VCC+ ≤ 15 V
25°C
80
80
dB
AV
Voltage gain
100
dB
–40°C to 85°C
25°C
CMRR > 55 dB
CMVR
Input common-mode
voltage range
VOH
High-level output
voltage
Iload = 2.5 mA
VOL
Low-level output
voltage
Iload = 2.5 mA
–40°C to 85°C
2.7
3
–0.3
3
–0.2
–0.3
0
25°C
2.4
–40°C to 85°C
2.3
25°C
2.5
25°C
25°C
–40°C to 85°C
–0.2
0.2
0.3
2.5
0.2
0.4
7
12
V
10
12
0.3
0.4
7
14
5
V
0
2.4
2.3
–40°C to 85°C
Supply current
2.9
mV
µV/°C
2.7
–40°C to 85°C
VOUT = High-Idle
(1)
2.9
–40°C to 85°C
VOUT = Low
18
100
25°C
25°C
CMRR > 55 dB
ICC
8
12
14
5
V
10
µA
12
Input offset voltage average drift is calculated by dividing the accelerated operating life VOS drift by the equivalent operational time. This
represents worst-case input conditions and includes the first 30 days of drift.
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3
TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
5-V Electrical Characteristics
VCC+ = 5 V, VCC– = GND, VCM = VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLV7211A
MIN
25°C
TLV7211
TYP
MAX
3
5
MIN
TYP
MAX
3
15
UNIT
VOS
Input offset voltage
TCVOS
Input offset voltage
temperature drift
25°C
1
1
Input offset voltage
average drift (1)
25°C
3.3
3.3
µV/month
IB
Input current
25°C
0.04
0.04
pA
IOS
Input offset current
25°C
0.02
0.02
pA
CMRR
Common-mode
rejection ratio
25°C
75
75
dB
PSRR
Power-supply rejection
ratio
25°C
80
80
dB
AV
Voltage gain
100
dB
–40°C to 85°C
5 V ≤ VCC+ ≤ 10 V
25°C
–40°C to 85°C
Input common-mode
voltage range
VOH
High-level output
voltage
Iload = 5 mA
VOL
Low-level output
voltage
Iload = 5 mA
5.3
–0.3
5.3
–0.3
0
25°C
4.6
–40°C to 85°C
4.45
25°C
4.8
0.2
7
4.8
0.4
0.2
5
–40°C to 85°C
V
0.4
0.55
14
7
18
25°C
V
0
4.6
0.55
25°C
–0.2
4.45
–40°C to 85°C
VOUT = High-Idle
–0.2
mV
µV/°C
5
–40°C to 85°C
Supply current
5.2
5
–40°C to 85°C
VOUT = Low
18
100
5.2
25°C
CMRR > 55 dB
ICC
8
25°C
CMRR > 55 dB
CMVR
14
18
10
5
13
V
10
µA
13
IOH
Short-circuit output
current
Isource
25°C
30
30
mA
IOL
Short-circuit output
current
Isink, VO < 12 V (2)
25°C
45
45
mA
(1)
(2)
4
TJ
Input offset voltage average drift is calculated by dividing the accelerated operating life VOS drift by the equivalent operational time. This
represents worst-case input conditions and includes the first 30 days of drift.
Do not short circuit the output to V+ if V+ is >12 V.
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TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
15-V Electrical Characteristics
VCC+ = 15 V, VCC– = GND, VCM = VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
TJ
TLV7211A
MIN
25°C
TLV7211
TYP
MAX
3
5
MIN
TYP
MAX
3
15
UNIT
VOS
Input offset voltage
TCVOS
Input offset voltage
temperature drift
25°C
4
4
µV/°C
Input offset voltage average
drift (1)
25°C
4
4
µV/month
IB
Input current
25°C
0.04
0.04
pA
IOS
Input offset current
25°C
0.02
0.02
pA
CMRR
Common-mode rejection
ratio
25°C
82
82
dB
PSRR
Power-supply rejection ratio
25°C
80
80
dB
AV
Voltage gain
100
dB
–40°C to 85°C
5 V ≤ VCC+ ≤ 10 V
25°C
CMRR > 55 dB
CMVR
Input common-mode voltage
range
CMRR > 55 dB
VOH
High-level output voltage
Iload = 5 mA
VOL
Low-level output voltage
Iload = 5 mA
IOL
(1)
(2)
Short-circuit output current
15.3
–40°C to 85°C
Isink, VO < 12
V (2)
–0.2
–0.3
0
25°C
14.6
–40°C to 85°C
14.45
14.8
7
14.8
0.4
0.2
–40°C to 85°C
V
0.4
0.55
14
7
18
5
V
0
14.6
0.55
25°C
–0.2
14.45
0.2
mV
15.3
15
–0.3
–40°C to 85°C
Isource
15.2
15
25°C
25°C
Supply current
Short-circuit output current
–40°C to 85°C
18
100
15.2
25°C
VOUT = High-Idle
IOH
25°C
–40°C to 85°C
VOUT = Low
ICC
8
14
18
12
5
14
V
12
µA
14
25°C
30
30
mA
25°C
45
45
mA
Input offset voltage average drift is calculated by dividing the accelerated operating life VOS drift by the equivalent operational time. This
represents worst-case input conditions and includes the first 30 days of drift.
Do not short circuit the output to V+ if V+ is >12 V.
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5
TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
Switching Characteristics
TJ = 25°C, VCC+ = 5 V, VCC– = GND, VCM = VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
TYP
UNIT
trise
Rise time
PARAMETER
f = 10 kHz, CL = 50 pF (1), Overdrive = 10 mV
TEST CONDITIONS
0.3
µs
tfall
Fall time
f = 10 kHz, CL = 50 pF (1), Overdrive = 10 mV
0.3
µs
f = 10 kHz, CL = 50 pF (1)
tPHL
Propagation delay time, high to low (2)
VCC+ = 2.7 V, f = 10 kHz, CL = 50 pF (1)
f = 10 kHz, CL = 50 pF (1)
tPLH
Propagation delay time, low to high (2)
VCC+ = 2.7 V, f = 10 kHz, CL = 50 pF (1)
(1)
(2)
6
CL includes probe and jig capacitance.
Input step voltage for propagation delay measurement is 2 V.
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10 mV
10
100 mV
4
10 mV
10
100 mV
4
10 mV
6
100 mV
4
10 mV
7
100 mV
4
µs
µs
TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
(SOURCING)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
(SINKING)
18
7
TA = -40°C
6
TA = -40°C
16
TA = 25°C
TA = 25°C
4
Supply Current – µA
Supply Current – µA
14
5
TA = 85°C
3
TA = 125°C
2
10
TA = 125°C
8
6
4
Positive Input = 0.1 V
Negative Input = 0 V
1
Positive Input = 0 V
Negative Input = 0.1 V
2
0
0
0
1
2
3
4
5
6
7
8
0
9 10 11 12 13 14 15
1
2
3
4
SUPPLY CURRENT
vs
TEMPERATURE
(SOURCING)
6
7
8
9 10 11 12 13 14 15
SUPPLY CURRENT
vs
TEMPERATURE
(SINKING)
18
6
VCC = 15 V
16
VCC = 2.7 V
15 V
Supply Current – µA
14
Supply Current – µA
5
Supply Voltage – V
Supply Voltage – V
5
TA = 85°C
12
4
VCC = 5 V
3
2
12
5V
10
8
6
2.7 V
4
1
Positive Input = 0.1 V
Negative Input = 0 V
0
-40 -25
-10
5
20
35
50
65
80
95
Positive Input = 0 V
Negative Input = 0.1 V
2
0
-40
-25
-10
5
20
35
50
65
80
95
110 125
110 125
Temperature – °C
Temperature – °C
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TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
OUTPUT SOURCING CURRENT
vs
SUPPLY VOLTAGE
OUTPUT SINKING CURRENT
vs
SUPPLY VOLTAGE
80
120
Positive Input = 0.1 V
Negative Input = 0 V
70
Positive Input = 0.1 V
Negative Input = 0 V
100
Sinking Current – mA
Source Current – mA
60
TA = -40°C
50
40
TA = 25°C
30
20
TA = 85°C
80
TA = -40°C
60
TA = 25°C
40
TA = 85°C
20
10
TA = 125°C
TA = 125°C
0
0
1
2
3
4
5
6
7
8
9
0
10 11 12
0
1
2
3
Supply Voltage – V
OUTPUT VOLTAGE
vs
OUTPUT SOURCING CURRENT
5
6
7
8
9
10 11 12
OUTPUT VOLTAGE
vs
OUTPUT SINKING CURRENT
900
1200
VCC = 5 V
VCC = 5 V
800
Output Voltage to GND – mV
1000
OutputVoltage
Voltage to
to VCCCC– –
mV
Output
mV
4
Supply Voltage – V
800
TA = 125°C
600
TA = 85°C
400
TA = 25°C
200
700
600
TA = 125°C
500
TA = 85°C
400
300
TA = 25°C
200
100
TA = -40°C
0
TA = -40°C
0
0
0
1
2
3
4
5
6
7
8
9
10
Output Sourcing Current – mA
8
Submit Documentation Feedback
1
2
3
4
5
6
7
Output Sinking Current – mA
8
9
10
TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
vs
OUTPUT SOURCING CURRENT
OUTPUT VOLTAGE
vs
OUTPUT SINKING CURRENT
1600
900
VCC = 15 V
VCC = 15 V
800
Output Voltage to GND – mV
OutputVoltage
Voltage to
to VCCCC– mV
Output
– mV
1400
1200
1000
TA = 125°C
800
TA = 85°C
600
TA = 25°C
400
700
600
TA = 125°C
500
TA = 85°C
400
TA = 25°C
300
200
100
200
TA = -40°C
TA = -40°C
0
0
0
1
2
3
4
5
6
7
8
9
0
10
1
3
4
5
6
7
8
9
10
Output Sinking Current – mA
Output Sourcing Current – mA
Response Time (tPLH) for Various Input Overdrives
(VCC = 2.7 V)
20 mV
2
Response Time (tPHL) for Various Input Overdrives
(VCC = 2.7 V)
10 mV
100 mV
100 mV
20 mV
10 mV
5 mV
1 V per Division
1 V per Division
5 mV
Input
2 µs per Division
2 µs per Division
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TLV7211,, TLV7211A
CMOS COMPARATORS
WITH RAIL-TO-RAIL INPUT AND PUSH-PULL OUTPUT
www.ti.com
SLCS149B – AUGUST 2006 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
Response Time (tPHL) for Various Input Overdrives
(VCC = 5 V)
100 mV
20 mV
10 mV
5 mV
100 mV
20 mV
10 mV
5 mV
1 V per Division
1 V per Division
Response Time (tPLH) for Various Input Overdrives
(VCC = 5 V)
Input
Input
2 µs per Division
2 µs per Division
Response Time (tPLH) for Various Input Overdrives
(VCC = 15 V)
100 mV
20 mV
10 mV
5 mV
3 V per Division
3 V per Division
100 mV
20 mV
10 mV
5 mV
Response Time (tPHL) for Various Input Overdrives
(VCC = 15 V)
Input
Input
2 µs per Division
10
2 µs per Division
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV7211AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
7211AI
TLV7211AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YBNM
TLV7211AIDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y8A
TLV7211AIDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y8A
TLV7211AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
7211AI
TLV7211ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY7211
TLV7211IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YBKM
TLV7211IDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y7A
TLV7211IDCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y7A
TLV7211IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY7211
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
25-Sep-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV7211AIDBVR
SOT-23
DBV
5
3000
178.0
9.0
TLV7211AIDCKR
SC70
DCK
6
3000
180.0
TLV7211AIDCKT
SC70
DCK
6
250
180.0
TLV7211AIDR
SOIC
D
8
2500
TLV7211IDBVR
SOT-23
DBV
5
TLV7211IDCKR
SC70
DCK
TLV7211IDCKT
SC70
DCK
TLV7211IDR
SOIC
D
3.3
3.2
1.4
4.0
8.0
Q3
8.4
2.41
2.41
1.2
4.0
8.0
Q3
8.4
2.41
2.41
1.2
4.0
8.0
Q3
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
6
3000
180.0
8.4
2.41
2.41
1.2
4.0
8.0
Q3
6
250
180.0
8.4
2.41
2.41
1.2
4.0
8.0
Q3
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV7211AIDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV7211AIDCKR
SC70
DCK
6
3000
202.0
201.0
28.0
TLV7211AIDCKT
SC70
DCK
6
250
202.0
201.0
28.0
TLV7211AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV7211IDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV7211IDCKR
SC70
DCK
6
3000
202.0
201.0
28.0
TLV7211IDCKT
SC70
DCK
6
250
202.0
201.0
28.0
TLV7211IDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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