LOG104 LOG 104 SBOS243C – MAY 2002 – REVISED APRIL 2005 Precision LOGARITHMIC AND LOG RATIO AMPLIFIER FEATURES DESCRIPTION ● EASY-TO-USE COMPLETE CORE FUNCTION The LOG104 is a versatile integrated circuit that computes the logarithm or log ratio of an input current relative to a reference current. ● HIGH ACCURACY: 0.01% FSO Over 5 Decades ● WIDE INPUT DYNAMIC RANGE: 7.5 Decades, 100pA to 3.5mA ● LOW QUIESCENT CURRENT: 1mA The LOG104 is tested over a wide dynamic range of input signals. In log ratio applications, a signal current can come from a photodiode, and a reference current from a resistor in series with a precision external reference. ● WIDE SUPPLY RANGE: ±4.5V to ±18V The output signal at VOUT is trimmed to 0.5V per decade of input current, allowing seven decades of input current, dynamic range. APPLICATIONS ● LOG, LOG RATIO COMPUTATION: Communication, Analytical, Medical, Industrial, Test, General Instrumentation ● PHOTODIODE SIGNAL COMPRESSION AMP ● ANALOG SIGNAL COMPRESSION IN FRONT OF ANALOG-TO-DIGITAL(A/D) CONVERTER I2 Low DC offset voltage and temperature drift allow accurate measurement of low-level signals over a wide environmental temperature range. The LOG104 is specified over the temperature range –5°C to +75°C, with operation over –40°C to +85°C. Note: Protected under US Patent #6,667,650; other patents pending. CC VOUT = 0.5 LOG (I1/I2) V+ 4 8 I1 LOG104 1 Q1 Q2 3 A2 A1 VOUT R2 R1 5 6 GND V– Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2002-2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, V+ to V– .................................................................... 36V Input Voltage ....................................................... V– (–0.5) to V+ (+0.5V) Input Current ................................................................................... ±10mA Output Short-Circuit(2) .............................................................. Continuous Operating Temperature .................................................... –40°C to +85°C Storage Temperature ..................................................... –55°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Short-circuit to ground. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN DESCRIPTION Top View SO I1 1 8 I2 NC 2 7 NC VOUT 3 6 GND V+ 4 5 V– LOG104 NC = No Internal Connection PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING LOG104AID SO -8 D LOG104 NOTES: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = –5°C to +75°C. At TA = +25°C, VS = ±5V, ROUT = 10kΩ, unless otherwise noted. LOG104AID PARAMETER CONDITION MIN CORE LOG FUNCTION IIN / VOUT Equation LOG CONFORMITY ERROR(1) Initial over Temperature GAIN(3) Initial Value Gain Error vs Temperature INPUT, A1 and A2 Offset Voltage vs Temperature vs Power Supply (PSRR) Input Bias Current vs Temperature Voltage Noise Current Noise Common-Mode Voltage Range (Positive) (Negative) Common-Mode Rejection Ratio (CMRR) OUTPUT, A2 (VOUT) Output Offset, VOSO, Initial vs Temperature Full-Scale Output (FSO) Short-Circuit Current 2 TYP MAX VO = (0.5V)log (I1/I2) 1nA to 100µA (5 decades) 100pA to 3.5mA (7.5 decades) 1nA to 100µA (5 decades) 100pA to 3.5mA (7.5 decades)(2) 0.01 0.06 0.0001 0.0005 1nA to 100µA 1nA to 100µA TMIN to TMAX 0.5 0.15 0.003 TMIN to TMAX VS = ±4.5V to ±18V TMIN to TMAX f = 10Hz to 10kHz f = 1kHz f = 1kHz TMIN to TMAX VS = ±5V V 0.2 ±1 0.01 ±0.3 ±2 5 ±5 Doubles Every 10°C 3 30 4 (V+) – 2 (V+) – 1.5 (V–) + 2 (V–) + 1.2 105 ±3 ±2 (V–) + 1.2 ±1.5 50 % % %/ °C %/ °C V/decade % %/ °C mV µV/°C µV/V pA µVrms nV/√Hz fA/√Hz V V dB ±15 (V+) – 1.5 ±18 UNITS mV µV/°C V mA LOG104 www.ti.com SBOS243C ELECTRICAL CHARACTERISTICS (Cont.) Boldface limits apply over the specified temperature range, TA = –5°C to +75°C. At TA = +25°C, VS = ±5V, RL = 10kΩ, unless otherwise noted. LOG104AID PARAMETER TOTAL Initial ERROR(4)(5) vs Temperature vs Supply CONDITION MIN MAX UNITS ±75 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±3.0 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.25 ±0.1 ±0.1 mV mV mV mV mV mV mV mV mV mV mV/ °C mV/ °C mV/ °C mV/ °C mV/ °C mV/ °C mV/ °C mV/ °C mV/ °C mV/ °C mV/ V mV/ V mV/ V mV/ V mV/ V mV/ V mV/ V mV/V mV/ V mV/ V CC = 4500pF CC = 150pF CC = 150pF CC = 50pF 0.1 38 40 45 kHz kHz kHz kHz CC = 150pF CC = 150pF CC = 150pF 11 7 110 µs µs µs CC = 150pF CC = 150pF CC = 150pF 45 20 550 µs µs µs I1 or I2 remains fixed while other varies. Min to Max I1 or I2 = 3.5mA I1 or I2 = 1mA I1 or I2 = 100µA I1 or I2 = 10µA I1 or I2 = 1µA I1 or I2 = 100nA I1 or I2 = 10nA I1 or I2 = 1nA I1 or I2 = 350pA I1 or I2 = 100pA I1 or I2 = 3.5mA I1 or I2 = 1mA I1 or I2 = 100µA I1 or I2 = 10µA I1 or I2 = 1µA I1 or I2 = 100nA I1 or I2 = 10nA I1 or I2 = 1nA I1 or I2 = 350pA I1 or I2 = 100pA I1 or I2 = 3.5mA I1 or I2 = 1mA I1 or I2 = 100µA I1 or I2 = 10µA I1 or I2 = 1µA I1 or I2 = 100nA I1 or I2 = 10nA I1 or I2 = 1nA I1 or I2 = 350pA I1 or I2 = 100pA FREQUENCY RESPONSE, CORE LOG(6) BW, 3dB I2 = 10nA I2 = 1µA I2 = 10µA I2 = 1mA Step Response Increasing I2 = 1µA to 1mA I2 = 100nA to 1µA I2 = 10nA to 100nA Decreasing I2 = 1mA to 1µA I2 = 1µA to 100nA I2 = 100nA to 10nA POWER SUPPLY Operating Range Quiescent Current VS IO = 0 TEMPERATURE RANGE Specified Range, TMIN to TMAX Operating Range Storage Range Thermal Resistance, θJA SO-8 TYP ±1.2 ±0.4 ±0.1 ±0.05 ±0.05 ±0.09 ±0.2 ±0.3 ±0.1 ±0.3 ±4.5 ±1 –5 –40 –55 ±18 ±1.5 V mA 75 85 125 °C °C °C °C/W 150 NOTES: (1) Log Conformity Error is peak deviation from the best-fit straight line of VOUT versus log (I1 / I2) curve expressed as a percent of peak-to-peak full-scale. (2) May require higher supply for full dynamic range. (3) Output core log function is trimmed to 0.5V output per decade change of input current. (4) Worst-case Total Error for any ratio of I1 /I2 is the largest of the two errors, when I1 and I2 are considered separately. (5) Total I1 + I2 should be kept below 4.5mA on ±5V supply. (6) Bandwidth (3dB) and transient response are a function of both the compensation capacitor and the level of input current. LOG104 SBOS243C www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±5V, RL = 10kΩ, unless otherwise noted. ONE CYCLE OF NORMALIZED TRANSFER FUNCTION NORMALIZED TRANSFER FUNCTION 2.0 VOUT = 0.5V LOG (I1/I2) Normalized Output Voltage (V) Normalized Output Voltage (V) 1.5 0.50 1.0 0.5 0.0 –0.5 –1.0 –1.5 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 –2.0 0.0001 0.001 0.01 0.1 1 10 100 1k 1 10k 2 Current Ratio, I1/I2 6 4 8 10 Current Ratio, I1/I2 TOTAL ERROR vs INPUT CURRENT 120 3 GAIN ERROR (I2 = 1µA) 5.8 +85°C 100 4.8 +75°C Gain Error (%) Total Error (mV) +75°C 80 60 40 +25°C 3.8 +25°C 2.8 –5°C to –40°C 1.8 –5°C 20 0.8 0 100pA 1nA 10nA 100nA 1µA –0.2 100pA 1nA 10µA 100µA 1mA 10mA 10nA 100nA 1µA Input Current (I1 or I2) 1M 10µA I1 = 100pA I1 = 1nA 100k CC (pF) 1M 3dB Frequency Response (Hz) 10M Select CC for I1 min. and I2 max. Values below 2pF may be ignored. I1 = 10nA 10k I1 = 100nA 1µA 1k 100 I1 = 10µA 100µA 1mA 10 1 100pA 1nA 10nA 100nA 1µA 100k 1k 100µA 100µA 1mA I1 = 1mA 1µA 10k 100µA CC =1 F 0p 100µA 1nA A 1µA 1mA to 10µA I1 = 1nA 10 1 1µ to µA 10 10nA 10nA 100 CC =1 00 0p 100nA 10nA F CC I1 = 1nA µF =1 0.1 10µA 100µA 1mA 10mA 100pA 1nA 10nA 100nA 1µA 10µA 100µA 1mA I2 I2 4 10mA 3dB FREQUENCY RESPONSE MINIMUM VALUE OF COMPENSATION CAPACITOR 100M 10µA 100µA 1mA Input Current (I1 or I2) LOG104 www.ti.com SBOS243C TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = ±5V, RL = 10kΩ, unless otherwise noted. LOG CONFORMITY vs INPUT CURRENT 17 15 7 Decades (100pA to 1mA) 300 13 Log Conformity (m%) Log Conformity (mV) LOG CONFORMITY vs TEMPERATURE 350 +85°C 11 9 7 +75°C 5 –40°C to +25°C 250 6 Decades (1nA to 1mA) 200 150 5 Decades (1nA to 100µA) 100 3 50 1 –1 100pA 1nA 10nA 100nA 1µA 10µA 100µA 0 –40 –30 –20 –10 0 1mA 10 20 30 40 50 60 70 80 90 Temperature (°C) Input Current (I1 or I2) APPLICATION INFORMATION INPUT CURRENT RANGE The LOG104 is a true logarithmic amplifier that uses the base-emitter voltage relationship of bipolar transistors to compute the logarithm, or logarithmic ratio of a current ratio. Figure 1 shows the basic connections required for operation of the LOG104. In order to reduce the influence of lead inductance of power-supply lines, it is recommended that each supply be bypassed with a 10µF tantalum capacitor in parallel with a 1000pF ceramic capacitor, as shown in Figure 1. Connecting the capacitors as close to the LOG104 as possible will contribute to noise reduction as well. On ±5V supplies, the total input current (I1 + I2) is limited to 4.5mA. Due to compliance issues internal to the LOG104, to accommodate larger total input currents, supplies should be increased. Currents smaller than 100pA will result in increased errors due the input bias currents of op amps A1 and A2 (typically 5pA). The input bias currents may be compensated for, as shown in Figure 2. The input stages of the amplifiers have FET inputs, with input bias current doubling every 10°C, which makes the nulling technique shown practical only where the temperature is fairly stable. V+ 10µF To maintain specified accuracy, the input current range of the LOG104 should be limited from 100pA to 3.5mA. Input currents outside of this range may compromise LOG104 performance. Input currents larger than 3.5mA result in increased nonlinearity. An absolute maximum input current rating of ±10mA is included to prevent excessive power dissipation that may damage the logging transistor. 1000pF 4 1 R2 10kΩ 6 3 LOG104 VOUT V– V+ R1 1MΩ 8 5 1 I1 I2 3 5 VOUT I1 CC LOG104 6 GND 8 10µF 1000pF I2 V– R1' > 1MΩ 4 CC V– FIGURE 1. Basic Connections of the LOG104. R2' 10kΩ V+ FIGURE 2. Bias Current Nulling. LOG104 SBOS243C www.ti.com 5 SETTING THE REFERENCE CURRENT V+ V+ When the LOG104 is used to compute logarithms, either I1 or I2 can be held constant and becomes the reference current to which the other is compared. I1 = 2.5nA to 1mA REF3025 4 2.5V 3 1 VOUT 1GΩ to 2.5kΩ VOUT is expressed as: LOG104 100kΩ I2 = 2.5nA VOUT = (0.5V) • log (I1/I2) 1MΩ (1) IREF can be derived from an external current source (such as shown in Figure 3), or it may be derived from a voltage source with one or more resistors. When a single resistor is used, the value may be large depending on IREF. If IREF is 10nA and +2.5V is used: 5 3 +2.5V CC 100Ω 6 GND V– OPA335 Chopper Op Amp –2.5V (2) RREF = 2.5V/10nA = 250M 8 +2.5mV FIGURE 5. Current Source with Offset Compensation. IREF 2N2905 at different levels of input signals. Smaller input currents require greater gain to maintain full dynamic range, and will slow the frequency response of the LOG104. RREF 3.6kΩ 2N2905 +15V –15V 6V IN834 IREF = FREQUENCY COMPENSATION 6V RREF FIGURE 3. Temperature Compensated Current Source. A voltage divider may be used to reduce the value of the resistor (as shown in Figure 4). When using this method, one must consider the possible errors caused by the amplifier’s input offset voltage. The input offset voltage of amplifier A1 has a maximum value of 1.5mV, making VREF a suggested value of 100mV. In an application, highest overall bandwidth can be achieved by detecting the signal level at VOUT, then switching in appropriate values of compensation capacitors. VREF = 100mV R1 R3 1 +5V R2 Frequency compensation for the LOG104 is obtained by connecting a capacitor between pins 3 and 8. The size of the capacitor is a function of the input currents, as shown in the Typical Characteristic Curves (Minimum Value of Compensation Capacitor). For any given application, the smallest value of the capacitor which may be used is determined by the maximum value of I2 and the minimum value of I1. Larger values of CC will make the LOG104 more stable, but will reduce the frequency response. VOS + – IREF NEGATIVE INPUT CURRENTS A1 The LOG104 will function only with positive input currents (conventional current flows into pins 1 and 8). In situations where negative input currents are needed, the circuits in Figures 6, 7, and 8 may be used. R3 >> R2 FIGURE 4. T Network for Reference Current. Figure 5 shows a low-level current source using a series resistor. The low offset op-amp reduces the effect of the LOG104’s input offset voltage. QA IIN QB National LM394 FREQUENCY RESPONSE The frequency response curves seen in the Typical Characteristics Curves are shown for constant DC I1 and I2 with a small-signal AC current on one input. D1 The 3dB frequency response of the LOG104 is a function of the magnitude of the input current levels and of the value of the frequency compensation capacitor. See Typical Characteristic Curve, 3dB Frequency Response for details. D2 OPA703 IOUT The transient response of the LOG104 is different for increasing and decreasing signals. This is due to the fact that a log amp is a nonlinear gain element and has different gains FIGURE 6. Current Inverter/Current Source. 6 LOG104 www.ti.com SBOS243C VOLTAGE INPUTS V+ The LOG104 gives the best performance with current inputs. Voltage inputs may be handled directly with series resistors, but the dynamic input range is limited to approximately three decades of input voltage by voltage noise and offsets. The transfer function of Equation (13) applies to this configuration. I1 VOUT LOG104 λ 1´ λ1 Light λ 1 Source TLV271 or 1 OPA2335 2 +3.3V(1) 3 D1 Sample I2 +5V 4 1 8 6 5 D2 1/2 OPA2335 CC 1.5kΩ V– 1.5kΩ +5V FIGURE 9. Absorbance Measurement. 10nA to 1mA (Back Bias 1/2 OPA2335 BSH203 OPERATION ON SINGLE SUPPLY +3.3V) 10nA to 1mA Pin 1 or Pin 8 LOG104 Many applications do not have the dual supplies required to operate the LOG104. Figure 10 shows the LOG104 configured for operation with a single +5V supply. Photodiode NOTE: (1) +3.3V bias is an arbitrary dc level < 5V that also appears on the −IN through the op amp where it applies a reverse bias to the photodiode. FIGURE 7. Precision Current Inverter/Current Source. Single Supply +5V 4 APPLICATION CIRCUITS 3 1 LOG RATIO I1 LOG104 One of the more common uses of log ratio amplifiers is to measure absorbance. A typical application is shown in Figure 9. Absorbance of the sample is A = logλ1´/ λ1 (3) If D1 and D2 are matched A ∝ (0.5V) logI1 / I2 (4) 6 8 5 I2 CC 1µF 3 2 DATA COMPRESSION In many applications the compressive effects of the logarithmic transfer function are useful. For example, a LOG104 preceding a 12-bit A/D converter can produce the dynamic range equivalent to a 20-bit converter. VOUT 5 TPS(1) 1µF 4 1 –5V 1µF (1) TPS60402DBV negative charge pump. FIGURE 10. Single +5V Power-Supply Operation. 1.5kΩ 100kΩ 100kΩ +5V 10nA to 1mA Back Bias +3.3V(1) +5V 1/2 OPA2335 1.5kΩ 1/2 OPA2335 Photodiode 1.5kΩ NOTE: (1) +3.3V bias is an arbitrary dc level < 5V that also appears on the −IN through the op amp where it applies a reverse bias to the photodiode. 100kΩ 100kΩ LOG104 10nA to 1mA Pin 1 or Pin 8 FIGURE 8. Precision Current Inverter/Current Source. LOG104 SBOS243C www.ti.com 7 INSIDE THE LOG104 also Using the base-emitter voltage relationship of matched bipolar transistors, the LOG104 establishes a logarithmic function of input current ratios. Beginning with the base-emitter voltage defined as: VBE = VT ln IC IS where : VT = kT q VOUT = VL VOUT = (1) k = Boltzmann’s constant = 1.381 • 10–23 (9) R1 + R 2 I n VT log 1 R1 I2 VOUT = 0.5V • log or T = Absolute temperature in degrees Kelvin R1 + R 2 R1 (10) I1 I2 (11) q = Electron charge = 1.602 • 10–19 Coulombs IC = Collector current IS = Reverse saturation current From the circuit in Figure 11, we see that: VL = VBE1 – VBE 2 Q1 I1 I1 IS1 – VT2 ln 1 2 A1 IS 2 I I VL = VT1 ln 1 – ln 2 I I S S I1 VL = VT ln and since I2 R2 VL R1 FIGURE 11. Simplified Model of a Log Amplifier. (4) (5) ln x = 2.3 log10 x (6) I VL = n VT log 1 I2 (7) where n = 2.3 (8) DEFINITION OF TERMS 3.5 TRANSFER FUNCTION 3.0 A 0p 10 I 2 = nA 1 I 2 = 0nA 1 = I2 2.5 The ideal transfer function is: 2.0 1.5 (5) See Figure 12 for the graphical representation of the transfer over valid operating range for the LOG104. 1.0 VOUT (V) VOUT = 0.5V • logI1/I2 I1 I2 I2 (3) If the transistors are matched and isothermal and VTI = VT2, then (3) becomes: 0.5 0.0 –0.5 –1.0 ACCURACY –1.5 Accuracy considerations for a log ratio amplifier are somewhat more complicated than for other amplifiers. This is because the transfer function is nonlinear and has two inputs, each of which can vary over a wide dynamic range. The accuracy for any combination of inputs is determined from the total error specification. 8 A2 VBE VOUT = (0.5V) LOG I2 VOUT + VBE Substituting (1) into (2) yields: VL = VT1 ln I2 Q2 – + I1 (2) – –2.0 –2.5 –3.0 100 pA 1nA 10n A 0n 10 I 2 = µA 1 I 2 = 0µA 1 = I 2 00µA 1 = I 2 mA 1 I 2= A 100 nA µA 1 10 µ A 100 µA 1m A 10m I1 A VOUT = (0.5V) • LOG (I1/I2) –3.5 FIGURE 13. Transfer Function with Varying I 2 and I1. LOG104 www.ti.com SBOS243C TOTAL ERROR MEASURING AVALANCHE PHOTODIODE CURRENT The total error is the deviation (expressed in mV) of the actual output from the ideal output of VOUT = 0.5V • log(I1/I2). The wide dynamic range of the LOG104 is useful for measuring avalanche photodiode current (APD), as shown in Figure 13. Thus, VOUT(ACTUAL) = VOUT(IDEAL) ± Total Error. (6) It represents the sum of all the individual components of error normally associated with the log amp when operated in the current input mode. The worst-case error for any given ratio of I1/I2 is the largest of the two errors when I1 and I2 are considered separately. Temperature can affect total error. ERRORS RTO AND RTI As with any transfer function, errors generated by the function itself may be Referred-to-Output (RTO) or Referred-toInput (RTI). In this respect, log amps have a unique property: Given some error voltage at the log amp’s output, that error corresponds to a constant percent of the input regardless of the actual input level. LOG CONFORMITY For the LOG104, log conformity is calculated the same as linearity and is plotted I1 /I2 on a semi-log scale. In many applications, log conformity is the most important specification. This is true because bias current errors are negligible (5pA compared to input currents of 100pA and above) and the scale factor and offset errors may be trimmed to zero or removed by system calibration. This leaves log conformity as the major source of error. Log conformity is defined as the peak deviation from the best fit straight line of the VOUT versus log (I1/I2) curve. This is expressed as a percent of ideal full-scale output. Thus, the nonlinearity error expressed in volts over m decades is: VOUT (NONLIN) = 0.5V/dec • 2Nm V (7) where N is the log conformity error, in percent. ISHUNT +15V to +60V 500Ω Irx = 1µA to 1mA Receiver 5kΩ 5kΩ 10Gbits/sec +5V APD INA168 SOT23-5 I to V Converter IOUT = 0.1 • ISHUNT 1 2 IOUT CC 1.2kΩ 1kΩ +5V 4 1 3 Q1 Q2 OPA703 VOUT = 2.5V to 0V A2 A1 100µA 25kΩ 8 REF3025 2.5V LOG104 SO-8 6 5 –5V FIGURE 14. High Side Shunt for Avalanche Photodiode (APD) Measures 3-Decades of APD Current. LOG104 SBOS243C www.ti.com 9 INDIVIDUAL ERROR COMPONENTS Example: what is the error when The ideal transfer function with current input is: VOUT = (0.5V) • log I1 I2 (8) VOUT = (0.5 ± 0.0015) log The actual transfer function with the major components of error is: VOUT = (0.5V) (1 ± ∆K ) log I1 – IB1 ± Nm ± VOS O I2 – IB 2 (9) (11) Since the ideal output is 0.5V, the error as a percent of reading is % error = 0.5055 • 100% = 1.1% 0.5 (12) For the case of voltage inputs, the actual transfer function is IB1 = bias current of A1 (5pA, typ) IB2 = bias current of A2 (5pA, typ) N = log conformity error (0.01%, 0.06%, typ) 10 −6 − 5 • 10 −12 ± (2)(0.0001)5 ± 3.0mV 10 −7 − 5 • 10 −12 = 0.5055V The individual component of error is: ∆K = gain accuracy (0.15%, typ), as specified in specification table. (10) I1 = 1µA and I2 = 100nA VOUT 0.01% for n = 5, 0.06% for n = 7.5 E OS1 V1 – IB1 ± R1 R1 = (0.5V) (1 ± ∆K ) log ± Nm ± VOSO E OS2 V2 – IB2 ± R2 R2 (13) VOSO = output offset voltage (3mV, typ) m = number of decades over which N is specified: Where EOS1 E and OS2 are considered to be zero for large R1 R2 values of resistance from external input current sources. 10 LOG104 www.ti.com SBOS243C PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LOG104AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LOG 104A LOG104AIDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LOG 104A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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