Texas Instruments | Wideband Fixed-Gain Amplifier (Rev. B) | Datasheet | Texas Instruments Wideband Fixed-Gain Amplifier (Rev. B) Datasheet

Texas Instruments Wideband Fixed-Gain Amplifier (Rev. B) Datasheet
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
WIDEBAND FIXED-GAIN AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fixed Closed-Loop Gain Amplifier
– 10 V/V (20 dB)
Wide Bandwidth: 1.8 GHz
High Slew Rate: 5500 V/µs
Low Total Input Referred Noise: 2.5 nV/√Hz
Low Distortion
– HD2: –65 dBc at 70 MHz
– HD3: –76 dBc at 70 MHz
– IMD3: –85 dBc at 100 MHz
– OIP3: 34 dBm at 100 MHz
– IMD3: –70 dBc at 300 MHz
– OIP3: 27 dBm at 300 MHz
High Output Drive: ±180 mA
Power Supply Voltage: 3 V or 5 V
Wideband Signal Processing
Wireless Transceivers
IF Amplifier
ADC Preamplifier
DAC Output Buffers
Test, Measurement, and Instrumentation
Medical and Industrial Imaging
DESCRIPTION
The THS4303 device is a wideband, fixed-gain amplifier that offers high bandwidth, high slew rate, low
noise, and low distortion. This combination of specifications enables analog designers to transcend current performance limitations and process analog signals at much higher speeds than previously possible
with closed-loop, complementary amplifier designs.
The devices are offered in a 16-pin leadless package
and incorporate a power-down mode for quiescent
power savings.
VS+
+
FB
22 µF
0.1 µF
47 pF
SMALL SIGNAL FREQUENCY RESPONSE
22
30.1 Ω
Rg
50 Ω Source
50 Ω Load
_
+
VI
THS4303
49.9 Ω
VO
49.9 Ω
VS−
20
Small Signal Gain − dB
Rf
18
16
14
12
RL = 100 Ω
VO = 100 mVPP
VS = 5 V
10
+
22 µF
FB
100 k
47 pF
0.1 µF
1M
10 M
100 M
1G
10 G
f − Frequency − Hz
30.1 Ω
FB = Ferrite Bead
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
VS
Supply voltage
6V
VI
Input voltage
±VS
IO
Output current
200 mA
Continuous power dissipation See Dissipation Rating Table
TJ( (2))
( (3))
Maximum junction temperature
150°C
TJ
Maximum junction temperature, continuous operation, longterm reliability
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
125°C
300°C
ESD ratings:
(1)
(2)
(3)
HBM
3000
CDM
1500
MM
200
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The THS4303 device may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which can permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
RGT PACKAGE
2
11
3
10
4
5
6
7
VOUT
NC = No connect
2
NC
V IN−
16 15 14 13
12
Rg
1
Rf
VS−
V IN+
PD
(TOP VIEW)
8
9
VS+
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
RECOMMENDED OPERATING CONDITIONS
(1)
Dual supply
Supply voltage, (VS+ and VS–)
MAX
±1.5
±2.5
3
5
VS–+1
VS+–1
Single supply
Input common-mode voltage range
(1)
MIN
UNIT
V
V
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. x 3 in. PCB. For further information, refer to
Application Information section of this data sheet.
PACKAGE DISSIPATION RATINGS
(1)
(2)
PACKAGE
ΘJC(°C/W)
ΘJA(°C/W)
RGT-16 (2)
2.4
39.5
POWER RATING (1)
TA≤ 25°C
TA =85°C
2.53 W
1.01 W
Power rating is determined with a junction temperature of 125°C. This is the point where distortion
starts to substantially increase. Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and long term reliability.
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. x 3 in. PCB.
For further information, refer to Application Information section of this data sheet.
AVAILABLE OPTIONS
PACKAGED DEVICES (1)
TA
LEADLESS
GAIN
–40°C to 85°C
(1)
RGT-16
THS4303RGTR
+10
THS4303RGTT
Packages are available taped and reeled. The R suffix standard quantity is 3000. The T suffix
standard quantity is 250.
INTERNAL FIXED RESISTOR VALUES
DEVICE
GAIN (V/V)
Rf
Rg
THS4303
+10
450
50
3
THS4303
www.ti.com
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS
THS4303 (Gain = +10 V/V) Specifications: VS = 5 V, RL = 100 Ω, (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
UNITS
MIN/
MAX
1.8
GHz
Typ
18
GHz
Typ
25°C
25°C
0°C to
70°C
–40°C to
85°C
AC PERFORMANCE
Small signal bandwidth
G = +10, VO = 200 mVRMS
Gain bandwidth product
Full-power bandwidth
G = +10, VO = 2 Vpp
Slew rate
G = +10, VO = 2 V Step
1.5
GHz
Typ
5500
V/µs
Min
RL = 100 Ω
–65
dBc
RL = 1 k Ω
–75
dBc
RL = 100 Ω
–76
dBc
RL = 1 kΩ
–80
dBc
Harmonic distortion
Second harmonic distortion
G = +10, VO = 1 VPP,
f = 70 MHz
Third harmonic distortion
Typ
Typ
Third order intermoduation
(IMD3)
VO = 1 VPP envelope,
200 kHz tone spacing
fc= 100 MHz
–85
dBc
fc = 300 MHz
–70
dBc
Third order output intercept
(OIP3)
VO = 1 VPP,
200 kHz tone spacing
fc = 100 MHz
34
dBm
fc = 300 MHz
27
dBm
Total input referred noise
f = 1 MHz
2.5
nV/√Hz
Typ
Noise figure
f = 100 MHz
16
dB
Typ
Typ
Typ
DC PERFORMANCE
Voltage gain
VI = ±50 mV, VCM = 2.5 V
Input offset voltage
Average offset voltage drift
Input bias current
VCM = 2.5 V
9.9
9.8
9.8
9.8
V/V
Min
9.9
10
10
10
V/V
Max
1.5
4.25
5.25
5.25
mV
Max
±20
±20
µV/°C
Typ
7
10
13
15
µA
Max
±55
±55
nA/°C
Typ
Min
Average bias current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
VCM = 2 V to 3 V
Noninverting input impedance
1/4
1.1 / 3.9
1.2 / 3.8
1.2 / 3.8
V
60
52
50
50
dB
Min
MΩ pF
Typ
1.6
1
OUTPUT CHARACTERISTICS
Output voltage swing
1/4
1.1 / 3.9
1.2 / 3.8
1.2 / 3.8
V
Min
180
170
165
160
mA
Min
RL = 5 Ω
180
170
165
160
mA
Min
f = 10 MHz
0.08
Ω
Typ
Output current (sourcing)
RL = 5 Ω
Output current (sinking)
Output impedance
POWER SUPPLY
Specified operating voltage
5
5.5
5.5
5.5
V
Max
Maximum quiescent current
34
41
46
48
mA
Max
Minimum quiescent current
34
27
25
23
mA
Min
Power supply rejection (PSRR +) VS+ = 5 V to 4.5 V, VS– = 0 V
63
54
52
51
dB
Min
Power supply rejection (PSRR –) VS+ = 5 V, VS– = 0 V to 0.5 V
65
58
56
54
dB
Min
4
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS (continued)
THS4303 (Gain = +10 V/V) Specifications: VS = 5 V, RL = 100 Ω, (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
–40°C to
85°C
UNITS
MIN/
MAX
mA
Max
POWER-DOWN CHARACTERISTICS
Maximum power-down current
0.9
1.2
Power-on voltage threshold
PD = 0 V
1.1
1.5
1.3
1.4
V
Min
Power-down voltage threshold
1.1
0.9
V
Max
Turnon time delay [t(ON)]
90% of final value
42
ns
Typ
Turnoff time delay [t(Off)]
10% of final value
35
ns
Typ
100
kΩ
Typ
470
Ω
Typ
Input impedance
Output impedance
f = 100 kHz
SCHEMATIC DIAGRAM
Input Stage
Gain Stage
Output Stage
VCC
I24
I25
R13
I30
R17
I29
D7
D10
Q56
Q55
Q53
Q51
Q65
Q61
Q60
Q64
IN_POS
R14
OUT
Q54
Q52
Q58
Q57
D9
C3
Q63
Q66
Q59
Q62
I28
D8
I26
I31
I27
R15
R16
VEE
VCC
D13
R19
R18
IN_NEG
D14
VEE
5
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS (5 V)
FIGURE
S-parameter vs Frequency
1
Small signal frequency response
2
Large signal frequency response
3
Slew rate vs Output voltage
4
Harmonic distortion vs Frequency
5, 6
Harmonic distortion vs Output voltage swing
7
Second order intermodulation distortion vs Frequency
8
Third order intermodulation distortion vs Frequency
9
Second order intercept point vs Frequency
10
Third order intercept point vs Frequency
11
Voltage and current noise vs Frequency
12
Settling time
13, 14
Quiescent current vs Supply voltage
15
Output voltage vs Load resistance
16
Capacitive load frequency response
17
Gain vs Case temperature
18
Rejection ratio vs vs Frequency
19
Rejection ratios vs Case temperature
20
Common-mode rejection ratio vs Input common-mode range
21
Input offset voltage vs Case temperature
22
Positive input bias current vs Case temperature
23
Small signal transient response
24
Large signal transient response
25
Overdrive recovery
26
Closed-loop output impedance vs Frequency
27
Power-down quiescent current vs Supply voltage
28
Power-down S-parameter vs Frequency
29
Power-down output impedance vs Frequency
30
Turnon and turnoff delay times
31
TABLE OF GRAPHS (3 V)
FIGURE
S-parameter vs Frequency
32
Small signal frequency response
33
Large signal frequency response
34
Harmonic distortion vs Frequency
35
Slew rate vs Output voltage
36
Capacitive load frequency response
37
Gain vs Case temperature
38
Input offset voltage vs Case temperature
39
Positive input bias current vs Case temperature
40
Overdrive recovery
41
Power-down S-parameter vs Frequency
42
6
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL TEST DATA
S-Parameter (Measured using standard THS4303EVM, edge number 6454762, with VS = 5 V in a 50 Ω test system)
Frequency
(MHz)
S11 (dB)
S11 (Ang)
S21 (dB)
S21 (Ang)
1
–50.68359
–9.936035
20.07422
1.007886
2
–50.80664
–3.452515
20.08398
2.060587
10
–51.10547
–38.07227
20.02734
10.158346
50
–37.71289
–76.30078
20.08252
50.078859
100
–34.61719
–109.6055
20.29541
150
–31.50684
–105.7422
200
–29.81348
–105.3516
250
–29.20801
300
S12 (dB)
S12 (Ang)
S22 (dB)
S22 (Ang)
–75.9375
74.27344
–52.6047
–9.367676
–77.44531
–30.31445
–51.9668
8.862793
–80.94922
53.79102
–47.64258
42.5957
–63.52539
–72.41406
–59.52539
–91.70703
102.38457
–57.58594
74.66016
–30.39063
125.332
20.40576
150.47685
–52.71875
18.20898
–24.91895
102.4297
20.44922
198.11759
–53.94141
53.86523
–22.96484
89.09766
–129.6016
20.43213
246.87998
–52.35938
40.63672
–22.02344
79.55469
–26.57422
–100.0703
20.40088
307.6446
–54.19336
81.05859
–21.18359
73.59766
350
–25.90137
–102.1328
20.34033
362.84524
–53.47266
–38.93164
–20.597766
71.20313
400
–24.89551
–111.4609
20.2959
405.04485
–54.37109
12.90479
–20.03906
71.91797
450
–24.7002
–76.46094
20.22754
452.15154
–53.91797
14.76416
–19.84668
74.58203
500
–25.76758
–95.54688
20.16406
504.73809
–55.60156
34.66016
–19.11621
73.60547
550
–24.86231
–98.39844
20.05273
563.4396
–57.78125
–114.1016
–18.54688
78.37109
600
–23.49805
–106.6992
19.97656
595.30346
–61.00977
–60.50586
–18.15332
76.28125
700
–21.07422
–84.68359
19.76318
702.11941
–64.83984
–67.44531
–17.24609
79.64063
800
–19.82617
–86.29688
19.60352
828.09966
–72.0625
72.92578
–15.36182
84.96875
900
–18.98828
–86.40625
19.44287
924.40782
–61.43359
172.7109
–14.03223
87.03125
1000
–17.16211
–82.15234
19.24219
1031.9205
–54.25391
165.2578
–12.65723
87.64844
1250
–14.66065
–83.30469
18.59424
1285.9052
–46.52148
163.7813
–10.12158
81.31641
1500
–12.67529
–90.48438
17.96533
1516.6333
–41.23242
159.5156
–8.850586
79.875
1750
–11.51025
–104.2656
17.229
1788.7621
–37.59766
145.8125
–7.762695
76.54688
2000
–10.52832
–106.4531
16.30127
1996.8001
–35.54688
154.1719
–7.215088
76.26953
7
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL THS4303 CHARACTERISTICS (5 V)
S-PARAMETER
vs
FREQUENCY
SMALL SIGNAL
FREQUENCY RESPONSE
22
40
VS = 5 V
20
0
S22
−20
S11
−40
−60
18
16
14
RL = 100 Ω
VO = 100 mVPP
VS = 5 V
S12
12
−80
1M
10 M
100 M
1G
10 G
100 k
1M
−55
10 M
100 M
1G
0
10 G
100 k
Rise
3000
2000
0.5
1
1.5
2
VO − Output Voltage − VPP
−55
RL = 100 Ω
VS = 5 V
−60
Harmonic Distortion − dBc
1M
10 M
100 M
f − Frequency − Hz
1G
HD3, VO = 2 VPP
−65
HD2, VO = 2 VPP
−70
−75
−80
HD3,
VO = 1 VPP
−85
HD2,
VO = 1 VPP
−90
−70
−75
−85
−90
−100
−100
10
f − Frequency − MHz
HD2, VO = 2 VPP
−80
−95
1
HD3, VO = 2 VPP
−65
−95
2.5
10 G
RL = 1 kΩ
VS = 5 V
−60
100
HD2, VO = 1 VPP
HD3, VO = 1 VPP
1
10
f − Frequency − MHz
100
Figure 6.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
SECOND-ORDER
INTERMODULATION DISTORTION
vs
FREQUENCY
THIRD-ORDER
INTERMODULATION DISTORTION
vs
FREQUENCY
HD2, f = 64 MHz
−70
−80
−90
HD2, f = 8 MHz
HD3, f = 8 MHz
0.5
1
1.5
2
2.5
IMD
VO − Output Voltage Swing − VPP
Figure 7.
−50
−55
−60
VO = 2 VPP
Envelope
−65
VO = 1 VPP
Envelope
−70
−75
−80
RL = 100 Ω
VS = 5 V
200 kHz Tone Spacing
−85
−90
10 M
100 M
−50
−55
−60
VO = 2 VPP
−65
Envelope
−70
−75
VO = 1 VPP
Envelpoe
−80
−85
RL = 100 Ω
VS = 5 V
200 kHz Tone Spacing
−90
−95
−100
3
HD3, f = 64 MHz
2
RL = 100 Ω
VS = 5 V
− Third-Order Intermodulation Distortion − dBc
Figure 5.
− Second-Order Intermodulation Distortion − dBc
Figure 4.
1G
IMD
SR − Slew Rate − V/ µ s
2
HARMONIC DISTORTION
vs
FREQUENCY
0
Harmonic Distortion − dBc
RL = 100 Ω
VO = 2 VPP
VS = 5 V
4
HARMONIC DISTORTION
vs
FREQUENCY
1000
8
6
SLEW RATE
vs
OUTPUT VOLTAGE
Fall
0
8
Figure 3.
4000
−60
10
Figure 2.
5000
−50
12
Figure 1.
RL = 100 Ω
VS = 5 V
−40
14
f − Frequency − Hz
7000
0
16
10
f − Frequency − Hz
6000
18
Harmonic Distortion − dBc
−100
100 k
Large Signal Response − dB
20
Small Signal Gain − dB
S-Parameter − dB
22
S21
20
−100
LARGE SIGNAL
FREQUENCY RESPONSE
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
Figure 8.
Figure 9.
1G
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL THS4303 CHARACTERISTICS (5 V) (continued)
THIRD-ORDER OUTPUT INTERCEPT
vs
FREQUENCY
70
49.9
−2.5V
65
Note: Add 3 dB to Reference Data to
The Output of the Amplifier.
60
55
50
VO = 1 VPP Envelope
RL = 100 Ω
VS = 5 V
200 kHz Tone Spacing
45
40
0
50
100
150
200
250
300
f − Frequency − MHz
41
−2.5V
35
Note: Add 3 dB to Reference Data to
The Output of the Amplifier.
33
31
VO = 1 VPP Envelope
RL = 100 Ω
VS = 5 V
200 kHz Tone Spacing
29
27
25
50
100
VO− Output Voltage − VPP
0.2
0
−0.2
−0.4
−0.6
−1
0
1
2
3
4
5
6
7
8
100
9
1k
100 k
1M
Figure 12.
SETTLING TIME
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
0.2
0
−0.2
Output
40
TA = −40°C
30
25
20
15
10
0
8
9
3.25 3.5 3.75 4 4.25 4.5 4.75 5
Figure 13.
Figure 14.
Figure 15.
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
CAPACITIVE LOAD FREQUENCY
RESPONSE
GAIN
vs
CASE TEMPERATURE
22
7
2.5 2.75 3
t − Time − ns
3
4
5 6
t − Time − ns
VS = 5 V
TA = −40 to 85°C
2
TA = 25°C
35
5
Input Pulse x 10
1
TA = 85°C
45
0.4
−0.4
VS − Supply Voltage − V
20.1
RL = 100 Ω
VS = 5 V
20.08
20
20.06
RISO = 25 Ω, CL = 10 pF
Signal Gain − dB
3.5
3
2.5
2
1.5
1
18
RISO = 15 Ω, CL = 47 pF
16
RISO= 10 Ω, CL = 100 pF
14
RISO
−
+
12
10 M
50
0.6
0
10 k
f − Frequency − Hz
−1
4
VO − Output Voltage − V
300
Figure 11.
−0.8
5
4.5
250
−0.6
RL = 100 Ω
VS = 5 V
−0.8
200
Closed-Loop Gain − dB
VO − Output Voltage − V
Input Pulse x 10
0.4
150
RL = 100 Ω
VS = 5 V
0.8
0.6
Vn
f − Frequency − MHz
1
Output
In
10
1
0
SETTLING TIME
0.8
49.9
37
Figure 10.
1
50 Test
Equipment
THS4303
49.9
39
Hz
50 Test
Equipment
49.9
Hz
49.9
THS4303
49.9
100
Test data
measurement
point
+2.5V
50 Source
I n − Current Noise − pA/
75
43
V n − Voltage Noise − nV/
Test data
measurement
point
+2.5V
50 Source
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
Quiescent Current − mA
80
OIP3 − Third−Order Output Intercept Point − dBm
OIP 2 − Second-Order Output Intercept Point − dBm
SECOND-ORDER
OUTPUT INTERCEPT
vs
FREQUENCY
CL
0.5
20.04
VS = 5 V
20.02
20
19.98
19.96
19.94
19.92
10
0
1
19.9
RL − Load Resistance − Ω
f − Frequency − Hz
−40−30−20−100 10 20 30 40 50 60 70 80 90
TC − Case Temperature − °C
Figure 16.
Figure 17.
Figure 18.
10
100
1000
1M
10 M
100 M
1G
9
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL THS4303 CHARACTERISTICS (5 V) (continued)
REJECTION RATIOS
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
75
70
VS = 5 V
70
PSRR+
60
CMMR
Rejection Ratios − dB
50
CMRR
40
30
20
65
60
PSRR+
55
50
45
10
VS = 5 V
0
100 k
1M
10 M
100 M
f − Frequency − Hz
40
−40−30 −20−10 0 10 20 30 40 50 60 70 80 90
1G
TC − Case Temperature − °C
50
40
30
20
10
VS = 5 V
0
−10
0
1
2
3
4
5
VICR − Input Common-Mode Voltage Range − V
Figure 20.
Figure 21.
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
POSITIVE INPUT BIAS CURRENT
vs
CASE TEMPERATURE
SMALL-SIGNAL
TRANSIENT RESPONSE
14
2.5
2
VS = 5 V
1.5
1
0.5
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
0.15
12
VO − Output Voltage − V
I IB+ − Positive Input Bias Current − µ A
VOS − Input Offset Voltage − mV
60
Figure 19.
3
10
VS = 5V
8
6
4
0.05
0
RL = 100 Ω
Input tr/tf = 60 ps
VS = 5 V
−0.05
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
−0.1
0
TC − Case Temperature − °C
Figure 22.
Figure 23.
0.25
VS = 5 V
2
V O − Output Voltage − V
1
0.2
0.15
1.5
0.1
1
0.05
0.5
0
0
−0.05
−0.5
−1
−1
−0.1
−0.15
−1.5
RL = 100 Ω
Input tr/tf = 60 ps
VS = 5 V
−2
−0.2
−0.25
−2.5
−1.5
−3
0
2
4
6
t − Time − ns
Figure 25.
8
10
12
8
0.3
2.5
−0.5
6
OVERDRIVE RECOVERY TIME
3
0
4
Figure 24.
1.5
0.5
2
t − Time − ns
LARGE-SIGNAL TRANSIENT RESPONSE
VO − Output Voltage − V
0.1
2
TC − Case Temperature − °C
10
70
0
−0.3
100 200 300 400 500 600 700 800 900 1000
t − Time − ns
Figure 26.
VI − Input Voltage − V
Rejection Ratios − dB
PSRR−
CMRR − Common-Mode Rejection Ratio − dB
REJECTION RATIO
vs
FREQUENCY
10
12
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL THS4303 CHARACTERISTICS (5 V) (continued)
POWER-DOWN
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
0.1
1M
10 M
100 M
1G
1000
900
10
S22
0
TA = 85°C
TA = 25°C
800
TA = −40°C
700
600
500
400
300
200
f − Frequency − Hz
S11
−30
−40
−50
−60
−70
S12
−90
100 k
VS − Supply Voltage − V
Figure 27.
10 M
1M
I O − Output Current Level − mA
2
RL = 100 Ω
VS = 5 V
1
0.5
Input
0
1M
−0.5
−1
Output
−2
−1.5
−2.5
f − Frequency − Hz
Figure 30.
100 M
1G
1
0
−1
−1.5
10 M
1.5
0.5
−0.5
100 k
10 G
TURN-ON AND TURN-OFF TIMES DELAY TIME
1.5
RL = 100 Ω
VO = 200 mV
VS = 5 V
1G
Figure 29.
1000
100
100 M
f − Frequency − Hz
Figure 28.
POWER-DOWN OUTPUT IMPEDANCE
vs
FREQUENCY
10
VS = 5 V
−20
−80
100
0
2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5
10 G
−10
V I − Input Voltage Level − V
1
1100
Power-Down S-Parameter − dB
10
0.01
100 k
POWER-DOWN S-PARAMETER
vs
FREQUENCY
1200
RL = 100 Ω
VO = 200 mV
VS = 5 V
Power-Down Quiescent Current − µ A
100
Powerdown Output Impedance − Ω
ZO − Closed-Loop Output Impedance − Ω
CLOSED-LOOP
OUTPUT IMPEDANCE
vs
FREQUENCY
0
−2
100 200 300 400 500 600 700 800
t − Time − ns
Figure 31.
11
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL THS4303 CHARACTERISTICS (3 V)
S-PARAMETER
vs
FREQUENCY
SMALL SIGNAL
FREQUENCY RESPONSE
40
S21
20
20
20
0
S22
−20
S11
−40
−60
S12
18
18
16
14
RL = 100 Ω
VO = 100 VPP
VS = 3 V
12
−80
1M
10 M
100 M
1G
1M
10 M
100 M
f − Frequency − Hz
1G
1M
10 M
100 M
f − Frequency − Hz
1G
HARMONIC DISTORTION
vs
FREQUENCY
SLEW RATE
vs
OUTPUT VOLTAGE
CAPACITIVE LOAD
FREQUENCY RESPONSE
2000
SR − Slew Rate − V/ µ s
HD2, RL = 100 Ω
−60
HD2,
RL = 1 kΩ
−70
22
RL = 100 Ω
VS = 3 V
1800
Fall
1400
1200
Rise
1000
800
600
400
0
10
f − Frequency − MHz
RISO = 25 Ω, CL = 10 pF
RISO = 15 Ω, CL = 47 pF
18
RISO = 10 Ω, CL = 100 pF
16
14
RL = 100 Ω
VS = 3 V
100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
RISO
−
+
12
200
−90
10 G
20
1600
HD3, RL = 1 kΩ
CL
10
0.8
10 M
1M
VO − Output Voltage −V
100 M
1G
f − Frequency − Hz
Figure 35.
Figure 36.
Figure 37.
GAIN
vs
CASE TEMPERATURE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
POSITIVE INPUT BIAS CURRENT
vs
CASE TEMPERATURE
1.5
14
20.04
VS = 3 V
20
19.98
19.96
19.94
19.92
19.9
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 38.
VOS − Input Offset Voltage − mV
20.06
1.25
1
VS = 3 V
0.75
0.5
0.25
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
TC − Case Temperature − °C
Figure 39.
I IB − Posaitive Input Bias Current − µ A
20.08
Closed-Loop Gain − dB
RL = 100 Ω
VO = 1 VPP
VS = 3 V
100 k
10 G
−80
12
6
Figure 34.
HD3 RL = 100 Ω
20.02
8
Figure 33.
−50
1
10
Figure 32.
VO = 0.5 VPP
VS = 3 V
−40
12
0
100 k
f − Frequency − Hz
−30
14
2
10
10 G
16
4
Signal Gain − dB
−100
100 k
Large Signal Gain − dB
Small Signal Gain − dB
S-Parameter − dB
22
22
VS = 3 V
Harmonic Distortion − dBc
LARGE SIGNAL
FREQUENCY RESPONSE
VS = 3 V
12
10
8
6
4
2
0
−40−30−20−10 0
10 20 30 40 50 60 70 80 90
TC − Case Temperature − °C
Figure 40.
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
TYPICAL THS4303 CHARACTERISTICS (3 V) (continued)
POWER-DOWN S-PARAMETER
vs
FREQUENCY
OVERDRIVE RECOVERY TIME
VS = 3 V
10
0.15
0
S22
0.1
1
0.5
0.05
0
0
−0.5
−0.05
−1
−0.1
−1.5
−0.15
−2
0
−0.2
100 200 300 400 500 600 700 800 900 1000
t − Time − ns
Figure 41.
VI − Input Voltage − V
VO − Output Voltage − V
1.5
0.2
Power-Down S-Parameter − dB
2
−10
VS = 3 V
−20
S11
−30
−40
−50
−60
−70
S12
−80
−90
100 k
1M
10 M
100 M
1G
10 G
f − Frequency − Hz
Figure 42.
13
THS4303
www.ti.com
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
APPLICATION INFORMATION
HIGH-SPEED OPERATIONAL AMPLIFIERS
The THS4303 fixed gain operational amplifier set new
performance levels, combining low distortion, high
slew rates, low noise, and a gain bandwidth in excess
of 1.8 GHz. To achieve the full performance of the
amplifier, careful attention must be paid to
printed-circuit board layout and component selection.
equipment, provides a 100-Ω load. The total 100-Ω
load at the output, combined with the 500-Ω total
feedback network load, presents the THS4303 with
an effective output load of 83 Ω for the circuit of
Figure 43.
INTERNAL FIXED RESISTOR VALUES
In addition, the devices provide a power-down mode
with the ability to save power when the amplifier is
inactive.
APPLICATIONS SECTION CONTENTS
• Wideband, Noninverting Operation
• Single Supply Operation
• Saving Power With Power-Down Functionality
• Driving an ADC With the THS4303
• Driving Capacitive Loads
• Power Supply Decoupling Techniques and Recommendations
• Board Layout
• Printed-Circuit Board Layout Techniques for Optimal Performance
• PowerPAD Design Considerations
• PowerPAD PCB Layout Considerations
• Thermal Analysis
• Design Tools
• Evaluation Fixtures and Application Support Information
• Additional Reference Material
• Mechanical Package Drawings
WIDEBAND, NONINVERTING OPERATION
The THS4303 is a fixed gain voltage feedback
operational amplifier, with power-down capability, designed to operate from a single 3-V to 5-V power
supply.
Figure 43 is the noninverting gain configuration used
to demonstrate the typical performance curves. Most
of the curves were characterized using signal sources
with 50-Ω source impedance, and with measurement
equipment presenting a 50-Ω load impedance. In
Figure 43, the 49.9-Ω shunt resistor at the VIN
terminal matches the source impedance of the test
generator. The 50-Ω series resistor at the VO terminal
in addition to the 50-Ω load impedance of the test
14
DEVICE
GAIN (V/V)
Rf
Rg
THS4303
+10
450
50
VS+
+
FB
22 µF
0.1 µF
47 pF
30.1 Ω
Rf
Rg
50 Ω Source
50 Ω Load
_
+
VI
THS4303
49.9 Ω
VO
49.9 Ω
VS−
+
22 µF
FB
47 pF
0.1 µF
30.1 Ω
FB = Ferrite Bead
Figure 43. Wideband, Noninverting
Gain Configuration
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
SINGLE SUPPLY OPERATION
The THS4303 is designed to operate from a single
3-V to 5-V power supply. When operating from a
single power supply, care must be taken to ensure
the input signal and amplifier are biased appropriately
to allow for the maximum output voltage swing. The
circuits shown in Figure 44 demonstrate methods to
configure an amplifier in a manner conducive for
single supply operation.
VS+
+
FB
22 µF
47 pF
0.1 µF
Rg
*2.5 V
VI
_
+
THS4303
50 Ω Load
The THS4303 amplifier can be used to drive
high-performance analog-to-digital converters. Two
example circuits are presented below.
49.9 Ω
VO
*2.5 V
FB = Ferrite Bead
* = Low Impedance
Figure 44. DC-Coupled Single Supply Operation
WITH
APPLICATION CIRCUITS
DRIVING AN ANALOG-TO-DIGITAL CONVERTER
WITH THE THS4303
49.9 Ω
SAVING
POWER
FUNCTIONALITY
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
30.1 Ω
Rf
50 Ω Source
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
POWER-DOWN
The first circuit uses a wideband transformer to
convert a single-ended input signal into a differential
signal. The amplified signal from the output of the
THS4303 is fed through a low-pass filter, via an
isolation resistor and an ac-coupling capacitor, to the
transformer.
For applications without signal content at dc, this
method of driving ADCs is very useful. Where dc
information content is required, the THS4500 family
of fully differential amplifiers may be applicable.
VS+
The THS4303 features a power-down pin (PD) which
lowers the quiescent current from 34 mA down to 1
mA, ideal for reducing system power.
The power-down pin of the amplifier defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
Enable Threshold Voltage, the device is on. Below
the Disable Threshold Voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high- impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
+
FB
22 µF
0.1 µF
47 pF
30.1 Ω
Rf
Rg
50 Ω Source
_
+
*2.5 V
VI
THS4303
49.9 Ω
*2.5 V
RISO
C
R
IN
ADC
FB = Ferrite Bead
* = Low Impedance
R
IN CM
Figure 45. Driving an ADC Via a Transformer
15
THS4303
www.ti.com
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
The second circuit depicts single-ended ADC drive.
While not recommended for optimum performance
using converters with differential inputs, satisfactory
performance can sometimes be achieved with singleended input drive. An example circuit is shown here
for reference.
VS+
+
FB
22 µF
0.1 µF
47 pF
30.1 Ω
Rf
Rg
50 Ω Source
_
+
*2.5 V
VI
THS4303
sponse flatness, pulse response fidelity, or distortion,
the simplest and most effective solution is to isolate
the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4303. Long PC board traces,
unmatched cables, and connections to multiple devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4303 output pin (see Board Layout
Guidelines).
The criterion for setting this R(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load.
49.9 Ω
*2.5 V
FB = Ferrite Bead
* = Low Impedance
22
RISO
C
RL = 100 Ω
VS = 5 V
20
RISO = 25 Ω, CL = 10 pF
C
CM
IN
R
ADC
C
Figure 46. Driving an ADC With a Single-Ended
Input
Signal Gain − dB
IN
18
RISO = 15 Ω, CL = 47 pF
16
RISO= 10 Ω, CL = 100 pF
14
RISO
−
+
12
CL
10
1M
10 M
100 M
1G
f − Frequency − Hz
NOTE:
For best performance,
high-speed ADCs should
be driven differentially.
See the THS4500 family
of devices for more information.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
High-speed amplifiers like the THS4303 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
directly on the output pin. When the amplifier's
open-loop output resistance is considered, this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin.
When the primary considerations are frequency re-
16
Figure 47. Driving Capacitive Loads
POWER SUPPLY DECOUPLING TECHNIQUES
AND RECOMMENDATIONS
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of performance.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply. Inductance in series
with the bypass capacitors will degrade performance. Note that a narrow lead or trace has about
0.8 nH of inductance for every millimeter of
length. Each printed-circuit board (PCB) via also
has between 0.3 and 0.8 nH depending on length
and diameter. For these reasons, it is recommended to use a power supply trace about the
width of the package for each power supply lead
THS4303
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SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
to the caps, and 3 or more vias to connect the
caps to the ground plane.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Solid power planes can lead to PCB resonances
when they are not properly terminated to the
ground plane over the area and along the perimeter of the power plane by high frequency
capacitors. Doing so assures that there are no
power plane resonances in the needed frequency
range. Values used are in the range of 2 pF - 50
pF, depending on the frequencies to be suppressed, with numerous vias for each.
4. Using 0402 or smaller component sizes is recommended. An approximate expression for the
resonate frequencies associated with a length of
one of the power plane dimensions is given in
equation (1). Note that a power plane of arbitrary
shape can have a number of resonant frequencies. A power plane without distributed capacitors and with active parts near the center of
the plane usually has n even (≥2) due to the half
wave resonant nature of the plane.
frequency res n (44 GHz mm)
where:
frequencyres = the approximate power plane resonant
frequencies in GHz
= the length of the power plane dimensions in
millimeters
n = an integer (n > 1) related to the mode of the oscillation
•
For guidance on capacitor spacing over the area
of the ground plane, specify the lowest resonant
frequency to be tolerated, then solve for in
equation (1) above, with n = 2. Use this length for
the capacitor spacing. It is recommended that a
power plane, if used, be either small enough, or
decoupled as described, so that there are no
resonances in the frequency range of interest. An
alternative is to use a ferrite bead outside of the
opamp high frequency bypass caps to decouple
the amplifier, and mid and high frequency bypass
capacitors, from the power plane. When a trace is
used to deliver power, its self-resonance is given
approximately by equation (1), substituting the
trace length for power plane dimension.
1. Bypass capacitors, since they have a
self-inductance, resonate with each other. To
achieve optimum transfer characteristics through
2 GHz, it is recommended that the bypass
arrangement employed in the prototype board be
used. The 30.1-Ω resistor in series with the
0.1-µF capacitor reduces the Q of the resonance
of the lumped parallel elements including the
0.1-µF and 47-pF capacitors, and the power
supply input of the amplifier. The ferrite bead
isolates the low frequency 22-µF capacitor and
power plane from the remainder of the bypass
network.
2. By removing the 30.1-Ω resistor and ferrite bead,
the frequency response characteristic above 400
MHz may be modified. However, bandwidth, distortion, and transient response remain optimal.
3. Recommended values for power supply decoupling include a bulk decoupling capacitor (22 µF),
a ferrite bead with a high self-resonant frequency,
a mid-range decoupling capacitor (0.1 µF) in
series with a 30.1-Ω resistor, and a high frequency decoupling capacitor (47 pF).
BOARD LAYOUT
Printed-Circuit Board Layout Techniques for Optimal Performance
Achieving optimum performance with a high frequency amplifier like the THS4303 requires careful
attention to board layout parasitics and external
component types.
Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. However,
if using a transmission line at the I/O, then place
the matching resistor as close to the part as
possible. Except for when transmission lines are
used, parasitic capacitance on the output and the
noninverting input pins can react with the load
and source impedances to cause unintentional
band limiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be
opened in all of the ground and power planes
around those pins. Otherwise, ground planes and
power planes (if used) should be unbroken elsewhere on the board, and terminated as described
in the Power Supply Decoupling section.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. Note that each millimeter of a line,
that is narrow relative to its length, has ~ 0.8 nH
of inductance. The power supply connections
should always be decoupled with the recommended capacitors. If not properly decoupled,
distortion performance is degraded. Larger
(6.8-µF to 22-µF) decoupling capacitors, effective
at lower frequency, should also be used on the
main supply lines, preferably decoupled from the
amplifier and mid and high frequency capacitors
by a ferrite bead. Reference the Power Supply
Decoupling Techniques section. The larger caps
may be placed somewhat farther from the device
17
THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
and may be shared among several devices in the
same area of the PC board. A very low inductance path should be used to connect the inverting pin of the amplifier to ground. A minimum
of 5 vias as close to the part as possible is
recommended.
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4303. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Axially-leaded parts do not provide good
high frequency performance, since they have ~
0.8 nH of inductance for every mm of current
path length. Again, keep PC board trace length
as short as possible. Never use wirewound type
resistors in a high frequency application. Since
the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position
the terminating resistors, if any, as close as
possible to the noninverting and output pins.
Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor
values can create significant time constants that
can degrade performance. Good axial metal-film
or surface-mount resistors have approximately
0.2 pF in shunt with the resistor.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set RISO from the
plot of recommended RISO vs Capacitive Load.
Low parasitic capacitive loads (<4 pF) may not
need an RISO since the THS4303 is nominally
compensated to operate with a 2 pF parasitic
load. Higher parasitic capacitive loads without an
RISO are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6 dB signal loss
intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). With a
characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the
output of the THS4303 is used as well as a
terminating shunt resistor at the input of the
destination device. Remember also that the terminating impedance is the parallel combination of
the shunt resistor and the input impedance of the
18
www.ti.com
destination device: this total effective impedance
should be set to match the trace impedance. If
the 6 dB attenuation of a doubly terminated
transmission line is unacceptable, a long trace
can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the
plot of RISO vs Capacitive Load. This does not
preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
A 50-Ω environment is normally not necessary on
board as long as the lead lengths are short, and
in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. Uncontrolled impedance traces
without double termination results in reflections at
each end, and hence, produces PCB resonances.
It is recommended that if this approach is used,
the trace length be kept short enough to avoid
resonances in the band of interest. For guidance
on useful lengths, use equation (1) given in the
Power Supply Decoupling Techniques section for
approximate resonance frequencies verses trace
length. This relation provides an upper bound on
the resonant frequency, because additional capacitive coupling to the trace from other leads or
the ground plane causes extra distributed loading
and slows the signal propagation along the trace.
5. Socketing a high-speed part like the THS4303
is not recommended. The additional lead length
inductance and pin-to-pin capacitance introduced
by the socket creates an extremely troublesome
parasitic network, which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS4303 onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS4303 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which
the die is mounted [see Figure 48(a) and Figure 48(b)]. This arrangement results in the lead frame
being exposed as a thermal pad on the underside of
the package [see Figure 48(c)]. Because this thermal
pad has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a
good thermal path away from the thermal pad.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
THS4303
www.ti.com
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also
be soldered to a copper area underneath the package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the heretofore awkward mechanical methods of heatsinking.
4.
5.
DIE
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 48. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
6.
0.144
0.049
7.
0.012
Pin 1
0.0095
0.015
0.144
0.0195 0.0705
0.010
vias
0.032
0.030
0.0245
Top View
Figure 49. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as
shown in Figure 49. There should be etch for the
leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
They holes should be 13 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
8.
area. They help dissipate the heat generated by
the IC. These additional vias may be larger than
the 13-mil diameter vias directly under the thermal pad. They can be larger because they are
not in the thermal pad area to be soldered, so
that wicking is not a problem.
Connect all holes to the internal ground plane.
When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This resistance makes the
soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the IC
PowerPAD package should make their connection to the internal ground plane, with a complete
connection around the entire circumference of the
plated-through hole.
The top-side solder mask should leave the terminals of the package and the thermal pad area
with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that
is properly installed.
The next consideration is the package constraints.
The two sources of heat within an amplifier are
quiescent power and output power. The designer
should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output
stages (Class AB), most of the heat dissipation is at
low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB.
The PowerPAD devices are extremely useful for heat
dissipation. But, the device should always be
soldered to a copper plane to fully use the heat
dissipation properties of the PowerPAD. The SOIC
package, on the other hand, is highly dependent on
how it is mounted on the PCB. As more trace and
copper area is placed around the device,Θ JA decreases and the heat dissipation capability increases.
For a single package, the sum of the RMS output
currents and voltages should be used to choose the
proper package.
19
THS4303
www.ti.com
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
THERMAL ANALYSIS
The THS4303 device does not incorporate automatic
thermal shutoff protection, so the designer must take
care to ensure that the design does not violate the
absolute maximum junction temperature of the device. Failure may result if the absolute maximum
junction temperature of 150° C is exceeded.
The thermal characteristics of the device are dictated
by the package and the PC board. For a given ΘJA,
maximum power dissipation for a package can be
calculated using the following formula.
P Dmax Tmax–T A
JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to
the case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
The THS4303 is offered in a 16-pin leadless MSOP
with PowerPAD. The thermal coefficient for the
MSOP PowerPAD package is substantially improved
over the traditional packages. Maximum power dissipation levels are depicted in the graph below. The
data for the RGT package assumes a board layout
that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application notes in the Additional Reference Material
section at the end of the data sheet.
PD − Maximum Power Dissipation − W
7
6
5
16-Pin RGT Package
4
3
2
1
0
−40
−20
0
20
40
60
TA − Ambient Temperature − °C
80
θJA = 39.5°C/W for 16-Pin MSOP (RGT)
TJ = 150°C, No Airflow
Figure 50. Maximum Power Dissipation
vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
20
important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often
maximum power is difficult to quantify because the
signal pattern is inconsistent, but an estimate of the
RMS power dissipation can provide visibility into a
possible problem.
DESIGN TOOLS
Evaluation Fixtures
Information
and
Application
Support
Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has
been developed for the THS4303 operational amplifier. The evaluation board is available and easy to
use allowing for straight-forward evaluation of the
device. These evaluation board can be obtained by
ordering through the Texas Instruments web site,
www.ti.com, or through your local Texas Instruments
Sales Representative. A schematic for the evaluation
board is shown in Figure 51 with their default
component values. Unpopulated footprints are shown
to provide insight into design flexibility
Computer simulation of circuit performance using
SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS4303 device is available through the
Texas Instruments web site at www.ti.com. The
Product Information Center (PIC) is also available for
design assistance and detailed product information.
These models do a good job of predicting
small-signal ac and transient performance under a
wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between
the package types in their small-signal ac performance. Detailed information about what is and is not
modeled is contained in the model file itself.
THS4303
www.ti.com
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
VS+
FB2
J3
C2
22 µF
+
13
NC
14
47 pF
C4
0.1 µF
R5
30.1 Ω
9
_
+
PD
J6
A
Rf
Rg
J1
R4
49.9 Ω
C9
*
6454762
12 11 10
VI
C6
U1
8
7
6
5
R2
49.9 Ω
16
J2
VO
R3
*
C1
1 2
1 µF
VS−
3
C7
*
J4
C3
22 µF
4
+
C8
47 pF
FB1
C5
0.1 µF
R4
30.1 Ω
* = Not populated
Figure 51. Typical THS4303 EVM Circuit Configuration
Figure 52. THS4303EVM Layout
(Top Layer and Silkscreen Layer)
Figure 53. THS4303EVM Board Layout
(Ground Layers 2 and 3)
Figure 54. THS4303EVM Board Layout
(Bottom Layer)
21
THS4303
www.ti.com
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
BILL OF MATERIALS
THS4303RGT EVM
ITEM
(1)
DESCRIPTION
SMD SIZE
REFERENCE
DESIGNATOR
PCB
QUANTITY
MANUFACTURER'S PART NUMBER (1)
1206
FB1, FB2
2
(Steward) HI1206N800R-00
D
C2, C3
2
(AVX) TAJD226K025R
(AVX) 08053G105ZAT2A
1
Bead, ferrite, 3 A, 80 Ω
2
Capacitor 22 µF, tantalum, 25 V, 10%
3
Capacitor 1 µF, ceramic, 25 V, Y5V
0805
C1
1
4
Open
0402
C6, C7
2
5
Capacitor 47 pF, ceramic, 50 V, NPO
0402
C8, C9
2
(AVX) 04025A470JAT2A
6
Capacitor 0.1 µF, ceramic, 16 V, X7R
0603
C4, C5
2
(AVX) 0603YC104KAT2A
7
Resistor, 30.1 Ω, 1/16 W, 1%
0402
R4, R5
2
(KOA) RK73H1E30R1F
8
Open
0603
R3
1
0603
9
Resistor, 49.9 Ω, 1/16 W, 1%
10
Jack, banana receptance, 0.25” dia. hole
11
Test point, red
12
Test point, black
13
Connector, edge, SMA PCB jack
14
IC THS4303
15
Standoff, 4-40 hex, 0.625” length
4
(Keystone) 1808
16
Screw, phillips, 4-40, .250”
4
SHR-0440-016-SN
17
Board, printed-circuit
1
(TI) EDGE # 6454762 Rev. A
R1, R2
2
(Phycomp) 9C06031A49R9FKRFT
J3, J4, J5
3
(HH Smith) 101
(Keystone) 5000
J6
1
TP1
1
(Keystone) 5001
J1, J2
2
(Johnson) 142-0701-801
U1
1
(TI) THS4303RGT
The manufacturer's part numbers are used for test purposes only.
ADDITIONAL REFERENCE MATERIAL
•
•
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.
Input Range, VS+ to VS–
3.0 V to 6.0 V
Input Range, VI
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS–
Output Range, VO
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS–
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
22
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4303RGTT
ACTIVE
VQFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4303
THS4303RGTTG4
ACTIVE
VQFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4303
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS4303RGTT
Package Package Pins
Type Drawing
VQFN
RGT
16
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4303RGTT
VQFN
RGT
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016A
VQFN - 1 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1.45 0.1
(0.2) TYP
5
12X 0.5
8
EXPOSED
THERMAL PAD
4
9
4X
1.5
SYMM
17
1
12
16X
PIN 1 ID
(OPTIONAL)
13
16
0.1
0.05
SYMM
16X
0.30
0.18
C A B
0.5
0.3
4219032/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.45)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
17
(0.475)
TYP
(2.8)
12X (0.5)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.475) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219032/A 02/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.34)
13
16
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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