Texas Instruments | Rail-to-Rail Input/Output Operational Amplifiers w/ Shutdown (Rev. J) | Datasheet | Texas Instruments Rail-to-Rail Input/Output Operational Amplifiers w/ Shutdown (Rev. J) Datasheet

Texas Instruments Rail-to-Rail Input/Output Operational Amplifiers w/ Shutdown (Rev. J) Datasheet
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
D
D
D
D
D
D
D
D
D
D
TLV2460
DBV PACKAGE
(TOP VIEW)
Rail-to-Rail Output Swing
Gain Bandwidth Product . . . 6.4 MHz
± 80 mA Output Drive Capability
Supply Current . . . 500 µA/channel
Input Offset Voltage . . . 100 µV
Input Noise Voltage . . . 11 nV/√Hz
Slew Rate . . . 1.6 V/µs
Micropower Shutdown Mode
(TLV2460/3/5) . . . 0.3 µA/Channel
Universal Operational Amplifier EVM
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
OUT
1
6
VDD+
GND
2
5
SHDN
IN+
3
4
IN −
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for
portable applications. The input common-mode voltage range extends beyond the supply rails for maximum
dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive
capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail
dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters.
The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current,
providing good ac performance with low power consumption. Three members of the family offer a shutdown
terminal, which places the amplifier in an ultralow supply current mode (IDD = 0.3 µA/ch). While in shutdown,
the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with
an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
This family is available in the low-profile SOT23, MSOP, and TSSOP packages. The TLV2460 is the first
rail-to-rail input/output operational amplifier with shutdown available in the 6-pin SOT23, making it perfect for
high-density circuits. The family is specified over an expanded temperature range (TA = − 40°C to 125°C) for
use in industrial control and automotive systems, and over the military temperature range
(TA = −55°C to 125°C) for use in military systems.
SELECTION GUIDE
DEVICE
VDD
[V]
VIO
[µV]
IDD/ch
[µA]
IIB
[pA]
GBW
[MHz]
SLEW RATE
[V/µs]
Vn, 1 kHz
[nV/√Hz]
IO
[mA]
SHUTDOWN
RAIL-RAIL
TLV246x(A)
2.7−6
150
550
1300
6.4
1.6
11
25
Y
I/O
TLV277x(A)
2.5−5.5
360
1000
2
5.1
10.5
17
6
Y
O
TLV247x(A)
2.7−6
250
600
2.5
2.8
1.5
15
20
Y
I/O
TLV245x(A)
2.7−6
20
23
500
0.22
0.11
52
10
Y
I/O
TLV225x(A)
2.7−8
200
35
1
0.2
0.12
19
3
—
—
TLV226x(A)
2.7−8
300
200
1
0.71
0.55
12
3
—
—
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998−2004, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" + &( !('$*%+!'(
('&!/&$/ 2&$$&!'30 $#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+
'+('!4 #" &.. ,&$&%+'+$(0
! ,$#/*)'( )#%,.&!' '# 5 &.. ,&$&%+'+$( &$+ '+('+/
*!.+(( #'1+$2(+ !#'+/0 ! &.. #'1+$ ,$#/*)'( ,$#/*)'#!
,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+ '+('!4 #" &.. ,&$&%+'+$(0
WWW.TI.COM
1
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TLV2460C/I/AI and TLV2461C/I/AI AVAILABLE OPTIONS
PACKAGED DEVICES
SOT-23†
SYMBOL
(DBV)
TA
VIOmax
AT 25°C
0°C to 70°C
2000 µV
TLV2460CD
TLV2461CD
TLV2460CDBV
TLV2461CDBV
VAOC
VAPC
TLV2460CP
TLV2461CP
2000 µV
TLV2460ID
TLV2461ID
TLV2460IDBV
TLV2461IDBV
VAOI
VAPI
TLV2460IP
TLV2461IP
1500 µV
TLV2460AID
TLV2461AID
SMALL OUTLINE
(D)
−40°C to 125°C
—
—
PLASTIC DIP
(P)
—
—
TLV2460AIP
TLV2461AIP
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460CDR).
‡ Chip forms are tested at TA = 25°C only.
TLV2460M/AM/Q/AQ and TLV2461M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE†
(D)
2000 µV
1500 µV
−40°C to 125°C
SMALL
OUTLINE†
(PW)
CERAMIC DIP
(JG)
CERAMIC
FLATPACK
(U)
CHIP CARRIER
(FK)
TLV2460QD
TLV2461QD
TLV2460QPW
TLV2461QPW
—
—
—
—
—
—
TLV2460AQD
TLV2461AQD
TLV2460AQPW
TLV2461AQPW
—
—
—
—
—
—
2000 µV
—
—
—
—
TLV2460MJG
TLV2461MJG
TLV2460MU
TLV2461MU
TLV2460MFK
TLV2461MFK
1500 µV
—
—
—
—
TLV2460AMJG
TLV2461AMJG
TLV2460AMU
TLV2461AMU
TLV2460AMFK
TLV2461AMFK
−55°C to 125°C
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460QDR).
TLV2462C/I/AI and TLV2463C/I/AI AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE†
(D)
MSOP
(DGK)
0°C to 70°C
2000 µV
TLV2462CD
TLV2463CD
TLV2462CDGK
—
2000 µV
TLV2462ID
TLV2463ID
1500 µV
TLV2462AID
TLV2463AID
−40
C to
−40°C
125°C
MSOP†
(DGS)
SYMBOL
PLASTIC DIP
(N)
PLASTIC DIP
(P)
xxTIAAI
—
TLV2463CDGS
—
xxTIAAK
—
TLV2463CN
TLV2462CP
—
TLV2462IDGK
—
xxTIAAJ
—
TLV2463IDGS
—
xxTIAAL
—
TLV2463IN
TLV2462IP
—
—
—
—
—
—
—
—
—
—
TLV2463AIN
TLV2462AIP
—
SYMBOL
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2462CDR).
‡ Chip forms are tested at TA = 25°C only.
2
WWW.TI.COM
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TLV2462M/AM/Q/AQ and TLV2463M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE†
(D)
SMALL
OUTLINE†
(PW)
CERAMIC DIP
(JG)
CERAMIC
DIP
(J)
CERAMIC
FLATPACK
(U)
CHIP CARRIER
(FK)
2000 µV
TLV2462QD
TLV2463QD
TLV2462QPW
TLV2463QPW
—
—
—
—
—
—
—
—
1500 µV
TLV2462AQD
TLV2463AQD
TLV2462AQPW
TLV2463AQPW
—
—
—
—
—
—
—
—
−40°C to 125°C
2000 µV
—
—
—
—
TLV2462MJG
—
—
TLV2463MJ
TLV2462MU
TLV2462MFK
TLV2463MFK
1500 µV
—
—
—
—
TLV2462AMJG
—
—
TLV2463AMJ
TLV2462AMU
TLV2462AMFK
TLV2463AMFK
−55°C to 125°C
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2462QDR).
TLV2464C/I/AI and TLV2465C/I/AI AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
0°C to 70°C
2000 µV
TLV2464CD
TLV2465CD
TLV2464CN
TLV2465CN
TLV2464CPW
TLV2465CPW
2000 µV
TLV2464ID
TLV2465ID
TLV2464IN
TLV2465IN
TLV2464IPW
TLV2465IPW
1500 µV
TLV2464AID
TLV2465AID
TLV2464AIN
TLV2465AIN
TLV2464AIPW
TLV2465AIPW
−40°C to 125°C
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
TSSOP
(PW)
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number(e.g., TLV2464CDR).
‡ Chip forms are tested at TA = 25°C only.
TLV2464M/AM/Q/AQ and TLV2465M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE†
(D)
2000 µV
1500 µV
- 40°C to 125°C
SMALL
OUTLINE†
(PW)
CERAMIC DIP
(J)
CHIP CARRIER
(FK)
TLV2464QD
TLV2465QD
TLV2464QPW
TLV2465QPW
—
—
—
—
TLV2464AQD
TLV2465AQD
TLV2464AQPW
TLV2465AQPW
—
—
—
—
2000 µV
—
—
—
—
TLV2464MJ
TLV2465MJ
TLV2464MFK
TLV2465MFK
1500 µV
—
—
—
—
TLV2464AMJ
TLV2465AMJ
TLV2464AMFK
TLV2465AMFK
−55°C to 125°C
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number
(e.g., TLV2464QDR).
WWW.TI.COM
3
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TLV246x PACKAGE PINOUTS(1)
TLV2460
DBV PACKAGE
(TOP VIEW)
OUT
GND
IN+
1
2
3
6
5
4
VDD+
SHDN
IN −
TLV2461
D, P, JG, OR PW PACKAGE
(TOP VIEW)
NC
IN −
IN +
GND
1
8
2
7
3
6
4
5
TLV2460
D, P, JG, OR PW PACKAGE
(TOP VIEW)
TLV2461
DBV PACKAGE
(TOP VIEW)
NC
VDD+
OUT
NC
OUT
GND
IN+
1
5
VDD+
2
3
4
IN −
NC
IN −
IN +
GND
1
8
2
7
3
6
4
5
VDD+
2OUT
2IN −
2IN+
7
3
6
4
5
SHDN
VDD+
OUT
NC
1OUT
1IN −
1IN+
GND
1SHDN
1
2
3
4
5
10
9
8
7
6
VDD+
2OUT
2IN −
2IN+
2SHDN
TLV2463
D, N, J, OR PW PACKAGE
TLV2464
D, N, PWP, J, OR PW PACKAGE
TLV2465
D, N, PWP, J, OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1OUT
1IN −
1IN+
GND
NC
1SHDN
NC
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD+
2OUT
2IN −
2IN+
NC
2SHDN
NC
1OUT
1IN −
1IN+
VDD+
2IN+
2IN −
2OUT
1
14
2
13
3
4
5
12
11
10
6
9
7
8
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
1OUT
1IN −
1IN+
VDD+
2IN+
2IN −
2OUT
1/2SHDN
NC − No internal connection
(1) SOT−23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
4
8
2
TLV2463
DGS PACKAGE
(TOP VIEW)
TLV2462
D, DGK, P, JG, OR PW PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
GND
1
Pin 1
Stripe
Pin 1
Bevel Edges
WWW.TI.COM
Pin 1
Molded ”U” Shape
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
4OUT
4IN −
4IN+
GND
3IN +
3IN−
3OUT
3/4SHDN
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TLV246x PACKAGE PINOUTS (continued)(1)
TLV2461
U PACKAGE
(TOP VIEW)
4
18 NC
IN−
5
17 VDD
IN−
5
17 VDD
NC
6
16 NC
NC
6
16 NC
IN+
7
15 OUT
IN+
7
NC
8
14 NC
NC
8
1IN+
4
18 2IN−
NC
5
17 NC
GND
6
16 2IN+
2OUT
18 2IN−
NC
5
17 NC
GND
6
16 2IN+
15 OUT
NC
7
15 NC
14 NC
NC
8
14 NC
10 11 12 13
NC
NC
NC
NC
NC
1
20 19
4
18 4IN+
NC
5
17 NC
VDD+
6
16 GND
4OUT
2
1IN+
NC
3
4IN−
4OUT
20 19
4
TLV2465
FK PACKAGE
(TOP VIEW)
NC
V DD
1
20 19
9
1OUT
NC
2
1
10 11 12 13
1IN−
1OUT
3
2
TLV2464
FK PACKAGE
(TOP VIEW)
2OUT
1IN−
TLV2463
FK PACKAGE
(TOP VIEW)
3
1IN+
GND
NC
9
NC
10 11 12 13
NC
NC
9
NC
NC
GND
18 NC
V DD
20 19
4
NC
1
TLV2462
FK PACKAGE
(TOP VIEW)
NC
2
NC
VDD+
2OUT
2IN−
2IN+
1OUT
NC
3
10
9
8
7
6
1IN−
NC
20 19
NC
SHDN
1
NC
NC
2
TLV2461
FK PACKAGE
(TOP VIEW)
NC
NC
3
1
2
3
4
5
NC
NC
NC
1OUT
VDD
1IN−
OUTPUT 1IN+
NC
GND
1OUT
3
2
1
20 19
1IN+
4
18 4IN+
VDD+
5
17 GND
NC
6
16 NC
7
15 3IN+
8
14 3IN−
8
14 NC
2IN+
8
14 3IN+
2IN−
3OUT
3/4SHDN
10 11 12 13
3OUT
9
NC
10 11 12 13
2SHDN
9
NC
10 11 12 13
NC
9
1/2SHDN
NC
2OUT
15 NC
3IN−
7
2OUT
NC
2IN−
15 NC
NC
7
1SHDN
NC
2IN+
NC
NC
NC
TLV2460
FK PACKAGE
(TOP VIEW)
10
9
8
7
6
4IN−
1
2
3
4
5
NC
NC
IN−
IN+
GND
NC
NC
SHDN
VDD
OUTPUT
NC
1IN−
10
9
8
7
6
NC
1
2
3
4
5
NC
NC
IN−
IN+
GND
TLV2462
U PACKAGE
(TOP VIEW)
NC
TLV2460
U PACKAGE
(TOP VIEW)
NC − No internal connection
(1) SOT−23 may or may not be indicated
WWW.TI.COM
5
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.2 V to VDD + 0.2 V
Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 175 mA
Total input current, II (into VDD +) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
Total output current, IO (out of GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I and Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE FOR C and I SUFFIX
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
25 C
POWER RATING
TA < 125
125°C
C
POWER RATING
D (8)
38.3
176
710 mW
142 mW
D (14)
26.9
122.6
1022 mW
204.4 mW
D (16)
25.7
114.7
1090 mW
218 mW
DBV (5)
55
324.1
385 mW
77.1 mW
DBV (6)
55
294.3
425 mW
84.9 mW
DGK
54.2
259.9
481 mW
96.2 mW
DGS
54.1
257.7
485 mW
97 mW
N (14, 16)
32
78
1600 mW
320.5 mW
P (8)
41
104
1200 mW
240.4 mW
PW (14)
29.3
173.6
720 mW
144 mW
PW (16)
28.7
161.4
774 mW
154.9 mW
NOTE: Thermal resistances are not production tested and are for informational
purposes only.
DISSIPATION RATING TABLE FOR Q and M SUFFIX
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C‡
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
JG
1050 mW
8.4 mW/°C
672 mW
546 mW
210 mW
TA = 125
125°C
C
POWER RATING
U
675 mW
5.4 mW/°C
432 mW
350 mW
135 mW
‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for
informational purposes only.
6
WWW.TI.COM
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
recommended operating conditions
MIN
Single supply
Supply voltage, VDD
Split supply
2.7
6
±3
0
V
°C
C
0
VDD
70
I-suffix and Q-suffix
−40
125
M-suffix
−55
125
C-suffix
VIH
VIL
Shutdown on/off voltage level‡
UNIT
±1.35
Common-mode input voltage range, VICR
Operating free-air temperature, TA
MAX
2
0.7
V
V
‡ Relative to voltage on the GND terminal of the device.
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
MIN
25°C
VIO
αVIO
Input offset voltage
VDD = 3 V,
VIC = 1.5 V,
VO = 1.5 V,
RS = 50 Ω
IIB
Input bias current
TLV246xA
500
Full range
VDD = 3 V,
VIC = 1.5 V,
VO = 1.5 V,
RS = 50 Ω
2.8
Full range
20
Full range
75
25°C
4.4
Full range
25
TLV246xI/Q/M
Full range
75
High-level output voltage
VIC = 1.5 V,
IOL = 2.5 mA
Low-level output voltage
2.9
IOL = 10 mA
2.5
0.1
0.2
Full range
0.5
Full range
Full range
Short-circuit output current
AVD
Output current
Large-signal differential voltage
amplification
50
20
25°C
Sinking
Full range
Measured 1 V from rail
RL = 10 kΩ
kΩ,
VO(PP) = 1 V
40
mA
20
± 40
25°C
25°C
90
Full range
89
mA
105
ri(d)
Differential input resistance
25°C
109
† Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
WWW.TI.COM
V
0.3
25°C
Sourcing
V
2.7
25°C
VIC = 1.5 V,
nA
2.8
25°C
Full range
nA
14
TLV246xC
25°C
IO
µV/°C
TLV246xI/Q/M
Full range
µV
V
7
TLV246xC
IOH = − 10 mA
IOS
1500
UNIT
1700
25°C
VOL
2000
2
IOH = − 2.5 mA
VOH
500
2200
25°C
Temperature coefficient of input offset voltage
Input offset current
MAX
Full range
25°C
IIO
TYP
dB
Ω
7
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
(continued)
PARAMETER
TEST CONDITIONS
ci(c)
Common-mode input
capacitance
f = 10 kHz
zo
Closed-loop output impedance
f = 100 kHz,
CMRR
kSVR
Common-mode rejection ratio
Supply voltage rejection ratio
((∆V
VDD /∆V
/ VIO)
TA†
MIN
TYP
25°C
AV = 10
25°C
25°C
66
VICR = 0 to 3 V,
RS = 50 Ω
TLV246xC
Full range
64
TLV246xI/Q/M
Full range
60
VDD = 2.7 V to 6 V,
No load
VIC = VDD /2,
VDD = 3 V to 5 V,
No load
VIC = VDD /2,
25°C
80
Full range
75
25°C
85
Full range
80
25°C
IDD
Supply current (per channels)
VO = 1.5 V,
No load
IDD(SHDN)
Supply current in shutdown
(TLV2460, TLV2463, TLV2465)
SHDN < 0.7 V,
Per channel in shutdown
MAX
7
pF
33
Ω
80
dB
85
dB
95
0.5
0.575
0.9
Full range
25°C
UNIT
0.3
Full range
2.5
mA
µA
A
† Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
SR
Slew rate at unity gain
Vn
Equivalent input noise voltage
In
Equivalent input noise current
THD + N
t(on)
Total harmonic distortion plus
noise
Amplifier turnon time
TEST CONDITIONS
VO(PP) = 0.8 V,
RL = 10 kΩ
CL = 160 pF,
TA†
25°C
Full
range
Amplifier turnoff time
ts
φm
Settling time
1.6
16
25°C
11
f = 1 kHz
25°C
VO(PP) = 2 V,
RL = 10 kΩ, f = 1 kHz
AV = 1, RL = 10 kΩ
AV = 1
AV = 10
AV = 1, RL = 10 kΩ
Channel 1 only,
Channel 2 on
f = 10 kHz, CL = 160 pF
RL = 10 kΩ,
0.13
25°C
25
C
pA /√Hz
0.08%
7.6
25°C
7.65
µs
333
25°C
25
C
328
ns
329
25°C
5.2
V(STEP)PP = 2 V,
AV = −1, CL = 10 pF,
RL = 10 kΩ
0.1%
V(STEP)PP = 2 V,
AV = −1, CL = 56 pF,
RL = 10 kΩ
0.1%
1.77
0.01%
1.98
RL = 10 kΩ,
CL = 160 pF
WWW.TI.COM
nV/√Hz
0.02%
MHz
1.47
0.01%
1.78
25°C
25°C
44°
25°C
7
† Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
8
UNIT
0.006%
AV = 100
Both channels
Channel 1 only,
Channel 2 on
MAX
V/µs
0.8
25°C
Phase margin at unity gain
Gain margin
0.9
f = 1 kHz
Channel 2 only,
Channel 1 on
Gain-bandwidth product
TYP
f = 100 Hz
Both channels
t(off)
MIN
µss
dB
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
αVIO
IIO
IIB
Input offset voltage
Temperature coefficient of input offset voltage
Input offset current
Input bias current
TEST CONDITIONS
TA†
25°C
MIN
VDD = 5 V,
VIC = 2.5,
VO = 2.5 V,
RS = 50 Ω
25°C
TLV246xA
VDD = 5 V,
VIC = 2.5 V,
VO = 2.5 V,
RS = 50 Ω
500
Full range
25°C
2
25°C
0.3
15
Full range
60
TLV246xC
Full range
30
TLV246xI/Q/M
Full range
60
High-level output voltage
1.3
Full range
IOL = 2.5 mA
Low-level output voltage
4.7
0.1
0.2
Full range
Short-circuit output current
0.3
Output current
VIC = 2.5 V,
VO = 1 V to 4 V
92
Full range
90
Differential input resistance
ci(c)
Common-mode input capacitance
f = 10 kHz
zo
Closed-loop output impedance
f = 100 kHz,
kSVR
± 80
25°C
ri(d)
Supply voltage rejection ratio
((∆V
VDD /∆V
/ VIO)
60
25°C
Large-signal differential voltage
amplification
Common-mode rejection ratio
Full range
RL = 10 kΩ,
25°C
7
pF
25°C
29
Ω
25°C
71
TLV246xC
Full range
69
TLV246xI/Q/M
Full range
60
VDD = 2.7 V to 6 V,
No load
VIC = VDD /2,
25°C
80
Full range
75
VDD = 3 V to 5 V,
No load
VIC = VDD /2,
25°C
85
Full range
80
No load,
25°C
Supply current (per channel)
VO = 2.5 V,
IDD(SHDN)
Supply current in shutdown
(TLV2460, TLV2463, TLV2465)
SHDN < 0.7 V, Per channels in
shutdown
dB
Ω
VICR = 0 V to 5 V,
RS = 50 Ω
IDD
mA
109
109
25°C
AV = 10
mA
100
Measured at 1 V from rail
AVD
CMRR
145
60
25°C
Sinking
V
0.2
Full range
Full range
nA
V
4.8
25°C
Sourcing
14
4.9
25°C
IOL = 10 mA
nA
4.8
25°C
VIC = 2.5 V,
7
Full range
Full range
µV
V
µV/°C
V/°C
TLV246xI/Q/M
25°C
VIC = 2.5 V,
1500
UNIT
1700
25°C
IO
2000
TLV246xC
IOH = − 10 mA
IOS
500
2200
25°C
VOL
MAX
Full range
IOH = − 2.5 mA
VOH
TYP
85
dB
85
dB
95
dB
0.55
25°C
Full range
0.65
1
Full range
1
3
mA
µA
A
† Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
WWW.TI.COM
9
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
SR
Slew rate at unity gain
Vn
Equivalent input noise voltage
In
THD + N
t(on)
t(off)
TEST CONDITIONS
VO(PP) = 2 V,
RL = 10 kΩ
CL = 160 pF,
TA†
25°C
Full
range
0.9
1.6
14
f = 1 kHz
25°C
11
Equivalent input noise current
f = 100 Hz
25°C
0.13
Total harmonic distortion plus noise
VO(PP) = 4 V,
RL = 10 kΩ,
f = 10 kHz
Amplifier turnon time
Amplifier turnoff time
AV = 1, RL = 10 kΩ
AV = 1, RL = 10 kΩ
AV = 1
AV = 10
Settling time
Gain margin
7.6
25°C
25
C
7.65
Both channels
333
25
C
25°C
328
f = 10 kHz,
CL = 160 pF
RL = 10 kΩ,
V(STEP)PP = 2 V,
AV = −1,
CL = 10 pF,
RL = 10 kΩ
0.1%
V(STEP)PP = 2 V,
AV = −1,
CL = 56 pF,
RL = 10 kΩ
0.1%
3.13
0.01%
3.33
RL = 10 kΩ,
CL = 160 pF
WWW.TI.COM
µs
ns
329
25°C
6.4
MHz
1.53
0.01%
1.83
µss
25°C
25°C
45°
25°C
7
† Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
10
pA /√Hz
0.04%
7.25
Phase margin at unity gain
nV/√Hz
0.01%
Channel 2 only,
Channel 1 on
Channel 1 only,
Channel 2 on
UNIT
0.004%
25°C
25
C
AV = 100
Both channels
Channel 1 only,
Channel 2 on
MAX
V/µs
0.8
25°C
Gain-bandwidth product
φm
TYP
f = 100 Hz
Channel 2 only,
Channel 1 on
ts
MIN
dB
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
IIB
Input offset voltage
vs Common-mode input voltage
1, 2
Input bias current
vs Free-air temperature
3, 4
IIO
VOH
Input offset current
vs Free-air temperature
3, 4
High-level output voltage
vs High-level output current
5, 6
VOL
VO(PP)
Low-level output voltage
vs Low-level output current
7, 8
Peak-to-peak output voltage
vs Frequency
9, 10
Open-loop gain
vs Frequency
11, 12
Phase
vs Frequency
11, 12
Differential voltage amplification
vs Load resistance
13
Capacitive load
vs Load resistance
14
Zo
CMRR
Output impedance
vs Frequency
15, 16
Common-mode rejection ratio
vs Frequency
17
kSVR
Supply-voltage rejection ratio
vs Frequency
18, 19
AVD
IDD
Supply current
vs Supply voltage
20
vs Free-air temperature
21
Amplifier turnon characteristics
22
Amplifier turnoff characteristics
23
Supply current turnon
24
Supply current turnoff
SR
25
Shutdown supply current
vs Free-air temperature
Slew rate
vs Supply voltage
26
27
vs Frequency
28, 29
vs Common-mode input voltage
30, 31
Vn
Equivalent input noise voltage
THD
Total harmonic distortion
vs Frequency
32, 33
THD+N
Total harmonic distortion plus noise
vs Peak-to-peak signal amplitude
34, 35
vs Frequency
11, 12
φm
Phase margin
vs Load capacitance
36
vs Free-air temperature
37
vs Supply voltage
38
vs Free-air temperature
39
Gain bandwidth product
Large signal follower
40, 41
Small signal follower
42, 43
Inverting large signal
44, 45
Inverting small signal
46, 47
WWW.TI.COM
11
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
VDD = 5 V
TA = 25°C
0.8
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
0.8
1
VDD = 3 V
TA = 25°C
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
0.5
1
1.5
2
2.5
−1
3
0
VICR − Common-Mode Input Voltage − V
1
Figure 1
VDD = 3 V
VI = 1.5 V
4.5
IIB
4
3.5
3
2.5
2
1.5
1
0.5
IIO
−15
5
25
45
65
85
105
125
TA − Free-Air Temperature − °C
5
6
VDD = 5 V
VI = 2.5 V
5
IIB
4
3
2
1
IIO
0
−1
−55 −35
−15
5
25
45
65
85
TA − Free-Air Temperature − °C
Figure 3
12
4
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
I IB and I IO − Input Bias and Input Offset Current − nA
I IB and I IO − Input Bias and Input Offset Current − nA
5
−0.5
−55 −35
3
Figure 2
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
0
2
VICR − Common-Mode Input Voltage − V
Figure 4
WWW.TI.COM
105
125
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
5
VDD = 5 VDC
4.5
2.5
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
VDD = 3 VDC
TA = −55°C
2
1.5
TA = 125°C
TA = 85°C
TA = 25°C
1
TA = −40°C
0.5
TA = −55°C
4
3.5
3
TA = 125°C
TA = 85°C
2.5
2
TA = 25°C
1.5
TA = −40°C
1
0.5
0
0
10
20
30
40
50
60
70
0
80
0
IOH − High-Level Output Current − mA
20
40
60
Figure 5
100 120 140 160 180 200
Figure 6
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3
4.5
VDD = 3 VDC
VDD = 5 VDC
4
2.5
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
80
IOH − High-Level Output Current − mA
TA = −40°C
2
TA = 25°C
1.5
TA = 85°C
TA = 125°C
1
0.5
0
10
20
30
40
50
60
TA = −40°C
3
TA = 25°C
2.5
TA = 85°C
TA = 125°C
2
1.5
1
TA = −55°C
0.5
TA = −55°C
0
3.5
70
IOL − Low-Level Output Current − mA
0
0
20
40
60
80
100
120
140
160
IOL − Low-Level Output Current − mA
Figure 7
Figure 8
WWW.TI.COM
13
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
5.5
VDD = 3 V
AV = −10
THD = 1%
RL = 10 kΩ
2.5
VO(PP) − Peak-to-Peak Output Voltage − V
VO(PP) − Peak-to-Peak Output Voltage − V
3
2
1.5
1
0.5
0
10k
100k
1M
VDD = 5 V
AV = −10
THD = 1%
RL = 10 kΩ
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
10k
10M
100k
f − Frequency − Hz
1M
f − Frequency − Hz
Figure 9
Figure 10
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
VDD = ±1.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
90
80
60
0°
−20°
−40°
AVD
50
−60°
40
−80°
−100°
30
Phase
20
−120°
10
−140°
0
−160°
−10
−180°
−20
10
100
1k
10k
100k
f − Frequency − Hz
Figure 11
14
20°
WWW.TI.COM
1M
−200°
10M
Phase
Open-Loop Gain − dB
70
40°
10M
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
VDD = ±2.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
90
80
60
20°
0°
−20°
−40°
AVD
50
−60°
40
−80°
−100°
30
Phase
20
−120°
10
−140°
0
−160°
−10
−180°
−20
10
Phase
Open-Loop Gain − dB
70
40°
100
1k
100k
10k
1M
−200°
10M
f − Frequency − Hz
Figure 12
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
CAPACITIVE LOAD
vs
LOAD RESISTANCE
10000
TA = 25°C
160
140
CL − Capacitive Load − pF
A VD − Differential Voltage Amplification − V/mV
180
120
VDD = ±2.5 V
100
VDD = ±1.5 V
80
60
40
Phase Margin < 30°
1000
Phase Margin > 30°
VDD = 5 V
Phase Margin = 30°
TA = 25°C
20
0
100
1k
10k
100k
1M
RL − Load Resistance − Ω
100
10
100
1k
10k
RL − Load Resistance − Ω
Figure 14
Figure 13
WWW.TI.COM
15
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
VDD = ±1.5 V
TA = 25°C
100
Zo − Output Impedance − Ω
Zo − Output Impedance − Ω
100
10
AV = 100
1
AV = 10
0.1
VDD = ±2.5 V
TA = 25°C
AV = 1
10
AV = 100
1
AV = 10
0.1
AV = 1
0.01
100
1k
10k
100k
1M
0.01
100
10M
1k
f − Frequency − Hz
10k
Figure 15
Figure 16
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
90
85
80
VDD = 5 V
VIC = 2.5 V
75
VDD = 3 V
VIC = 1.5 V
70
65
60
10
100
1k
10k
100k
f − Frequency − Hz
Figure 17
16
100k
f − Frequency − Hz
WWW.TI.COM
1M
10M
1M
10M
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
90
+kSVR
VDD = ±1.5 V
TA = 25°C
100
k SVR − Supply Voltage Rejection Ratio − dB
k SVR − Supply Voltage Rejection Ratio − dB
110
90
−kSVR
80
70
60
+kSVR
50
−kSVR
40
10
100
1k
10k
100k
1M
+kSVR
80
−kSVR
70
60
+kSVR
50
−kSVR
40
10
10M
VDD = ±2.5 V
TA = 25°C
1k
100
f − Frequency − Hz
10k
100k
1M
10M
f − Frequency − Hz
Figure 18
Figure 19
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.8
0.80
IDD = 125°C
I DD − Supply Current − mA
I DD − Supply Current − mA
0.75
IDD = 85°C
0.7
0.6
0.5
0.40
IDD = 25°C
0.30
IDD = −55°C
VDD = 5 V
VI = 2.5 V
0.65
0.60
0.55
VDD = 3 V
VI = 1.5 V
0.50
0.45
0.40
IDD = −40°C
0.20
0.70
0.35
0.10
2.5
3
3.5
4
4.5
5
5.5
6
VDD − Supply Voltage − V
0.30
−55 −35
−15
5
25
45
65
85
105
125
TA − Free-Air Temperature − °C
Figure 20
Figure 21
WWW.TI.COM
17
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
AMPLIFIER WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
AMPLIFIER WITH A SHUTDOWN PULSE
TURNOFF CHARACTERISTICS
5
5
4
Shutdown Pin
3
2
1
0
Amplifier Output
3
2
1
0
−5
VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
Shutdown Pin
3
VSD − Shutdown Voltage − V
VSD − Shutdown Voltage − V
4
VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
−3
−1
2
1
0
Amplifier Output
3
2
1
1
3
5
9
7
0
−5
11
−3
−1
t − Time − µs
1
t − Time − µs
Figure 23
Figure 22
SUPPLY CURRENT WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
1
5.5
0.8
4.5
0.6
3.5
Supply Current
0.4
2.5
0.2
1.5
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
0
−0.2
−0.4
−0.2
0
0.2
t − Time − µs
Figure 24
18
WWW.TI.COM
0.4
0.5
−0.5
0.6
VSD − Shutdown Voltage − V
I DD − Supply Current − mA
Shutdown Pin
3
5
7
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TURNOFF SUPPLY CURRENT
WITH A SHUTDOWN PULSE
1
5.5
4.5
0.6
0.4
3.5
Supply Current
2.5
0.2
1.5
0
0.5
−0.2
−0.4
−0.2
0
0.2
VSD − Shutdown Voltage − V
Shutdown Pin
0.8
I DD − Supply Current − mA
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
−0.5
0.6
0.4
t − Time − µs
Figure 25
SLEW RATE
vs
SUPPLY VOLTAGE
3
1.8
2.5
1.75
1.7
VDD = 5 V
VI = 2.5 V
2
SR − Slew Rate − V/ µs
I DD − Shutdown Supply Current − µ A
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.5
1
VDD = 3 V
VI = 1.5 V
0.5
0
SR+
1.65
1.6
1.55
1.5
1.45
1.4
−0.5
−1
−55 −35
1.35
−15
5
25
45
65
85
105
125
TA − Free-Air Temperature − °C
SR−
1.3
2.5
VO(PP) = 2 V
CL = 160 pF
AV = 1
RL = 10 kΩ
TA = 25°C
3
3.5
4
4.5
5
5.5
6
VDD − Supply Voltage − V
Figure 26
Figure 27
WWW.TI.COM
19
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
18
VDD = 3 V
AV = 10
VI = 1.5 V
TA = 25°C
17
Vn − Equivalent Input Noise Voltage − nV/ Hz
Vn − Equivalent Input Noise Voltage − nV/ Hz
18
16
15
14
13
12
11
10
100
1k
10k
VDD = 5 V
AV = 10
VI = 2.5 V
TA = 25°C
17
16
15
14
13
12
11
10
100
100k
1k
f − Frequency − Hz
Figure 28
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
20
20
VDD = 3 V
AV = 10
f = 1 kHz
TA = 25°C
15
Vn − Equivalent Input Noise Voltage − nV/ Hz
Vn − Equivalent Input Noise Voltage − nV/ Hz
100k
Figure 29
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
14
13
12
11
10
0
0.5
1
1.5
2
2.5
3
VICR − Common-Mode Input Voltage − V
VDD = 5 V
AV = 10
f = 1 kHz
TA = 25°C
15
14
13
12
11
10
0
1
2
3
4
VICR − Common-Mode Input Voltage − V
Figure 30
20
10k
f − Frequency − Hz
Figure 31
WWW.TI.COM
5
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
1
VDD = ±1.5 V
VO(PP) = 2 V
RL = 10 kΩ
THD − Total Harmonic Distortion − %
THD − Total Harmonic Distortion − %
0.5
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
AV = 100
0.1
AV = 10
0.010
0.001
AV = 1
10
100
1k
10k
0.1
AV = 100
AV = 10
0.010
AV = 1
0.001
100k
VDD = ±2.5 V
VO(PP) = 4 V
RL = 10 kΩ
10
100
1k
f − Frequency − Hz
Figure 32
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
1
RL = 250 Ω
RL = 2 kΩ
0.1
RL = 10 kΩ
0.010
RL = 100 kΩ
0.001
1
1.2 1.4 1.6 1.8 2
100k
Figure 33
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
VDD = 3 V
AV = 1
TA = 25°C
10k
f − Frequency − Hz
2.2 2.4 2.6 2.8
3
3.2
Peak-to-Peak Signal Amplitude − V
1
RL = 250 Ω
RL = 2 kΩ
0.1
RL = 10 kΩ
0.010
RL = 100 kΩ
VDD = 5 V
AV = 1
TA = 25°C
0.001
4
4.1 4.2
4.3
4.4
4.5 4.6
4.7 4.8 4.9
5
Peak-to-Peak Signal Amplitude − V
Figure 34
Figure 35
WWW.TI.COM
21
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
90
80
RL = 10 kΩ
CL = 160 pF
55
70
φ m − Phase Margin − degrees
φ m − Phase Margin − degrees
60
VDD = ±2.5 V
TA = 25°C
RL = 10 kΩ
Rnull = 50 Ω
60
50
40
Rnull = 20 Ω
30
20
Rnull = 0 Ω
50
VDD = ±2.5 V
45
VDD = ±1.5 V
40
35
10
0
100
10
1k
30
−55 −35
100k
10k
CL − Load Capacitance − pF
−15
Figure 36
45
65
85
105
125
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
5
5
CL = 160 pF
RL = 10 kΩ
f = 10 kHz
TA = 25°C
4.75
Gain Bandwidth Product − MHz
Gain Bandwidth Product − MHz
25
Figure 37
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
4.75
5
TA − Free-Air Temperature − °C
4.5
4.25
4
3.75
4.5
RL = 10 kΩ
CL = 160 pF
VDD = ±2.5 V
4.25
4
3.75
3.5
VDD = ±1.5 V
3.25
3.5
2.5
3
3.5
4
4.5
5
5.5
6
VDD − Supply Voltage − V
−15
5
25
45
65
85
TA − Free-Air Temperature − °C
Figure 38
22
3
−55 −35
Figure 39
WWW.TI.COM
105
125
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
LARGE SIGNAL FOLLOWER
LARGE SIGNAL FOLLOWER
2.2
3.7
2
3.3
VO − Voltage − V
Input
VO − Voltage − V
Input
1.8
Output
1.6
1.4
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
1.2
1
0.8
−2
0
2
4
6
Input
2.9
Output
2.5
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
2.1
Output
1.7
8
10
12
14
16
1.3
−2
18
0
2
4
6
t − Time − µs
8
10
12
14
16
18
Figure 41
SMALL SIGNAL FOLLOWER
SMALL SIGNAL FOLLOWER
1.6
2.6
1.55
2.55
VO − Voltage − V
VO − Voltage − V
Output
t − Time − µs
Figure 40
Input
1.5
Output
1.45
1.4
−0.2
Input
Input
2.5
Output
2.45
VDD = 3 V
VI(PP) = 100 mV CL = 160 pF
AV = 1
VI = 1.5 V
TA = 25°C
RL = 10 kΩ
0
0.2
0.4
0.6
0.8
1
1.2 1.4
1.6 1.8
t − Time − µs
2.4
−0.2
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
0
0.2
0.4
0.6
CL = 160 pF
AV = 1
TA = 25°C
0.8
1
1.2 1.4
1.6 1.8
t − Time − µs
Figure 42
Figure 43
WWW.TI.COM
23
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
INVERTING LARGE SIGNAL
INVERTING LARGE SIGNAL
4
2.3
Input
2.1
Input
3.5
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
1.7
1.5
1.3
VO − Voltage − V
VO − Voltage − V
1.9
1.1
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
3
2.5
2
Output
0.9
Output
1.5
0.7
0.5
−0.2
0
0.2
0.4
0.6
0.8
1
1.2 1.4
1
−0.2
1.6 1.8
0
0.2
0.4
t − Time − µs
0.6
Figure 44
1.6 1.8
2.6
Input
Input
1.55
2.55
VDD = 3 V
VI(PP) = 100 mV
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
1.5
VO − Voltage − V
VO − Voltage − V
1.2 1.4
INVERTING SMALL SIGNAL
1.6
1.45
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
2.5
2.45
Output
0
0.2
0.4
0.6
0.8
Output
1
1.2 1.4
1.6 1.8
t − Time − µs
2.4
−0.2
0
0.2
0.4
0.6
0.8
1
t − Time − µs
Figure 46
24
1
Figure 45
INVERTING SMALL SIGNAL
1.4
−0.2
0.8
t − Time − µs
Figure 47
WWW.TI.COM
1.2 1.4
1.6 1.8
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
Rnull
_
+
RL
CL
Figure 48
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
RF
RG
RNULL
_
Input
Output
+
CLOAD
Figure 49. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB−
RG
+
−
VI
IIB+
V
OO
+V
IO
ǒ ǒ ǓǓ
1)
R
R
F
G
VO
+
RS
"I
IB)
R
S
ǒ ǒ ǓǓ
1)
R
R
F
G
"I
IB–
R
F
Figure 50. Output Offset Voltage Model
WWW.TI.COM
25
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 51).
RG
RF
−
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
1)
R
R
F
G
–3dB
Ǔǒ
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 51. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
RG =
Figure 52. 2-Pole Low-Pass Sallen-Key Filter
26
WWW.TI.COM
–3dB
+
(
1
2pRC
RF
1
2−
Q
)
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
shutdown function
Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2.
Therefore, when operating the device with split supply voltages (e.g. ± 2.5 V), the shutdown terminal needs to
be pulled to VDD− (not GND) to disable the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables.
circuit layout considerations
To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D Surface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
WWW.TI.COM
27
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
P
D
+
Where:
ǒ
T
Ǔ
–T
MAX A
q
JA
PD = Maximum power dissipation of THS246x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation − W
1.75
PDIP Package
Low-K Test PCB
θJA = 104°C/W
1.5
1.25
TJ = 150°C
MSOP Package
Low-K Test PCB
θJA = 260°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
−55 −40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
28
WWW.TI.COM
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are
generated using the TLV246x typical electrical and operating characteristics at TA = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
99
EGND +
R2
3
VDD +
−
+
ISS
RSS
CSS
VD
−
53
RP
10
2
IN −
J1
FB
6
7
+
9
VLIM
+
VB
8
GA
GCM
J2
−
−
DC
RO1
OUT
IN +
1
11
12
RD1
92
54
+
RD2
VE
+ DLP
91
+
VLP
−
−
−
+
90
HLIM
−
4
5
DLN
DE
C1
DP
GND
RO2
C2
VLN
RD1
3
11
2.8964E3
RD2
3
12
2.8964E3
R01
8
5
5.6000
R02
7
99
6.2000
RP
3
4
8.9127
RSS
10
99
10.610E6
VB
9
0
DC 0
VC
3
53
DC .7836
VE
54
4
DC .7436
VLIM
7
8
DC 0
VLP
91
0
DC 117
VLN
0
92
DC 117
.MODEL DX D (IS=800.00E−18)
.MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p)
.MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO= −1)
.MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO= −1)
.ENDS
.SUBCKT TLV246X 1 2 3 4 5
C1
11
12
2.46034E−12
C2
6
7
10.0000E−12
CSS
10
99
443.21E−15
DC
5
53
DY
DE
54
5
DY
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 21.600E6 −1E3 1E3 22E6 −22E6
GA
6
0
11
12 345.26E−6
GCM
0
6
10
99 15.4226E−9
ISS
10
4
DC 18.850E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX1
J2
12
1
10 JX2
R2
6
9
100.00E3
Figure 54. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
WWW.TI.COM
29
Device TLV2465A is Obsolete
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
macromodel information (continued)
rp
3
71
8.9127
rss
10
99
10.610E6
rs1
6
4
1G
rs2
6
4
1G
rs3
6
4
1G
rs4
6
4
1G
s1
71
4
6 4 s1x
s2
70
5
6 4 s1x
s3
10
74
6 4 s1x
s4
74
4
6 4 s2x
vb
9
0
dc 0
vc
3
53
dc .7836
ve
54
4
dc .7436
vlim
7
8
dc 0
vlp
91
0
dc 117
vln
0
92
dc 117
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model jx2 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0)
.model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5)
.ends
.subckt TLV_246Y 1 2 3 4 5 6
c1
11
12
2.4603E−12
c2
72
7
10.000E−12
css
10
99
443.21E−15
dc
70
53
dy
de
54
70
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
21.600E6 −1E3 1E3 22E6 −22E6
ga
72
0
11 12 345.26E−6
gcm
0
72
10 99 15.422E−9
iss
74
4
dc 18.850E−6
hlim
90
0
vlim 1K
j1
11
2
10 jx1
j2
12
1
10 jx2
r2
72
9
100.00E3
rd1
3
11
2.8964E3
rd2
3
12
2.8964E3
ro1
8
70
5.6000
ro2
7
99
6.2000
Figure 54. Boyle Macromodels and Subcircuit (Continued)
30
WWW.TI.COM
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-0051201QHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051201QHA
TLV2460M
5962-0051203QHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051203QHA
TLV2461M
5962-0051205QHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051205QHA
TLV2462M
5962-0051206Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59620051206Q2A
TLV2462A
MFKB
5962-0051206QHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051206QHA
TLV2462AM
5962-0051206QPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051206QPA
TLV2462AM
TLV2460AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2460AI
TLV2460AIP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2460AI
TLV2460CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2460C
TLV2460CDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VAOC
TLV2460CDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VAOC
TLV2460CDBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VAOC
TLV2460CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2460C
TLV2460CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2460C
TLV2460CP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLV2460C
TLV2460ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Addendum-Page 1
2460I
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2460IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAOI
TLV2460IDBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAOI
TLV2460IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAOI
TLV2460IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2460I
TLV2460IP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2460I
TLV2460MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051201QHA
TLV2460M
TLV2461AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2461AI
TLV2461AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2461AI
TLV2461AIP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2461AI
TLV2461CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2461C
TLV2461CDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VAPC
TLV2461CDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VAPC
TLV2461CDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VAPC
TLV2461CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2461C
TLV2461CP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLV2461C
TLV2461ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2461I
TLV2461IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAPI
TLV2461IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAPI
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2461IDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAPI
TLV2461IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2461I
TLV2461IP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2461I
TLV2461MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051203QHA
TLV2461M
TLV2462AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462AI
TLV2462AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462AI
TLV2462AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462AI
TLV2462AIP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2462AI
TLV2462AMFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59620051206Q2A
TLV2462A
MFKB
TLV2462AMJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLV2462AMJG
TLV2462AMJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051206QPA
TLV2462AM
TLV2462AMUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051206QHA
TLV2462AM
TLV2462AQD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
V2462A
TLV2462AQDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V2462A
TLV2462AQDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V2462A
TLV2462AQPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2462AQPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 3
-40 to 125
V2462A
V2462A
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2462CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2462C
TLV2462CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2462C
TLV2462CDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AAI
TLV2462CDGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AAI
TLV2462CDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AAI
TLV2462CDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AAI
TLV2462CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2462C
TLV2462CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2462C
TLV2462CP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLV2462CP
TLV2462CPE4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLV2462CP
TLV2462ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462I
TLV2462IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462I
TLV2462IDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AAJ
TLV2462IDGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AAJ
TLV2462IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AAJ
TLV2462IDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AAJ
TLV2462IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462I
TLV2462IP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2462IP
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2462MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
0051205QHA
TLV2462M
TLV2462QPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
V2462Q
TLV2462QPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2463AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2463AI
TLV2463AMJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLV2463AMJ
TLV2463CD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2463C
TLV2463CDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AAK
TLV2463CDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AAK
TLV2463CDGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AAK
TLV2463CDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2463C
TLV2463CN
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLV2463CN
TLV2463ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2463I
TLV2463IDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AAL
TLV2463IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AAL
TLV2463IN
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2463IN
TLV2464AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2464AI
TLV2464AIDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2464AI
TLV2464AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2464AI
Addendum-Page 5
V2462Q
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2464AIDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2464AI
TLV2464AIN
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2464AIN
TLV2464AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY2464A
TLV2464AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY2464A
TLV2464CD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2464C
TLV2464CDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2464C
TLV2464CN
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLV2464CN
TLV2464CNE4
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLV2464CN
TLV2464CPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TV2464
TLV2464CPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TV2464
TLV2464ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2464I
TLV2464IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2464I
TLV2464IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2464I
TLV2464IN
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2464IN
TLV2464IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY2464
TLV2464IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY2464
TLV2464IPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TY2464
TLV2465CD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
Addendum-Page 6
TLV2465C
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2465CDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2465C
TLV2465CPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
2465C
TLV2465ID
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2465I
TLV2465IDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2465I
TLV2465IN
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
TLV2465IN
TLV2465IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2465I
TLV2465IPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2465I
TLV2465IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2465I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 7
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2460, TLV2460A, TLV2460M, TLV2461, TLV2461A, TLV2461M, TLV2462, TLV2462A, TLV2462AM, TLV2462M, TLV2463, TLV2463A,
TLV2463AM, TLV2464A :
• Catalog: TLV2460, TLV2461, TLV2462A, TLV2462, TLV2463A
• Automotive:
TLV2460-Q1, TLV2460A-Q1, TLV2460-Q1, TLV2461-Q1, TLV2461A-Q1, TLV2461-Q1, TLV2462-Q1, TLV2462A-Q1, TLV2462A-Q1, TLV2462-Q1, TLV2463-Q1,
TLV2463A-Q1, TLV2463A-Q1, TLV2464A-Q1
• Enhanced Product: TLV2462A-EP, TLV2462A-EP, TLV2464A-EP
• Military: TLV2460M, TLV2461M, TLV2462M, TLV2462AM, TLV2463AM
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV2460AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2460CDBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV2460CDBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV2460CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2460IDBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV2460IDBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV2460IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2461AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2461CDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV2461CDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV2461CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2461IDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV2461IDBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV2461IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2462AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2462AQPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLV2462AQPWRG4
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLV2462CDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV2462CDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2462CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2462IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2462IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2462IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2462QPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLV2462QPWRG4
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLV2463AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2463CDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2463CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2463IDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2464AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2464AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV2464CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2464CPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV2464IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2464IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV2465CDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TLV2465IDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TLV2465IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV2460AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2460CDBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TLV2460CDBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TLV2460CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2460IDBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TLV2460IDBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
TLV2460IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2461AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2461CDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV2461CDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TLV2461CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2461IDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV2461IDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TLV2461IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2462AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2462AQPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
TLV2462AQPWRG4
TSSOP
PW
8
2000
367.0
367.0
35.0
TLV2462CDGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
TLV2462CDGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
TLV2462CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2462IDGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
TLV2462IDGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
TLV2462IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2462QPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
TLV2462QPWRG4
TSSOP
PW
8
2000
367.0
367.0
35.0
TLV2463AIDR
SOIC
D
14
2500
350.0
350.0
43.0
TLV2463CDGSR
VSSOP
DGS
10
2500
358.0
335.0
35.0
TLV2463CDR
SOIC
D
14
2500
350.0
350.0
43.0
TLV2463IDGSR
VSSOP
DGS
10
2500
358.0
335.0
35.0
TLV2464AIDR
SOIC
D
14
2500
333.2
345.9
28.6
TLV2464AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLV2464CDR
SOIC
D
14
2500
333.2
345.9
28.6
TLV2464CPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLV2464IDR
SOIC
D
14
2500
333.2
345.9
28.6
TLV2464IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLV2465CDR
SOIC
D
16
2500
350.0
350.0
43.0
TLV2465IDR
SOIC
D
16
2500
350.0
350.0
43.0
TLV2465IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 3
PACKAGE OUTLINE
U0010A
CFP - 2.03 mm max height
SCALE 1.400
CERAMIC FLATPACK
.045 MAX
TYP
.010 .002
PIN 1 ID
.27 MAX
GLASS
.005 MIN
TYP
1
10
8X .050 .005
.27 MAX
GLASS
10X .017 .002
5
6
5X .32 .01
.241
+.019
-.003
5X .32 .01
.005 .001
+.013
-.012
.067
.045
.026
4225582/A 01/2020
NOTES:
1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising