Texas Instruments | LP211, LP311 (Rev. D) | Datasheet | Texas Instruments LP211, LP311 (Rev. D) Datasheet

Texas Instruments LP211, LP311 (Rev. D) Datasheet
LP211, LP311
LOW-POWER DIFFERENTIAL COMPARATORS
WITH STROBES
SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003
D Low Power Drain . . . 900 μW Typical With
D
D
D
D
D
D
D
D
D
LP211 . . . D PACKAGE
LP311 . . . D, P, OR PS PACKAGE
(TOP VIEW)
5-V Supply
Operates From ±15 V or From a Single
Supply as Low as 3 V
Output Drive Capability of 25 mA
Emitter Output Can Swing Below Negative
Supply
Response Time . . . 1.2 μs Typ
Low Input Currents:
Offset Current . . . 2 nA Typ
Bias Current . . . 15 nA Typ
Wide Common-Mode Input Range:
−14.5 V to 13.5 V Using ±15-V Supply
Offset Balancing and Strobe Capability
Same Pinout as LM211, LM311
Designed To Be Interchangeable With
Industry-Standard LP311
EMIT OUT
IN+
IN−
VCC−
1
8
2
7
3
6
4
5
VCC+
COL OUT
BAL/STRB
BALANCE
description/ordering information
The LP211 and LP311 devices are low-power versions of the industry-standard LM211 and LM311 devices.
They take advantage of stable, high-value, ion-implanted resistors to perform the same function as the LM311
series, with a 30:1 reduction in power consumption, but only a 6:1 slowdown in response time. They are well
suited for battery-powered applications and all other applications where fast response times are not needed.
They operate over a wide range of supply voltages, from ±18 V down to a single 3-V supply with less than 300-μA
current drain, but are still capable of driving a 25-mA load. The LP211 and LP311 are quite easy to apply free
of oscillation if ordinary precautions are taken to minimize stray coupling from the output to either input or to the
trim pins. In addition, offset balancing is available to minimize input offset voltage. Strobe capability also is
provided to turn off the output (regardless of the inputs) by pulling the strobe pin low.
The LP211 is characterized for operation from −25°C to 85°C. The LP311 is characterized for operation from
0°C to 70°C.
ORDERING INFORMATION
TA
VIO max
AT 25°C
PACKAGE†
PDIP (P)
−0°C
0°C to 70°C
7 5 mV
7.5
SOIC (D)
SOP (PS)
−25°C
25°C to 85°C
†
7 5 mV
7.5
SOIC (D)
ORDERABLE
PART NUMBER
Tube of 50
LP311P
Tube of 75
LP311D
Reel of 2500
LP311DR
Reel of 2000
LP311PSR
Tube of 75
LP211D
Reel of 2500
LP211DR
TOP-SIDE
MARKING
LP311P
LP311
L311
LP211
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
LP211, LP311
LOW-POWER DIFFERENTIAL COMPARATORS
WITH STROBES
SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003
functional block diagram
BALANCE
BAL/STRB
IN+
COL OUT
IN−
EMIT OUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (see Note 1): VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input voltage, VI (either input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V
Voltage from emitter output to VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Voltage from collector output to VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V
Voltage from collector output to emitter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V
Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V
Package thermal impedance, θJA (see Notes 5 and 6): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W
PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this
specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC−.
2. Differential input voltages are at IN+ with respect to IN−.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage of ±15 V, whichever is less.
4. The output may be shorted to ground or to either power supply.
5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
2
(|VCC±| ≤ 15 V)
Input voltage
VCC+ − VCC−
Supply voltage
VCC− + 0.5
3.5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
VCC+ − 1.5
V
30
V
LP211, LP311
LOW-POWER DIFFERENTIAL COMPARATORS
WITH STROBES
SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003
electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
25°C
VID
VOL
Input offset voltage
Low-level output voltage
RS < 100 kΩ,
kΩ
See Note 7
VID < −10
10 mV,
See Note 8
IOL = 25 mA,
VCC = 4.5 V,
VID < −10
10 mV,
mV
See Note 8
VCC− = 0,
IOL = 1
1.6
6 mA
mA,
Input offset current
IIB
Input bias current
See Note 7
MAX
2
7.5
Full range
10
25°C
04
0.4
1
5
1.5
Full range
01
0.1
0
0.4
4
2
25
UNIT
mV
V
25°C
IIO
TYP†
Full range
35
25°C
15
Full range
nA
100
150
nA
Low level strobe current
Low-level
V(strobe) = 0.3 V,
See Note 9
VID < −10
10 mV,
IO(off)
Output off-state current
VID > 10 mV,
VCE = 35 V
AVD
Large signal differential
Large-signal
differential-voltage
voltage
amplification
RL = 5 kΩ
ICC+
Supply current from VCC+
VID = −50 mV,
RL = ∞
Full range
150
300
μA
ICC−
Supply current from VCC−
VID = 50 mV,
RL = ∞
Full range
− 80
− 180
μA
25°C
100
300
μA
A
25°C
0.2
100
nA
25°C
40
100
V/mV
All typical values are at VCC± = ±15 V, TA = 25°C.
NOTES: 7. The offset voltages and offset currents given are the maximum values required to drive the output within 1 V of either supply with
a 1-mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and input
impedance.
8. Voltages are with respect to EMIT OUT and VCC− tied together.
9. The strobe should not be shorted to ground; it should be current driven at 100 μA to 300 μA.
†
switching characteristics, VCC± = ±5 V, TA = 25°C (unless otherwise noted)
PARAMETER
Response time
TEST CONDITIONS
TYP
UNIT
See Note 10
1.2
μs
NOTE 10: The response time is specified for a 100-mV input step with 5-mV overdrive.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
LP211, LP311
LOW-POWER DIFFERENTIAL COMPARATORS
WITH STROBES
SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003
TYPICAL APPLICATION CIRCUIT
VCC+
3 kΩ
BAL/STRB
3 kΩ
BALANCE
TTL
Strobe
BAL/
STRB
2N2222
15 kΩ
NOTE: If offset balancing is not used,
the BALANCE and BAL/STRB
pins should be shorted together.
NOTE: Do not connect strobe pin
directly to ground, because the
output is turned off whenever
current is pulled from the strobe
pin.
Figure 2. Strobing
Figure 1. Offset Balancing
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP211D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
LP211
LP211DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
LP211
LP211DRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
LP211
LP211DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
LP211
LP311D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LP311
LP311DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LP311
LP311DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LP311
LP311P
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
LP311P
LP311PE4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
LP311P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
25-Sep-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP211DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LP311DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP211DR
SOIC
D
8
2500
340.5
338.1
20.6
LP311DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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