Texas Instruments | Inverting amplifier circuit (Rev. B) | Application notes | Texas Instruments Inverting amplifier circuit (Rev. B) Application notes

Texas Instruments Inverting amplifier circuit (Rev. B) Application notes
Analog Engineer's Circuit: Amplifiers
SBOA270B – February 2018 – Revised March 2019
Inverting amplifier circuit
Design Goals
Input
Output
Freq.
Supply
ViMin
ViMax
VoMin
VoMax
f
Vcc
Vee
–7 V
7V
–14 V
14 V
3 kHz
15 V
–15 V
Design Description
This design inverts the input signal, Vi, and applies a signal gain of –2 V/V. The input signal typically
comes from a low-impedance source because the input impedance of this circuit is determined by the
input resistor, R1. The common-mode voltage of an inverting amplifier is equal to the voltage connected to
the non-inverting node, which is ground in this design.
R1 10k
R2 20k
+
Vcc
Vi
Vcc 15
Vee
Vo
Vee 15
+
+
U1 TLV170
Vcc
Vee
Copyright © 2018, Texas Instruments Incorporated
Design Notes
1. Use the op amp in a linear operating region. Linear output swing is usually specified under the AOL test
conditions. The common-mode voltage in this circuit does not vary with input voltage.
2. The input impedance is determined by the input resistor. Make sure this value is large when compared
to the source output impedance.
3. Using high value resistors can degrade the phase margin of the circuit and introduce additional noise
in the circuit.
4. Avoid placing capacitive loads directly on the output of the amplifier to minimize stability issues.
5. Small-signal bandwidth is determined by the noise gain (or non-inverting gain) and op amp gainbandwidth product (GBP). Additional filtering can be accomplished by adding a capacitor in parallel to
R2. Adding a capacitor in parallel with R2 improves stability of the circuit if high value resistors are
used.
6. Large signal performance can be limited by slew rate. Therefore, check the maximum output swing
versus frequency plot in the data sheet to minimize slew-induced distortion.
7. For more information on op amp linear operating region, stability, slew-induced distortion, capacitive
load drive, driving ADCs, and bandwidth, see the Design References section.
SBOA270B – February 2018 – Revised March 2019
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Design Steps
The transfer function of this circuit is given below.
1. Determine the starting value of R1. The relative size of R1 to the signal source impedance affects the
gain error. Assuming the impedance from the signal source is low (for example, 100 Ω), set R1 = 10 kΩ
for 1% gain error.
2. Calculate the gain required for the circuit. Since this is an inverting amplifier, use ViMin and VoMax for the
calculation.
3. Calculate R2 for a desired signal gain of –2 V/V.
4. Calculate the small signal circuit bandwidth to ensure it meets the 3 kHz requirement. Be sure to use
the noise gain, or non-inverting gain, of the circuit.
5. Calculate the minimum slew rate required to minimize slew-induced distortion.
•
SRTLV170=0.4V/µs, therefore it meets this requirement.
6. To avoid stability issues, ensure that the zero created by the gain setting resistors and input
capacitance of the device is greater than the bandwidth of the circuit.
•
•
2
Ccm and Cdiff are the common-mode and differential input capacitances of the TLV170, respectively.
Since the zero frequency is greater than the bandwidth of the circuit, this requirement is met.
Inverting amplifier circuit
SBOA270B – February 2018 – Revised March 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
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Design Simulations
DC Simulation Results
T
14.0
Voltage (V)
7.0
0.0
-7.0
-14.0
-7.0
-3.5
0.0
Input voltage (V)
3.5
7.0
AC Simulation Results
The bandwidth of the circuit depends on the noise gain, which is 3 V/V. The bandwidth is determined by
looking at the –3dB point, which is located at 3dB given a signal gain of 6 dB. The simulation sufficiently
correlates with the calculated value of 400 kHz.
T
6.03
Gain (dB)
-3dB BW=519kHz
-20.00
1
10
100
1k
10k
Frequency (Hz)
100k
SBOA270B – February 2018 – Revised March 2019
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1M
10M
Inverting amplifier circuit
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Transient Simulation Results
The output is double the magnitude of the input and inverted.
Voltage (V)
T
13.99
0.00
-13.99
0
4
Inverting amplifier circuit
250u
500u
Time (s)
750u
1m
SBOA270B – February 2018 – Revised March 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
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References:
1. Analog Engineer's Circuit Cookbooks
2. SPICE Simulation File SBOC492
3. TI Precision Labs
Design Featured Op Amp
TLV170
Vss
±18 V (36 V)
VinCM
(Vee-0.1 V) to (Vcc-2 V)
Vout
Rail-to-rail
Vos
0.5 mV
Iq
125 µA
Ib
10 pA
UGBW
1.2 MHz
SR
0.4 V/µs
#Channels
1, 2, 4
www.ti.com/product/tlv170
Design Alternate Op Amp
LMV358A
Vss
2.5 V to 5.5 V
VinCM
(Vee–0.1 V) to (Vcc–1 V)
Vout
Rail-to-rail
Vos
1 mV
Iq
70 µA
Ib
10 pA
UGBW
1 MHz
SR
1.7 V/µs
#Channels
1 (LMV321A), 2 (LMV358A), 4
(LMV324A)
www.ti.com/product/lmv358A
Revision History
Revision
Date
A
January 2019
B
March 2019
Change
Downscale title.
Added link to circuit cookbook landing page.
Changed LMV358 to LMV358A in the Design Alternate Op Amp section.
SBOA270B – February 2018 – Revised March 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
Inverting amplifier circuit
5
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