Texas Instruments | Slew-rate limiter circuit (Rev. A) | Application notes | Texas Instruments Slew-rate limiter circuit (Rev. A) Application notes

Texas Instruments Slew-rate limiter circuit (Rev. A) Application notes
Analog Engineer's Circuit: Amplifiers
SBOA218A – January 2018 – Revised February 2019
Slew rate limiter circuit
Design Goals
Input
Output
Supply
ViMin
ViMax
VoMin
VoMax
Vcc
Vee
Vref
–10V
10V
–10V
10V
15V
–15V
0V
Design Description
This circuit controls the slew rate of an analog gain stage. This circuit is intended for symmetrical slew rate
applications. The desired slew rate must be slower than that of the op amp chosen to implement the slew
rate limiter.
Op Amp Gain Stage
Vcc
+
Vi
Vee 15
U1 OPA192
+
C1 470n
R1 1.69k
+
IC1 A
Vee
Vcc 15
Slew Rate Limiter
V+
Voa1
Vee
R2 1.6MEG
U2 OPA192
+
V+
Vcc
Vcc
Vo
RLoad 10
Vee
Design Notes
1. The gain stage op-amp and slew rate limiting op amp should both be checked for stability.
2. Verify that the current demands for charging or discharging C1 plus any load current out of U2 will not
limit the voltage swing of U2.
SBOA218A – January 2018 – Revised February 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
Slew rate limiter circuit
1
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Design Steps
1. Set slew rate and choose a standard value for the feedback capacitor, C1.
2. Choose the value of R2 to set the capacitor current necessary for the desired slew rate.
3. Compensate feedback network for stability. R1 adds a pole to the 1/β network. This pole should be
placed so that the 1/β curve levels off a decade before it intersects the open loop gain curve (200Hz,
for this example).
2
Slew rate limiter circuit
SBOA218A – January 2018 – Revised February 2019
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com
Design Simulations
Transient Simulation Results
9.37u
IC1
-9.37u
10.00
Vi
-10.00
10.00
Slew Rate = 19.94V/s
Vo
-10.00
15.00
Voa1
-15.00
2.75
0.00
5.50
Time (s)
8.25
11.00
AC Simulation Results
0.00
-3dB Frequency = 11.39kHz
Gain (dB)
-12.50
-25.00
-37.50
-50.00
Phase [deg]
0.00
-33.75
-67.50
-101.25
-135.00
10.00
100.00
1.00k
10.00k
Frequency (Hz)
SBOA218A – January 2018 – Revised February 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
100.00k
1.00MEG
Slew rate limiter circuit
3
www.ti.com
Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
See the circuit SPICE simulation file SBOC508.
See TIPD140, www.ti.com/tool/tipd140.
Design Featured Op Amp
OPA192
Vcc
4.5V to 36V
VinCM
Rail-to-rail
Vout
Rail-to-rail
Vos
5µV
Iq
1mA/Ch
Ib
5pA
UGBW
10MHz
SR
20V/µs
#Channels
1, 2, 4
www.ti.com/product/opa192
Design Alternate Op Amp
TLV2372
Vcc
2.7V to 16V
VinCM
Rail-to-rail
Vout
Rail-to-rail
Vos
2mV
Iq
750µA/Ch
Ib
1pA
UGBW
3MHz
SR
2.1V/µs
#Channels
1, 2, 4
www.ti.com/product/tlv2372
Revision History
4
Revision
Date
A
February 2019
Slew rate limiter circuit
Change
Downscale the title and changed title role to 'Amplifiers'.
Added links to circuit cookbook landing page and SPICE simulation file.
SBOA218A – January 2018 – Revised February 2019
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
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