Texas Instruments | High-voltage battery monitor circuit: ±20V, 0–10kHz, 18-bit fully differential (Rev. A) | Application notes | Texas Instruments High-voltage battery monitor circuit: ±20V, 0–10kHz, 18-bit fully differential (Rev. A) Application notes

Texas Instruments High-voltage battery monitor circuit: ±20V, 0–10kHz, 18-bit fully differential (Rev. A) Application notes
Analog Engineer's Circuit: Data
Converters
SBAA242A – December 2017 – Revised January 2019
High-voltage battery monitor circuit: ±20V, 0–10kHz,
18-bit fully differential
Bryan McKay, Arthur Kay
Input
ADC Input
Digital Output ADS8910
VinMin = –20V
VoutDif = 4.8V, VoutP = 4.9V, VoutN = 0.1V
1EB85 H or 125829 10
VinMax = 20V
VoutDif = –4.8V, VoutP = 0.1V, VoutN = 4.9V
2147B H or –125829 10
Power Supplies
Vcc
Vee
Vref
Vcm
5.3 V
0V
5V
2.5 V
Design Description
This design translates an input bipolar signal of ±20V into a fully differential ADC differential input scale of
±4.8V, which is within the output linear operation of amplifiers. The values in the component selection
section can be adjusted to allow for different input voltage levels.
This circuit implementation is applicable in accurate voltage measurement applications such as Battery
Maintenance Systems, Battery Analyzers, Battery Testing Equipment, ATE, and Remote Radio Units
(RRU) in wireless base stations.
Cf1 1.3n
Rg1 100k
Rf1 12k
Cfilt1 1.2n
VinMax 20
+
20V
Rg2 100k
INP
+ +
Rf2 12k
U3
OPA320
Vs
5V
Vcm
2.5V
RVDD
VREF
ADS8910B
VoutDif
4.8V
+
Cf2 1.3n
Vref
5.0V
VoutP
+0.1V
Rfilt1 47.5
-
Vcc
5.4V
INM
GND
VoutN
+4.9V
Cf3 1.3n
Vs
5V
Rf3 12k
+
Rfilt2
47.5
+
Rg3 100k
20V
+
-
Rg4 100k
U1
OPA320
Cfilt2 1.2n
Rf4 12k
Cf4 1.3n
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Specifications
Specification
Transient ADC Input Settling
Noise
Bandwidth
Calculated
Simulated
Measured
< 0.5LSB or 19µV
6.6µV
N/A
20.7µV rms
20.65µV rms
30.8µV rms
10.2kHz
10.4kHz
10.4kHz
Design Notes
1. Determine the linear range of the op amp based on common mode, output swing, and linear open-loop
gain specification. This is covered in the component selection section.
2. For capacitors in the signal path, select COG type to minimize distortion. In this circuit Cf1, Cf2, Cf3,
Cf4, Cfilt1, and Cfilt2 need to be COG type.
3. Use 0.1% 20ppm/°C film resistors or better for good gain drift and to minimize distortion.
4. Precision labs video series covers methods for error analysis. Review the Statistics Behind Error
Analysis for methods to minimize gain, offset, drift, and noise errors.
5. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt. These component values are dependent on the amplifier bandwidth, data converter
sampling rate, and data converter design. The values shown here will give good settling and AC
performance for the amplifier, gain settings, and data converter in this example. If the design is
modified, select a different RC filter. Refer to Introduction to SAR ADC Front-End Component Selection
for an explanation of how to select the RC filter for best settling and AC performance.
2
High-voltage battery monitor circuit: ±20V, 0–10kHz,18-bit fully differential
SBAA242A – December 2017 – Revised January 2019
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Component Selection
1. The general equation for this circuit.
2. Find op amp maximum and minimum output for linear operation.
3. Rearrange the equation from part 1 and solve for VoutDifMin and VoutDifMax. Find maximum and
minimum differential output voltage based on combined worst case from step 2.
4. Find differential gain based on results from step 3.
5. Find standard resistor values for differential gain. Use Analog Engineer's Calculator ("Amplifier and
Comparator\Find Amplifier Gain" section) to find standard values for Rf/Rg ratio.
6. Find Cf for cutoff frequency.
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DC Transfer Characteristics
The following graph shows a linear output response for inputs from –20V to +20V. Refer to Determining a
SAR ADC's Linear Range when using Operational Amplifiers for detailed theory on this subject.
T 5.00
Voltage (V)
2.50
Vin = 20V
VoutDif = 4.8V
0.00
Vin = -20V
VoutDif = -4.5V
-2.50
-5.00
-25
-20
-15
-10
-5
0
5
Input voltage (V)
10
15
20
25
AC Transfer Characteristics
The bandwidth is simulated to be 10.4 kHz, and the gain is –12.4dB which is a linear gain of 0.12. See Op
Amps: Bandwidth 1 for more details on this subject.
T -10.00
Gain (dB)
-20.00
Vdif
fc = 10.4kHz
-30.00
-40.00
-50.00
-60.00
10
4
100
1k
10k
Frequency (Hz)
High-voltage battery monitor circuit: ±20V, 0–10kHz,18-bit fully differential
100k
1MEG
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Transient ADC Input Settling Simulation
The following simulation shows settling to a –20V dc input signal. This type of simulation shows that the
sample and hold kickback circuit is properly selected. Refer to Introduction to SAR ADC Front-End
Component Selection for detailed theory on this subject.
T
1.00
Vacq
0.00
1.00
Vconv
0.00
-2.29
Vdif
-2.40
1.00m
Verror
4.6uV
Verror
-1.00m
2.00u
2.50u
Time (s)
3.00u
Noise Simulation
The following simplified noise calculation is provided for a rough estimate. We neglect resistor noise in this
calculation as it is attenuated for frequencies greater than 10kHz.
Note that calculated and simulated match well. Refer to Calculating the Total Noise for ADC Systems for
detailed theory on this subject.
Total noise (V)
T 20.65u
10.32u
0.00
10
100
1k
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10k
100k
Frequency (Hz)
1MEG
10MEG
100MEG
High-voltage battery monitor circuit: ±20V, 0–10kHz,18-bit fully differential
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Measure FFT
This performance was measured on a modified version of the ADS8910BEVM. The AC performance
indicates SNR = 99.4dB, and THD = –116.4dB. See Introduction to Frequency Domain for more details on
this subject.
Noise Measurement
The following measured result is for both inputs connected to ground. The histogram shows the system
offset and noise. The standard deviation in codes is given by the EVM GUI (0.81), and this can be used to
calculate the RMS noise (30.9µV rms) as shown in the following equation.
6
High-voltage battery monitor circuit: ±20V, 0–10kHz,18-bit fully differential
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Design Featured Devices
Device
Key Features
Link
Similar Devices
ADS8900B (1)
18-bit resolution, 1-Msps sample rate, Integrated reference buffer, fully
differential input, Vref input range 2.5V to 5V.
www.ti.com/product/ADS8900B
www.ti.com/adcs
OPA320 (2)
20-MHz bandwidth, Rail-to-Rail with Zero Crossover Distortion,
VosMax = 150 µV, VosDriftMax = 5uV/°C, en = 7nV/rtHz
www.ti.com/product/OPA320
www.ti.com/opamp
REF5050 (3)
3 ppm/°C drift, 0.05% initial accuracy, 4µVpp/V noise
www.ti.com/product/REF5050
www.ti.com/vref
(1)
(2)
(3)
The REF5050 can be directly connected to the ADS8910B without any buffer because the ADS8910B has a built in internal reference
buffer. Also, the REF5050 has the required low noise and drift for precision SAR ADC applications. The OPA320 is also commonly used
in 1Msps SAR applications as it has sufficient bandwidth to settle to charge kickback transients from the ADC input sampling.
Furthermore, the zero crossover distortion rail-to-rail input allows for linear swing across most of the ADC input range.
The REF5050 can be directly connected to the ADS8910B without any buffer because the ADS8910B has a built in internal reference
buffer. Also, the REF5050 has the required low noise and drift for precision SAR ADC applications. The OPA320 is also commonly used
in 1Msps SAR applications as it has sufficient bandwidth.
The REF5050 can be directly connected to the ADS8910B without any buffer because the ADS8910B has a built in internal reference
buffer. Also, the REF5050 has the required low noise and drift for precision SAR ADC applications. The OPA320 is also commonly used
in 1Msps SAR applications as it has sufficient bandwidth.
Link to Key Files for High Voltage Battery Monitor
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Design files for this circuit – http://www.ti.com/lit/zip/sbac171.
Revision History
Revision
Date
A
January 2019
Change
Downstyle title, update title role content, added link to circuit cookbook library page.
SBAA242A – December 2017 – Revised January 2019
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